The M74HC273 is an high speed CMOS OCTAL
D TYPE FLIP FLOP WITH CLEAR fabricated with
silicon gate C
2
MOS technology.
Information signals applied to D inputs are
transferred to the Q output s on the positive-goi ng
edge of the clock pulse.
TSSOPDIPSOP
ORDER CODES
PACKAGETUBET & R
DIPM74HC273B1R
SOPM74HC273M1RM74HC273RM13TR
TSSOPM74HC273TTR
When the CLEAR
input is held lo w, the Q output
are in the low logic level independent of the other
inputs.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/11July 2001
Page 2
M74HC273
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN NoSYMBOLNAME AND FUNCTION
1CLEAR
2, 5, 6, 9, 12,
15, 16, 19
3, 4, 7, 8, 13,
14, 17, 18
11CLOCK
10GNDGround (0V)
20VccPositive Supply Voltage
TRUTH TABLE
Q0 to Q7Flip Flop Outputs
D0 to D7Data Inputs
Master Reset Input
(Active LOW)
Clock Input (LOW to
HIGH, Edge Triggered)
CLEAR
LXXLCLEAR
HLL
HHH
HXQnNO CHANGE
X : Don’t Care
LOGIC DIAGRAM
INPUTSOUTPUTS
FUNCTION
CLOCKDQ
This log i c diagram has not be used to est i m at e propagation delays
2/11
Page 3
M74HC273
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
V
V
I
I
OK
I
I
or I
CC
P
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
FLOP), and the total CP D when n pcs of FL IP FLOP operat e can be gained by the following equations: CPD (total) = 32 + 11 x n
Input Capacitance
IN
Power Dissipation
PD
Capacitance (note 1)5.043pF
5.05101010pF
T
A
Min.Typ. Max.Min.Max. Min. Max.
-40 to 85°C -55 to 125°C
= CPD x VCC x fIN + ICC/8 (per FL IP
CC(opr)
Unit
5/11
Page 6
M74HC273
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and p robe capacit ance)
= Z
R
WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycl e )
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