The M74HC174 is an high speed CMOS HEX
D-TYPE FLIP FLOP WITH CLEAR fabricated with
silicon gate C
2
MOS technology.
Information signals applied to D inputs are
transferred to the Q output on the positive going
edge of the clock pulse. When the CLEAR
input is
TSSOPDIPSOP
ORDER CODES
PACKAGETUBET & R
DIPM74HC174B1R
SOPM74HC174M1RM74HC174RM13TR
TSSOPM74HC174TTR
held low, the Q outputs are held low independently
of the other inputs.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/11July 2001
Page 2
M74HC174
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN NoSYMBOLNAME AND FUNCTION
1CLEAR
2, 5, 7, 10,
12, 15
3, 4, 6, 11,
13, 14
9CLOCK
8GNDGround (0V)
16VccPositive Supply Voltage
TRUTH TABLE
Q0 to Q5Flip-Flop Outputs
D0 to D5 Data Inputs
Asynchronous Master
Reset (Active Low)
Clock Input (LOW to
HIGH, edge triggered)
CLEAR
LXXLCLEAR
HLL
HHH
HXQnNO CHANGE
X : Don’t Care
LOGIC DIAGRAM
INPUTSOUTPUTS
FUNCTION
DCKQ
This log i c diagram has not to be used to es t i m ate propagati on delays
2/11
Page 3
M74HC174
ABSOLUTE MAXIMUM RATINGS
SymbolParame terValueUnit
V
V
V
I
I
OK
I
I
or I
CC
P
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
FLOP)
And the to tal CPD when N pcs of FLIP-FLOP operate c an be gained by the followin g equation : CPD (total) = 38 + 15 x n
Input Capacitance
IN
Power Dissipation
PD
Capacitance (note 1)5.040pF
5.05101010pF
T
A
Min.Typ. Max. Min. Max. Min.Max.
-40 to 85°C -55 to 125°C
= CPD x VCC x fIN + ICC/6 (per FLIP/
CC(opr)
Unit
5/11
Page 6
M74HC174
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and p robe capacit ance)
R
= Z
of pulse generator (typically 50Ω)
T
OUT
WAVEFORM 1: PROPAGATION DELAY TIME, MINIMUM PULSE WIDTH (CLOCK), SETUP AND
HOLD TIME (nD TO CLOCK), CLOCK MAXIMUM FREQUENCY (f=1MHz; 50% duty cycle)
6/11
Page 7
WAVEFORM 2 :PROPAGATION DELAY TIME (nQ TO CLEAR)(f=1MHz; 50% duty cycle)
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