The M74HC107 is an high speed CMOS DUAL
J-K FLIP FLOP fabricated with silicon gate
2
C
MOS technology. These flip-flop are edge
sensitive to the clock input and cha nge state on
the negative going transition of the clock pulse.
Each one has independent J, K, CLOCK, and
TSSOPDIPSOP
ORDER CODES
PACKAGETUBET & R
DIPM74HC107B1R
SOPM74HC107M1RM74HC107RM13TR
TSSOPM74HC107TTR
CLEAR input and Q and Q
outputs. CLEAR is
independent of t he clock and accomplis hed by a
logic low on the input.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/11August 2001
Page 2
M74HC107
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN NoSYMBOLNAME AND FUNCTION
1, 8, 4, 11
2, 61Q
3, 51Q, 2QTrue Flip-Flop Outputs
12, 91CK
13, 101CLR, 2CLR
7GNDGround (0V)
14VccPositive Supply Voltage
TRUTH TABLE
1J, 2J, 1K, 2KSynchronous Inputs;
, 2Q
, 2CKClock Input
Flip-Flop 1 And 2
Complement Flip-Flop
Outputs
Asynchronous Reset
Inputs
INPUTSOUTPUTS
CLR
JKCKQQ
LXXXLHCLEAR
HLL
Q
n
Q
n
HLHLH---HHLHL---HHH
HXX
X : Don’t Care
Q
n
Q
n
Q
n
Q
n
LOGIC DIAGRAM
FUNCTION
NO CHANGE
TOGGLE
NO CHANGE
2/11
Page 3
M74HC107
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
V
V
I
I
OK
I
I
or I
CC
P
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
FLOP)
Input Capacitance
IN
Power Dissipation
PD
Capacitance (note 1)5.032pF
5.05101010pF
T
A
Min.Typ. Max.Min.Max. Min.Max.
-40 to 85°C -55 to 125°C
= CPD x VCC x fIN + ICC/2 (per FLIP/
CC(opr)
Unit
5/11
Page 6
M74HC107
TEST CIRCUIT
CL = 50pF or equivalent (in cludes jig and probe capaci tance)
= Z
R
WAVEFORM 1: MINIMUM REMOVAL TIME (f=1MHz; 50% duty cycle)
of pulse generator (typically 50Ω)
T
OUT
6/11
Page 7
M74HC107
WAVEFORM 2 : PROPAGATION DELAY TIME, MINIMUM PULSE WIDTH, SETUP AND HOLD TIME
(f=1MHz; 50% duty cycle)
WAVEFORM 3 : MINIMUM PULSE WUDTH AND REMOVAL TIME (f=1MHz; 50% duty cycle)
7/11
Page 8
M74HC107
Plastic DIP-14 MECHANICAL DATA
mm.inch
DIM.
MIN.TYPMAX.MIN.TYP.MAX.
a10.510.020
B1.391.650.0550.065
b0.50.020
b10.250.010
D200.787
E8.50.335
e2.540.100
e315.240.600
F7.10.280
I5.10.201
L3.30.130
Z1.272.540.0500.100
8/11
P001A
Page 9
SO-14 MECHANICAL DATA
M74HC107
DIM.
A1.750.068
a10.10.20.0030.007
a21.650.064
b0.350.460.0130.018
b10.190.250.0070.010
C0.50.019
c145° (typ.)
D8.558.750.3360.344
E5.86.20.2280.244
e1.270.050
e37.620.300
F3.84.00.1490.157
G4.65.30.1810.208
L0.51.270.0190.050
M0.680.026
S8° (max.)
MIN.TYPMAX.MIN.TYP.M AX.
mm.inch
PO13G
9/11
Page 10
M74HC107
TSSOP14 MECHANICAL DATA
mm.inch
DIM.
MIN.TYPMAX.MIN.TYP.M AX.
A1.20.047
A10.050.150.0020.0040.006
A20.811.050.0310.0390.041
b0.190.300.0070.012
c0.090.200.0040.0089
D4.955.10.1930.1970.201
E6.26.46.60.2440.2520.260
E14.34.44.480.1690.1730.176
e0.65 BSC0.0256 BSC
K0°8°0°8°
L0.450.600.750.0180.0240.030
A2
A
A1
b
e
c
K
L
E
D
E1
PIN 1 IDENTIFICATION
10/11
1
0080337D
Page 11
M74HC107
Information furnished is bel ieved to be accurate and reliable. However, STMicroe lectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No li cense is granted by i mp lication or otherwise under a ny patent or patent rig h ts of S TMic roelec tronics. Specifications
mentioned in this publication ar e subject to change without notice. This publication supersedes and replaces all information
previously supplied. S TMicroelectronics products are not authorized for use as critica l components in life suppo rt devices or
systems without express written approval of STMicroelectronics.
Australi a - Brazil - Chi na - Finlan d - F rance - Germ any - Hong Kon g - India - Italy - Japan - Ma l aysia - Malta - Morocco