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M6MGB160S4BVP
Datasheet (Mitsubishi)
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Datasheet M6MGT160S4BVP, M6MGB160S4BVP Datasheet (Mitsubishi)

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Page 1
MITSUBISHI LSIs
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144WORD BY 16-BIT / 524,288-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
The MITSUBISHI M6MGB/T160S4BVP is a Stacked Multi Chip Package (S-MCP) that contents 16M-bits flash memory and 4M-bits Static RAM in a 48-pin TSOP (TYPE-I).
16M-bits Flash memory is a 2097152 bytes /1048576 words,
3.3V-only, and high performance non-volatile memory fabricated by CMOS technology for the peripheral circuit and DINOR(DIvided bit-line NOR) architecture for the memory cell. 4M-bits SRAM is a 524288bytes / 262144words unsynchronous SRAM fabricated by silicon-gate CMOS technology.
M6MGB/T160S4BVP is suitable for the application of the mobile-communication-system to reduce both the mount space and weight .
PIN CONFIGURATION (TOP VIEW)
A15 A14 A13 A12 A11
A10
A19
S-CE
WE#
F-RP# F-WP# S-VCC
10.0 mm
F-RY/BY#
A18 A17
A7 A6 A5
A4 A2
A1
A9 A8
A3
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
FEATURES
• Access time Flash Memory 90ns (Max.) SRAM 85ns (Max.)
• Supply voltage Vcc=2.7 ~ 3.6V
• Ambient temperature W version Ta=-20 ~ 85°C
• Package : 48-pin TSOP (Type-I) , 0.4mm lead pitch
APPLICATION
Mobile communication products
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A16 BYTE# GND
DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 F-VCC
DQ11 DQ3 DQ10 DQ2 DQ9 DQ1
DQ8 DQ0 OE# GND
F-CE#
A0
14.0 mm
F-VCC S-VCC GND :GND for Flash/SRAM
A-1-A17
A18-A19 :Address for Flash DQ0-DQ15 :Data I/O F-CE# :Flash Chip Enable
S-CE :SRAM Chip Enable
OE#
WE#
F-WP# :Flash Write Protect
F-RP# :Flash Reset Power Down
F-RY/BY#
BYTE#
1
:Vcc for Flash :Vcc for SRAM
:Flash/SRAM common Address
:Flash/SRAM Output Enable :Flash/SRAM Write Enable
:Flash Ready /Busy :Flash/SRAM Byte Enable
NC:Non Connection
Sep. 1999 , Rev.2.0
Page 2
BLOCK DIAGRAM
MITSUBISHI LSIs
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144WORD BY 16-BIT / 524,288-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
16Mb Flash Memory
ADDRESS
INPUTS
CHIP ENABLE INPUT
OUTPUT ENABLE INPUT
WRITE ENABLE INPUT
WRITE PROTECT INPUT
RESET/POWER DOWN INPUT
BYTE ENABLE INPUT
READY/BUSY OUTPUT
F-RY/BY#
4Mb SRAM
A19 A18
A17 A16
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1
A0
F-CE# OE# WE# F-WP#
F-RP# BYTE#
X-DECODER
Y-DECODER
STATUS / ID REGISTER
WSM
CUI
WSM
128 WORD PAGE BUFFER
Main Block 32KW
Bank(II)
28
Main Block 32KW
Parameter Block7 16KW Parameter Block6 16KW
Bank(I)
Parameter Block5 16KW Parameter Block4 16KW Parameter Block3 16KW Parameter Block2 16KW Parameter Block1 16KW Boot Block 16KW
Y-GATE / SENSE AMP.
MULTIPLEXER
INPUT/OUTPUT
DQ15/A-1
DQ14DQ13DQ12 DQ2DQ1DQ0DQ3
DATA INPUTS/OUTPUTS
F-VCC (3.3V)
GND (0V)
BUFFERS
A-1
A0
A15
A17
S-CE
BYTE#
WE#
OE#
524288WORD x
8 BITS
262144 WORD x
16 BITS
ROW DECODER
ADDRESS INPUT BUFFER
CLOCK
GENERATOR
or
SENSE AMP.
SENSE AMP.
DATAINPUT
DATAINPUT
OUTPUT BUFFER
OUTPUT BUFFER
BUFFER
BUFFER
DQ0
DQ7
DQ 8
DQ15/A-1
S-VCC
GND
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Sep. 1999 , Rev.2.0
Page 3
MITSUBISHI LSIs
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144WORD BY 16-BIT / 524,288-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
1. Flash Memory
DESCRIPTION
The Flash Memory of M6MGB/T160S4BVP is 3.3V-only high speed 16,777,216-bit CMOS boot block Flash Memories with alternating BGO (Back Ground Operation) feature. The BGO feature of the device allows Program or Erase operations to be performed in one bank while the device simultaneously allows Read operations to be performed on the other bank. This BGO feature is suitable for mobile and personal computing, and communication products. The Flash Memory of M6MGB/T160S4BVP is fabricated by CMOS technology for the peripheral circuits and DINOR(Divided bit line NOR) architecture for the memory cells.
FEATURES
Organization 1048,576 word x 16bit
2,097,152 word x 8 bit
Supply voltage
Access time 90ns(Max.)
Power Dissipation Read 54 mW (Max. at 5MHz) (After Automatic Power saving) 0.33mW (typ.) Program/Erase 144 mW (Max.) Standby 0.33mW (typ.) Deep power down mode 0.33mW (typ.) Auto program for Bank(I) Program Time 4ms (typ.) Program Unit (Byte Program) 1word/1byte (Page Program) 128word/256byte Auto program for Bank(II) Program Time 4ms (typ.) Program Unit 128word/256byte Auto Erase Erase time 40 ms (typ.) Erase Unit Bank(I) Boot Block 16Kword/32Kbyte x 1 Parameter Block 16Kword/32Kbyte x 7 Bank(II) Main Block 32Kword/64Kbyte x 28
Program/Erase cycles 100Kcycles
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................................ VCC = 2.7~3.6V
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Boot Block M6MGB160S4BVP Bottom Boot M6MGT160S4BVP Top Boot
Other Functions Soft Ware Command Control Selective Block Lock Erase Suspend/Resume Program Suspend/Resume Status Register Read Alternating Back Ground Program/Erase Operation Between Bank(I) and Bank(II)
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Sep. 1999 , Rev.2.0
Page 4
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
4,194,304-BIT (262,144WORD BY 16-BIT / 524,288-WORD BY 8-BIT) CMOS SRAM
FUNCTION
The Flash Memory of M6MGB/T160S4BVP includes on-chip program/erase control circuitry. The Write State Machine (WSM) controls block erase and byte/page program operations. Operational modes are selected by the commands written to the Command User Interface (CUI). The Status Register indicates the status of the WSM and when the WSM successfully completes the desired program or block erase operation. A Deep Powerdown mode is enabled when the RP# pin is at GND, minimizing power consumption.
MITSUBISHI LSIs
M6MGB/T160S4BVP
3.3V-ONLY FLASH MEMORY &
Stacked-MCP (Multi Chip Package)
Deep Power-Down
When RP# is at VIL, the device is in the deep powerdown mode and its power consumption is substantially low. During read modes, the memory is deselected and the data input/output are in a high-impedance(High-Z) state. After return from powerdown, the CUI is reset to Read Array , and the Status Register is cleared to value 80H. During block erase or program modes, RP# low will abort either operation. Memory array data of the block being altered become invalid.
Read
The Flash Memory of M6MGB/T160S4BVP has three read modes, which accesses to the memory array, the Device Identifier and the Status Register. The appropriate read command are required to be written to the CUI. Upon initial device powerup or after exit from deep powerdown, the Flash Memory automatically resets to read array mode. In the read array mode, low level input to F-CE# and OE#, high level input to WE# and RP#, and address signals to the address inputs (A19-A-1:Byte Mode, A19-A0:Word Mode) output the data of the addressed location to the data input/output (D7-D0:Byte Mode, D15-D0:Word Mode).
Write
Writes to the CUI enables reading of memory array data, device identifiers and reading and clearing of the Status Register. They also enable block erase and program. The CUI is written by bringing WE# to low level, while F-CE# is at low level and OE# is at high level. Address and data are latched on the earlier rising edge of WE# and F-CE#. Standard micro-processor write timings are used.
Alternating Background Operation (BGO)
The Flash Memory of M6MGB/T160S4BVP allows to read array from one bank while the other bank operates in software command write cycling or the erasing / programming operation in the background. Read array operation with the other bank in BGO is performed by changing the bank address without any additional command. When the bank address points the bank in software command write cycling or the erasing / programming operation, the data is read out from the status register. The access time with BGO is the same as the normal read operation.
Automatic Power-Saving (APS)
The Automatic Power-Saving minimizes the power consumption during read mode. The device automatically turns to this mode when any addresses or F-CE# isn't changed more than 200ns after the last alternation. The power consumption becomes the same as the stand-by mode. While in this mode, the output data is latched and can be read out. New data is read out correctly when addresses are changed.
Output Disable
When OE# is at VIH, output from the devices is disabled. Data input/output are in a high-impedance(High-Z) state.
Standby
When F-CE# is at VIH, the device is in the standby mode and its power consumption is reduced. Data input/output are in a high-impedance(High-Z) state. If the memory is deselected during block erase or program, the internal control circuits remain active and the device consume normal active power until the operation completes.
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Sep. 1999 , Rev.2.0
Page 5
MITSUBISHI LSIs
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144WORD BY 16-BIT / 524,288-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
SOFTWARE COMMAND DEFINITIONS
The device operations are selected by writing specific software command into the Command User Interface.
Read Array Command (FFH) The device is in Read Array mode on initial device power up and after exit from deep powerdown, or by writing FFH to the Command User Interface. After starting the internal operation the device is set to the read status register mode automatically.
Read Device Identifier Command (90H) It can normally read device identifier codes when Read Device Identifier Code Command(90H) is written to the command latch. Following the command write, the manufacturer code and the device code can be read from address 0000H and 0001H, respectively.
Read Status Register Command (70H) The Status Register is read after writing the Read Status Register command of 70H to the Command User Interface. Also, after starting the internal operation the device is set to the Read Status Register mode automatically. The contents of Status Register are latched on the later falling edge of OE# or F-CE#. So F-CE# or OE# must be toggled every status read.
Clear Status Register Command (50H) The Erase Status, Program Status and Block Status bits are set to "1"s by the Write State Machine and can only be reset by the Clear Status Register command of 50H. These bits indicates various failure conditions.
C)Single Data Load to Page Buffer (74H) / Page Buffer to Flash (0EH/D0H)
Single data load to the page buffer is performed by writing 74H followed by a second write specifying the column address and data. Distinct data up to 256byte/128word can be loaded to the page buffer by this two-command sequence. On the other hand, all of the loaded data to the page buffer is programed simultaneously by writing Page Buffer to Flash command of 0EH followed by the confirm command of D0H. After completion of programing the data on the page buffer is cleared automatically. This command is valid for only Bank(I) alike Word/Byte Program.
Clear Page Buffer Command (55H) Loaded data to the page buffer is cleared by writing the Clear Page Buffer command of 55H followed by the Confirm command of D0H. This command is valid for clearing data loaded by Single Data Load to Page Buffer command.
Suspend/Resume Command (B0H/D0H) Writing the Suspend command of B0H during block erase operation interrupts the block erase operation and allows read out from another block of memory. Writing the Suspend command of B0H during program operation interrupts the program operation and allows read out from another block of memory. The Bank address is required when writing the Suspend/Resume Command. The device continues to output Status Register data when read, after the Suspend command is written to it. Polling the WSM Status and Suspend Status bits will determine when the erase operation or program operation has been suspended. At this point, writing of the Read Array command to the CUI enables reading data from blocks other than that which is suspended. When the Resume command of D0H is written to the CUI, the WSM will continue with the erase or program processes.
Block Erase / Confirm Command (20H/D0H) Automated block erase is initiated by writing the Block Erase command of 20H followed by the Confirm command of D0H. An address within the block to be erased is required. The WSM executes iterative erase pulse application and erase verify operation.
Program Commands
A)Word/Byte Program (40H)
Word/Byte program is executed by a two-command sequence. The Word/Byte Program Setup command of 40H is written to the Command Interface, followed by a second write specifying the address and data to be written. The WSM controls the program pulse application and verify operation. The Word/Byte Program Command is Valid for only Bank(I).
B)Page Program for Data Blocks (41H)
Page Program for Bank(I) and Bank(II) allows fast programming of 128words/256bytes of data. Writing of 41H initiates the page program operation for the Data area. From 2nd cycle to 257th cycle (Byte Mode)129th cycle (Word Mode), write data must be serially inputted. Address A6-A0,A-1 (Byte Mode) / A6-A0 (Word Mode) have to be incremented from 00H to 7FH/FFH. After completion of data loading, the WSM controls the program pulse application and verify operation.
DATA PROTECTION
The Flash Memory of M6MGB/T160S4BVP provides selectable block locking of memory blocks. Each block has an associated nonvolatile lock-bit which determines the lock status of the block. In addition, the Flash Memory has a master Write Protect pin (WP#) which prevents any modifications to memory blocks whose lock-bits are set to "0", when WP# is low. When WP# is high, all blocks can be programmed or erased regardless of the state of the lock-bits, and the lock-bits are cleared to "1" by erase. See the BLOCK LOCKING table on P.9 for details.
Power Supply Voltage
When the power supply voltage (F-Vcc) is less than V Lock-Out voltage, the device is set to the Read-only mode. Regarding DC electrical characteristics of V A delay time of 2 us is required before any device operation is initiated. The delay time is measured from the time F-Vcc reaches F-Vccmin (2.7V). During power up, RP#=GND is recommended. Falling in Busy status is not recommended for possibility of damaging the device.
MEMORY ORGANIZATION
The Flash Memory of M6MGB/T16S2BVP has one 32Kbyte boot block, seven 32Kbyte parameter blocks, for Bank(I) and twenty-eight 64Kbyte main blocks for Bank(II). A block is erased independently of other blocks in the array.
LKO, see P.10.
LKO, Low VCC
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Sep. 1999 , Rev.2.0
Page 6
MEMORY ORGANIZATION
MITSUBISHI LSIs
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144WORD BY 16-BIT / 524,288-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
x8 ( Bytemode) x16 ( Wordmode)
1F0000H-1FFFFFH
1E0000H-1EFFFFH
1D0000H-1DFFFFH
1C0000H-1CFFFFH
1B0000H-1BFFFFH
1A0000H-1AFFFFH
190000H-19FFFFH
180000H-18FFFFH
170000H-17FFFFH
160000H-16FFFFH
150000H-15FFFFH
140000H-14FFFFH
130000H-13FFFFH
120000H-12FFFFH
110000H-1FFFFFH
100000H-10FFFFH
F0000H-FFFFFH
E0000H-EFFFFH
D0000H-DFFFFH
C0000H-CFFFFH
B0000H-BFFFFH
A0000H-AFFFFH
90000H-9FFFFH
80000H-8FFFFH
70000H-7FFFFH
60000H-6FFFFH
50000H-5FFFFH
40000H-4FFFFH
38000H-3FFFFH
30000H-37FFFH
28000H-2FFFFH
20000H-27FFFH
18000H-1FFFFH
10000H-17FFFH
08000H-0FFFFH
00000H-07FFFH
A19-A-1 (Byte Mode)
F8000H-FFFFFH
F0000H-F7FFFH
E8000H-EFFFFH
E0000H-E7FFFH
D8000H-DFFFFH
D0000H-D7FFFH
C8000H-CFFFFH
C0000H-C7FFFH
B8000H-BFFFFH
B0000H-B7FFFH
A8000H-AFFFFH
A0000H-A7FFFH
98000H-9FFFFH
90000H-97FFFH
88000H-8FFFFH
80000H-87FFFH
78000H-7FFFFH
70000H-77FFFH
68000H-6FFFFH
60000H-67FFFH
58000H-5FFFFH
50000H-57FFFH
48000H-4FFFFH
40000H-47FFFH
38000H-3FFFFH
30000H-37FFFH
28000H-2FFFFH
20000H-27FFFH
1C000H-1FFFFH
18000H-1BFFFH
14000H-17FFFH
10000H-13FFFH
0C000H-0FFFFH
08000H-0BFFFH
04000H-07FFFH
00000H-03FFFH
A19-A0 (Word Mode)
32Kword MAIN BLOCK 35 32Kword MAIN BLOCK 34 32Kword MAIN BLOCK 33 32Kword MAIN BLOCK 32 32Kword MAIN BLOCK 31 32Kword MAIN BLOCK 30 32Kword MAIN BLOCK 29 32Kword MAIN BLOCK 28 32Kword MAIN BLOCK 27 32Kword MAIN BLOCK 26 32Kword MAIN BLOCK 25 32Kword MAIN BLOCK 24 32Kword MAIN BLOCK 23 32Kword MAIN BLOCK 22 32Kword MAIN BLOCK 21
32Kword MAIN BLOCK 20 32Kword MAIN BLOCK 19 32Kword MAIN BLOCK 18 32Kword MAIN BLOCK 17 32Kword MAIN BLOCK 16 32Kword MAIN BLOCK 15 32Kword MAIN BLOCK 14 32Kword MAIN BLOCK 13
32Kword MAIN BLOCK 12 32Kword MAIN BLOCK 11 32Kword MAIN BLOCK 10 32Kword MAIN BLOCK 9 32Kword MAIN BLOCK 8
16Kword PARAMETER BLOCK 7 16Kword PARAMETER BLOCK 6
16Kword PARAMETER BLOCK 5
16Kword PARAMETER BLOCK 4 16Kword PARAMETER BLOCK 3 16Kword PARAMETER BLOCK 2 16Kword PARAMETER BLOCK 1
16Kword BOOT BLOCK 0
Flash Memory of M6MGB160S4BVP Memory Map
x8 ( Bytemode)
1F8000H-1FFFFFH
1F0000H-1F7FFFH
1E8000H-1EFFFFH
1E0000H-1E7FFFH
1D8000H-1DFFFFH
1D0000H-1D7FFFH
1C8000H-1CFFFFH
1C0000H-1C7FFFH
1B0000H-1BFFFFH
1A0000H-1AFFFFH
190000H-19FFFFH
180000H-18FFFFH
170000H-17FFFFH
BANK(II)
160000H-16FFFFH
150000H-15FFFFH
140000H-14FFFFH
130000H-13FFFFH
120000H-12FFFFH
110000H-11FFFFH
100000H-10FFFFH
F0000H-FFFFFH
E0000H-EFFFFH
D0000H-DFFFFH
C0000H-CFFFFH
B0000H-BFFFFH
A0000H-AFFFFH
90000H-9FFFFH
80000H-8FFFFH
70000H-7FFFFH
60000H-6FFFFH
50000H-5FFFFH
BANK(I)
40000H-4FFFFH
30000H-3FFFFH
20000H-2FFFFH
10000H-1FFFFH
00000H-0FFFFH
A19-A-1 (Byte Mode)
x16 ( Wordmode)
FC000H-FFFFFH
F8000H-FBFFFH
F4000H-F7FFFH
F0000H-F3FFFH
EC000H-EFFFFH
E8000H-EBFFFH
E4000H-E7FFFH
E0000H-E3FFFH
D8000H-DFFFFH
D0000H-D7FFFH
C8000H-CFFFFH
C0000H-C7FFFH
B8000H-BFFFFH
B0000H-B7FFFH
A8000H-AFFFFH
A0000H-A7FFFH
98000H-9FFFFH
90000H-97FFFH
88000H-8FFFFH
80000H-87FFFH
78000H-7FFFFH
70000H-77FFFH
68000H-6FFFFH
60000H-67FFFH
58000H-5FFFFH
50000H-57FFFH
48000H-4FFFFH
40000H-47FFFH
38000H-3FFFFH
30000H-37FFFH
28000H-2FFFFH
20000H-27FFFH
18000H-1FFFFH
10000H-17FFFH
08000H-0FFFFH
00000H-07FFFH
A19-A0 (Word Mode)
16Kword BOOT BLOCK 35
16Kword PARAMETER BLOCK 34
16Kword PARAMETER BLOCK 33 16Kword PARAMETER BLOCK 32
16Kword PARAMETER BLOCK 31 16Kword PARAMETER BLOCK 30
16Kword PARAMETER BLOCK 29 16Kword PARAMETER BLOCK 28
32Kword MAIN BLOCK 27 32Kword MAIN BLOCK 26 32Kword MAIN BLOCK 25 32Kword MAIN BLOCK 24 32Kword MAIN BLOCK 23 32Kword MAIN BLOCK 22 32Kword MAIN BLOCK 21 32Kword MAIN BLOCK 20
32Kword MAIN BLOCK 19 32Kword MAIN BLOCK 18 32Kword MAIN BLOCK 17 32Kword MAIN BLOCK 16 32Kword MAIN BLOCK 15 32Kword MAIN BLOCK 14 32Kword MAIN BLOCK 13 32Kword MAIN BLOCK 12 32Kword MAIN BLOCK 11 32Kword MAIN BLOCK 10 32Kword MAIN BLOCK 9 32Kword MAIN BLOCK 8 32Kword MAIN BLOCK 7 32Kword MAIN BLOCK 6 32Kword MAIN BLOCK 5
32Kword MAIN BLOCK 4 32Kword MAIN BLOCK 3 32Kword MAIN BLOCK 2 32Kword MAIN BLOCK 1
32Kword MAIN BLOCK 0
Flash Memory of M6MGT160S4BVP Memory Map
BANK(I)
BANK(II)
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Sep. 1999 , Rev.2.0
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16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
4,194,304-BIT (262,144WORD BY 16-BIT / 524,288-WORD BY 8-BIT) CMOS SRAM
BUS OPERATIONS
Bus Operations for Word-Wide Mode
MITSUBISHI LSIs
M6MGB/T160S4BVP
3.3V-ONLY FLASH MEMORY &
Stacked-MCP (Multi Chip Package)
Mode
Read
Pins
Array Status Register
F-CE# OE# WE#
V VIL
Lock Bit Status VIL VIL
Output disable Stand by
Write
Identifier Code
Program Erase Others
VIL VIL VIH VIL VIL V
Deep Power Down
Bus Operations for Byte-Wide Mode
Mode
Array
Read
Status Register Lock Bit Status
Identifier Code Output disable Stand by
Program Write
Erase
Others Deep Power Down
Pins
F-CE# OE# WE#
VIL VIL V VIL VIL VIH VIL VIL V
IL
VIL VIL
VIL VIH
V VIH
IL VIH
X
VIL VIL
IL VIL
VIL VIH
V VIH
IL
VIH
X
DQ
RP#
VIH VIH VIH VIH VIH
2)
X
IH
X
V
IL
VIL
IL
V
X
X Hi-Z
V VIH VIH VIH VIH VIH VIH VIH V VIL
IH
Status Register Data
Lock Bit Data (DQ6)X
Command/Data in
IH
RP#
VIH VIH VIH VIH
VIH
2)
X
IH
X
V
IL
VIL
IL
V
X
X Hi-Z
V VIH VIH VIH VIH VIH VIH VIH V VIL
IH
Status Register Data
Lock Bit Data (DQ6)
Command/Data in
IH
0-15
Data out
Identifier Code
Hi-Z Hi-Z
Command
DQ
0-7
Data out
Identifier Code
Hi-Z Hi-Z
Command Command
RY/BY#
OH (Hi-Z)
V
X
V
OH (Hi-Z)
X X X X XCommand
VOH (Hi-Z)
RY/BY# V
OH (Hi-Z)
1)
X X
VOH (Hi-Z)
X X X X X
VOH (Hi-Z)
1)
1) X at RY/BY# is VOL or VOH(Hi-Z). *The RY/BY# is an open drain output pin and indicates status of the internal WSM. When low,it indicates that the WSM is Busy performing an operation. A pull-up resistor of 10K-100K Ohms is required to allow the RY/BY# signal to transition high indicating a Ready WSM condition.
2) X can be V
IH or VIL for control pins.
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Sep. 1999 , Rev.2.0
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16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
SOFTWARE COMMAND DEFINITION
Command List
MITSUBISHI LSIs
M6MGB/T160S4BVP
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144WORD BY 16-BIT / 524,288-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
1st bus cycle
Command
Mode
Address
Read Array Device Identifier Read Status Register Clear Status Register Clear Page Buffer Byte/Word Program Page Program
5)
7)
Single Data Load to Page Buffer Page Buffer to Flash
5)
Block Erase / Confirm Suspend Resume Read Lock Bit Status Lock Bit Program / Confirm Erase All Unlocked Blocks
1) In the word-wide version(Byte#=H), upper byte data (DQ8-DQ15) is ignored.
2) IA=ID Code Address : A0=VIL (Manufacturer's Code) : A0=VIH (Device Code), ID=ID Code
3) Bank = Bank Address (Bank(I) or Bank(II)) : A19-A17.
4) SRD = Status Register Data
5) Byte/Word Program, Single Data Load and Page Buffer to Flash Command is valid for only Bank(I).
6) WA = Write Address,WD = Write Data
7) WA0,WAn=Write Address, WD0,WDn=Write Data. Byte Mode : Write Address and Write Data must be provided sequentially from 00H to FFH for A6-A0,A-1. Page size is 256Byte (256byte x 8bit), and also A19-A7(Block Address, Page Address) must be valid. Word Mode : Write Address and Write Data must be provided sequentially from 00H to 7FH for A6-A0. Page size is 128word (128word x 16bit). and also A19-A7(Block Address, Page Address) must be valid.
8) WA = Write Address : Upper page address, A19-A7(Block Address, Page Address) must be valid.
9) BA = Block Address : BA = Block Address : A19-A14(Bank1) A19-A15(Bank2)
10) DQ6 provides Block Lock Status, DQ6 = 1 : Block Unlock, DQ6 = 0 : Block Locked.
Write
Bank
XWrite
XWrite Write 40H Write Write 41H
5)
Write Write Write Write Write Write Write Write
Bank(I)
Bank
Bank(I) Bank(I)
Bank
Bank Bank
X
Bank
X
3)
5)
5)
5)
Data
(DQ7-0)
(DQ15-0)
FFHXWrite
90HX 70HWrite 50H 55H
74H
0EH
20H B0H D0H
71H
77H A7H
1)
2nd bus cycle
Data
AddressMode
IARead
Bank
(DQ7-0)
(DQ15-0)
2)
ID
SRDRead
Write X D0H
6)
WD
7)
WD0
WDWA
8)
D0H
9)
D0H
DQ6 D0H
Write Write Write Write
Read Write Write
WA
WA BA
BA BA
XD0H
3rd ~257th bus cycles (Byte Mode) 3rd ~129th bus cycles (Word Mode)
AddressMode
2)
4)
1)
6)
7)
1)
1)
10)
1)
1)
WAnWA0
Data
(DQ7-0)
(DQ15-0)
7)
7)
WDnWrite
8
Sep. 1999 , Rev.2.0
Page 9
MITSUBISHI LSIs
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144WORD BY 16-BIT / 524,288-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
BLOCK LOCKING
Lock
WP#
RP#
VIL
VIH
1) DQ6 provides Lock Status of each block after writing the Read Lock Status command (71H). F-WP# pins must not be switched during performing Erase / Write operations or WSM Busy (WSMS = 0).
2) Erase/Write command for locked blocks is aborted. At this time read mode is not array read mode but status read mode and 00B0H is read. Please issue Clear Status Register command plus Read Array command to change the mode from status read mode to array read mode.
X
VIL
VIH
Bit
(Internally)
X
0 1
X
Unlocked Unlocked Unlocked Unlocked
STATUS REGISTER
Symbol
SR.7 SR.6 SR.5 SR.4 SR.3 SR.2 SR.1 SR.0
*The F-RY/BY# is an open drain output pin and indicates status of the internal WSM. When low,it indicates that the WSM is Busy performing an operation. A pull-up resistor of 10K-100K Ohms is required to allow the F-RY/BY# signal to transition high indicating a Ready WSM condition.
*DQ3 indicates the block status after the page programming, byte/word programming and page buffer to flash. When DQ3 is "1", the page has the over-programed cell . If over-program occurs, the device is block fail. However if DQ3 is "1", please try the block erase to the block. The block may revive.
(DQ (DQ (DQ (DQ (DQ (DQ (DQ1) (DQ
7)
6)
5)
4)
3)
2)
0)
Status
Write State Machine Status Suspend Status Erase Status Program Status Block Status after Program
Reserved Reserved Reserved
Write Protection Provided
BANK(I)
Boot Parameter Data Locked Locked Locked
Locked Locked Locked Locked Locked Locked
Unlocked Unlocked
BANK(II)
Lock Bit
Locked
Note
Deep Power Down Mode
All Blocks Unlocked
Definition
"1" "0"
Ready Busy
Suspended Operation in Progress / Completed
Error Successful Error Successful Error Successful
--
--
-
-
9
Sep. 1999 , Rev.2.0
Page 10
DEVICE IDENTIFIER CODE
MITSUBISHI LSIs
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144WORD BY 16-BIT / 524,288-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
Code
Pins
Manufacturer Code Device Code (-T160S4BVP) Device Code (-B160S4BVP)
In the word-wide mode, the upper data(D15-8) is "0".
A0
VIL
VIH 001
IH
V
DQ7
0
0
10
DQ5DQ6
DQ4
0
DQ3
1 1 1
0
DQ2
1 0 0
DQ1
1 0 0
0 0 0
DQ
0
0 0 1
ABSOLUTE MAXIMUM RATINGS
Symbol
F-V
cc
V
I1
Ta Tbs
stg
T
OUT
I
1) Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input/output pins is F-VCC+0.5V which, during transitions, may overshoot to F-VCC+1.5V for periods <20ns.
Flash Vcc voltage
All input or output voltage Ambient temperature Temperature under bias Storage temperature
Output short circuit current
Parameter
1)
Conditions
With respect to Ground
Min Max
4.6-0.2
-0.6 4.6
-20
85
-50 95
-65 125
Unit
V V
°C °C °C
mA100
CAPACITANCE
Symbol
C
IN
COUT
Note: The value of common pins to Flash Memory is the sum of Flash Memory and SRAM.
Input capacitance (Address, Control Pins)
Output capacitance
Parameter
Test conditions
Ta = 25°C, f = 1MHz, V
in = Vout = 0V
Min
Limits
Typ
Max
8
12
Hex. Data
1CH A0H
A1H
Unit
pF
pF
DC ELECTRICAL CHARACTERISTICS (Ta = -20~ 85°C, F-Vcc = 2.7V ~ 3.6V, unless otherwise noted)
Symbol Parameter
ILI Input leakage current mA ILO
SB1
I I
SB2 5
Output leakage current mA
F-V
CC standby current
F-VCC deep powerdown current
CC1
CC2 15 mAF-VCC Write current for Word or Byte
I
F-VCC read current for Word or Byte
ICC3 F-VCC program current mA35 ICC4 F-VCC erase current mA35
I
CC5
IL Input low voltage – 0.5
F-VCC suspend current
0V£V 0V£VOUT£F-VCC
F-VCC = 3.6V, VIN=VIL/VIH, F-CE# = F-RP# =F-WP# = VIH
F-V
CC = 3.6V, VIN=GND or F-VCC,
F-CE# = F-RP# = F-WP# = F-V F-VCC = 3.6V, VIN=VIL/VIH, F-RP# = VIL
F-VCC = 3.6V, VIN=GND or VCC, F-RP# =GND±0.3V
F-V
CC = 3.6V, VIN=VIL/VIH, F-CE# = VIL,
F-RP#=OE#=V
F-V
CC = 3.6V,VIN=VIL/VIH, F-CE# =WE#= VIL,
F-RP#=OE#=V
F-VCC = 3.6V, VIN=VIL/VIH, F-CE# = F-RP# =F-WP# = VIH F-VCC = 3.6V, VIN=VIL/VIH, F-CE# = F-RP# =F-WP# = VIH F-VCC = 3.6V, VIN=VIL/VIH, F-CE# = F-RP# =F-WP# = VIH
Test conditions Unit
IN£F-VCC
CC±0.3V
5MHz
IH, IOUT = 0mA
IH
1MHz
VIH Input high voltage V2.0
OL Output low voltage VIOL = 4.0mA 0.45
V V
OH1 IOH = –2.0mA
V
OH2 IOH = –100mA
Output high voltage
0.85(F-Vcc) F-Vcc–0.4
VLKO Low VCC Lock-Out voltage 2) 1.5 2.2 V
All currents are in RMS unless otherwise noted.
1) Typical values at F-Vcc=3.3V, Ta=25°C
2) To protect against initiation of write cycle during Vcc power-up/ down, a write cycle is locked out for Vcc less than VLKO.
If Vcc is less than VLKO, Write State Machine is reset to read mode. When the Write State Machine is in Busy state, if Vcc is less than VLKO, the alteration of memory contents may occur.
Min
Limits
8 2
MaxTyp1)
±2.0
±11
5
15
4
200
0.8V
F-Vcc+0.5
mAI
mA20050 mA0.1
mA155ISB3 mA0.1ISB4
mA
V
V V
10
Sep. 1999 , Rev.2.0
Page 11
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
4,194,304-BIT (262,144WORD BY 16-BIT / 524,288-WORD BY 8-BIT) CMOS SRAM
AC ELECTRICAL CHARACTERISTICS (Ta = -20 ~85°C)
Read-Only Mode
Symbol
tRC Read cycle timetAVAV ta (AD) Address access timetAVQV ta (CE)
Chip enable access timetELQV
ta (OE) Output enable access timetGLQV
tCLZ Chip enable to output in low-ZtELQX
tDF(CE)
Chip enable high to output in high ZtEHQZ
tOLZ tGLQX Output enable to output in low-Z
DF(OE) tGHQZ Output enable high to output in high Z
t
t
PHZ
ta(BYTE)
F-RP# low to output high-Z
t
PLQZ
FL/HQV
t
BYTE# access time
tBHZ BYTE# low to output high-ZtFLQZ
OH
t
tOH
tELFL/H
BCD
t tBAD tAVFL/H
tWHGL
OEH
t
t
PS tPHEL
Timing measurements are made under AC waveforms for read operations.
Output hold from F-CE#, OE#, addresses F-CE# low to BYTE# high or low Address to BYTE# high or low OE# hold from WE# high F-RP# recovery to F-CE# low
Parameter
MITSUBISHI LSIs
M6MGB/T160S4BVP
3.3V-ONLY FLASH MEMORY &
Stacked-MCP (Multi Chip Package)
Limits
Speed Item: -90
F-Vcc=2.7~3.6V
MaxMin Typ
90
90 90
30
0
25
0
25
150
90 25
0
5 5
10
150
Unit
ns ns ns ns ns ns ns ns ns
ns ns
ns ns ns ns ns
AC ELECTRICAL CHARACTERISTICS (Ta = -20 ~85°C)
Write Mode (WE# control)
Symbol
tAVAV
tWC tAS tAH tDS tDH
t
RE
tCS tCH tWP tWPH
Write cycle time
tAVWH
Address set-up time
tWHAX
Address hold time
tDVWH
Data set-up time
tWHDX
Data hold time
WHGLtOEH
t
OE# hold from WE# high
-
Latency between Read and Write FFH or 71H
tELWL
Chip enable set-up time
tWHEH
Chip enable hold time
WLWH
t
Write pulse width
tWHWL
Write pulse width high
FL/HWHtBS
t
Byte enable high or low set-up time
tWHFL/HtBH
Byte enable high or low hold time OE# hold to WE# LowtGHWLtGHWL
tBLS
tPHHWH
Block Lock set-up to write enable high
tQVPH
tBLH tDAP
tDAE
tPS
Block Lockhold from valid SRD
tWHRH1
Duration of auto-program operation
tWHRH2
Duration of auto-block erase operation
t
WHRLtWHRL ns
WE# high to RY/BY# low
tPHWL
F-RP# high recovery to write enable low
Parameter
Limits Speed Item: -90 F-Vcc=2.7~3.6V
Min Typ
90 50
0
50
0
10 30
0
0 60 30 50
90
0
90
0
40
150
Unit
Max
ns ns ns ns
ns ns ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
80
600
ms ms
90
ns
11
Read timing parameters during command write operations mode are the same as during read-only operations mode. Typical values at F-Vcc=3.3V, Ta=25°C
Sep. 1999 , Rev.2.0
Page 12
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
4,194,304-BIT (262,144WORD BY 16-BIT / 524,288-WORD BY 8-BIT) CMOS SRAM
AC ELECTRICAL CHARACTERISTICS (Ta = -20 ~ 85°C)
Write Mode (CE# control)
Symbol
tAVAV
tWC tAS tAH tDS tDH
t
RE
tWS tWH tCEP
Write cycle time
tAVWH
Address set-up time
tEHAX
Address hold time
tDVWH
Data set-up time
tEHDX
Data hold time
EHGLtOEH
t
OE# hold from F-CE# high
-
Latency between Read and Write FFH or 71H
tWLEL
Write enable set-up time
tEHWH
Write enable hold time
tELEH
F-CE# pulse width F-CE# pulse width hightEHELtCEPH
FL/HWHtBS
t
tBH
t tBLS tBLH tDAP tDAE
tPS
Read timing parameters during command write operation mode are the same as during read-only operation mode. Typical values at F-Vcc=3.3V, Ta=25°C
Byte enable high or low set-up time
tWHFL/H
Byte enable high or low hold time
GHELtGHEL
OE# hold to F-CE# Low
tPHHEH
Block Lock set-up to write enable high
tQVPH
Block Lockhold from valid SRD
tEHRH1
Duration of auto-program operation
tEHRH2
Duration of auto-block erase operation
EHRLtEHRL
t
F-CE# high to RY/BY# low
PHWL
t
F-RP# high recovery to write enable low
Parameter
MITSUBISHI LSIs
M6MGB/T160S4BVP
3.3V-ONLY FLASH MEMORY &
Stacked-MCP (Multi Chip Package)
Limits
Speed Item: -90
F-Vcc=2.7~3.6V
Min Typ
90 50
0
50
0 10 30
0
0 60 30
50 90
90
0
40
150
Max
4
80
600
90
Unit
ns ns ns ns ns ns ns ns ns
ns ns ns
ns
ns90
ns
ns ms
ms
ns
ns
Erase and Program Performance
Parameter
Block Erase Time Main Block Write Time (Page Mode) Page Write Time
Min
40
1.0
Max
600
1.8
4
80
UnitTyp
ms sec ms
Program Suspend Latency / Erase Suspend Time
Parameter
Program Suspend Latency Erase Suspend Time
Please see page 19.
Min
Typ
Max
15 15
Unit
ms
ms
Vcc Power Up / Down Timing
Symbol UnitTyp
t
VCS
Please see page 12.
During power up/down, by the noise pulses on control pins, the device has possibility of accidental erasure or programming. The device must be protected against initiation of write cycle for memory contents during power up/down. The delay time of min.2msec is always required before read operation or write operation is initiated from the time F-Vcc reaches F-Vccmin during power up/down. By holding F-RP# VIL, the contents of memory is protected during F-Vcc power up/down. During power up, F-RP# must be held VIL for min.2ms from the time F-Vcc reaches F-Vccmin. During power down, F-RP# must be held VIL until Vcc reaches GND. F-RP# doesn't have latch mode ,therefore F-RP# must be held VIH during read operation or erase/program operation.
RP# =V
Parameter
IH set-up time from Vccmin ms
2
MaxMin
12
Sep. 1999 , Rev.2.0
Page 13
MITSUBISHI LSIs
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144WORD BY 16-BIT / 524,288-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
Vcc POWER UP / DOWN TIMING
Read /Write Inhibit
tVCS
F-V
CC
F-RP#
F-CE#
WE#
3.3V
GND
VIH VIL
VIH VIL
VIH VIL
tPS
Read /Write Inhibit
tPS
AC WAVEFORMS FOR READ OPERATION AND TEST CONDITIONS
ADDRESSES
F-CE#
OE#
WE#
DATA
F-RP#
VIH VIL
VIH VIL
VIH VIL
VIH VIL
VOH VOL
VIH VIL
HIGH-Z
tPS
tOEH
ADDRESS VALID
ta (AD)
ta (CE)
ta (OE)
tOLZ
tCLZ
tRC
OUTPUT VALID
tDF(CE)
t
DF(OE)
tOH
tPHZ
HIGH-Z
Read /Write Inhibit
TEST CONDITIONS FOR AC CHARACTERISTICS
Input voltage : V Input rise and fall times : £5ns Reference voltage at timing measurement : 1.5V
Output load : 1TTL gate + CL(30pF) or
IL = 0V, VIH = 3.0V
DUT
1.3V 1N914
3.3kW
C
L =30pF
13
Sep. 1999 , Rev.2.0
Page 14
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
4,194,304-BIT (262,144WORD BY 16-BIT / 524,288-WORD BY 8-BIT) CMOS SRAM
AC WAVEFORMS FOR WRITE FFH or 71H AND READ OPERATION
ADDRESSES
F-CE#
OE#
WE#
DATA
F-RP#
VIH VIL
VIH VIL
VIH VIL
VIH VIL
VOH
HIGH-Z
VOL VIH
VIL
In the case of use F-CE# is Low fixed, it is allowed to define a timming specification of tRE from rising edge of WE# to falling edge of OE#, and valid data is read after spec of tRE+ta(CE). (This is only for FFH,71H program and read)
FFH or 71H
tRE
Valid
tPS
ADDRESS VALID
ta (AD)
ta (CE)
ta (OE)
tOLZ
tCLZ
tRC
OUTPUT VALID
MITSUBISHI LSIs
M6MGB/T160S4BVP
3.3V-ONLY FLASH MEMORY &
Stacked-MCP (Multi Chip Package)
tDF(CE)
tDF(OE)
tOH
HIGH-Z
tPHZ
BYTE AC WAVEFORMS FOR READ OPERATION
ADDRESSES (A
0 - A19,A-1*)
F-CE#
OE#
BYTE#
DATA (D
0 - D7)
DATA (D
8 - D14)
D15 / A-1
VIH VIL
ta(AD)
VIH VIL
VIH VIL
VIH VIL
VIH
HIGH-Z
VIL
VIH
HIGH-Z
VIL
IH
V VIL
When BYTE#=VIH, F-CE#=OE#=VIL , D15/A-1 is output status. At this time, input signal must not be applied.
ta(CE)
tBCD
tBAD
ADDRESS VALID
ta(OE)
ta(BYTE)
tOLZ
tCLZ
A-1
tBAD
OUTPUT VALID
ta(BYTE)
ADDRESS VALID
VALID
tBHZ
VALID
tDF(CE)
tDF(OE)
tOH
VALID
ta(AD)
A-1D15
14
Sep. 1999 , Rev.2.0
Page 15
MITSUBISHI LSIs
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144WORD BY 16-BIT / 524,288-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
AC WAVEFORMS FOR PAGE PROGRAM OPERATION (WE# control)
The other bank
tOEH
address
VALID
VALID
tAH
ta(CE)
tDH
ta(OE)
DOUT
ADDRESS VALID
01H~FEH 01H~7EH
tGHWL
DIN
A19~A7
BYTE#=VIL (A6~A-1)
BYTE#=VIH (A6 ~A0)
F-CE#
OE#
WE#
DATA
F-RY/BY#
BYTE#
F-RP#
F-WP#
VIH
BANK ADDRESS
VIL VIH
VIL
VIH VIL
tCS tCH
VIH VIL
VIH VIL
VIH VIL
VOH VOL
VIH
IL
V
tPS
VIH VIL
VIH VIL
VALID
tWC
tWP
41H DIN
VALID
00H 00H
tAS
tWPH
tDS
tBS
tBLS
FFH
7FH
DIN
PROGRAM
tOEH tDAP
tWHRL
READ STATUS
REGISTER
BANK ADDRESS VALID
tBH
tBLH
ta(CE)
ta(OE)
SRD
WRITE READ
ARRAY COMMAND
FFH
AC WAVEFORMS FOR PAGE PROGRAM OPERATION (F-CE# control)
The other bank
address
VALIDVALID
VALID
tAH
ta(CE)
ta(OE)
tOEH tGHEL
tDH
DOUT
ADDRESS VALID
01H~FEH 01H~7EH00H
DIN SRDDIN
A19~A7
BYTE#=VIL (A6~A-1)
BYTE#=VIH (A6 ~A0)
F-CE#
OE#
WE#
DATA
F-RY/BY#
BYTE#
F-RP#
F-WP#
VIH VIL
VIH VIL
VIH VIL
VIH VIL
VIH VIL
VIH VIL
VOH VOL
VIH
IL
V VIH
VIL
VIH VIL
BANK ADDRESS
VALID
tWC
tCEP
tWS tWH
tPS
00H
tAS
tCEPH
tDS
41H DIN
tBS
tBLS
FFH
7FH
PROGRAM
tOEH tDAP
tEHRL
tBH
READ STATUS
REGISTER
BANK ADDRESS VALID
ARRAY COMMAND
ta(CE)
ta(OE)
tBLH
WRITE READ
FFH
15
Sep. 1999 , Rev.2.0
Page 16
MITSUBISHI LSIs
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144WORD BY 16-BIT / 524,288-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
AC WAVEFORMS FOR BYTE / WORD PROGRAM OPERATION (WE# control) (to only BANK(I))
ADDR
F-CE#
OE#
WE#
DATA
F-RY/BY#
BYTE#
F-RP#
F-WP#
VIH VIL
VIH VIL VIH VIL VIH VIL VIH
V VIH V VIH
V
VIH VIL VIH VIL
WRITE READ ARRAY COMMAND
ta(CE)
ta(OE)
BANK ADDRESS
tCS
VALID
ADDRESS
VALID
tAStWC
tCH
tWP
tAH
PROGRAM
tOEH
READ STATUS REGISTER
BANK(I) ADDRESS VALID
tWPH
tDS
IL
40H DIN
SRD FFH
tDH
IL
IL
tPS
tBS
tWHRL
tBH
tDAP
tBLS
tBLH
AC WAVEFORMS FOR BYTE / WORD PROGRAM OPERATION (F-CE# control) (to only BANK(I))
WRITE READ ARRAY COMMAND
ta(CE)
ta(OE)
SRD FFH
tBLH
ADDR
F-CE#
OE#
WE#
DATA
F-RY/BY#
BYTE#
F-RP#
F-WP#
VIH VIL VIH VIL VIH VIL VIH VIL VIH
V VIH
VIL VIH V
VIH VIL VIH VIL
READ STATUS REGISTER
BANK(I) ADDRESS VALID
BANK ADDRESS
tWS
VALID
ADDRESS
VALID
tAStWC
tCEP
tWH
PROGRAM
tAH
tOEH
tDS
IL
40H DIN
tDH
tEHRL
tBS
IL
tPS
tBH
tDAP
tBLS
16
Sep. 1999 , Rev.2.0
Page 17
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
4,194,304-BIT (262,144WORD BY 16-BIT / 524,288-WORD BY 8-BIT) CMOS SRAM
AC WAVEFORMS FOR ERASE OPERATIONS (WE# control)
ADDRESSES
F-CE#
OE#
WE#
DATA
F-RY/BY#
BYTE#
VIH VIL
VIH VIL
VIH VIL
VIH VIL
VIH VIL
VOH VOL VIH
IL
V
BANK ADDRESS
VALID
ADDRESS VALID
tWC
tCS tCH
tWPH
tWP
20H D0H
tBS
tAS
tDS
tAH
tDH
tOEH
tDAE
tWHRL
MITSUBISHI LSIs
M6MGB/T160S4BVP
3.3V-ONLY FLASH MEMORY &
Stacked-MCP (Multi Chip Package)
ERASE
tBH
READ STATUS
REGISTER
BANK ADDRESS VALID
ta(CE)
ta(OE)
WRITE READ
ARRAY COMMAND
FFHSRD
F-RP#
F-WP#
VIH VIL
VIH VIL
tBLS
AC WAVEFORMS FOR ERASE OPERATIONS (F-CE# control)
tPS
ADDRESSES
F-CE#
OE#
WE#
DATA
F-RY/BY#
BYTE#
VIH VIL
VIH VIL
VIH VIL
VIH VIL
VIH VIL
VOH VOL
VIH
V
IL
BANK ADDRESS
VALID
tWC
tCEP
tWS
tWH
20H D0H
tBS
ADDRESS VALID
tAS
tCEPH
tDS
tAH
tDH
tOEH
tDAE
tEHRL
ERASE
tBH
tBLH
READ STATUS
REGISTER
BANK ADDRESS VALID
ta(CE)
ta(OE)
WRITE READ
ARRAY COMMAND
FFHSRD
F-RP#
F-WP#
17
VIH
VIL
VIH VIL
tPS
tBLS
tBLH
Sep. 1999 , Rev.2.0
Page 18
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144WORD BY 16-BIT / 524,288-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
AC WAVEFORMS FOR PAGE PROGRAM OPERATION WITH BGO (WE# control)
Change Bank Address
PROGRAM DATA TO ONE BANK
A19~A7
BYTE#=VIL (A6~A-1)
BYTE#=VIH (A6 ~A0)
F-CE#
OE#
WE#
DATA
F-RY/BY#
VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL
BANK ADDRESS
tCS
VALID
tWC tAS
tCH
tWP
tWPH
41H DIN
00H 00H
01H~FEH 01H~7EH
tAH
tDS
tDH
ADDRESS VALID
FFH 7FH
tOEH
DIN DIN SRD
tWHRL
MITSUBISHI LSIs
ARRAY READ FROM THE OTHER BANK WITH BGO
VALID VALID
VALID VALID
ta(CE)
ta(OE)
DOUT
DOUT
AC WAVEFORMS FOR PAGE PROGRAM OPERATION WITH BGO (F-CE# control)
Change Bank Address
PROGRAM DATA TO ONE BANK
A19~A7
BYTE#=VIL (A6~A-1)
BYTE#=VIH (A6 ~A0)
F-CE#
OE#
WE#
DATA
F-RY/BY#
VIH VIL VIH VIL
VIH VIL
VIH VIL VIH VIL VIH
VIL VIH VIL
BANK ADDRESS
tCEP
tWS
VALID
tWC
tCEPH
41H DIN
tAS
tCH
00H 00H
01H~FEH 01H~7EH
tAH
tDS
tDH
ADDRESS VALID
FFH 7FH
tOEH
DIN DIN SRD
tEHRL
ARRAY READ FROM THE OTHER BANK WITH BGO
VALID VALID
VALID VALID
ta(CE)
ta(OE)
DOUT
DOUT
18
Sep. 1999 , Rev.2.0
Page 19
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144WORD BY 16-BIT / 524,288-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
AC WAVEFORMS FOR BYTE / WORD PROGRAM OPERATION WITH BGO (WE# control)
Change Bank Address
ARRAY READ FROM BANK(II) WITH BGO
VALID VALID
VALID VALID
ta(CE)
ta(OE)
DOUT
A19~A7
BYTE#=VIL (A6~A-1)
BYTE#=VIH (A6 ~A0)
F-CE#
OE#
WE#
DATA
F-RY/BY#
VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH
VIL VIH VIL
BANK ADDRESS
tCS
PROGRAM DATA TO BANK(I)
VALID
VALID
tWC tAS
tCH
tWP
tWPH
40H DIN
ADDRESS VALID
tAH
tOEH
tDS
tDH
tWHRL
READ STATUS
REGISTER
SRD
MITSUBISHI LSIs
DOUT
AC WAVEFORMS FOR BYTE / WORD PROGRAM OPERATION WITH BGO (F-CE# control)
Change Bank Address
ARRAY READ FROM BANK(II) WITH BGO
VALID VALID
VALID VALID
A19~A7
BYTE#=VIL (A6~A-1)
BYTE#=VIH (A6 ~A0)
F-CE#
OE#
WE#
DATA
F-RY/BY#
VIH VIL VIH VIL
VIH VIL
VIH VIL VIH VIL VIH VIL VIH VIL
BANK ADDRESS
tCEP
tWS
VALID
tWC
tCEPH
40H
PROGRAM DATA TO BANK(I)
VALID
tAS
tOEH
tCH
tDS
DIN
tDH
READ STATUS
REGISTER
ADDRESS VALID
SRD
tEHRL
ta(CE)
ta(OE)
DOUT
DOUT
19
Sep. 1999 , Rev.2.0
Page 20
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144WORD BY 16-BIT / 524,288-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
AC WAVEFORMS FOR BLOCK ERASE OPERATION WITH BGO (WE# control)
Change Bank Address
READ STATUS
ADDRESS VALID
tOEH
tDS
tDH
tWHRL
REGISTER
tAH
SRD
ADDRESSES
F-CE#
OE#
WE#
DATA
F-RY/BY#
VIH VIL
VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL
BANK ADDRESS
tCS
BLOCK ERASE IN ONE BANK
VALID
tWC tAS
tCH
tWP
tWPH
20H D0H
MITSUBISHI LSIs
ARRAY READ FROM THE OTHER BANK WITH BGO
VALID VALID
ta(CE)
ta(OE)
DOUT
DOUT
AC WAVEFORMS FOR BLOCK ERASE OPERATION WITH BGO (F-CE# control)
Change Bank Address
ADDRESSES
F-CE#
OE#
WE#
DATA
F-RY/BY#
VIH VIL
VIH VIL
VIH VIL VIH VIL VIH
VIL VIH VIL
BANK ADDRESS
tCEP
tWS
BLOCK ERASE IN ONE BANK
VALID
tWC
tAS
tCEPH
tCH
20H D0H DOUTSRD
READ STATUS
ADDRESS VALID
tOEH
tDS
tDH
REGISTER
tAH
tEHRL
READ DATA FROM THE OTHER BANK WITH BGO
VALID VALID
ta(CE)
ta(OE)
DOUT
20
Sep. 1999 , Rev.2.0
Page 21
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
4,194,304-BIT (262,144WORD BY 16-BIT / 524,288-WORD BY 8-BIT) CMOS SRAM
AC WAVEFORMS FOR SUSPEND OPERATION (WE# control)
ADDRESSES
F-CE#
OE#
WE#
DATA
VIH VIL
VIH VIL
VIH VIL
VIH VIL
VIH VIL
BANK ADDRESS VALID
tAS
tCS
tWP
B0H
tAH
tCH
tOEH
Program Suspend Latency
MITSUBISHI LSIs
M6MGB/T160S4BVP
3.3V-ONLY FLASH MEMORY &
Stacked-MCP (Multi Chip Package)
READ STATUS
REGISTER
BANK ADDRESS VALID
ta(CE)
ta(OE)
S.R.6,7=1
VALID SRD
F-RY/BY#
F-RP#
F-WP#
VOH VOL
VIH VIL
VIH VIL
tBLS
AC WAVEFORMS FOR SUSPEND OPERATION (F-CE# control)
ADDRESSES
F-CE#
OE#
WE#
DATA
VIH VIL
VIH VIL
VIH VIL
VIH VIL
VIH VIL
BANK ADDRESS VALID
tAS
tCEP
tWS
B0H
tAH
tOEH
Program Suspend Latency
tWH
tBLH
READ STATUS
REGISTER
BANK ADDRESS VALID
ta(CE)
ta(OE)
S.R.6,7=1
VALID SRD
F-RY/BY#
F-RP#
F-WP#
21
VOH VOL
VIH VIL
VIH VIL
tBLS
tBLH
Sep. 1999 , Rev.2.0
Page 22
MITSUBISHI LSIs
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144WORD BY 16-BIT / 524,288-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
FULL STATUS CHECK PROCEDURE
STATUS REGISTER
READ
SR.4 =1
and
SR.5 =1
?
NO
SR.5 = 0 ?
YES
SR.4 = 0 ?
YES
SR.3 = 0 ?
YES
SUCCESSFUL
(BLOCK ERASE, PROGRAM)
COMMAND SEQUENCE ERROR
YES
NO
NO
NO
BLOCK ERASE ERROR
PROGRAM ERROR
(PAGE, LOCK BIT)
PROGRAM ERROR
(BLOCK)
LOCK BIT PROGRAM FLOW CHART
START
WRITE 77H
WRITE D0H
BLOCK ADDRESS
SR.7 = 1 ?
SR.4 = 0 ?
LOCK BIT PROGRAM
SUCCESSFUL
YES
YES
NO
NO
LOCK BIT PROGRAM
FAILED
BYTE PROGRAM FLOW CHART
START
WRITE 40H
WRITE
ADDRESS , DATA
STATUS REGISTER
READ
SR.7 = 1 ?
FULL STATUS CHECK
IF DESIRED
PAGE PROGRAM
COMPLETED
* Byte/Word program is admitted to only BANK(I).
NO
YES
WRITE B0H ?
YES
SUSPEND LOOP
WRITE D0H
YES
NO
PAGE PROGRAM FLOW CHART
START
WRITE 41H
n = 0
WRITE
ADDRESS n, DATA n
n = FFH ?
or
n = 7FH ?
STATUS REGISTER
READ
SR.7 = 1 ?
YES
YES
NO
NO
WRITE B0H ?
n = n+1
NO
YES
22
FULL STATUS CHECK
IF DESIRED
PAGE PROGRAM
COMPLETED
SUSPEND LOOP
WRITE D0H
YES
Sep. 1999 , Rev.2.0
Page 23
CLEAR PAGE BUFFER
START
MITSUBISHI LSIs
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144WORD BY 16-BIT / 524,288-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
SUSPEND / RESUME FLOW CHART
START
WRITE 55H
WRITE D0H
PAGE BUFFER CLEAR
COMPLETED
SINGLE DATA LOAD TO PAGE BUFFER
START
WRITE 74H
WRITE
ADDRESS , DATA
DONE
LOADING?
NO
WRITE B0H
STATUS REGISTER
READ
SR.7 = 1?
YES
SR.6 =1?
YES
WRITE FFH
READ ARRAY DATA
DONE
READING ?
YES
WRITE D0H
NO
NO
NO
SUSPEND
PROGRAM / ERASE
RESUME
COMPLETED
YES
SINGLE DATA LOAD
TO PAGE BUFFER
COMPLETED
PAGE BUFFER TO FLASH
START
WRITE 0EH
WRITE D0H
PAGE ADDRESS
STATUS REGISTER
READ
SR.7 = 1 ?
FULL STATUS CHECK
IF DESIRED
PAGE BUFFER TO FLASH
COMPLETED
NO
WRITE B0H ?
YES
SUSPEND LOOP
WRITE D0H
YES
NO
OPERATION
RESUMED
* The bank address is required when writing this command. Also, there is no need to suspend the erase or program operation when reading data from the other bank. Please use BGO function.
BLOCK ERASE FLOW CHART
START
WRITE 20H
WRITE D0H
BLOCK ADDRESS
STATUS REGISTER
READ
SR.7 = 1 ?
YES
FULL STATUS CHECK
IF DESIRED
BLOCK ERASE
COMPLETED
NO
WRITE B0H ?
SUSPEND LOOP
WRITE D0H
NO
YES
YES
23
Sep. 1999 , Rev.2.0
Page 24
24
OPERATION STATUS and EFFECTIVE COMMAND
Read/Standby State
Setup State
Clear
Page Buffer
Setup
Clear
Status Register
55H
Single Data Load
to Page Buffer
Setup
74H
Ready
50H
D0H
Page Buffer to Flash
WD
Setup
OTHER
Internal State
90H
Read
Device Identifier
90H
FFH
0EH
Page Program
Setup
D0H
Status Register
70H
71H
71H
71H
FFH
Status Register
70H
90H
FFH
Read
70H
Read Array
41H 77H
40H
Byte Program
Setup
WDi i=0-255
WD
D0H
Program &
Verify
Read
D0H
Read
Lock Status
Lock Bit Program
Setup
OTHER
B0H
B0H D0H
20H
Block Erase
Setup
Erase &
Verify
Read
Status Register
A7H
Erase All Unlocked
OTHER OTHER
D0HD0H
Blocks Setup
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
4,194,304-BIT (262,144WORD BY 16-BIT / 524,288-WORD BY 8-BIT) CMOS SRAM
3.3V-ONLY FLASH MEMORY &
Stacked-MCP (Multi Chip Package)
M6MGB/T160S4BVP
Sep. 1999 , Rev.2.0
Change Bank Address
Read State with BGO
Read Array
(From The Other Bank)
Change Bank Address
Suspend State
Read
Status Register
70H
FFH
Read Array
70H
MITSUBISHI LSIs
Page 25
2. SRAM
MITSUBISHI LSIs
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144WORD BY 16-BIT / 524,288-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
The SRAM of M6MGB/T160S4BVP is organized as 262,144-word by 16-bit/ 524,288-word by 8-bit. These devices operate on a single +2.7~3.6V powersupply, and are directly TTL compatible to both input and output. Its fully static circuit needs no clocks and no refresh, and makes it useful. The operation mode are determined by a combination of the device control inputs BYTE#, S-CE , WE# and OE#. Each mode is summarized in the function table. A write operation is executed whenever the low level WE# overlaps with the high level S-CE. The address(A-1~A17:byte mode, A0~A17:word mode) must be set up before the write cycle and must be stable during the entire cycle. A read operation is executed by setting WE# at a high level and OE# at a low level while S-CE are in an active state(S-CE=H).
FUNCTION TABLE
S-CE
L H H H H H H
BYTE#
WE#
OE#
X High-Z
XX
H H Read Dout ActiveL H Active
H H High-Z L L Write Din ActiveX L
H L
H
Mode
Non selection
XLH Din Active
Write
Read
L
H
When setting BYTE# at the low level and other pins are in anactive stage , lower-byte I/O are in a selesctable mode in whichboth reading and writing are enabled, and upper-byte are in anon-selectable mode. When setting S-CE at a low level,the chips are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in ahigh-impedance state, allowing OR-tie with other chips and memory expansion by S-CE. The power supply current is reduced as low as 0.3mA(25 C,typical), and the memory data can be held at +2V powersupply, enabling battery back-up operation during power failure or power-down operation in the non-selected mode.
DQ0~7
Dout
DQ8~15 Icc
High-Z Standby
Din
Dout High-Z High-Z High-Z
High-Z
Active ActiveHigh-Z
25
Sep. 1999 , Rev.2.0
Page 26
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
4,194,304-BIT (262,144WORD BY 16-BIT / 524,288-WORD BY 8-BIT) CMOS SRAM
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter
S-V
V VO Pd
Ta
Supply voltage
cc
Input voltage
I
Output voltage
Power dissipation
Operating temperature
Conditions
With respect to GND With respect to GND With respect to GND
Ta=25 C W-version
MITSUBISHI LSIs
M6MGB/T160S4BVP
3.3V-ONLY FLASH MEMORY &
Stacked-MCP (Multi Chip Package)
Ratings
-0.5* ~ +4.6
-0.5
* ~ S-Vcc + 0.5
0 ~ S-Vcc
700
- 20 ~ +85
Units
V
mW
C
Tstg
Storage temperature
DC ELECTRICAL CHARACTERISTICS
Symbol
VIH
VIL
VOH1
V
OH2
V
OL
I
I
IO
1
Icc
Icc2
Icc3
Parameter
High-level input voltage Low-level input voltage
High-level output voltage 1 High-level output voltage 2 Low-level output voltage
Input leakage current Output leakage current
Active supply current ( AC,MOS level )
Active supply current ( AC,TTL level )
Stand by supply current ( AC,MOS level )
Conditions Units
IOH= -0.5mA IOH= -0.05mA IOL=2mA
VI =0 ~ S-Vcc
S-CE=VIL or OE#=VIH, VI/O=0 ~ S-Vcc
<
S-CE S-Vcc-0.2V
=
other inputs 0.2V or S-Vcc-0.2V
Output - open (duty 100%) S-CE=VIH
other pins =VIH or VIL Output - open (duty 100%)
S-CE 0.2V
Other inputs=0~S-Vcc
<
=
<
=
- 65 ~ +150
* -3.0V in case of AC (Pulse width 30ns)
( S-Vcc=2.7 ~ 3.6V, unless otherwise noted)
Limits
Min
Typ
2.2
-0.3 *
2.4
S-Vcc-0.5V
C
<
=
Max
S-Vcc+0.3V
0.6 V
0.4
±1
±1
>
=
-W
f= 10MHz f= 1MHz
f= 10MHz f= 1MHz
+70 ~ +85 C
+40 ~ +70 C +25 ~ +40 C
-
-
7
-
-
-
-
-
-
-
1
7050
15
7050
157 40
20
3.6
mA
mA
mA
Stand by supply current
Icc4
( AC,TTL level )
Note 1: Direction for current flowing into IC is indicated as positive (no mark)
Note 2: Typical value is for S-Vcc=3.0V and Ta=25 C
S-CE=VIL
Other inputs= 0 ~ S-Vcc
CAPACITANCE
Symbol
CI CO
Note: The value of common pins to SRAM is the sum of Flash Memory and SRAM.
26
Parameter
Input capacitance
Output capacitance
Conditions
VI=GND, VI=25mVrms, f=1MHz
O=GND,VO=25mVrms, f=1MHz
V
- 20 ~ +25 C
(S-Vcc=2.7 ~ 3.6V, unless otherwise noted)
- 0.3
-
* -3.0V in case of AC (Pulse width 30ns)
-
Limits
1.2
0.5
MaxTypMin
mA
< =
Units
10 10
pF
Sep. 1999 , Rev.2.0
Page 27
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
4,194,304-BIT (262,144WORD BY 16-BIT / 524,288-WORD BY 8-BIT) CMOS SRAM
AC ELECTRICAL CHARACTERISTICS
(1) TEST CONDITIONS
MITSUBISHI LSIs
M6MGB/T160S4BVP
3.3V-ONLY FLASH MEMORY &
Stacked-MCP (Multi Chip Package)
(S-Vcc=2.7 ~ 3.6V, unless otherwise noted)
Supply voltage Input pulse Input rise time and fall time
Reference level
Output loads
2.7V~3.6V V
IH=2.4V,VIL=0.4V
5ns
OH=VOL=1.5V
V
Transition is measured ±500mV from steady state voltage.(for t
en,tdis)
Fig.1,CL=30pF CL=5pF (for ten,tdis)
DQ
(2) READ CYCLE
Limits
Symbol
t
CR ns
ta(A) ta(CE)
ta(OE) tdis(CE) tdis(OE) ten(CE)
ten(OE) tV(A)
Read cycle time
Address access time
Chip select access time
Output enable access time
Output disable time after S-CE low Output disable time after OE# high Output enable time after S-CE high
Output enable time after OE# low
Data valid time after address
Parameter
85
10
5
10
SRAM
MaxMin
85 85 45 30 30
1TTL
CL
Including scope and jig capacitance
Fig.1 Output load
Units
ns ns ns ns
ns ns
ns ns
(3) WRITE CYCLE
Symbol
tCW tw(W) tsu(A) tsu(A-WH) tsu(CE) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE)
27
Write cycle time Write pulse width Address setup time Address setup time with respect to WE# Chip select setup time Data setup time Data hold time
Write recovery time Output disable time from WE# low Output disable time from OE# high
Output enable time from WE# high
Output enable time from OE# low
Parameter
Min
85 60
0 70 70 35
0
0
5
5
Limits
SRAM
Max
30 30
Units
ns ns ns ns ns ns ns
ns ns ns ns ns
Sep. 1999 , Rev.2.0
Page 28
(4)TIMING DIAGRAMS
MITSUBISHI LSIs
M6MGB/T160S4BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144WORD BY 16-BIT / 524,288-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
Read cycle
A0~17
(Word Mode)
A-1~17
(Byte Mode)
S-CE
OE#
WE# = "H" level
DQ0~15
(Word Mode)
DQ0~7
(Byte Mode)
Write cycle
tCR
ta(A)
tv (A)
ta(CE)
(Note3)
tdis (CE)
ta (OE)
(Note3) (Note3)
ten (OE)
tdis (OE)
ten (CE)
VALID DATA
( WE# control mode )
(Note3)
A0~17
(Word Mode)
A-1~17
(Byte Mode)
S-CE
OE#
WE#
DQ0~15
(Word Mode)
DQ0~7
(Byte Mode)
(Note3)
tsu (A)
tdis(OE)
tsu (CE)
tsu (A-WH)
tw (W)
tdis (W)
tCW
DATA IN STABLE
(Note3)
trec (W)
ten(OE) ten (W)
th (D)tsu (D)
28
Sep. 1999 , Rev.2.0
Page 29
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
Write cycle (S-CE control mode)
A0~17
(Word Mode)
A-1~17
(Byte Mode)
S-CE
(Note4)
WE#
MITSUBISHI LSIs
M6MGB/T160S4BVP
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144WORD BY 16-BIT / 524,288-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
tCW
tsu (A)
tsu (CE)
trec (W)
(Note3)
th (D)tsu (D)
DQ0~15
(Word Mode)
DQ0~7
(Byte Mode)
Note 3: Hatching indicates the state is "don't care". Note 4: When the falling edge of WE# is simultaneously or priorto the rising edge of S-CE,
the outputs are maintained in the high impedance state.
Note 5: Don't apply inverted phase signal externally when DQ pin is in output mode.
DATA IN STABLE
(Note3)
29
Sep. 1999 , Rev.2.0
Page 30
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
4,194,304-BIT (262,144WORD BY 16-BIT / 524,288-WORD BY 8-BIT) CMOS SRAM
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS
MITSUBISHI LSIs
M6MGB/T160S4BVP
3.3V-ONLY FLASH MEMORY &
Stacked-MCP (Multi Chip Package)
Symbol
S-Vcc (PD)
VI (S-CE)
Icc (PD)
Parameter
Power down supply voltage
Chip select input S-CE
Power down supply current
(2) TIMING REQUIREMINTS
Symbol
tsu (PD)
trec (PD)
Parameter Test conditions
Power down set up time Power down recovery time
(3) TIMING DIAGRAM
S-CE control mode
S-Vcc
S-Vcc=3.0V
>
S-CE 0.2V
=
other inputs=0~3V
Test conditions
-W
+70 ~ +85 C
+40 ~ +70 C +25 ~ +40 C
-20 ~ +25 C
Limits
Min Typ Max
2.0
0.2
-
-
-
-
Min Typ Max
-
-
1
0.3
Typical value is for Ta=25 C
Limits
30 15
3
1
0
5
Units
V V
mA
mA
mA
mA
Units
ns
ms
S-CE
0.2V
BYTE# TIMING DIAGRAM
(1) TIMING REQUIREMINTS
Symbol
tsu (BYTE)
trec (BYTE)
Parameter Test conditions
BYTE# set up time BYTE# recovery time
(2) TIMING DIAGRAM
S-CE
tsu (PD)
2.7V
tsu (BYTE)
<
S-CE 0.2V
=
2.7V
trec (BYTE)
trec (PD)
Limits
Min Typ Max
5 5
0.2V
Units
ms ms
30
BYTE#
Sep. 1999 , Rev.2.0
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