Datasheet M68Z512 Datasheet (SGS Thomson Microelectronics)

4 Mbit (512Kb x8) Low Power SRAM with Output Enable

■ ULTRA LOW DATA RETENTION CURRENT

– 100nA (typical)
–10µA (max)

■OPERATION VOLTAGE: 5V ±10%

■ 512 Kbit x8 SRAM with OUTPUT ENABLE

■ EQUAL CYCLE and ACCESS TIMES: 70ns

■ LOW V

■ TRI-STATE COMMON I/O

■ CMOS for OPTIMUM SPEED/POWER

■ AUTOMATIC POWER-DOWN WHEN

DESELECTED

■ INTENDED FOR USE WITH ST

ZEROPOWER

CONTROLLERS

DATA RETENTION: 2V

CC

®

AND TIMEKEEPER®

M68Z512

32

1

TSOP II 32 (NC)

10 x 20mm

Figure 1. Logic Diagram

DESCRIPTION

The M68Z512 is a 4 Mbit (4,194,304 bit) CMOS
SRAM, organized as 524,288 words by 8 bits. The
device features fully static operat ion requiring no
external clocks or timing strobes, with equal ad­dress access and cycle times. It requires a single

5V ±10% supply, and all inputs and outputs are
TTL compatible.

This device has an automatic power-down feature,
reducing the power consumption by over 99%
when deselected.

The M68Z512 is a vailable in a 32 lea d TSOP II
(10 x 20mm) package.

Table 1. Signal Names

A0-A18 Address Inputs
DQ0-DQ7 Data Input/Output

E
G

W

V

CC

Chip Enable
Output Enable

Write Enable

Supply Voltage

A0-A18

W

V

CC

19

M68Z512

E

G

V

SS

8

DQ0-DQ7

AI03030

V

SS

Ground

1/12March 2000

M68Z512

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

T

A

T

STG

(2)

V

IO

V

CC

(3)

I

O

P

D

Note: 1. Ex cept for the rating "Operati ng Temperat ure Range" , stresses above th ose listed i n the Tab l e "Absolute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indi cated in the Operating sections of this s pecification is not impli ed. Exposure to Absolute M aximum Rating condi­tions for extended per iods may aff ect device reliabilit y. Refer also to the STMicroel ectronics SURE Program an d other relevan t qual ­ity docum en ts .

2. Up to a maxim um operatin g V

3. One output at a tim e, not to exceed 1 secon d duration.

Ambient Operating Temperature

Storage Temperature –65 to 150 °C
Input or Output Voltage
Supply Voltage –0.3 to 7.0 V
Output Current 20 mA
Power Dissipation 1 W

of 5.5V only.

CC

Figure 2. TSOP Connection s

(1)

READ MODE

0 to 70 °C

–0.3 to V

CC

+ 0.3

V

The M68Z512 is in the Read mode whenever
Write Ena ble (W
Low, and Chip Enable (E

) is High with Output Enable (G)

) is asserted. This pro-

vides access to data from e ight of the 4,194,304

A17
A16
A14
A12

A7
A6
A5
A4
A3
A2
A1

A0
DQ0
DQ1
DQ2
V

SS

1

8
9

M68Z512

32

25
24

16 17

AI03031

V

CC

A15
A18
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3

locations in the static memory array, specified by
the 19 address inputs. Valid data wil l be availa ble
at the eight output pins within t
stable address, providing G

is Low and E is Low.

after the last

AVQV

If Chip Enable or Output Enable access times are
not met, data access will be measured from the
limiting parameter (t
address. Data out may be indeterminate at t
and t
t

AVQV

, but data lines will always be valid at

GLQX

.

ELQV

or t

) rather than the

GLQV

ELQX

WRITE MODE

The M68Z512 is in the Write mode whenever the

and E pins are Low. Either the Chip Enable in-

W
put (E

) or the Write E nabl e i nput (W) must be de­asserted during Address transitions for subse­quent write cycles. Write begins with the concur­rence of Chip Enable being active with W

low.
Therefore, address setup time is referenced to
Write Enable and Chip Enable as t

AVWL

and t

AVEH

respectively, and is determined by the latter occur­ring edge.

The Write cycle can be terminated by the earlier
rising edge of E

if the Output is enabled (E
then W
within t

will return the outputs to high impedance

WLQZ

, or W.

= Low and G = Low),

of its falling edge. Care must be taken
to avoid bus c ontention in this type of operation.
Data input must be valid for t
ing edge of Write Enable, or for t
rising edge of E
main v a lid for t

, whichever occurs first, and re-

or t

WHDX

EHDX

before the ris-

DVWH

DVEH

.

before the

2/12

Table 3. Operating Modes

Operation E W G DQ0-DQ7 Power

Read
Read
Write
Deselect

Note: 1. X = VIH or VIL.

M68Z512

V

IL

V

IL

V

IL

V

IH

V

IH

V

IH

V

IL

X

V

IH

V

IL

Hi-Z Active

Data Output Active
X Data Input Active
X

Hi-Z Standby

Table 4. AC Measurement Conditions

Input Rise and Fall Times ≤ 5ns

Figure 3. AC Testing Load Circuit

5.0V

Input Pulse Voltages 0 to 3V
Input and Output Timing Ref. Voltages 1.5V

Note: Output Hi -Z is de fin ed as the po int whe re data is no l onge r

driven.

OPERATIONAL MODE

The M68Z512 has a Chip Enable power down fea­ture which invokes an automatic standby mode
whenever Chip Enable is de-as serted (E
An Output Enable (G

) signal provides a high

= High).

DEVICE
UNDER

TEST

994Ω

1838Ω

OUT

CL = 100pF or 5pF

speed tri-state control, allowing fast read/write cy­cles to be achieved with the common I/O data bus.
Operational modes are determined by device con­trol inputs W

and E as summarized in the Ope ra t-

CL includes JIG capacitance

AI03032

ing Modes table.

Table 5. Capacitance

Symbol Parameter Test Condition Min Max Unit

C

C

OUT

Note: 1. Sampled only, not 100% tested.

Input Capacitance on all pins (except DQ)

IN

(2)

Output Capacitanc e

2. Outputs desel ected.

(1)

(TA = 25°C, f = 1 MHz)

T

= 25°C, f = 1MHz, VCC = 5V

A

T

= 25°C, f = 1MHz, VCC = 5V

A

6pF
8pF

3/12

M68Z512

Figure 4. Block Diagram

A

A

CHIP ENABLE.

(10)

ROW

DECODER

MEMORY

ARRAY

V

CC

V

SS

DQ

(8)

DQ

E

W

G

INPUT

DATA
CTRL

CHIP ENABLE.

I/O CIRCUITS

COLUMN

DECODER

(9)

A A

AI03033

Table 6. DC Characteristics

(T

= 0 to 70°C; VCC = 5V ±10%)

A

Symbol Parameter Test Condition Min Typ Max Unit

I

Input Leakage Current

LI

I

I

CC1

I

CC2

I

CC3

V

V
V
V

Note: 1. Av erage AC cu rrent, Outputs open, cyc l i ng at t

Output Leakage Current

LO

(1)

Supply Current

(2)

Supply Current (Standby) TTL

(3)

Supply Current (Standby) CMOS
Input Low Voltage –0.3 0.8 V

IL

Input High Voltage 2.2

IH

Output Low Voltage

OL

Output High Voltage

OH

2. All other Inputs at V

3. All other Inputs at V

≤ 0.8V or VIH ≥ 2.2V.

IL

≤ 0.3V or VIH ≥ VCC –0.3V.

IL

0V ≤ V

0V

V

V

CC

= 5.5V, E ≥ V

V

CC

minimum.

AVAV

≤ V

IN

CC

≤ V

≤ V

OUT

= 5.5V, (-55)

CC

= 5.5V, E = VIH

CC

f=0

I

= 2.1mA

OL

I

= –1mA

OH

CC

– 0.3V,

±1 µA
±1 µA

90 mA
15 mA

1.6 20 µA

V

+ 0.3

CC

0.4 V

2.4 V

V

4/12

M68Z512

Table 7. Read and Standby Modes AC Characteristics

(TA = 0 to 70°C; VCC = 5V ±10%)

Symbol Parameter

t

AVAV

t

AVQV

t

ELQV

t

GLQV

t

ELQX

t

GLQX

t

EHQZ

t

GHQZ

t

AXQX

t

PU

t

PD

Note: 1. CL = 100pF.

2. C

3. At any given tem perature and voltage condition, t

Read Cycle Time 70 ns

(1)

Address Valid to Output Valid 70 ns

(1)

Chip Enable Low to Output Valid 70 ns

(1)

Output Enable Low to Output Valid 35 ns

(3)

Chip Enable Low to Output Transition 10 ns

(3)

Output Enable Low to Output Transition 5 ns

(2,3)

Chip Enable High to Output Hi-Z 25 ns

(2,3)

Output Enable High to Output Hi-Z 25 ns

(1)

Address Transition to Output Transition 10 ns
Chip Enable Low to Power Up 0 ns

Chip Enable High to Power Down 70 ns

= 5pF.

L

is less than t

EHQZ

ELQX

and t

is less than t

GHQZ

M68Z512

Min Max

for any given device.

GLQX

Unit-70

Figure 5. Address Controlled, Read Mode AC Waveforms

tAVAV

A0-A18

tAVQV tAXQX

DQ0-DQ7

Note: E = Low, G = Low, W = High.

VALID

DATA VALID

AI03034

5/12

M68Z512

Figure 6. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms.

tAVAV

A0-A18

tAVQV tAXQX

tELQV

E

tELQX

G

tGLQX

DQ0-DQ7

Note: Write Enable (W) = High.

Figure 7. Standby Mode AC Waveforms

tGLQV

VALID

tEHQZ

tGHQZ

VALID

AI03035

6/12

E

I

CC1

I

CC2

tPU

50%

tPD

AI03036

Table 8. Write Mode AC Characteristics

(T

= 0 to 70°C; VCC = 5V ±10%)

A

M68Z512

M68Z512

Symbol Parameter

t

AVAV

t

AVWL

t

AVWH

t

AVEH

t

WLWH

t

WHAX

t

WHDX

t

WHQX

t

WLQZ

t

AVEL

t

ELEH

t

EHAX

t

DVWH

t

DVEH

Note: 1. CL = 5pF.

2. At any given tem perature and voltage condition, t

Write Cycle Time 70 ns
Address Valid to Write Enable Low 0 ns
Address Valid to Write Enable High 60 ns
Address Valid to Chip Enable High 60 ns
Write Enable Pulse Width 55 ns
Write Enable High to Address Transition 0 ns
Write Enable High to Input Transition 0 ns

(2)

Write Enable High to Output Transition 5 ns

(1,2)

Write Enable Low to Output Hi-Z 25 ns
Address Valid to Chip Enable Low 0 ns
Chip Enable Low to Chip Enable High 45 ns

Chip Enable High to Address Transition 0 ns
Input Valid to Write Enable High 25 ns
Input Valid to Chip Enable High 25 ns

is less than t

WLQZ

for any given device.

WHQX

Unit-70

Min Max

7/12

M68Z512

Figure 8. Write Enable Controlled, Write AC Waveforms

tAVAV

A0-A18

tAVEL

E

tAVWL

W

tWLQZ

DQ0-DQ7

Note: Output Enable (G) = Low.

VALID

tAVWH

tWLWH

Figure 9. Chip Enable Controlled, Write AC Waveforms

tWHAX

tWHQX

tWHDX

DATA INPUT

tDVWH

AI03037

(1,2)

A0-A18

E

W

DQ0-DQ7

Note: 1. Output Enable ( G) = Hi gh.

goes High with W high, the output remains in a hi gh-impedance state.

2. If E

8/12

tAVEL

tAVWL

tAVAV
VALID

tAVEH

tELEH

tEHAX

tEHDX

DATA INPUT

tDVEH

AI03038

M68Z512

Table 9. Low VCC Data Retention Characteristics

(T

= 0 to 70°C)

A

Symbol Parameter Test Condition Min Typ Max Unit

(1)

I

CCDR

V
t

CDR

t

ER

Note: 1. Typical condition: TA = 25°C.

Supply Current (Data Retention)

Supply Voltage (Data Retention)

DR

Chip Disable to Power Down

(2)

Operation Recovery Time

2. See Figure 10 for measur em ent points. Guaranteed but not test ed.

Figure 10. Low VCC Data Retention AC Waveforms

V

CC

E

≥ V

E

≥ V

= 3V, E ≥ V

– 0.3V, f = 0

CC

– 0.3V, f = 0

CC

t

– 0.3V

CC

is Read cycl e time.

AVAV

0.1 10 µA
2V
0ns

t

AVAV

ns

5V

VCC 3V

V

> 2.0V

DR

E 2.2V

tCDR

DATA RETENTION MODE

E ≥ V

DR

– 0.3V

tER

AI03039

9/12

M68Z512

Table 10. Ordering Information Scheme

Example: M68Z512 -70 NC 1 T

Device Type

M68Z

Device Function

512 = 4 Mbit (512Kb x8)

Operating Voltage

blank = 4.5V to 5.5V

Speed

-70 = 70 ns

Package

NC = TSOP II 32 (10 x 20mm)

Temperature Range

1 = 0 to 70 °C

Shipping Method

T = Tape & Reel Packing

For a list of available options (Speed, Pac kage, etc...) or for furthe r information on any aspect of this de­vice, please contact the STMicroelectronics Sales Office nearest to you.

Table 11. Revision History

Date Revision Details

May 1999 First Issue

03/14/00

TSOP32 II Package Dimension Changed (Table 12)
From Preliminary Data to Data Sheet

10/12

M68Z512

Table 12. TSOP II 32 - 32 lead Plastic Thin Small Outline II, 10 x 20 mm, Package Mechanical Data

Symbol

Typ Min Max Typ Min Max

A 1.20 0.047
A1 0.05 0.15 0.002 0.006
A2 0.95 1.05 0.037 0.041

b 0.30 0.52 0.012 0.020

C 0.12 0.21 0.005 0.008

CP 0.10 0.004

D 20.82 21.08 0.820 0.830

e 1.27 – – 0.050 – –

E 11.56 11.96 0.455 0.471
E1 10.03 10.29 0.395 0.405

L 0.40 0.60 0.016 0.024

α 0° 5° 0° 5°

N32 32

mm inch

Figure 11. TSOP II 32 - 32 lead Plastic Thin Small Outline II, 10 x 20 mm, Package Outline

D

16

17

A

CP

1

E

E1

32

eb

A2

C

α

A1

L

Drawing is not to scale.

TSOP-d

11/12

M68Z512

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