Datasheet M68Z128W Datasheet (SGS Thomson Microelectronics)

M68Z128W

3V, 1 Mbit (128Kb x8) Low Power SRAM with Output Enable

■ LOW VOLTAGE: 3.0V (+0.6V / –0.3V)

■ 128Kb x 8 LOW POWER SRAM with OUTPUT

ENABLE

■ EQUAL CYCLE and ACC ESS TIMES: 70ns

■ LOW V

■ TRI-STATE COMMON I/O

■ LOW ACTIVE and STAN DB Y POWER

■ INTENDED for USE with ST ZEROPOWER

and TIMEKEEPER

DESCRIPTION

The M68Z128W is a 1 Mbit (1,048,576 bi t) Fast
CMOS SRAM, organized as 131,072 words by 8
bits. The device features fully static opera tion re­quiring no external clocks or timing strobes, with
equal address access and cycle times. It requires

a single 3.0V (+0.6V / –0.3V) supply, and all inputs
and outputs are TTL compatible. This device has
an automatic power-down feature, reducing the
power consumption by over 99% when desel ect­ed. The M68Z128 W is available in the sta ndard
450mil-wide TSOP type 1 package.

DATA RETENTION: 1.4V

CC

®

CONTROLLERS

®

TSOP32 (N)

8 x 20mm

Figure 1. Logic Diagram

V

CC

Table 1. Signal Names

A0-A16 Address Inputs
DQ0-DQ7 Data Input/Output

E1
E2 Chip Enable 2

G

W
V

CC

V

SS

NC Not Connected Internally

Chip Enable 1

Output Enable

Write Enable

Supply Voltage

Ground

A0-A16

W

E1

E2

17

M68Z128W

G

V

SS

8

DQ0-DQ7

AI01878B

1/12March 2000

M68Z128W

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

T

A

T

STG

(2)

V

IO

V

CC

(3)

I

O

P

D

Note: 1. Except for the ratin g " Operati ng Temperat ure Range" , stresses above th ose listed i n the Tab l e "Absolute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indi cated in the Operating sections of this s pecification is not i mplied. Exposu re to Ab solute Ma xi m um Rati ng condi­tions for extended per iods may aff ect device reliabilit y. Refer also to the STMicroel ectronics SURE Program an d other relevan t qual ­ity docum en ts .

2. Up to a m aximum op erating V

3. One out put at a time, not to exceed 1 s econd durat i on.

Ambient Operating Temperature

Storage Temperature –65 to 150 °C
Input or Output Voltage
Supply Voltage –0.5 to 4.6 V
Output Current 20 mA
Power Dissipation 1 W

of 3.6V only.

CC

Figure 2. TSOP Connection s

(1)

0 to 70 °C

–0.5 to V

CC

+ 0.5

V

the 1,048,576 locations in the static memory array,
specified by the 17 address inputs. Val id dat a wi ll
be available at the eight output pins within t

AVQV

after the last stable address, providing G is Low,

is Low and E2 is High. If Chip Enable or Output

A11 G

1
A9
A8

A13

W

E2

A15

V

CC
NC

8

9

M68Z128W

A16
A14
A12

A7
A6
A5
A4 A3

16 17

32

25
24

AI00698B

A10
E1
DQ7
DQ6
DQ5
DQ4
DQ3
V

SS

DQ2
DQ1
DQ0
A0
A1
A2

READ MODE

The M68Z128W is in the Read mode whenever
Write Ena ble (W
Low, and both Chip Enables (E1

) is High with Output Enable (G)

and E2) are as-

serted. This provides acc ess to dat a fr om eight of

E1
Enable access times are not met, data access will
be measured from the limiting parameter (t

E2HQV

, or t

t
may be indeterminate at t

) rather than the address. Data out

GLQV

E1LQX

, t

E2HQX

but data lines will always be valid at t

and t

AVQV

E1LQV

GLQX

.

WRITE MODE

The M68Z128W is in the Write mode whenever

and E1 pins are Lo w, with E2 High. Either

the W
the Chip Enable input s (E1
Enable input (W

) must be de-asserted during Ad-

and E2) or the Write

dress transitions for subsequent write cycles.
Write begins with the concurrence of both Chip
Enables being active with W

low. Therefore, ad­dress setup time is r eferenced to Write Enable and
both Chip Enables as t

AVWL

, t

AVE1L

and t

AVE2H

re­spectively, and is determined by the latter occur­ring edge.

The Write cycle can be terminated by the earlier
rising edge of E1

If the Output is enabled (E1

= Low), then W will return the outputs to high im-

G
pedance within t

, W, or the falling edge of E2.

= Low, E2 = High and

of its falling edge. Care must

WLQZ

be taken to avoid bus contention in this type of op­eration. Data input must be valid for t
the rising edge of Write E nable, o r for t
fore the rising edge of E1

or for t

DVE2L

before

DVWH

DVE1H

before the

be-

falling edge of E2, whi chever occurs f irst, and re­main v a lid for t

WHDX

, t

E1HDX

or t

E2LDX

.

,
,

2/12

Table 3. Operating Modes

Operation E1 E2 W G DQ0-DQ7 Power

Read
Read
Write
Deselect
Deselect X

Note: 1. X = VIH or VIL.

V

IL

V

IL

V

IL

V

IH

V

IH

V

IH

V

IH

V

IH

V

IH

V

IL

XX

V

IL

X

V

IH

V

IL

X

Data Output

Data Input Active
X
X

Hi-Z Active

Hi-Z Standby
Hi-Z Standby

M68Z128W

Active

Table 4. AC Measurement Conditions

Input Rise and Fall Times ≤ 15ns
Input Pulse Voltages 0 to 3V
Input and Output Timing Ref. Voltages 1.5V

Note: O ut put H i-Z is defin ed as t he poi nt w here da ta is no lo nger

driven.

OPERATIONAL MODE

The M68Z128W has a Chip Enable power down
feature which invokes an automatic standby mode
whenever either Chip Enable is de-asserted (E1
High or E2 = Low). An Output Enable (G

=

) signal
provides a high speed tri-state control, allowing
fast read/write cycles to be achieved with the com­mon I/O data bu s. Operational mo des are deter­mined by device control inputs W

, E1, and E2 as

summarized in the Operating Modes table.

Table 5. Capacitance

Symbol Parameter

C

IN

(2)

C

OUT

Note: 1. Sampled only, not 100% tested.

2. Outputs deselected.

(1)

(TA = 25 °C, f = 1 MHz)

Input Capacitance on all pins (except DQ)
Output Capacitance

Figure 3. AC Testing Load Circuit

3.3V

1213Ω

DEVICE
UNDER

TEST

1378Ω

CL includes JIG capacitance

Test

Condition

V

= 0V

IN

V

= 0V

OUT

Min Max Unit

CL = 50pF or 5pF

6pF
8pF

OUT

AI00697

3/12

M68Z128W

Figure 4. Block Diagram

A

A

CHIP ENABLE.

(9)

ROW

DECODER

MEMORY

ARRAY

V

CC

V

SS

E1
E2

DQ

(8)

DQ

CHIP

ENABLE

W

G

INPUT

DATA
CTRL

CHIP ENABLE.

I/O CIRCUITS

COLUMN

DECODER

(8)

A A

AI00665

Table 6. DC Characteristics

(T

= 0 to 70°C; VCC = 3.0V + 0.6V / –0.3V)

A

Symbol Parameter Test Condition Min Typ Max Unit

I

Input Leakage Current

LI

I

I

CC1

I

CC2

I

CC3

V

V
V
V

Note: 1. Average AC current, Ou tputs open, c ycling at t

Output Leakage Current

LO

(1)

Supply Current

(2)

Supply Current (Standby) TTL

(3)

Supply Current (Standby) CMOS
Input Low Voltage –0.5 0.8 V

IL

Input High Voltage 2

IH

Output Low Voltage

OL

Output High Voltage

OH

2. All other Inputs at V

3. All other Inputs at V

≤ 0.8V or VIH ≥ 2.0V.

IL

≤ 0.2V or VIH ≥ VCC –0.2V.

IL

0V ≤ V

0V

V

V

CC

= 3.6V , E1 ≥ V

V

CC

or E2 ≤ 0.2V, f =0

minimum.

AVAV

≤ V

IN

CC

≤ V

≤ V

OUT

= 3.6V, (-70)

CC

CC

= 3.6V, E1 = VIH or
E2 = V

I
I

= 2.1mA

OL

= –1mA

OH

IL

, f =0

CC

– 0.2V

±1 µA
±1 µA

20 40 mA
15 300 µA

0.4 15 µA

V

+ 0.5

CC

0.4 V

2.4 V

V

4/12

M68Z128W

Table 7. Read and Standby Modes AC Characteristics
(TA = 0 to 70°C; VCC = 3.0V + 0.6V / –0.3V)

Symbol Parameter

t

AVAV

t

AVQV

t

E1LQV

t

E2HQV

t

GLQV

t

E1LQX

t

E2HQX

t

GLQX

t

E1HQZ

t

E2LQZ

t

GHQZ

t

AXQX

t

PU

t

PD

Note: 1. CL = 50pF (see Figure 3).

2. C

3. At any given temperature and voltage condition, t

Read Cycle Time 70 ns

(1)

Address Valid to Output Valid 70 ns

(1)

Chip Enable 1 Low to Output Valid 70 ns

(1)

Chip Enable 2 High to Output Valid 70 ns

(1)

Output Enable Low to Output Valid 35 ns

(3)

Chip Enable 1 Low to Output Transition 10 ns

(3)

Chip Enable 2 High to Output Transition 10 ns

(3)

Output Enable Low to Output Transition 10 ns

(2,3)

Chip Enable 1 High to Output Hi-Z 0 25 ns

(2,3)

Chip Enable 2 Low to Output Hi-Z 0 25 ns

(2,3)

Output Enable High to Output Hi-Z 0 25 ns

(1)

Address Transition to Output Transition 10 ns
Chip Enable 1 Low or Chip Enable 2 High to Power Up 0 ns

Chip Enable 1 High or Chip Enable 2 Low to Power Down 70 ns

= 5pF (see Figure 3).

L

given devic e.

EIHQZ

+ t

EZHQZ

is less than t

EILQX

and t

M68Z128W

Min Max

, t

EZLQX

is less than t

GHQZ

GLQX

Unit-70

for any

Figure 5. Address Controlled, Read Mode AC Waveforms

tAVAV

A0-A16

tAVQV tAXQX

DQ0-DQ7

Note: E1 = Low, E2 = High, G = Low, W = High.

VALID

DATA VALID

AI01078

5/12

M68Z128W

Figure 6. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms.

tAVAV

A0-A16

E1

E2

G

DQ0-DQ7

Note: Write Enable (W) = High.

VALID

tAVQV tAXQX

tE1LQV

tE1LQX

tE2HQV

tE2HQX

tGLQX

tGLQV

tGHQZ

VALID

tE1HQZ

tE2LQZ

AI00805

Figure 7. Standby Mode AC Waveforms

E1

E2

I

CC1

I

CC2

tPU

50%

tPD

AI00806B

6/12

Table 8. Write Mode AC Characteristics

(T

= 0 to 70°C; VCC = 3.0V + 0.6V / –0.3V)

A

M68Z128W

M68Z128W Unit

Symbol Parameter

t

AVAV

t

AVWL

t

AVWH

t

AVE1H

t

AVE2L

t

WLWH

t

WHAX

t

WHDX

t

WHQX

t

WLQZ

t

AVE1L

t

AVE2H

t

E1LE1H

t

E2HE2L

t

E1HAX

t

E2LAX

t

DVWH

t

DVE1H

t

DVE2L

Note: 1. CL = 5pF.

2. At any gi ven temperature and voltage condition, t

Write Cycle Time 70 ns
Address Valid to Write Enable Low 0 ns
Address Valid to Write Enable High 60 ns
Address Valid to Chip Enable 1 High 60 ns
Address Valid to Chip Enable 2 Low 60 ns
Write Enable Pulse Width 55 ns
Write Enable High to Address Transition 0 ns
Write Enable High to Input Transition 0 ns

(2)

Write Enable High to Output Transition 0 ns

(1,2)

Write Enable Low to Output Hi-Z 25 ns
Address Valid to Chip Enable 1 Low 0 ns

Address Valid to Chip Enable 2 High 0 ns
Chip Enable 1 Low to Chip Enable 1 High 60 ns
Chip Enable 2 High to Chip Enable 2 Low 60 ns
Chip Enable 1 High to Address Transition 0 ns
Chip Enable 2 Low to Address Transition 0 ns
Input Valid to Write Enable High 30 ns
Input Valid to Chip Enable 1 High 30 ns
Input Valid to Chip Enable 2 Low 30 ns

WHQX

is less than t

for any given device.

WLQZ

-70

Min Max

7/12

M68Z128W

Figure 8. Write Enable Controlled, Write AC Waveforms

tAVAV

A0-A16

tAVE1L

E1

tAVE2H

E2

tAVWL

W

tWLQZ

DQ0-DQ7

Note: Output E nable (G) = Low.

VALID

tAVWH

tWLWH

Figure 9. Chip Enable Controlled, Write AC Waveforms

tDVWH

(1,2)

tWHAX

tWHQX

tWHDX

DATA INPUT

AI00807

A0-A16

E1

E2

W

DQ0-DQ7

Note: 1. Output Enable (G) = High.

goes High or E2 goes Low si m ul t aneously wi th W high, th e out put remains in a high-impedance st ate.

2. If E1

tAVAV
VALID

tAVE1H

tAVE1L

tAVE2H tE2HE2L

tAVWL

tE1LE1H

tAVE2L

tDVE1H

tDVE2L

tE1HAX

tE2LAX

tE1HDX

tE2LDX

DATA INPUT

AI00808

8/12

M68Z128W

Table 9. Low VCC Data Retention Characteristics

(T

= 0 to 70°C)

A

Symbol Parameter Test Condition Min Typ Max Unit

V

= 3V, E1 ≥ V

E1

E1

CC

E2 ≤ 0.2V, f = 0

≥ V

– 0.2V, E2 ≤ 0.2V, f= 0

CC

≥ V

– 0.2V, E2 ≤ 0.2V, f=0

CC

(1)

I

CCDR

V

DR

t

CDR

t

R

Note: 1. All other Inputs at VIH ≥ V

Supply Current (Data Retention)

(1)

Supply Voltage (Data Retention)

(1,2)

Chip Disable to Power Down

(2)

Operation Recovery Time

– 0.2V or VIL ≤ 0.2V .

2. See Fi gure 10 for m easuremen t p oi nts. Guara nteed but not tested.

CC

Figure 10. Low VCC Data Retention AC Waveforms

– 0.2V,

CC

t

is Read cycl e time.

AVAV

0.01 2 µA

1.4 V
0ns

t

AVAV

ns

3.6V

VCC 3V

V

> 1.4V

DR

E1 2.2V

E2 0.8V

tCDR

DATA RETENTION MODE

E1 ≥ V

– 0.2V

DR

E2 ≤ 0.2V

tR

AI00664

9/12

M68Z128W

Table 10. Ordering Information Scheme

Example: M68Z128W -70 N 1 T

Device Type

M68Z

Device Function

128 = 1 Mbit (128Kb x8)

Operating Voltage

W = 3V +0.6/–0.3V

Speed

-70 = 70 ns

Package

N = TSOP32 type 1 (8 x 20mm)

Temperature Range

1 = 0 to 70 °C

Shipping Method

T = Tape & Reel Packing

For a list of available options (Speed, Pac kage, etc...) or for furthe r information on any aspect of this de­vice, please contact the STMicroelectronics Sales Office nearest to you.

Table 11. Revision History

Date Revision Details

November 1999 First Issue
03/20/00 TSOP32 Package Mechanical Data changed (Table 12)

10/12

M68Z128W

Table 12. TSOP32 (Type I) - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Mechanical Data

Symbol

Typ Min Max Typ Min Max

A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 0.950 1.050 0.0374 0.0413

B 0.150 0.270 0.0059 0.0106

C 0.100 0.210 0.0039 0.0083

D 19.800 20.200 0.7795 0.7953
D1 18.300 18.500 0.7205 0.7283

e 0.500 – – 0.0197 – –

E 7.900 8.100 0.3110 0.3189

L 0.500 0.700 0.0197 0.0276

α 0° 5° 0° 5°

CP 0.100 0.0039

N32 32

mm inch

Figure 11. TSOP32 (Type I) - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Outline

A2

1 N

e

E

B

N/2

D1

D

DIE

A

CP

C

TSOP-a

Drawing is not to scale.

LA1 α

11/12

M68Z128W

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