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Freescale Semiconductor, Inc.
M68HC11E Family
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Data Sheet
cale Semiconductor,
Frees
M68HC11
Microcontrollers
MOTOROLA.COM/SEMICONDUCTORS
M68HC11E/D
Rev. 5
6/2003
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Go to: www.freescale.com
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Freescale Semiconductor, Inc.
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cale Semiconductor,
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For More Information On This Product,
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Freescale Semiconductor, Inc.
MC68HC11E Family
Data Sheet
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cale Semiconductor,
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To provide the most up-to-date information, the revision of our documents on the
World Wide Web will be the most current. Your printed copy may be an earlier
revision. To verify you have the latest information available, refer to:
http://www.motorola.com/semiconductors/
The following revision history table summarizes changes contained in this
document. For your convenience, the page number designators have been linked
to the appropriate location.
Motorola and the Stylized M Logo are registered trademarks of Motorola, Inc.
DigitalDNA is a trademark of Motorola, Inc. © Motorola, Inc., 2003
M68HC11E Family — Rev. 5 Data Sheet
MOTOROLA 3
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Page 4
Revision History
Freescale Semiconductor, Inc.
Revision History
Date
May, 2001 3.1
June, 2001 3.2
December,
2001
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July, 2002 4
June, 2003 5
cale Semiconductor,
Revision
Level
3.3
Description
2.3.3.1 System Configuration Register — Addition to NOCOP bit
description
Added 10.21 EPROM Characteristics 191
10.21 EPROM Characteristics — For clarity, addition to note 2 following the
table
7.7.2 Serial Communications Control Register 1 — SCCR1 bit 4 (M)
description corrected
10.7 MC68L11E9/E20 DC Electrical Characteristics — Title changed to
include the MC68L11E20
10.8 MC68L11E9/E20 Supply Currents and Power Dissipation — Title
changed to include the MC68L11E20
10.10 MC68L11E9/E20 Control Timing — Title changed to include the
MC68L11E20
10.12 MC68L11E9/E20 Peripheral Port Timing — Title changed to include
the MC68L11E20
10.14 MC68L11E9/E20 Analog-to-Digital Converter Characteristics —
Title changed to include the MC68L11E20
10.16 MC68L11E9/E20 Expansion Bus Timing Characteristics — Title
changed to include the MC68L11E20
10.18 MC68L11E9/E20 Serial Peirpheral Interface Characteristics — Title
changed to include the MC68L11E20
— Title changed to include the MC68L11E20 191
11.4 Extended Voltage Device Ordering Information (3.0 Vdc to 5.5 Vdc)
— Updated table to include MC68L1120
Format updated to current publications standards Throughout
1.4.6 Non-Maskable Interrupt (XIRQ/VPPE) — Added Caution note
pertaining to EPROM programming of the MC68HC711E9 device only.
10.21 EPROM Characteristics — Added note pertaining to EPROM
programming of the MC68HC711E9 device only.
Page
Number(s)
49
191
123
169
170
173
179
183
185
188
197
26
191
Frees
Data Sheet M68HC11E Family — Rev. 5
4 Revision History MOTOROLA
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Data Sheet — M68HC11E Family
Section 1. General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Section 2. Operating Modes and On-Chip Memory. . . . . . . . . . . . . . .33
Section 3. Analog-to-Digital (A/D) Converter . . . . . . . . . . . . . . . . . . . .63
List of Sections
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Section 4. Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . .73
Section 5. Resets and Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Section 6. Parallel Input/Output (I/O) Ports . . . . . . . . . . . . . . . . . . . .109
Section 7. Serial Communications Interface (SCI). . . . . . . . . . . . . . .117
Section 8. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . .133
Section 9. Timing System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
Section 10. Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . .165
Section 11. Ordering Information
and Mechanical Specifications . . . . . . . . . . . . . . . . . . .193
Appendix A. Development Support. . . . . . . . . . . . . . . . . . . . . . . . . . .203
Appendix B. EVBU Schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
AN1060 — M68HC11 Bootstrap Mode . . . . . . . . . . . . . . . . . . . . . . . .209
EB184 — Enabling the Security Feature
on the MC68HC711E9 Devices with PCbug11
on the M68HC711E9PGMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255
EB188 — Enabling the Security Feature
on M68HC811E2 Devices with PCbug11
on the M68HC711E9PGMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259
EB296 — Programming MC68HC711E9 Devices
with PCbug11 and the M68HC11EVBU . . . . . . . . . . . . . . . . . . . . .263
M68HC11E Family — Rev. 5 Data Sheet
MOTOROLA List of Sections 5
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List of Sections
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cale Semiconductor,
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Data Sheet M68HC11E Family — Rev. 5
6 List of Sections MOTOROLA
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Freescale Semiconductor, Inc.
Technical Data — M68HC11E Family
Section 1. General Description
1.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.3 Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.4 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.4.1 V
1.4.2 RESET
1.4.3 Crystal Driver and External Clock Input
1.4.4 E-Clock Output (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.4.5 Interrupt Request (IRQ
1.4.6 Non-Maskable Interrupt (XIRQ
1.4.7 MODA and MODB (MODA/LIR
1.4.7.1 V
1.4.8 STRA/AS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.4.9 STRB/R/W
1.4.10 Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.4.10.1 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.4.10.2 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.4.10.3 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.4.10.4 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.4.10.5 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.2 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.2.1 Single-Chip Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.2.2 Expanded Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.2.3 Test Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.2.4 Bootstrap Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.3 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.3.1 RAM and Input/Output Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.3.2 Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
and VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
(XTAL and EXTAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
and VRH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
RL
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Section 2. Operating Modes and On-Chip Memory
Table of Contents
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
/V
). . . . . . . . . . . . . . . . . . . . . . . . 26
PPE
and MODB/V
) . . . . . . . . . . . . . 26
STBY
M68HC11E Family — Rev. 5 Data Sheet
MOTOROLA Table of Contents 7
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Table of Contents
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2.3.3 System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
2.3.3.1 System Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.3.3.2 RAM and I/O Mapping Register . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.3.3.3 System Configuration Options Register . . . . . . . . . . . . . . . . . . . . 51
2.4 EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.4.1 Programming an Individual EPROM Address. . . . . . . . . . . . . . . . . . 53
2.4.2 Programming the EPROM with Downloaded Data. . . . . . . . . . . . . . 54
2.4.3 EPROM and EEPROM Programming Control Register . . . . . . . . . . 54
2.5 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.5.1 EEPROM and CONFIG Programming and Erasure. . . . . . . . . . . . . 57
2.5.1.1 Block Protect Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.5.1.2 EPROM and EEPROM Programming Control Register . . . . . . . . 58
2.5.1.3 EEPROM Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.5.1.4 EEPROM Row Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.5.1.5 EEPROM Byte Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.5.1.6 CONFIG Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.5.2 EEPROM Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
cale Semiconductor,
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Section 3. Analog-to-Digital (A/D) Converter
3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.2.1 Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.2.2 Analog Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.2.3 Digital Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.2.4 Result Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.2.5 A/D Converter Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.2.6 Conversion Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.3 A/D Converter Power-Up and Clock Select . . . . . . . . . . . . . . . . . . . . . . 66
3.4 Conversion Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.5 Channel Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.6 Single-Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.7 Multiple-Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.8 Operation in Stop and Wait Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.9 A/D Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.10 A/D Converter Result Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Section 4. Central Processor Unit (CPU)
4.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.2 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.2.1 Accumulators A, B, and D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.2.2 Index Register X (IX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.2.3 Index Register Y (IY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
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4.2.4 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.2.5 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.2.6 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.2.6.1 Carry/Borrow (C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.2.6.2 Overflow (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.2.6.3 Zero (Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.2.6.4 Negative (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.2.6.5 Interrupt Mask (I). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.2.6.6 Half Carry (H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.2.6.7 X Interrupt Mask (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.2.6.8 STOP Disable (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.3 Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.4 Opcodes and Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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4.5 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.5.1 Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.5.2 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.5.3 Extended. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.5.4 Indexed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.5.5 Inherent. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.5.6 Relative. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.6 Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Section 5. Resets and Interrupts
5.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.2.1 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.2.2 External Reset (RESET
5.2.3 Computer Operating Properly (COP) Reset. . . . . . . . . . . . . . . . . . . 90
5.2.4 Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.2.5 System Configuration Options Register . . . . . . . . . . . . . . . . . . . . . . 92
5.2.6 Configuration Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.3.1 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.3.2 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.3.3 Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.3.4 Real-Time Interrupt (RTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.3.5 Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.3.6 Computer Operating Properly (COP) . . . . . . . . . . . . . . . . . . . . . . . . 95
5.3.7 Serial Communications Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . 95
5.3.8 Serial Peripheral Interface (SPI). . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
5.3.9 Analog-to-Digital (A/D) Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . 95
5.3.10 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
5.4 Reset and Interrupt Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5.4.1 Highest Priority Interrupt and Miscellaneous Register . . . . . . . . . . . 97
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
M68HC11E Family — Rev. 5 Data Sheet
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5.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.5.1 Interrupt Recognition and Register Stacking . . . . . . . . . . . . . . . . . 100
5.5.2 Non-Maskable Interrupt Request (XIRQ
5.5.3 Illegal Opcode Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5.5.4 Software Interrupt (SWI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5.5.5 Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5.5.6 Reset and Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5.6 Low-Power Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.6.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
) . . . . . . . . . . . . . . . . . . . . 100
Section 6. Parallel Input/Output (I/O) Ports
6.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.2 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.3 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
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6.4 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.5 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.6 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.7 Handshake Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.8 Parallel I/O Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Section 7. Serial Communications Interface (SCI)
7.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
7.2 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
7.3 Transmit Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
7.4 Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
7.5 Wakeup Feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
7.5.1 Idle-Line Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
7.5.2 Address-Mark Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
7.6 SCI Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
7.7 SCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
7.7.1 Serial Communications Data Register . . . . . . . . . . . . . . . . . . . . . . 122
7.7.2 Serial Communications Control Register 1. . . . . . . . . . . . . . . . . . . 123
7.7.3 Serial Communications Control Register 2. . . . . . . . . . . . . . . . . . . 124
7.7.4 Serial Communication Status Register. . . . . . . . . . . . . . . . . . . . . . 125
7.7.5 Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
7.8 Status Flags and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
7.9 Receiver Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Data Sheet M68HC11E Family — Rev. 5
10 Table of Contents MOTOROLA
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Table of Contents
Section 8. Serial Peripheral Interface (SPI)
8.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
8.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
8.3 SPI Transfer Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
8.4 Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
8.5 SPI Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
8.5.1 Master In/Slave Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
8.5.2 Master Out/Slave In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
8.5.3 Serial Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
8.5.4 Slave Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
8.6 SPI System Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
8.7 SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
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8.7.1 Serial Peripheral Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 138
8.7.2 Serial Peripheral Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . 139
8.7.3 Serial Peripheral Data I/O Register . . . . . . . . . . . . . . . . . . . . . . . . 140
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Section 9. Timing System
9.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
9.2 Timer Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
9.3 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
9.3.1 Timer Control Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
9.3.2 Timer Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
9.3.3 Timer Input Capture 4/Output Compare 5 Register . . . . . . . . . . . . 148
9.4 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
9.4.1 Timer Output Compare Registers. . . . . . . . . . . . . . . . . . . . . . . . . . 149
9.4.2 Timer Compare Force Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
9.4.3 Output Compare Mask Register. . . . . . . . . . . . . . . . . . . . . . . . . . . 152
9.4.4 Output Compare Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
9.4.5 Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
9.4.6 Timer Control Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
9.4.7 Timer Interrupt Mask 1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . 154
9.4.8 Timer Interrupt Flag 1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
9.4.9 Timer Interrupt Mask 2 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . 155
9.4.10 Timer Interrupt Flag Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
9.5 Real-Time Interrupt (RTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
9.5.1 Timer Interrupt Mask Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . 157
9.5.2 Timer Interrupt Flag Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
9.5.3 Pulse Accumulator Control Register. . . . . . . . . . . . . . . . . . . . . . . . 159
9.6 Computer Operating Properly (COP) Watchdog Function . . . . . . . . . . 159
9.7 Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
9.7.1 Pulse Accumulator Control Register. . . . . . . . . . . . . . . . . . . . . . . . 161
9.7.2 Pulse Accumulator Count Register. . . . . . . . . . . . . . . . . . . . . . . . . 162
9.7.3 Pulse Accumulator Status and Interrupt Bits . . . . . . . . . . . . . . . . . 162
M68HC11E Family — Rev. 5 Data Sheet
MOTOROLA Table of Contents 11
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Table of Contents
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Section 10. Electrical Characteristics
10.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
10.2 Maximum Ratings for Standard
and Extended Voltage Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
10.3 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
10.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
10.5 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
10.6 Supply Currents and Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . 168
10.7 MC68L11E9/E20 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . 169
10.8 MC68L11E9/E20 Supply Currents
and Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
10.9 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
10.10 MC68L11E9/E20 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
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10.11 Peripheral Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
10.12 MC68L11E9/E20 Peripheral Port Timing . . . . . . . . . . . . . . . . . . . . . . . 179
10.13 Analog-to-Digital Converter Characteristics . . . . . . . . . . . . . . . . . . . . . 182
10.14 MC68L11E9/E20 Analog-to-Digital
Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
10.15 Expansion Bus Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 184
10.16 MC68L11E9/E20 Expansion Bus Timing Characteristics. . . . . . . . . . . 185
10.17 Serial Peripheral Interface Timing Characteristics . . . . . . . . . . . . . . . . 187
10.18 MC68L11E9/E20 Serial Peripheral Interface Characteristics. . . . . . . . 188
10.19 EEPROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
10.20 MC68L11E9/E20 EEPROM Characteristics. . . . . . . . . . . . . . . . . . . . . 191
10.21 EPROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Section 11. Ordering Information
and Mechanical Specifications
11.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
11.2 Standard Device Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . 193
11.3 Custom ROM Device Ordering Information . . . . . . . . . . . . . . . . . . . . . 196
11.4 Extended Voltage Device Ordering Information
(3.0 Vdc to 5.5 Vdc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
11.5 52-Pin Plastic-Leaded Chip Carrier (Case 778). . . . . . . . . . . . . . . . . . 198
11.6 52-Pin Windowed Ceramic-Leaded Chip Carrier
(Case 778B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
11.7 64-Pin Quad Flat Pack (Case 840C) . . . . . . . . . . . . . . . . . . . . . . . . . . 200
11.8 52-Pin Thin Quad Flat Pack (Case 848D) . . . . . . . . . . . . . . . . . . . . . . 201
Data Sheet M68HC11E Family — Rev. 5
12 Table of Contents MOTOROLA
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11.9 56-Pin Dual in-Line Package (Case 859). . . . . . . . . . . . . . . . . . . . . . . 202
11.10 48-Pin Plastic DIP (Case 767) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table of Contents
Appendix A. Development Support
A.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
A.2 Motorola M68HC11 E-Series Development Tools . . . . . . . . . . . . . . . . 203
A.3 EVS — Evaluation System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
A.4 Motorola Modular Development System (MMDS11) . . . . . . . . . . . . . . 204
A.5 SPGMR11 — Serial Programmer for M68HC11 MCUs . . . . . . . . . . . . 206
Appendix B. EVBU Schematic
MC68HC11EVBU Schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
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AN1060
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AN1060 — M68HC11 Bootstrap Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
EB184
EB184 — Enabling the Security Feature on the MC68HC711E9
Devices with PCbug11 on the M68HC711E9PGMR . . . . . . . . . . . . . . . . . 255
EB188
EB188 — Enabling the Security Feature on M68HC811E2
Devices with PCbug11 on the M68HC711E9PGMR . . . . . . . . . . . . . . . . . 259
EB296
EB296 — Programming MC68HC711E9 Devices
with PCbug11 and the M68HC11EVBU . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
M68HC11E Family — Rev. 5 Data Sheet
MOTOROLA Table of Contents 13
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Table of Contents
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Freescale Semiconductor, Inc.
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Data Sheet M68HC11E Family — Rev. 5
14 Table of Contents MOTOROLA
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Page 15
Freescale Semiconductor, Inc.
Data Sheet — M68HC11E Family
Section 1. General Description
1.1 Introduction
This document contains a detailed description of the M68HC11 E series of 8-bit
microcontroller units (MCUs). These MCUs all combine the M68HC11 central
processor unit (CPU) with high-performance, on-chip peripherals.
The E series is comprised of many devices with various configurations of:
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• Random-access memory (RAM)
• Read-only memory (ROM)
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1.2 Features
• Erasable programmable read-only memory (EPROM)
• Electrically erasable programmable read-only memory (EEPROM)
• Several low-voltage devices are also available.
With the exception of a few minor differences, the operation of all E-series MCUs
is identical. A fully static design and high-density complementary metal-oxide
semiconductor (HCMOS) fabrication process allow the E-series devices to operate
at frequencies from 3 MHz to dc with very low power consumption.
Features of the E-series devices include:
• M68HC11 CPU
• Power-saving stop and wait modes
• Low-voltage devices available (3.0–5.5 Vdc)
• 0, 256, 512, or 768 bytes of on-chip RAM, data retained during standby
• 0, 12, or 20 Kbytes of on-chip ROM or EPROM
• 0, 512, or 2048 bytes of on-chip EEPROM with block protect for security
• 2048 bytes of EEPROM with selectable base address in the MC68HC811E2
• Asynchronous non-return-to-zero (NRZ) serial communications interface
(SCI)
• Additional baud rates available on MC68HC(7)11E20
• Synchronous serial peripheral interface (SPI)
• 8-channel, 8-bit analog-to-digital (A/D) converter
M68HC11E Family — Rev. 5 Data Sheet
MOTOROLA General Description 15
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Page 16
General Description
• 16-bit timer system:
• 8-bit pulse accumulator
• Real-time interrupt circuit
• Computer operating properly (COP) watchdog system
• 38 general-purpose input/output (I/O) pins:
Freescale Semiconductor, Inc.
– Three input capture (IC) channels
– Four output compare (OC) channels
– One additional channel, selectable as fourth IC or fifth OC
– 16 bidirectional I/O pins
– 11 input-only pins
– 11 output-only pins
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1.3 Structure
• Several packaging options:
– 52-pin plastic-leaded chip carrier (PLCC)
– 52-pin windowed ceramic leaded chip carrier (CLCC)
– 52-pin plastic thin quad flat pack, 10 mm x 10 mm (TQFP)
– 64-pin quad flat pack (QFP)
– 48-pin plastic dual in-line package (DIP), MC68HC811E2 only
– 56-pin plastic shrink dual in-line package, .070-inch lead spacing (SDIP)
See Figure 1-1 for a functional diagram of the E-series MCUs. Differen ces among
devices are noted in the table accompanying Figure 1-1.
Data Sheet M68HC11E Family — Rev. 5
16 General Description MOTOROLA
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Page 17
MODA/
LIR
MODB/
V
STBY
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XTAL EXTAL E IRQ XIRQ/V
PPE*
RESET
General Description
Structure
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MODE CONTROL
TIMER
SYSTEM
COPPULSE ACCUMULATOR
OC2
OC3
OC4
OC5/IC4/OC1
IC1
PAI
PORT A
PA7/PAI
PA6/OC2/OC1
PA5/OC3/OC1
* V
applies only to devices with EPROM/OTPROM.
PPE
IC2
PA2/IC1
PA1/IC2
PA4/OC4/OC1
PA3/OC5/IC4/OC1
OSC
CLOCK LOGIC
PERIODIC INTERRUPT
BUS EXPANSION
ADDRESS
IC3
PORT B
PA0/IC3
PB7/ADDR15
PB6/ADDR14
M68HC11 CPU
ADDRESS/DATA
STROBE AND HANDSHAKE
PARALLEL I/O
PB1/ADDR9
PB5/ADDR13
PB4/ADDR12
PB0/ADDR8
PB3/ADDR11
PB2/ADDR10
PC7/ADDR7/DATA7
INTERRUPT
CONTROL
PORT C
PC6/ADDR6/DATA6
PC5/ADDR5/DATA5
PC4/ADDR4/DATA4
LOGIC
PC3/ADDR3/DATA3
PC2/ADDR2/DATA2
PC1/ADDR1/DATA1
R/W
STRB
STRB/R/W
PC0/ADDR0/DATA0
SERIAL
PERIPHERAL
AS
INTERFACE
STRA
STRA/AS
DEVICE
MC68HC11E0
MC68HC11E1
MC68HC11E9
MC68HC711E9
MC68HC11E20
MC68HC711E20
SPI
SCK
SS
CONTROL
PD5/SS
PORT D
PD4/SCK
ROM OR EPROM
(SEE TABLE)
EEPROM
(SEE TABLE)
RAM
(SEE TABLE)
COMMUNICATION
INTERFACE
MOSI
MISO
TxD
RxD
PD1/TxD
PD2/MISO
PD0/RxD
ROM
—
—
12 K
—
20 K
—
PD3/MOSI
RAM
512
512
512
512
768
768
256 — — 2048MC68HC811E2
SERIAL
SCI
A/D CONVERTER
PORT E
PE7/AN7
PE6/AN6
EPROM
—
—
—
12 K
—
20 K
PE5/AN5
PE4/AN4
PE3/AN3
EEPROM
PE2/AN2
—
512
512
512
512
512
V
DD
V
SS
V
RH
V
RL
PE1/AN1
PE0/AN0
Figure 1-1. M68HC11 E-Series Block Diagram
M68HC11E Family — Rev. 5 Data Sheet
MOTOROLA General Description 17
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General Description
1.4 Pin Descriptions
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Freescale Semiconductor, Inc.
M68HC11 E-series MCUs are available packaged in:
• 52-pin plastic-leaded chip carrier (PLCC)
• 52-pin windowed ceramic leaded chip carrier (CLCC)
• 52-pin plastic thin quad flat pack, 10 mm x 10 mm (TQFP)
• 64-pin quad flat pack (QFP)
• 48-pin plastic dual in-line package (DIP), MC68HC811E2 only
• 56-pin plastic shrink dual in-line package, .070-inch lead spacing (SDIP)
Most pins on these MCUs serve two or more functions, as described in the
following paragraphs. Refer to Figure 1-2, Figure 1-3, Figure 1-4, Figure 1-5, and
Figure 1-6 which show the M68HC11 E-series pin assignments for the
PLCC/CLCC, QFP, TQFP, SDIP, and DIP packages.
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EXTAL
STRB/R/WESTRA/AS
7
6
5
4
XTAL
8
PC0/ADDR0/DATA0
PC1/ADDR1/DATA1
PC2/ADDR2/DATA2
PC3/ADDR3/DATA3
PC4/ADDR4/DATA4
PC5/ADDR5/DATA5
PC6/ADDR6/DATA6
PC7/ADDR7/DATA7
RESET
* XIRQ/V
PD0/RxD
* V
applies only to devices with EPROM/OTPROM.
PPE
PPE
IRQ
9
10
11
12
13
14
15
16
17
18
19
20
2122232425
PD1/TxD
PD2/MISO
M68HC11 E SERIES
PD4/SCK
PD3/MOSI
STBY
MODA/LIR
MODB/V
VSSVRHVRLPE7/AN7
312
26
2728293031
DD
V
PD5/SS
PA7/PAI/OC1
52
51
50
PA6/OC2/OC1
PA5/OC3/OC1
PA4/OC4/OC1
PE3/AN3
PE6/AN648PE2/AN2
49
PA2/IC132PA1/IC2
PA3/OC5/IC4/OC1
47
45
44
43
42
41
40
39
38
37
36
35
34
33
PE5/AN546
PE1/AN1
PE4/AN4
PE0/AN0
PB0/ADDR8
PB1/ADDR9
PB2/ADDR10
PB3/ADDR11
PB4/ADDR12
PB5/ADDR13
PB6/ADDR14
PB7/ADDR15
PA0/IC3
Figure 1-2. Pin Assignments for 52-Pin PLCC and CLCC
Data Sheet M68HC11E Family — Rev. 5
18 General Description MOTOROLA
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General Description
Pin Descriptions
PA1/IC2
PA2/IC1
PA3/OC5/IC4/OC1NCNC
64
63626160595857
PA0/IC3
PB7/ADDR15
PB6/ADDR14
PB5/ADDR13
PB4/ADDR12
PB3/ADDR11
PB2/ADDR10
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PB1/ADDR9
PB0/ADDR8
PE0/AN0
PE4/AN4
PE1/AN1
PE5/AN5
1. V
PPE
1
NC
2
NC
3
NC
4
5
6
7
8
9
10
11
12
13
14
15
16
17181920212223
PE2/AN2
PE6/AN6
PE3/AN3
applies only to devices with EPROM/OTPROM.
PA4/OC4/OC1
PA5/OC3/OC1
PA6/OC2/OC1
PA7/PAI/OC1
56
M68HC11 E SERIES
25
24
PE7/AN7
RL
V
SS
RH
VSSV
V
STBY
MODB/V
PD5/SS
VDDPD4/SCK
55
26
NC
PD3/MOSI
5352515049
54
2829303132
27
E
STRA/AS
MODA/LIR
Figure 1-3. Pin Assignments for 64-Pin QFP
cale Semiconductor,
SS
PD2/MISO
PD1/TxD
V
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
NC
EXTAL
STRB/R/W
NC
PD0/RxD
IRQ
XIRQ/V
NC
RESET
PC7/ADDR7/DATA7
PC6/ADDR6/DATA6
PC5/ADDR5/DATA5
PC4/ADDR4/DATA4
PC3/ADDR3/DATA3
PC2/ADDR2/DATA2
PC1/ADDR1/DATA1
NC
PC0/ADDR0/DATA0
XTAL
PPE
(1)
Frees
M68HC11E Family — Rev. 5 Data Sheet
MOTOROLA General Description 19
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Page 20
General Description
nc...
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Freescale Semiconductor, Inc.
PA0/IC3
PB7/ADDR15
PB6/ADDR14
PB5/ADDR13
PB4/ADDR12
PB3/ADDR11
PB2/ADDR10
PB1/ADDR9
PB0/ADDR8
PE0/AN0
PE4/AN4
PE1/AN1
PE5/AN5
PA1/IC2
PA2/IC1
PA3/OC5/IC4/OC1
PA4/OC4/OC1
PA5/OC3/OC1
PA6/OC2/OC1
PA7/PAI/OC1
52
51504948474645
1
2
3
4
5
6
7
8
9
10
11
12
13
M68HC11 E SERIES
1415161718192021222423
PD5/SS
VDDPD4/SCK
44
PD3/MOSI
PD2/MISO
PD1/TxD
42
43
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
25
26
PD0/RxD
IRQ
XIRQ/V
RESET
PC7/ADDR7/DATA7
PC6/ADDR6/DATA6
PC5/ADDR5/DATA5
PC4/ADDR4/DATA4
PC3/ADDR3/DATA3
PC2/ADDR2/DATA2
PC1/ADDR1/DATA1
PC0/ADDR0/DATA0
XTAL
PPE
(1)
cale Semiconductor,
Frees
RL
SS
RH
V
V
V
PE2/AN2
PE6/AN6
PE3/AN3
PE7/AN7
1. V
applies only to devices with EPROM/OTPROM.
PPE
STBY
MODB/V
E
STRA/AS
MODA/LIR
EXTAL
STRB/R/W
Figure 1-4. Pin Assignments for 52-Pin TQFP
Data Sheet M68HC11E Family — Rev. 5
20 General Description MOTOROLA
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Page 21
Freescale Semiconductor, Inc.
General Description
Pin Descriptions
V
SS
STBY
EXTAL
XTAL
PPE
IRQ
EV
SS
V
DD
V
SS
1
2
3
4
E
5
6
7
8
9
10
11
12
13
14
15
M68HC11 E SERIES
16
17
18
19
20
21
22
23
24
25
26
27
28
MODB/V
MODA/LIR
STRA/AS
STRB/R/W
PC0/ADDR0/DATA0
PC1/ADDR1/DATA1
PC2/ADDR2/DATA2
PC3/ADDR3/DATA3
PC4/ADDR4/DATA4
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cale Semiconductor,
PC5/ADDR5/DATA5
PC6/ADDR6/DATA6
PC7/ADDR7/DATA7
RESET
* XIRQ/V
PD0/RxD
PD1/TxD
PD2/MISO
PD3/MOSI
PD4/SCK
PD5/SS
* V
applies only to devices with EPROM/OTPROM.
PPE
Figure 1-5. Pin Assignments for 56-Pin SDIP
EV
56
SS
V
RH
55
V
54
RL
PE7/AN7
53
PE3/AN3
52
PE6/AN6
51
PE2/AN2
50
PE5/AN5
49
PE1/AN1
48
PE4/AN4
47
PE0/AN0
46
PB0/ADDR8
45
PB1/ADDR9
44
PB2/ADDR10
43
PB3/ADDR11
42
PB4/ADDR12
41
PB5/ADDR13
40
PB6/ADDR14
39
PB7/ADDR15
38
PA0/IC3
37
PA1/IC2
36
PA2/IC1
35
PA3/OC5/IC4/OC1
34
PA4/OC4/OC1
33
PA5/OC3/OC1
32
PA6/OC2/OC1
31
PA7/PAI/OC1
30
EV
29
DD
Frees
M68HC11E Family — Rev. 5 Data Sheet
MOTOROLA General Description 21
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Page 22
General Description
Freescale Semiconductor, Inc.
PA7/PAI/OC1
PA6/OC2/OC1
PA5/OC3/OC1
PA4/OC4/OC1
PA3/OC5/IC4/OC1
PA2/IC1
PA1/IC2
PA0/IC3
PB7/ADDR15
PB6/ADDR14
PB5/ADDR13
PB4/ADDR12
PB3/ADDR11
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PB2/ADDR10
PB1/ADDR9
PB0/ADDR8
PE0/AN0
PE1/AN1
PE2/AN2
PE3/AN3
MODB/V
V
V
V
STBY
1
2
3
4
5
6
7
8
9
10
11
MC68HC811E2
12
13
14
15
16
17
18
19
20
21
RL
22
RH
23
SS
24
Figure 1-6. Pin Assignments for 48-Pin DIP (MC68HC811E2)
cale Semiconductor,
V
48
DD
PD5/SS
47
PD4/SCK46
PD3/MOSI
45
PD2/MISO44
PD1/TxD
43
PD0/RxD42
IRQ
41
XIRQ
40
RESET
39
PC7/ADDR7/DATA7
38
PC6/ADDR6/DATA6
37
PC5/ADDR5/DATA5
36
PC4/ADDR4/DATA4
35
PC3/ADDR3/DATA3
34
PC2/ADDR2/DATA2
33
PC1/ADDR1/DATA1
32
PC0/ADDR0/DATA0
31
XTAL
30
EXTAL
29
STRB/R/W
28
E27
STRA/AS26
25
MODA/LIR
Frees
Data Sheet M68HC11E Family — Rev. 5
22 General Description MOTOROLA
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Page 23
1.4.1 VDD and VSS
Freescale Semiconductor, Inc.
General Description
Pin Descriptions
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I
cale Semiconductor,
Frees
Power is supplied to the MCU through V
and VSS. VDD is the power supply, VSS
DD
is ground. The MCU operates from a single 5-volt (nominal) power supply.
Low-voltage devices in the E series operate at 3.0–5.5 volts.
Very fast signal transitions occur on the MCU pins. The short rise and fall times
place high, short duration current demands on the power supply. To prevent noise
problems, provide good power supply bypassing at the MCU. Also, use bypass
capacitors that have good
high-frequency characteristics and situate them as close to the MCU as possible.
Bypass requirements vary, depending on how heavily the MCU pins are loaded.
V
DD
2
IN
RESET
MC34(0/1)64
GND
3
V
DD
4.7 kΩ
1
TO RESET
OF M68HC11
Figure 1-7. External Reset Circuit
MANUAL
RESET SWITCH
4.7 kΩ
V
DD
IN
RESET
V
DD
4.7 kΩ
MC34064
GND
V
DD
4.7 kΩ
TO RESET
OF M68HC11
1.0 µF
IN
RESET
MC34164
GND
OPTIONAL POWER-ON DELAY AND MANUAL RESET SWITCH
Figure 1-8. External Reset Circuit with Delay
M68HC11E Family — Rev. 5 Data Sheet
MOTOROLA General Description 23
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Page 24
General Description
1.4.2 RESET
Freescale Semiconductor, Inc.
A bidirectional control signal, RESET
known startup state. It also acts as an open-drain output to indicate that an internal
failure has been detected in either the clock monitor or computer operating prop erly
(COP) watchdog circuit. The CPU distinguishes between internal and external
reset conditions by sensing whether the reset pin rises to a logic 1 in less than t wo
E-clock cycles after a reset has occurred. See Figure 1-7 and Figure 1-8.
, acts as an input to initialize the MCU to a
CAUTION: Do not connect an external resistor capacitor (RC) power-up delay circuit to the
reset pin of M68HC11 devices because the circuit charge time constant can cause
the device to misinterpret the type of reset that occurred.
Because the CPU is not able to fetch and execute instructions properly when V
falls below the minimum operating voltage level, reset must be controlled. A
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cale Semiconductor,
low-voltage inhibit (LVI) circuit is required primarily for protection of EEPROM
contents. However, since the configuration register (CONFIG) value is read from
the EEPROM, protection is required even if the EEPROM array is not being used.
Presently, there are several economical ways to solve this problem. For example,
two good external components for LVI reset are:
1. The Seiko S0854HN (or other S805 series devices):
a. Extremely low power (2 µA)
a. TO-92 package
a. Limited temperature range, –20°C to +70°C
a. Available in various trip-point voltage ranges
2. The Motorola MC34064:
a. TO-92 or SO-8 package
a. Draws about 300 µA
a. Temperature range –40°C to 85°C
a. Well controlled trip point
a. Inexpensive
DD
Frees
Refer to Section 5. Resets and Interrupts for further information.
1.4.3 Crystal Driver and External Clock Input (XTAL and EXTAL)
These two pins provide the interface for either a crystal or a CMOS- compatible
clock to control the internal clock generator circuitry. The frequency applied to
these pins is four times higher than the desired E-clock rate.
The XTAL pin must be left unterminated when an external CMOS- compatible clock
input is connected to the EXTAL pin. The XTAL output is normally intended to drive
only a crystal. Refer to Figure 1-9 and Figure 1-10.
Data Sheet M68HC11E Family — Rev. 5
24 General Description MOTOROLA
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Page 25
Freescale Semiconductor, Inc.
General Description
Pin Descriptions
CAUTION: In all cases, use caution around the oscillator pins. Load capacitances shown in the
oscillator circuit are specified by the crystal manufacturer and should include all
stray layout capacitances.
C
EXTAL
L
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cale Semiconductor,
Frees
1.4.4 E-Clock Output (E)
E is the output connection for the internally generated E clock. The signal from E
is used as a timing reference. The frequency of the E-clock outpu t is one fourth that
of the input frequency at the XTAL and EXTAL pins. When E-clock output is low,
an internal process is taking place. When it is high, data is being accessed.
All clocks, including the E clock, are halted when the MCU is in stop mode. To
reduce RFI emissions, the E-clock output of most E-series devices can be disabled
while operating in single-chip modes.
The E-clock signal is always enabled on the MC68HC811E2.
MCU
XTAL
Figure 1-9. Common Parallel Resonant Crystal Connections
EXTAL
MCU
XTAL
Figure 1-10. External Oscillator Connections
NC
10 MΩ
4 x E
CRYSTAL
C
L
4 x E
CMOS-COMPATIBLE
EXTERNAL OSCILLATOR
1.4.5 Interrupt Request (IRQ
The IRQ
MCU. Either negative edge-sensitive triggering or level-sensitive triggering is
program selectable (OPTION register). IRQ
triggering at reset. When using IRQ
connect an external pullup resistor, typically 4.7 kΩ, to V
M68HC11E Family — Rev. 5 Data Sheet
MOTOROLA General Description 25
)
input provides a means of applying asynchronous interrupt requests to the
is always configured to level-sensitive
in a level-sensitive wired-OR configuration,
.
DD
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Page 26
General Description
Freescale Semiconductor, Inc.
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cale Semiconductor,
Frees
1.4.6 Non-Maskable Interrupt (XIRQ/V
The XIRQ
reset initialization. During reset, the X bit in the condition code register (CCR) is set
and any interrupt is masked until MCU software enables it. Because the XIRQ
is level-sensitive, it can be connected to a multiple-source wired-OR network with
an external pullup resistor to V
interrupt.
Whenever XIRQ
drive the interrupt input with an open-drain type of driver to avoid contention
between outputs.
NOTE: IRQ
source of IRQ
There should be a single pullup resistor near the MCU interrupt input pin (typically
4.7 kΩ). There must also be an interlock mechanism at each interrupt source so
that the source holds the interrupt line low until the MCU recognizes and
acknowledges the interrupt request. If one or more interrupt sources are still
pending after the MCU services a request, the interrupt line will still be held low and
the MCU will be interrupted again as soon as the interrupt mask bit in the MCU is
cleared (normally upon return from an interrupt). Refer to Section 5. Resets and
Interrupts.
V
PPE
EPROM/OTPROM programming. On devices without EPROM/OTPROM, this pin
is only an XIRQ
input provides a means of requesting a non-maskable interrupt after
or IRQ is used with multiple interrupt sources each source must
must be configured for level-sensitive operation if there is more than one
interrupt.
is the input for the 12-volt nominal programming voltage required for
input.
CAUTION: During EPROM programming of the MC68HC711E9 device, the V
may latch-up and be damaged if the input current is not limited to 10 mA. For mo re
information please refer to MC68HC711E9 8-Bit Microcontroller Unit Mask Set
Errata 3 (Motorola document order number 68HC711E9MSE3.
1.4.7 MODA and MODB (MODA/LIR
During reset, MODA and MODB select one of the four operating modes:
• Single-chip mode
• Expanded mode
• Test mode
• Bootstrap mode
and MODB/V
PPE
)
input
. XIRQ is often used as a power loss detect
DD
STBY
pin circuitry
PPE
)
Refer to Section 2. Operating Modes and On-Chip Memory.
After the operating mode has been selected, the load instru ction register (LIR
provides an open-drain output to indicate that execution of an instruction has
begun. A series of E-clock cycles occurs during execution of each instruction. The
signal goes low during the first E-clock cycle of each instruction (opcode fetch).
LIR
This output is provided for assistance in program debugging.
Data Sheet M68HC11E Family — Rev. 5
26 General Description MOTOROLA
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) pin
Page 27
Freescale Semiconductor, Inc.
General Description
Pin Descriptions
The V
When the voltage on this pin is more than one MOS threshold (about 0.7 volts)
above the V
from this signal rather than the V
without V
removed and must remain low until V
1.4.7.1 V
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1.4.8 STRA/AS
cale Semiconductor,
1.4.9 STRB/R/W
and VRH
RL
These two inputs provide the reference voltages for the analog-to-digital (A/D)
converter circuitry:
•V
•V
For proper A/D converter operation:
•V
•V
The strobe A (STRA) and address strobe (AS) pin performs either o f two separate
functions, depending on the operating mode:
• In single-chip mode, STRA performs an input handshake (strobe input)
• In the expand ed multiplexed mode, AS provides an address strobe function.
AS can be used to demultiplex the address and data signals at port C. Refer to
Section 2. Operating Modes and On-Chip Memory.
The strobe B (STRB) and read/write (R/W
a data bus direction indicator, depending on the operating mode.
pin is used to input random-access memory (RAM) standby power.
STBY
voltage, the internal RAM and part of the reset logic are powered
DD
input. This allows RAM contents to be retained
DD
power applied to the MCU. Reset must be driven low before VDD is
DD
has been restored to a valid level.
DD
is the low reference, typically 0 Vdc.
RL
is the high reference.
RH
should be at least 3 Vdc greater than VRL.
RH
and VRH should be between VSS and VDD.
RL
function.
) pin act as either an output strobe or as
Frees
In single-chip operating mode, STRB acts as a programmable strobe for
handshake with other parallel devices. Refer to Section 6. Parallel Input/Output
(I/O) Ports for further information.
In expanded multiplexed operating mode, R/W
transfers on the external data bus. A low on the R/W
written to the external data bus. A high on this pin indicates that a read cycle is in
progress. R/W
double-byte store. It is possible for data to be driven out of port C, if internal read
visibility (IRV) is enabled and an internal address is read, even though R/W
high-impedance state. Refer to Section 2. Operating Modes and On-Chip
Memory for more information about IRVNE (internal read visibility not E).
M68HC11E Family — Rev. 5 Data Sheet
MOTOROLA General Description 27
stays low during consecutive data bus write cycles, such as a
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is used to indicate the direction of
pin indicates data is being
is in a
Page 28
General Description
1.4.10 Port Signals
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1.4.10.1 Port A
Freescale Semiconductor, Inc.
Port pins have different functions in different operating modes. Pin functions for
port A, port D, and port E are independent of operating modes. Port B and port C,
however, are affected by operating mode. Port B provides eight general-purpose
output signals in single-chip operating modes. When the microcontroller is in
expanded multiplexed operating mode, port B pins are the eight high-order address
lines.
Port C provides eight general-purpose input/output signals when the MCU is in the
single-chip operating mode. When the microcontroller is in the expanded
multiplexed operating mode, port C pins are a multiplexed address/data bus.
Refer to Table 1-1 for a functional description of the 40 port signals within different
operating modes. Terminate unused inputs and input/output (I/O) pins configured
as inputs high or low.
cale Semiconductor,
Frees
In all operating modes, port A can be configured for three timer input capture (IC)
functions and four timer output compare (OC) functions. An additional pin can be
configured as either the fourth IC or the fifth OC. Any port A pin that is not currently
being used for a timer function can be used as either a general-purpose input or
output line. Only port A pins PA7 and PA3 have an associated data direction
control bit that allows the pin to be selectively configured as input or output. Bits
DDRA7 and DDRA3 located in PACTL register control data direction for PA7 and
PA3, respectively. All other port A pins are fixed as either input or output.
PA7 can function as general-purpose I/O or as timer output compare for OC1. PA7
is also the input to the pulse accumulator, even while functioning as a
general-purpose I/O or an OC1 output.
PA6–PA4 serve as either general-purpose outputs, timer input captures, or timer
output compare 2–4. In addition, PA6–PA4 can be controlled by OC1.
PA3 can be a general-purpose I/O pin or a timer IC/OC pin. Timer functions
associated with this pin include OC1 and IC4/OC5. IC4/OC5 is software selectable
as either a fourth input capture or a fifth output compare. PA3 can also be
configured to allow OC1 edges to trigger IC4 captures.
PA2–PA0 serve as general-purpose inputs or as IC1–IC3.
PORTA can be read at any time. Reads of pins configured as inputs return the logic
level present on the pin. Pins configured as outputs return the logic level present
at the pin driver input. If written, PORTA stores the data in an internal latch, bits 7
and 3. It drives the pins only if they are configured as outputs. Writes to PORTA do
not change the pin state when pins are configured for timer input captures or output
compares. Refer to Section 6. Parallel Input/Output (I/O) Ports.
Data Sheet M68HC11E Family — Rev. 5
28 General Description MOTOROLA
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Page 29
Freescale Semiconductor, Inc.
Table 1-1. Port Signal Functions
General Description
Pin Descriptions
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cale Semiconductor,
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Port/Bit
PA0 PA0/IC3
PA1 PA1/IC2
PA2 PA2/IC1
PA3 PA3/OC5/IC4/OC1
PA4 PA4/OC4/OC1
PA5 PA5/OC3/OC1
PA6 PA6/OC2/OC1
PA7 PA7/PAI/OC1
PB0 PB0 ADDR8
PB1 PB1 ADDR9
PB2 PB2 ADDR10
PB3 PB3 ADDR11
PB4 PB4 ADDR12
PB5 PB5 ADDR13
PB6 PB6 ADDR14
PB7 PB7 ADDR15
PC0 PC0 ADDR0/DATA0
PC1 PC1 ADDR1/DATA1
PC2 PC2 ADDR2/DATA2
PC3 PC3 ADDR3/DATA3
PC4 PC4 ADDR4/DATA4
PC5 PC5 ADDR5/DATA5
PC6 PC6 ADDR6/DATA6
PC7 PC7 ADDR7/DATA7
PD0 PD0/RxD
PD1 PD1/TxD
PD2 PD2/MISO
PD3 PD3/MOSI
PD4 PD4/SCK
PD5 PD5/SS
— STRA AS
—STRB R/W
PE0 PE0/AN0
PE1 PE1/AN1
PE2 PE3/AN2
PE3 PE3/AN3
PE4 PE4/AN4
PE5 PE5/AN5
PE6 PE6/AN6
PE7 PE7/AN7
Single-Chip and
Bootstrap Modes
Expanded and
Test Modes
M68HC11E Family — Rev. 5 Data Sheet
MOTOROLA General Description 29
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Page 30
General Description
1.4.10.2 Port B
During single-chip operating modes, all port B pins are general-purpose output
pins. During MCU reads of this port, the level sensed at the input side of the po rt B
output drivers is read. Port B can also be used in simple strobed output mode. In
this mode, an output pulse appears at the STRB signal each time data is written to
port B.
In expanded multiplexed operating modes, all of the port B pins act as high order
address output signals. During each MCU cycle, bits 15–8 of the address bus are
output on the PB7–PB0 pins. The PORTB register is treated as an external
address in expanded modes.
1.4.10.3 Port C
Freescale Semiconductor, Inc.
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cale Semiconductor,
Frees
While in single-chip operating modes, all port C pins are general-purpose I/O pins.
Port C inputs can be latched into an alternate PORTCL register by providing an
input transition to the STRA signal. Port C can also be used in full handshake
modes of parallel I/O where the STRA input and STRB output act as handshake
control lines.
When in expanded multiplexed modes, all port C pins are configured as
multiplexed address/data signals. During the address portion of each MCU cycle,
bits 7–0 of the address are output on the PC7–PC0 pins. During the data portion
of each MCU cycle (E high), PC7–PC0 are bidirectional data signals,
DATA7–DATA0. The direction of data at the port C pins is indicated by the R/W
signal.
The CWOM control bit in the PIOC register disables the port C P-channel output
driver. CWOM simultaneously affects all eight bits of port C. Because the
N-channel driver is not affected by CWOM, setting CWOM causes port C to
become an open-drain type output port suitable for wired-OR operation.
In wired-OR mode:
• When a port C bit is at logic level 0, it is driven low by the N-channel driver.
• When a port C b it is at logic level 1, the associated pin has high-impedance,
as neither the N-channel nor the P-channel devices are active.
It is customary to have an external pullup resistor on lines that are driven by
open-drain devices. Port C can only be configured for wired-OR operation when
the MCU is in single-chip mode. Refer to Section 6. Parallel Input/Output (I/O)
Ports for additional information about port C functions.
Data Sheet M68HC11E Family — Rev. 5
30 General Description MOTOROLA
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Page 31
Freescale Semiconductor, Inc.
1.4.10.4 Port D
Pins PD5–PD0 can be used for general-purpose I/O signals. These pins alternately
serve as the serial communication interface (SCI) and serial peripheral interface
(SPI) signals when those subsystems are enabled.
• PD0 is the receive data input (RxD) signal for the SCI.
• PD1 is the transmit data output (TxD) signal for the SCI.
• PD5–PD2 are dedicated to the SPI:
– PD2 is the master in/slave out (MISO) signal.
– PD3 is the master out/slave in (MOSI) signal.
– PD4 is the serial clock (SCK) signal.
– PD5 is the slave select (SS
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1.4.10.5 Port E
General Description
Pin Descriptions
) input.
cale Semiconductor,
Frees
Use port E for general-purpose or analog-to-digital (A/D) inputs.
CAUTION: If high accuracy is required for A/D conversions, avoid reading port E during
sampling, as small disturbances can reduce the accuracy of that result.
M68HC11E Family — Rev. 5 Data Sheet
MOTOROLA General Description 31
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Page 32
General Description
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Freescale Semiconductor, Inc.
cale Semiconductor,
Frees
Data Sheet M68HC11E Family — Rev. 5
32 General Description MOTOROLA
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Page 33
Freescale Semiconductor, Inc.
Data Sheet — M68HC11E Family
Section 2. Operating Modes and On-Chip Memory
2.1 Introduction
This section contains information about the operating modes and the on-chip
memory for M68HC11 E-series MCUs. Except for a few minor differences,
operation is identical for all devices in the E series. Differences are noted where
necessary.
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2.2 Operating Modes
cale Semiconductor,
Frees
The values of the mode select inputs MODB and MODA during reset determine the
operating mode. Single-chip and expanded multiplexed are the normal modes.
Each of the two normal modes is paired with a special mode:
2.2.1 Single-Chip Mode In single-chip mode, ports B and C and strobe pins A (STRA) and B (STRB) are
available for general-purpose parallel input/output (I/O). In this mode, all software
needed to control the MCU is contained in internal resources. If present, read-only
memory (ROM) and/or erasable, programmable read-only memory (EPROM) will
always be enabled out of reset, ensuring that the reset and interrupt vectors will be
available at locations $FFC0–$FFFF.
NOTE: For the MC68HC811E2, the vector locations are the same; however, they are
contained in the 2048-byte EEPROM array.
• In single-chip mode only on-chip memory is available.
• Expanded mode, however, allows access to external memory.
• Bootstrap, a variation of the single-chip mode, is a special mode that
executes a bootloader program in an internal bootstrap ROM.
• Test is a special mode that allows privileged access to internal resources.
2.2.2 Expanded Mode
In expanded operating mode, the MCU can access the full 64-Kbyte address
space. The space includes:
• The same on-chip memory addresses used for single-chip mode
• Addresses for external peripherals and memory devices
M68HC11E Family — Rev. 5 Data Sheet
MOTOROLA Operating Modes and On-Chip Memory 33
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Page 34
Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
The expansion bus is made up of ports B and C, and control signals AS (address
strobe) and R/W
8-bit data bus to be multiplexed on the same pins. During the first half of each bus
cycle address information is present. During the second half of each bus cycle the
pins become the bidirectional data bus. AS is an active-high latch enable signal fo r
an external address latch. Address information is allowed through the transparent
latch while AS is high and is latched when AS drives low.
(read/write). R/W and AS allow the low-order address and the
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The address, R/W
, and AS signals are active and valid for all bus cycles, including
accesses to internal memory locations. The E clock is used to enable external
devices to drive data onto the internal data bus during the second half of a read bus
cycle (E clock high). R/W
when data is being written to the internal data bus. R/W
controls the direction of data transfers. R/W drives low
will remain low during
consecutive data bus write cycles, such as when a double-byte store occurs.
Refer to Figure 2-1.
NOTE: The write enable signal for an external memory is the NAND of the E clock and th e
inverted R/W
signal.
MCU
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
AS
R/W
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
HC373
Q1
D1
Q2
D2
Q3
D3
Q4
D4
Q5
D5
Q6
D6
Q7
D7
Q8
D8
LE
OE
E
ADDR8
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
WE
OE
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
Figure 2-1. Address/Data Demultiplexing
2.2.3 Test Mode
Test mode, a variation of the expanded mode, is primarily used during Motorola’s
internal production testing; however, it is accessible for programming the
Data Sheet M68HC11E Family — Rev. 5
34 Operating Modes and On-Chip Memory MOTOROLA
For More Information On This Product,
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Page 35
Freescale Semiconductor, Inc.
configuration (CONFIG) register, programming calibration data into electrically
erasable, programmable read-only memory (EEPROM), and supporting emulation
and debugging during development.
2.2.4 Bootstrap Mode
When the MCU is reset in special bootstrap mode, a small on-chip read-only
memory (ROM) is enabled at address $BF00–$BFFF. The ROM contains a
bootloader program and a special set of interrupt and reset vectors. The MCU
fetches the reset vector, then executes the bootloader.
Bootstrap mode is a special variation of the single-chip mode. Bootstrap mode
allows special-purpose programs to be entered into internal random-access
memory (RAM). When bootstrap mode is selected at reset, a small bootstrap ROM
becomes present in the memory map. Reset and interrupt vectors are located in
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this ROM at $BFC0–$BFFF. The bootstrap ROM contains a small program which
initializes the serial communications interface (SCI) and allows the user to
download a program into on-chip RAM. The size of the downloaded program can
be as large as the size of the on-chip RAM. After a 4-character delay, or after
receiving the character for the highest address in RAM, control passes to the
loaded program at $0000. Refer to Figure 2-2, Figure 2-3, Figure 2-4, Figure 2-5,
and Figure 2-6.
Use of an external pullup resistor is required when using the SCI transmitter pin
because port D pins are configured for wired-OR operation by the bootloader. In
bootstrap mode, the interrupt vectors are directed to RAM. This allows the use of
interrupts through a jump table. Refer to the application note AN1060 entitled
M68HC11 Bootstrap Mode, that is included in this data book.
2.3 Memory Map
cale Semiconductor,
The operating mode determines memory mapping and whether external
addresses can be accessed. Refer to Figure 2-2, Figure 2-3, Figure 2-4,
Figure 2-5, and Figure 2-6, which illustrate the memory maps for each of the three
families comprising the M68HC11 E series of MCUs.
Operating Modes and On-Chip Memory
Memory Map
Frees
Memory locations for on-chip resources are the same for both expanded and
single-chip modes. Control bits in the configuration (CONFIG) register allow
EPROM and EEPROM (if present) to be disabled from the memory map. The RAM
is mapped to $0000 after reset. It can be placed at any 4-Kbyte boundary ($x000 )
by writing an appropriate value to the RAM and I/O map register (INIT). The 64-byte
register block is mapped to $1000 after reset and also can be placed at any 4-Kbyte
boundary ($x000) by writing an appropriate value to the INIT register. If RAM and
registers are mapped to the same boundary, the first 64 bytes of RAM will be
inaccessible.
Refer to Figure 2-7, which details the MCU register and control bit assignments.
Reset states shown are for single-chip mode only.
M68HC11E Family — Rev. 5 Data Sheet
MOTOROLA Operating Modes and On-Chip Memory 35
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Operating Modes and On-Chip Memory
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$0000
$1000
$B600
$D000
$FFFF
$0000
$1000
$B600
$D000
EXT
EXT EXT
EXPANDED
BOOTSTRAP SPECIAL
Figure 2-2. Memory Map for MC68HC11E0
EXT
EXT EXT
EXT
EXT
TEST
EXT
EXT
0000
512 BYTES RAM
01FF
1000
64-BYTE REGISTER BLOCK
103F
BOOT
BF00
ROM
BFFF
NORMAL
FFC0
MODES
INTERRUPT
FFFF
VECTORS
0000
512 BYTES RAM
01FF
1000
64-BYTE REGISTER BLOCK
103F
B600
512 BYTES EEPROM
B7FF
BOOT
BF00
ROM
BFFF
BFC0
BFFF
BFC0
BFFF
SPECIAL MODES
INTERRUPT
VECTORS
SPECIAL MODES
INTERRUPT
VECTORS
NORMAL
FFC0
MODES
INTERRUPT
FFFF
$FFFF
EXPANDED
BOOTSTRAP SPECIAL
TEST
VECTORS
Figure 2-3. Memory Map for MC68HC11E1
Data Sheet M68HC11E Family — Rev. 5
36 Operating Modes and On-Chip Memory MOTOROLA
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Page 37
Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
Memory Map
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$0000
$1000
$B600
$D000
$FFFF
$0000
$1000
$9000
$B600
$D000
SINGLE
CHIP
0000
EXT
EXT EXT
EXT
EXPANDED
BOOTSTRAP SPECIAL
EXT
EXT
TEST
01FF
1000
103F
B600
B7FF
BF00
BFFF
D000
FFFF
Figure 2-4. Memory Map for MC68HC(7)11E9
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
512 BYTES RAM
64-BYTE REGISTER BLOCK
512 BYTES EEPROM
BOOT
ROM
12 KBYTES ROM/EPROM
0000
768 BYTES RAM
02FF
1000
64-BYTE REGISTER BLOCK
103F
9000
8 KBYTES ROM/EPROM *
AFFF
B600
512 BYTES EEPROM
B7FF
BOOT
BF00
ROM
BFFF
12 KBYTES ROM/EPROM *
D000
BFC0
BFFF
FFC0
FFFF
BFC0
BFFF
SPECIAL MODES
INTERRUPT
VECTORS
NORMAL
MODES
INTERRUPT
VECTORS
SPECIAL MODES
INTERRUPT
VECTORS
NORMAL
FFC0
MODES
INTERRUPT
VECTORS
$FFFF
SINGLE
CHIP
* 20 Kbytes ROM/EPROM are contained in two segments of 8 Kbytes and 12 Kbytes each.
EXPANDED
BOOTSTRAP SPECIAL
TEST
FFFF
FFFF
Figure 2-5. Memory Map for MC68HC(7)11E20
M68HC11E Family — Rev. 5 Data Sheet
MOTOROLA Operating Modes and On-Chip Memory 37
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Page 38
Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
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$0000
$1000
$F800
$FFFF
SINGLE
CHIP
EXT
EXT EXT
EXPANDED
BOOTSTRAP SPECIAL
EXT
TEST
0000
256 BYTES RAM
00FF
1000
64-BYTE REGISTER BLOCK
103F
BOOT
BF00
ROM
BFFF
2048 BYTES EEPROM
F800
FFFF
BFC0
BFFF
FFC0
FFFF
SPECIAL MODES
INTERRUPT
VECTORS
NORMAL
MODES
INTERRUPT
VECTORS
Figure 2-6. Memory Map for MC68HC811E2
Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0
Port A Data Register
$1000
$1001 Reserved R R R R R R R R
Parallel I/O Control Register
$1002
Port C Data Register
$1003
Port B Data Register
$1004
(PORTA)
See page 110.
(PIOC)
See page 115.
(PORTC)
See page 111.
(PORTB)
See page 111.
Read:
Write:
Reset: I 0 0 0 I I I I
Read:
Write:
Reset: 0 0 0 0 0 U 1 1
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
STAF STAI CWOM HNDS OIN PLS EGA INVB
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
= Unimplemented R = Reserved U = Unaffected
I = Indeterminate after reset
Figure 2-7. Register and Control Bit Assignments (Sheet 1 of 6)
Data Sheet M68HC11E Family — Rev. 5
38 Operating Modes and On-Chip Memory MOTOROLA
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Page 39
Freescale Semiconductor, Inc.
Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0
Port C Latched Register
$1005
$1006 Reserved R R R R R R R R
(PORTCL)
See page 112.
Read:
Write:
Reset: Indeterminate after reset
Operating Modes and On-Chip Memory
Memory Map
PCL7 PCL6 PCL5 PCL4 PCL3 PCL2 PCL1 PCL0
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Port C Data Direction Register
$1007
Port D Data Register
$1008
Port D Data Direction Register
$1009
Port E Data Register
$100A
Timer Compare Force Register
$100B
Output Compare 1 Mask Register
$100C
Output Compare 1 Data Register
$100D
Timer Counter Register High
$100E
Timer Counter Register Low
$100F
Timer Input Capture 1 Register
$1010
Timer Input Capture 1 Register
$1011
(DDRC)
See page 112.
(PORTD)
See page 112.
(DDRD)
See page 113.
(PORTE)
See page 113.
(CFORC)
See page 151.
(OC1M)
See page 152.
(OC1D)
See page 152.
(TCNTH)
See page 153.
(TCNTL)
See page 153.
High (TIC1H)
See page 147.
Low (TIC1L)
See page 147.
Read:
DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: U U I I I I I I
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: 0 0 0 0 0 0 0 0
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: Indeterminate after reset
0 0 PD5 PD4 PD3 PD2 PD1 PD0
DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0
FOC1 FOC2 FOC3 FOC4 FOC5
OC1M7 OC1M6 OC1M5 OC1M4 OC1M3
OC1D7 OC1D6 OC1D5 OC1D4 OC1D3
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
= Unimplemented R = Reserved U = Unaffected
I = Indeterminate after reset
Figure 2-7. Register and Control Bit Assignments (Sheet 2 of 6)
M68HC11E Family — Rev. 5 Data Sheet
MOTOROLA Operating Modes and On-Chip Memory 39
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Operating Modes and On-Chip Memory
Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0
Read:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: 11 1 1 1 1 11
Read:
Write:
Reset: 11 1 1 1 1 11
Read:
Write:
Reset: 11 1 1 1 1 11
Read:
Write:
Reset: 11 1 1 1 1 11
Read:
Write:
Reset: 11 1 1 1 1 11
Read:
Write:
Reset: 11 1 1 1 1 11
Read:
Write:
Reset: 11 1 1 1 1 11
Read:
Write:
Reset: 11 1 1 1 1 11
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
I = Indeterminate after reset
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Timer Input Capture 2 Register
$1012
TImer Input Capture 2 Register
$1013
Timer Input Capture 3 Register
$1014
Timer Input Capture 3 Register
$1015
Timer Output Compare 1 Register
$1016
Timer Output Compare 1 Register
$1017
Timer Output Compare 2 Register
$1018
Timer Output Compare 2 Register
$1019
Timer Output Compare 3 Register
$101A
Timer Output Compare 3 Register
$101B
Timer Output Compare 4 Register
$101C
Timer Output Compare 4 Register
$101D
High (TIC2H)
See page 147.
Low (TIC2L)
See page 147.
High (TIC3H)
See page 147.
Low (TIC3L)
See page 147.
High (TOC1H)
See page 149.
Low (TOC1L)
See page 149.
High (TOC2H)
See page 150.
Low (TOC2L)
See page 150.
High (TOC3H)
See page 150.
Low (TOC3L)
See page 150.
High (TOC4H)
See page 150.
Low (TOC4L)
See page 150.
= Unimplemented R = Reserved U = Unaffected
Figure 2-7. Register and Control Bit Assignments (Sheet 3 of 6)
Data Sheet M68HC11E Family — Rev. 5
40 Operating Modes and On-Chip Memory MOTOROLA
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Page 41
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Freescale Semiconductor, Inc.
Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0
Timer Input Capture 4/Output
$101E
$101F
$1020
$1021
$1022
$1023
$1024
$1025
$1026
$1027
$1028
$1029
Compare 5 Register High
(TI4/O5) See page 148.
Timer Input Capture 4/Output
Compare 5 Register Low
(TI4/O5) See page 148.
Timer Control Register 1
Timer Control Register 2
Timer Interrupt Mask 1 Register
Timer Interrupt Flag 1
Timer Interrupt Mask 2 Register
Timer Interrupt Flag 2
Pulse Accumulator Control
Pulse Accumulator Count
Serial Peripheral Control Register
Serial Peripheral Status Register
(TCTL1)
See page 153.
(TCTL2)
See page 146.
(TMSK1)
See page 154.
(TFLG1)
See page 154.
(TMSK2)
See page 155.
(TFLG2)
See page 158.
Register (PACTL)
See page 159.
Register (PACNT)
See page 162.
(SPCR)
See page 138.
(SPSR)
See page 139.
Read:
Write:
Reset: 11 1 1 1 1 11
Read:
Write:
Reset: 11 1 1 1 1 11
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: 0 0 0 0 0 1 U U
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Operating Modes and On-Chip Memory
Memory Map
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
OM2 OL2 OM3 OL3 OM4 OL4 OM5 OL5
EDG4B EDG4A EDG1B EDG1A EDG2B EDG2A EDG3B EDG3A
OC1I OC2I OC3I OC4I I4/O5I IC1I IC2I IC3I
OC1F OC2F OC3F OC4F I4/O5F IC1F IC2F IC3F
TOI RTII PAOVI PAII
TOF RTIF PAOVF PAIF
DDRA7 PAEN PAMOD PEDGE DDRA3 I4/O5 RTR1 RTR0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SPIE SPE DWOM MSTR CPOL CPHA SPR1 SPR0
SPIF WCOL
= Unimplemented R = Reserved U = Unaffected
I = Indeterminate after reset
MODF
PR1 PR0
Figure 2-7. Register and Control Bit Assignments (Sheet 4 of 6)
M68HC11E Family — Rev. 5 Data Sheet
MOTOROLA Operating Modes and On-Chip Memory 41
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Operating Modes and On-Chip Memory
Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: 0 0 0 0 0 U U U
Read:
Write:
Reset: I I 0 0 0 0 0 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: 1 1 0 0 0 0 0 0
Read:
Write:
Reset: Indeterminate after reset
Read: CCF
Write:
Reset: 0 0 Indeterminate after reset
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: Indeterminate after reset
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: Indeterminate after reset
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: Indeterminate after reset
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: 0 0 0 1 1 1 1 1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TCLR SCP2
R8 T8
TIE TCIE RIE ILIE TE RE RWU SBK
TDRE TC RDRF IDLE OR NF FE
R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 R2/T2 R1/T1 R0/T0
I = Indeterminate after reset
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Serial Peripheral Data I/O
$102A
$102B
Serial Communications Control
$102C
Serial Communications Control
$102D
Serial Communications Status
$102E
1. SCP2 adds ÷39 to SCI prescaler and is present only in MC68HC(7)11E20.
Serial Communications Data
$102F
Analog-to-Digital Control Status
$1030
$1031
$1032
$1033
$1034
$1035
Register (SPDR)
See page 140.
Baud Rate Register
(BAUD)
See page 126.
Register 1 (SCCR1)
See page 123.
Register 2 (SCCR2)
See page 124.
Register (SCSR)
See page 125.
Register (SCDR)
See page 122.
Register (ADCTL)
See page 69.
Analog-to-Digital Results
Register 1 (ADR1)
See page 71.
Analog-to-Digital Results
Register 2 (ADR2)
See page 71.
Analog-to-Digital Results
Register 3 (ADR3)
See page 71.
Analog-to-Digital Results
Register 4 (ADR4)
See page 71.
Block Protect Register
(BPROT)
See page 58.
(1)
SCP1 SCP0 RCKB SCR2 SCR1 SCR0
M WAKE
SCAN MULT CD CC CB CA
PTCON BPRT3 BPRT2 BPRT1 BPRT0
= Unimplemented R = Reserved U = Unaffected
Figure 2-7. Register and Control Bit Assignments (Sheet 5 of 6)
Data Sheet M68HC11E Family — Rev. 5
42 Operating Modes and On-Chip Memory MOTOROLA
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Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0
EPROM Programming Control
$1036
$1037 Reserved R R R R R R R R
1. MC68HC711E20 only
$1038 Reserved R R R R R R R R
Register (EPROG)
See page 59.
Read:
(1)
Write:
Reset: 0 0 0 0 0 0 0 0
MBE
Operating Modes and On-Chip Memory
Memory Map
ELAT EXCOL EXROW T1 T0 PGM
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System Configuration Options
$1039
Arm/Reset COP Timer Circuitry
$103A
$103B
$103C
$103D
$103E Reserved R R R R R R R R
$103F
$103F
1. Can be written only once in first 64 cycles out of reset in normal modes or at any time during special modes.
2. MC68HC711E9 only
3. MC68HC811E2 only
Programming Control Register
Highest Priority I Bit Interrupt and
Miscellaneous Register (HPRIO)
RAM and I/O Mapping Register
System Configuration Register
System Configuration Register
Register (OPTION)
See page 51.
Register (COPRST)
See page 91.
EPROM and EEPROM
(PPROG) See page 54.
See page 46.
See page 50.
(CONFIG)
See page 48.
(CONFIG)
See page 48.
Read:
Write:
Reset: 0 0 0 1 0 0 0 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: 0 0 0 0 0 1 1 0
Read:
(INIT)
Write:
Reset: 0 0 0 0 0 0 0 1
Read:
Write:
Reset: 0 0 0 0 U U 1 U
Read:
(3)
Write:
Reset: 1 1 1 1 U U 1 1
ADPU CSEL IRQE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ODD EVEN ELAT
RBOOT SMOD MDA IRV(NE) PSEL3 PSEL2 PSEL1 PSEL0
RAM3 RAM2 RAM1 RAM0 REG3 REG2 REG1 REG0
EE3 EE2 EE1 EE0 NOSEC NOCOP
= Unimplemented R = Reserved U = Unaffected
I = Indeterminate after reset
(1)
(2)
(1)
DLY
BYTE ROW ERASE EELAT EPGM
CME CR1
NOSEC NOCOP ROMON EEON
(1)
CR0
EEON
(1)
Figure 2-7. Register and Control Bit Assignments (Sheet 6 of 6)
M68HC11E Family — Rev. 5 Data Sheet
MOTOROLA Operating Modes and On-Chip Memory 43
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Operating Modes and On-Chip Memory
2.3.1 RAM and Input/Output Mapping
Hardware priority is built into RAM and I/O mapping. Registers have priority over
RAM and RAM has priority over ROM. When a lower priority resource is mapped
at the same location as a higher priority resource, a read/write of a location results
in a read/write of the higher priority resource only. For example, if both the register
block and the RAM are mapped to the same location, only the register block will be
accessed. If RAM and ROM are located at the same position, RAM has priority.
The fully static RAM can be used to store instructions, variables, and temporary
data. The direct addressing mode can access RAM locations using a 1-byte
address operand, saving program memory space and execution time, depending
on the application.
RAM contents can be preserved during periods of processor inactivity by two
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methods, both of which reduce power consumption. They are:
1. In the software-based stop mode, the clocks are stopped while V
the MCU. Because power supply current is directly related to operating
frequency in CMOS integrated circuits, only a very small amount of leakage
exists when the clocks are stopped.
2. In the second method, the MODB/V
battery backup or from a second power supply. Figure 2-8 shows a typical
standby voltage circuit for a standard 5-volt device. Adjustments to the
circuit must be made for devices that operate at lower voltages. Using the
MODB/V
a significant amount of external circuitry is operating from V
used to maintain RAM contents, reset must be held low whenever V
below normal operating level. Refer to Section 5. Resets and Interrupts.
STBY
cale Semiconductor,
Frees
powers
DD
pin can supply RAM power from a
STBY
pin may require external hardware, but can be justified when
. If V
4.8-V
NiCd
DD
V
DD
MAX
690
V
DD
V
OUT
V
BATT
+
4.7 k
TO MODB/V
OF M68HC11
STBY
STBY
DD
is
is
Figure 2-8. RAM Standby MODB/V
The bootloader program is contained in the internal bootstrap ROM. This ROM,
which appears as internal memory space at locations $BF00–$BFFF, is enabled
only if the MCU is reset in special bootstrap mode.
Data Sheet M68HC11E Family — Rev. 5
44 Operating Modes and On-Chip Memory MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Connections
STBY
Page 45
Freescale Semiconductor, Inc.
In expanded modes, the ROM/EPROM/OTPROM (if present) is enabled out of
reset and located at the top of the memory map if the ROMON bit in the CONFIG
register is set. ROM or EPROM is enabled out of reset in single-chip and bootstrap
modes, regardless of the state of ROMON.
For devices with 512 bytes of EEPROM, the EEPROM is located at $B600–$B7FF
and has the same read cycle time as the internal ROM. The 512 bytes of EEPROM
cannot be remapped to other locations.
For the MC68HC811E2, EEPROM is located at $F800–$FFFF and can be
remapped to any 4-Kbyte boundary. EEPROM mapping control bits (EE[3:0] in
CONFIG) determine the location of the 2048 bytes of EEPROM and are present
only on the MC68HC811E2. Refer to 2.3.3.1 System Configuration Register for
a description of the MC68HC811E2 CONFIG register.
Operating Modes and On-Chip Memory
Memory Map
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2.3.2 Mode Selection
EEPROM can be programmed or erased by software and an on-chip charge pump,
allowing EEPROM changes using the single V
The four mode variations are selected by the logic states of the MODA and MODB
pins during reset. The MODA and MODB logic levels determine the logic state of
SMOD and the MDA control bits in the highest priority I-bit interrupt and
miscellaneous (HPRIO) register.
After reset is released, the mode select pins no longer influence the MCU ope rating
mode. In single-chip operating mode, the MODA pin is connected to a logic level 0.
In expanded mode, MODA is normally connected to V
of 4.7 kΩ. The MODA pin also functions as the load instruction register LIR
when the MCU is not in reset. The open-drain active low LIR
during the first E cycle of each instruction. The MODB pin also functions as standby
power input (V
.
V
DD
Refer to Table 2-1, which is a summary of mode pin operation, the mode control
bits, and the four operating modes.
), which allows RAM contents to be maintained in absence of
STBY
Table 2-1. Hardware Mode Select Summary
supply.
DD
through a pullup resistor
DD
output pin drives low
pin
Input Levels
at Reset
MODB MODA RBOOT SMOD MDA
1 0 Single chip 0 0 0
1 1 Expanded 0 0 1
00Bootstrap110
01Special test011
M68HC11E Family — Rev. 5 Data Sheet
MOTOROLA Operating Modes and On-Chip Memory 45
For More Information On This Product,
Go to: www.freescale.com
Mode
Control Bits in HPRIO
(Latched at Reset)
Page 46
Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
A normal mode is selected when MODB is logic 1 during reset. One of thre e reset
vectors is fetched from address $FFFA–$FFFF, and program execution begins
from the address indicated by this vector. If MODB is logic 0 during reset, the
special mode reset vector is fetched from addresses $BFFA–$BFFF, and software
has access to special test features. Refer to Section 5. Resets and Interrupts.
Address: $103C
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
Resets:
Single chip:0000 0110
Expanded: 0 0 1 0 0110
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Bootstrap:1100 0110
Test:0111 0110
1. The reset values depend on the mode selected at the RESET pin rising edge.
RBOOT
(1)
SMOD
(1)
MDA
(1)
IRV(NE)
(1)
PSEL3 PSEL2 PSEL1 PSEL0
cale Semiconductor,
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Figure 2-9. Highest Priority I-Bit Interrupt and Miscellaneous
Register (HPRIO)
RBOOT — Read Bootstrap ROM Bit
Valid only when SMOD is set (bootstrap or special test mode); can be written
only in special modes
0 = Bootloader ROM disabled and not in map
1 = Bootloader ROM enabled and in map at $BE00–$BFFF
SMOD and MDA — Special Mode Select and Mode Select A Bits
The initial value of SMOD is the inverse of the logic level present on the MODB
pin at the rising edge of reset. The initial value of MDA equals the logic level
present on the MODA pin at the rising edge of reset. These two bits can be read
at any time. They can be written anytime in special modes. MDA can be written
only once in normal modes. SMOD cannot be set once it has been cleared.
Input
Mode
MODB MODA SMOD MDA
1 0 Single chip 0 0
1 1 Expanded 0 1
0 0 Bootstrap 1 0
0 1 Special test 1 1
Latched at Reset
Data Sheet M68HC11E Family — Rev. 5
46 Operating Modes and On-Chip Memory MOTOROLA
For More Information On This Product,
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Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
Memory Map
IRV(NE) — Internal Read Visibility (Not E) Bit
IRVNE can be written once in any mode. In expanded modes, IRVNE
determines whether IRV is on or off. In special test mode, IRVNE is reset to 1.
In all other modes, IRVNE is reset to 0. For the MC68HC811E2, this bit is IRV
and only controls the internal read visibility function.
0 = No internal read visibility on external bus
1 = Data from internal reads is driven out the external data bus.
In single-chip modes this bit determines whether the E clock drives out from the
chip. For the MC68HC811E2, this bit has no meaning or effect in single-chip and
bootstrap modes.
0 = E is driven out from the chip.
1 = E pin is driven low. Refer to the following table.
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cale Semiconductor,
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Mode
Single chip 0 On Off E Once
Expanded 0 On Off IRV Once
Bootstrap 0 On Off E Once
Special test 1 On On IRV Once
IRVNE Out
of Reset
E Clock Out
of Reset
IRV Out
of Reset
IRVNE
Affects Only
PSEL[3:0] — Priority Select Bits
Refer to Section 5. Resets and Interrupts.
2.3.3 System Initialization
Registers and bits that control initialization and the basic operation of the MCU are
protected against writes except under special circumstances. Table 2-2 lists
registers that can be written only once after reset or that must be written within th e
first 64 cycles after reset.
Table 2-2. Write Access Limited Registers
Operating
Mode
SMOD = 0 $x024 Timer interrupt mask 2 (TMSK2) Bits [1:0], once only Bits [7:2]
SMOD = 1 $x024 Timer interrupt mask 2 (TMSK2) — All, set or clear
Register
Address
$x035 Block protect register (BPROT) Clear bits, once only Set bits only
$x039 System configuration options (OPTION) Bits [5:4], bits [2:0], once only Bits [7:6], bit 3
$x03C
$x03D RAM and I/O map register (INIT) Yes, once only —
$x035 Block protect register (BPROT) — All, set or clear
$x039 System configuration options (OPTION) — All, set or clear
$x03C
$x03D RAM and I/O map register (INIT) — All, set or clear
Highest priority I-bit interrupt
and miscellaneous (HPRIO)
Highest priority I-bit interrupt an d
miscellaneous (HPRIO)
Register Name
Must be Written
in First 64 Cycles
See HPRIO description See HPRIO description
See HPRIO description See HPRIO description
Write
Anytime
IRVNE Can
Be Written
M68HC11E Family — Rev. 5 Data Sheet
MOTOROLA Operating Modes and On-Chip Memory 47
For More Information On This Product,
Go to: www.freescale.com
Page 48
Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
2.3.3.1 System Configuration Register
The system configuration register (CONFIG) consists of an EEPROM byte and
static latches that control the startup configuration of the MCU. The contents of the
EEPROM byte are transferred into static working latches during reset sequences.
The operation of the MCU is controlled directly by these latches and not by
CONFIG itself. In normal modes, changes to CONFIG do not affect operation of the
MCU until after the next reset sequence. When programming, the CONFIG register
itself is accessed. When the CONFIG register is read, the static latches are
accessed. See 2.5.1 EEPROM and CONFIG Programming and Erasure for
information on modifying CONFIG.
To take full advantage of the MCU’s functionality, customers can program the
CONFIG register in bootstrap mode. This can be accomplished by setting the
mode pins to logic 0 and downloading a small program to internal RAM. For more
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information, Motorola application note AN1060 entitled M68HC11 Bootstrap
Mode has been included at the back of this document. The downloadable talker
will consist of:
cale Semiconductor,
Frees
• Bulk erase
• Byte programming
• Communication server
All of this functionality is provided by PCbug11 which can be found on the Motorola
Web site at http://www.motorola.com/semiconductors/. For more information
on using PCbug11 to program an E-series device, Motorola engineering bulletin
EB296 entitled Programming MC68HC711E9 Devices with PCbug11 and the
M68HC11EVBU has been included at the back of this document.
NOTE: The CONFIG register on the 68HC11 is an EEPROM cell and must be
programmed accordingly.
Operation of the CONFIG register in the MC68HC811E2 differs from other devices
in the M68HC11 E series. See Figure 2-10 and Figure 2-11.
Address: $103F
Bit 7654321Bit 0
Read:
Write:
Resets:
Single chip:
Bootstrap:
Expanded:
Test:
U indicates a previously programmed bit. U(L) indicates that the bit resets to the logic level held in the latch prior to reset,
but the function of COP is controlled by the DISR bit in TEST1 register.
0
0
0
0
0
0
0
0
= Unimplemented
0
0
0
0
0
0
0
0
NOSEC NOCOP ROMON EEON
U
U
1
1
U
U(L)
U
U(L)
1
U
U
U
U
U
U
U
Figure 2-10. System Configuration Register (CONFIG)
Data Sheet M68HC11E Family — Rev. 5
48 Operating Modes and On-Chip Memory MOTOROLA
For More Information On This Product,
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Freescale Semiconductor, Inc.
Address: $103F
Read:
Write:
Resets:
Single chip:
Bootstrap:
Expanded:
Test:
U indicates a previously programmed bit. U(L) indicates that the bit resets to the logic level held in the latch prior to reset,
but the function of COP is controlled by the DISR bit in TEST1 register.
Operating Modes and On-Chip Memory
Memory Map
Bit 7654321Bit 0
EE3 EE2 EE1 EE0 NOSEC NOCOP
1
1
U
U
1
1
U
U
= Unimplemented
1
1
U
U
1
1
U
U
U
U
1
1
U
U(L)
U
U(L)
1
1
1
1
EEON
1
1
U
0
Figure 2-11. MC68HC811E2 System Configuration Register (CONFIG)
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EE[3:0] — EEPROM Mapping Bits
EE[3:0] apply only to MC68HC811E2 and allow the 2048 bytes of EEPROM to
be remapped to any 4-Kbyte boundary. See Table 2-3.
cale Semiconductor,
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Table 2-3. EEPROM Mapping
EE[3:0] EEPROM Location
0 0 0 0 $0800–$0FFF
0 0 0 1 $1800–$1FFF
0 0 1 0 $2800–$2FFF
0 0 1 1 $3800–$3FFF
0 1 0 0 $4800–$4FFF
0 1 0 1 $5800–$5FFF
0 1 1 0 $6800–$6FFF
0 1 1 1 $7800–$7FFF
1 0 0 0 $8800–$8FFF
1 0 0 1 $9800–$9FFF
1 0 1 0 $A800–$AFFF
1 0 1 1 $B800–$BFFF
1 1 0 0 $C800–$CFFF
1 1 0 1 $D800–$DFFF
1 1 1 0 $E800–$EFFF
1 1 1 1 $F800–$FFFF
M68HC11E Family — Rev. 5 Data Sheet
MOTOROLA Operating Modes and On-Chip Memory 49
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Page 50
Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
NOSEC — Security Disable Bit
NOSEC is invalid unless the security mask option is specified before the MCU
is manufactured. If the security mask option is omitted NOSEC always reads 1.
The enhanced security feature is available in the MC68S711E9 MCU. The
enhancement to the standard security feature protects the EPROM as well as
RAM and EEPROM.
0 = Security enabled
1 = Security disabled
NOCOP — COP System Disable Bit
Refer to Section 5. Resets and Interrupts.
1 = COP disabled
0 = COP enabled
ROMON — ROM/EPROM/OTPROM Enable Bit
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When this bit is 0, the ROM or EPROM is disabled and that memory space
becomes externally addressed. In single-chip mode, ROMON is forced to 1 to
enable ROM/EPROM regardless of the state of the ROMON bit.
0 = ROM disabled from the memory map
1 = ROM present in the memory map
cale Semiconductor,
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EEON — EEPROM Enable Bit
When this bit is 0, the EEPROM is disabled and that memory space becomes
externally addressed.
0 = EEPROM removed from the memory map
1 = EEPROM present in the memory map
2.3.3.2 RAM and I/O Mapping Register
The internal registers used to control the operation of the MCU can be relocated
on 4-Kbyte boundaries within the memory space with the use of the RAM and I/O
mapping register (INIT). This 8-bit special-purpose register can change the default
locations of the RAM and control registers within the MCU memory map. It can be
written only once within the first 64 E-clock cycles after a reset in normal modes,
and then it becomes a read-only register.
Address: $103D
Bit 7654321Bit 0
Read:
Write:
Reset: 00000001
RAM3 RAM2 RAM1 RAM0 REG3 REG2 REG1 REG0
Figure 2-12. RAM and I/O Mapping Register (INIT)
RAM[3:0] — RAM Map Position Bits
These four bits, which specify the upper hexadecimal digit of the RAM address,
control position of RAM in the memory map. RAM can be positioned at the
beginning of any 4-Kbyte page in the memory map. It is initialized to address
$0000 out of reset. Refer to Table 2-4.
Data Sheet M68HC11E Family — Rev. 5
50 Operating Modes and On-Chip Memory MOTOROLA
For More Information On This Product,
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Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
Memory Map
REG[3:0] — 64-Byte Register Block Position
These four bits specify the upper hexadecimal digit of the address for the
64-byte block of internal registers. The register block, positioned at the
beginning of any 4-Kbyte page in the memory map, is initialized to address
$1000 out of reset. Refer to Table 2-5.
Table 2-4. RAM Mapping Table 2-5. Register Mapping
RAM[3:0] Address REG[3:0] Address
0000 $0000–$0xFF 0000 $0000–$003F
0001 $1000–$1xFF 0001 $1000–$103F
0010 $2000–$2xFF 0010 $2000–$203F
0011 $3000–$3xFF 0011 $3000–$303F
0100 $4000–$4xFF 0100 $4000–$403F
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2.3.3.3 System Configuration Options Register
The 8-bit, special-purpose system configuration options register (OPTION) sets
cale Semiconductor,
internal system configuration options during initialization. The time protected
control bits, IRQE, DLY, and CR[1:0], can be written only once after a reset and
then they become read-only. This minimizes the possibility of any accidental
changes to the system configuration.
0101 $5000–$5xFF 0101 $5000–$503F
0110 $6000–$6xFF 0110 $6000–$603F
0111 $7000–$7xFF 0111 $7000–$703F
1000 $8000–$8xFF 1000 $8000–$803F
1001 $9000–$9xFF 1001 $9000–$903F
1010 $A000–$AxFF 1010 $A000–$A03F
1011 $B000–$BxFF 1011 $B000–$B03F
1100 $C000–$CxFF 1100 $C000–$C03F
1101 $D000–$DxFF 1101 $D000–$D03F
1110 $E000–$ExFF 1110 $E000–$E03F
1111 $F000–$FxFF 1111 $F000–$F03F
Frees
Address: $1039
Bit 7654321Bit 0
Read:
Write:
Reset: 00010000
1. Can be written only once in first 64 cycles out of reset in normal modes or at any time during
special modes.
ADPU CSEL IRQE
= Unimplemented
(1)
DLY
(1)
CME CR1
(1)
CR0
(1)
Figure 2-13. System Configuration Options Register (OPTION)
M68HC11E Family — Rev. 5 Data Sheet
MOTOROLA Operating Modes and On-Chip Memory 51
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Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
ADPU — Analog-to-Digital Converter Power-Up Bit
Refer to Section 3. Analog-to-Digital (A/D) Converter.
CSEL — Clock Select Bit
Selects alternate clock source for on-chip EEPROM charge pump. Refer to
2.5.1 EEPROM and CONFIG Programming and Erasure for more information
on EEPROM use.
CSEL also selects the clock source for the A/D converter, a function discussed
in Section 3. Analog-to-Digital (A/D) Converter.
IRQE — Configure IRQ
Refer to Section 5. Resets and Interrupts.
DLY — Enable Oscillator Startup Delay Bit
0 = The oscillator startup delay coming out of stop mode is bypassed and the
MCU resumes processing within about four bus cycles.
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1 = A delay of approximately 4000 E-clock cycles is imposed as the MCU is
started up from the stop power-saving mode. This delay allows the
crystal oscillator to stabilize.
CME — Clock Monitor Enable Bit
Refer to Section 5. Resets and Interrupts.
Bit 2 — Not implemented
Always reads 0
CR[1:0] — COP Timer Rate Select Bits
The internal E clock is divided by 2
These control bits determine a scaling factor for the watchdog timer. Refer to
Section 5. Resets and Interrupts.
2.4 EPROM/OTPROM
Certain devices in the M68HC11 E series include on-chip EPROM/OTPROM. For
cale Semiconductor,
instance:
• The MC68HC711E9 devices contain 12 Kbytes of on-chip EPROM
(OTPROM in non-windowed package).
for Edge-Sensitive Only Operation Bit
15
before it enters the COP watchdog system.
Frees
• The MC68HC711E20 has 20 Kbytes of EPROM (OTPROM in
non-windowed package).
• The MC68HC711E32 has 32 Kbytes of EPROM (OTPROM in
non-windowed package).
Standard MC68HC71E9 and MC68HC711E20 devices are shipped with the
EPROM/OTPROM contents erased (all 1s). The programming operation programs
zeros. Windowed devices must be erased using a suitable ultraviolet light source
before reprogramming. Depending on the light source, erasing can take from 15 to
45 minutes.
Data Sheet M68HC11E Family — Rev. 5
52 Operating Modes and On-Chip Memory MOTOROLA
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Freescale Semiconductor, Inc.
Using the on-chip EPROM/OTPROM programming feature requires an external
12-volt nominal power supply (V
the EPROM/OTPROM programming register (PPROG).
PPROG is the combined EPROM/OTPROM and EEPROM programming register
on all devices with EPROM/OTPROM except the MC68HC711E20. For the
MC68HC711E20, there is a separate register for EPROM/OTPROM programming
called the EPROG register.
As described in the following subsections, these two methods of programming and
verifying EPROM are possible:
1. Programming an individual EPROM address
2. Programming the EPROM with downloaded data
Operating Modes and On-Chip Memory
EPROM/OTPROM
). Normal programming is accomplished using
PPE
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2.4.1 Programming an Individual EPROM Address
In this method, the MCU programs its own EPROM by controlling the PPROG
register (EPROG in MC68HC711E20). Use these procedures to program the
EPROM through the MCU with:
• The ROMON bit set in the CONFIG register
• The 12-volt nominal programming voltage present on the XIRQ
• The IRQ
NOTE: Any operating mode can be used.
This example applies to all devices with EPROM/OTPROM except for the
MC68HC711E20.
EPROG LDAB #$20
pin must be pulled high.
STAB $103B Set ELAT bit in (EPGM = 0) to enable
STAA $0,X Store data to EPROM address
LDAB #$21
STAB $103B Set EPGM bit with ELAT = 1 to enable
JSR DLYEP Delay 2–4 ms
CLR $103B Turn off programming voltage and set
EPROM latches.
EPROM programming voltage
to READ mode
/V
PPE
pin
This example applies only to MC68HC711E20.
EPROG LDAB #$20
STAB $1036 Set ELAT bit (EPGM = 0) to enable
STAA $0,X Store data to EPROM address
LDAB #$21
STAB $1036 Set EPGM bit with ELAT = 1 to enable
JSR DLYEP Delay 2–4 ms
CLR $1036 Turn off programming voltage and set
M68HC11E Family — Rev. 5 Data Sheet
MOTOROLA Operating Modes and On-Chip Memory 53
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EPROM latches.
EPROM programming voltage
to READ mode
Page 54
Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
2.4.2 Programming the EPROM with Downloaded Data
When using this method, the EPROM is programmed by software while in the
special test or bootstrap modes. User-developed software can be uploaded
through the SCI or a ROM-resident EPROM programming utility can be used. The
12-volt nominal programming voltage must be present on the XIRQ
use the resident utility, bootload a 3-byte program consisting of a single jump
instruction to $BF00. $BF00 is the starting address of a resident EPROM
programming utility. The utility program sets the X and Y index registers to default
values, then receives programming data from an external host, and puts it in
EPROM. The value in IX determines programming delay time. The value in IY is a
pointer to the first address in EPROM to be programmed (default = $D000).
When the utility program is ready to receive programming data, it sends the host
the $FF character. Then it waits. When the host sees the $FF character, the
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EPROM programming data is sent, starting with the first location in the EPROM
array. After the last byte to be programmed is sent and the corresponding
verification data is returned, the programming operation is terminated by resetting
the MCU.
/V
PPE
pin. To
cale Semiconductor,
Frees
For more information, Motorola application note AN1060 entitled M68HC11
Bootstrap Mode has been included at the back of this document.
2.4.3 EPROM and EEPROM Programming Control Register
The EPROM and EEPROM programming control register (PPROG) enables the
EPROM programming voltage and controls the latching of data to be programmed.
• For MC68HC711E9, PPROG is also the EEPROM programming control
register.
• For the MC68HC711E20, EPROM programming is controlled by the
EPROG register and EEPROM programming is controlled by the PPROG
register.
Address: $103B
Bit 7654321Bit 0
Read:
Write:
Reset: 00000000
1. MC68HC711E9 only
ODD EVEN ELAT
Figure 2-14. EPROM and EEPROM Programming
Control Register (PPROG)
(1)
BYTE ROW ERASE EELAT EPGM
ODD — Program Odd Rows in Half of EEPROM (Test) Bit
Refer to 2.5 EEPROM.
EVEN — Program Even Rows in Half of EEPROM (Test) Bit
Refer to 2.5 EEPROM.
Data Sheet M68HC11E Family — Rev. 5
54 Operating Modes and On-Chip Memory MOTOROLA
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ELAT — EPROM/OTPROM Latch Control Bit
When ELAT = 1, writes to EPROM cause address and data to be latched and
the EPROM/OTPROM cannot be read. ELAT can be read any time. ELAT can
be written any time except when EPGM = 1; then the write to ELAT is disabled.
0 = EPROM address and data bus configured for normal reads
1 = EPROM address and data bus configured for programming
For the MC68HC711E9:
a. EPGM enables the high voltage necessary for both EEPROM and
b. ELAT and EELAT are mutually exclusive and cannot both equal 1.
BYTE — Byte/Other EEPROM Erase Mode Bit
Refer to 2.5 EEPROM.
ROW — Row/All EEPROM Erase Mode Bit
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Refer to 2.5 EEPROM.
ERASE — Erase Mode Select Bit
Refer to 2.5 EEPROM.
Operating Modes and On-Chip Memory
EPROM/OTPROM
EPROM/OTPROM programming.
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EELAT — EEPROM Latch Control Bit
Refer to 2.5 EEPROM.
EPGM —EPROM/OTPROM/EEPROM Programming Voltage Enable Bit
EPGM can be read any time and can be written only when ELAT = 1 (for
EPROM/OTPROM programming) or when EELAT = 1 (for EEPROM
programming).
0 = Programming voltage to EPROM/OTPROM/EEPROM array
disconnected
1 = Programming voltage to EPROM/OTPROM/EEPROM array connected
Address: $1036
Bit 7654321Bit 0
Read:
Write:
Reset: 00000000
MBE — Multiple-Byte Programming Enable Bit
When multiple-byte programming is enabled, address bit 5 is considered a don’t
care so that bytes with address bit 5 = 0 and address bit 5 = 1 both get
programmed. MBE can be read in any mode and always reads 0 in normal
modes. MBE can be written only in special modes.
0 = EPROM array configured for normal programming
1 = Program two bytes with the same data
MBE
= Unimplemented
Figure 2-15. MC68HC711E20 EPROM Programming
ELAT EXCOL EXROW T1 T0 PGM
Control Register (EPROG)
M68HC11E Family — Rev. 5 Data Sheet
MOTOROLA Operating Modes and On-Chip Memory 55
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Operating Modes and On-Chip Memory
Bit 6 — Unimplemented
Always reads 0
ELAT — EPROM/OTPROM Latch Control Bit
When ELAT = 1, writes to EPROM cause address and data to be latched and
the EPROM/OTPROM cannot be read. ELAT can be read any time. ELAT can
be written any time except when PGM = 1; then the write to ELAT is disabled.
0 = EPROM/OTPROM address and data bus configured for normal reads
1 = EPROM/OTPROM address and data bus configured for programming
EXCOL — Select Extra Columns Bit
0 = User array selected
1 = User array is disabled and extra columns are accessed at bits [7:0].
Addresses use bits [13:5] and bits [4:0] are don’t care. EXCOL can be
read and written only in special modes and always returns 0 in normal
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EXROW — Select Extra Rows Bit
modes.
0 = User array selected
1 = User array is disabled and two extra rows are available. Addresses use
bits [7:0] and bits [13:8] are don’t care. EXROW can be read and written
only in special modes and always returns 0 in normal modes.
cale Semiconductor,
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T[1:0] — EPROM Test Mode Select Bits
These bits allow selection of either gate stress or drain stress test modes. They
can be read and written only in special modes and always read 0 in normal
modes.
T1 T0 Function Selected
0 0 Normal mode
01 Reserved
1 0 Gate stress
1 1 Drain stress
PGM — EPROM Programming Voltage Enable Bit
PGM can be read any time and can be written only when ELAT = 1.
0 = Programming voltage to EPROM array disconnected
1 = Programming voltage to EPROM array connected
Data Sheet M68HC11E Family — Rev. 5
56 Operating Modes and On-Chip Memory MOTOROLA
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Operating Modes and On-Chip Memory
EEPROM
2.5 EEPROM
Some E-series devices contain 512 bytes of on-chip EEPROM. The
MC68HC811E2 contains 2048 bytes of EEPROM with selectable base address. All
E-series devices contain the EEPROM-based CONFIG register.
2.5.1 EEPROM and CONFIG Programming and Erasure
The erased state of an EEPROM bit is 1. During a read operation, bit lines are
precharged to 1. The floating gate devices of programmed bits conduct and pull the
bit lines to 0. Unprogrammed bits remain at the precharged level and are read as
ones. Programming a bit to 1 causes no change. Programming a bit to 0 changes
the bit so that subsequent reads return 0.
When appropriate bits in the BPROT register are cleared, the PPROG register
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controls programming and erasing the EEPROM. The PPROG register can be read
or written at any time, but logic enforces defined programming and erasing
sequences to prevent unintentional changes to EEPROM data. When the EELAT
bit in the PPROG register is cleared, the EEPROM can be read as if it were a ROM.
cale Semiconductor,
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The on-chip charge pump that generates the EEPROM programming voltage from
uses MOS capacitors, which are relatively small in value. The efficiency of this
V
DD
charge pump and its drive capability are affected by the level of V
frequency of the driving clock. The load depends on the number of bits being
programmed or erased and capacitances in the EEPROM array.
The clock source driving the charge pump is software selectable. When the clock
select (CSEL) bit in the OPTION register is 0, the E clock is used; when CSEL is 1,
an on-chip resistor-capacitor (RC) oscillator is used.
The EEPROM programming voltage power supply voltage to the EEPROM array
is not enabled until there has been a write to PPROG with EELAT set and PGM
cleared. This must be followed by a write to a valid EEPROM location or to the
CONFIG address, and then a write to PPROG with both the EELAT and EPGM bits
set. Any attempt to set both EELAT and EPGM during the same write operation
results in neither bit being set.
2.5.1.1 Block Protect Register
This register prevents inadvertent writes to both the CONFIG register and
EEPROM. The active bits in this register are initialized to 1 out of reset and can be
cleared only during the first 64 E-clock cycles after reset in the normal modes.
When these bits are cleared, the associated EEPROM section and the CONFIG
register can be programmed or erased. EEPROM is only visible if the EEON bit in
the CONFIG register is set. The bits in the BPROT register can be written to 1 at
any time to protect EEPROM and the CONFIG register. In test or bootstrap modes,
write protection is inhibited and BPROT can be written repeatedly. Address ranges
for protected areas of EEPROM differ significantly for the MC68HC811E2. Refer to
Figure 2-16.
and the
DD
M68HC11E Family — Rev. 5 Data Sheet
MOTOROLA Operating Modes and On-Chip Memory 57
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Operating Modes and On-Chip Memory
Address: $1035
Bit 7654321Bit 0
Read:
Write:
Reset: 00011111
Figure 2-16. Block Protect Register (BPROT)
Bits [7:5] — Unimplemented
Always read 0
PTCON — Protect CONFIG Register Bit
0 = CONFIG register can be programmed or erased normally.
1 = CONFIG register cannot be programmed or erased.
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BPRT[3:0] — Block Protect Bits for EEPROM
When set, these bits protect a block of EEPROM from being programmed or
electronically erased. Ultraviolet light, however, can erase the entire
EEPROM contents regardless of BPRT[3:0] (windowed packages only). Refer
to Table 2-6 and Table 2-7.
PTCON BPRT3 BPRT2 BPRT1 BPRT0
= Unimplemented
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When cleared, BPRT[3:0] allow programming and erasure of the associated
block.
Table 2-6. EEPROM Block Protect
Bit Name Block Protected Block Size
BPRT0 $B600–$B61F 32 bytes
BPRT1 $B620–$B65F 64 bytes
BPRT2 $B660–$B6DF 128 bytes
BPRT3 $B6E0–$B7FF 288 bytes
Table 2-7. EEPROM Block Protect in MC68HC811E2 MCUs
Bit Name Block Protected Block Size
BPRT0
BPRT1
BPRT2
BPRT3
1. x is determined by the value of EE[3:0] in CONFIG register. Refer to Figure 2-13.
2.5.1.2 EPROM and EEPROM Programming Control Register
$x800–$x9FF
$xA00–$xBFF
$xC00–$xDFF
$xE00–$xFFF
(1)
(1)
(1)
(1)
512 bytes
512 bytes
512 bytes
512 bytes
The EPROM and EEPROM programming control register (PPROG) selects and
controls the EEPROM programming function. Bits in PPROG enable the
programming voltage, control the latching of data to be programmed, and select
the method of erasure (for example, byte, row, etc.).
Data Sheet M68HC11E Family — Rev. 5
58 Operating Modes and On-Chip Memory MOTOROLA
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Address: $103B
Read:
Write:
Reset: 0
1. MC68HC711E9 only
ODD — Program Odd Rows in Half of EEPROM (Test) Bit
EVEN — Program Even Rows in Half of EEPROM (Test) Bit
ELAT — EPROM/OTPROM Latch Control Bit
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For the MC68HC711E9, EPGM enables the high voltage necessary for both
EPROM/OTPROM and EEPROM programming.
For MC68HC711E9, ELAT and EELAT are mutually exclusive and cannot both
equal 1.
0 = EPROM address and data bus configured for normal reads
1 = EPROM address and data bus configured for programming
Operating Modes and On-Chip Memory
EEPROM
Bit 7654321Bit 0
(1)
ODD EVEN ELAT
0000000
Figure 2-17. EPROM and EEPROM Programming
Control Register (PPROG)
BYTE ROW ERASE EELAT EPGM
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BYTE — Byte/Other EEPROM Erase Mode Bit
This bit overrides the ROW bit.
0 = Row or bulk erase
1 = Erase only one byte
ROW — Row/All EEPROM Erase Mode Bit
If BYTE is 1, ROW has no meaning.
0 = Bulk erase
1 = Row erase
Table 2-8. EEPROM Erase
BYTE ROW Action
0 0 Bulk erase (entire array)
0 1 Row erase (16 bytes)
1 0 Byte erase
1 1 Byte erase
ERASE — Erase Mode Select Bit
0 = Normal read or program mode
1 = Erase mode
EELAT — EEPROM Latch Control Bit
0 = EEPROM address and data bus configured for normal reads and cannot
be programmed
1 = EEPROM address and data bus configured for programming or erasing
and cannot be read
M68HC11E Family — Rev. 5 Data Sheet
MOTOROLA Operating Modes and On-Chip Memory 59
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Operating Modes and On-Chip Memory
EPGM — EPROM/OTPROM/EEPROM Programming Voltage Enable Bit
0 = Programming voltage to EEPROM array switched off
1 = Programming voltage to EEPROM array switched on
During EEPROM programming, the ROW and BYTE bits of PPROG are not used.
If the frequency of the E clock is 1 MHz or less, set the CSEL bit in the OPTION
register. Recall that 0s must be erased by a separate erase operation before
programming. The following examples of how to program an EEPROM byte
assume that the appropriate bits in BPROT are cleared.
PROG LDAB #$02 EELAT = 1
STAB $103B Set EELAT bit
STAA $XXXX Store data to EEPROM address
LDAB #$03 EELAT = 1, EPGM = 1
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STAB $103B Turn on programming voltage
JSR DLY10 Delay 10 ms
CLR $103B Turn off high voltage and set
(for valid EEPROM address see memory
map for each device)
to READ mode
cale Semiconductor,
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2.5.1.3 EEPROM Bulk Erase
This is an example of how to bulk erase the entire EEPROM. The CONFIG register
is not affected in this example.
BULKE LDAB #$06 EELAT = 1, ERASE = 1
2.5.1.4 EEPROM Row Erase
This example shows how to perform a fast erase of large sections of EEPROM.
ROWE LDAB #$0E ROW = 1, ERASE = 1, EELAT = 1
STAB $103B Set to BULK erase mode
STAA $XXXX Store data to any EEPROM address (for
valid EEPROM address see memory map
for each device)
LDAB #$07 EELAT = 1, EPGM = 1, ERASE = 1
STAB $103B Turn on high voltage
JSR DLY10 Delay 10 ms
CLR $103B Turn off high voltage and set
to READ mode
STAB $103B Set to ROW erase mode
STAB 0,X Write any data to any address in ROW
LDAB #$0F ROW = 1, ERASE = 1, EELAT = 1, EPGM = 1
STAB $103B Turn on high voltage
JSR DLY10 Delay 10 ms
CLR $103B Turn off high voltage and set
to READ mode
Data Sheet M68HC11E Family — Rev. 5
60 Operating Modes and On-Chip Memory MOTOROLA
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2.5.1.5 EEPROM Byte Erase
This is an example of how to erase a single byte of EEPROM.
BYTEE LDAB #$16 BYTE = 1, ERASE = 1, EELAT = 1
2.5.1.6 CONFIG Register Programming
STAB $103B Set to BYTE erase mode
STAB 0,X Write any data to address to be erased
LDAB #$17 BYTE = 1, ERASE = 1, EELAT = 1,
STAB $103B Turn on high voltage
JSR DLY10 Delay 10 ms
CLR $103B Turn off high voltage and set
Operating Modes and On-Chip Memory
EEPROM
EPGM = 1
to READ mode
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cale Semiconductor,
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Because the CONFIG register is implemented with EEPROM cells, use EEPROM
procedures to erase and program this register. The procedure for programming is
the same as for programming a byte in the EEPROM array, except that the
CONFIG register address is used. CONFIG can be programmed or erased
(including byte erase) while the MCU is operating in any mode, provided that
PTCON in BPROT is clear.
To change the value in the CONFIG register, complete this procedure.
NOTE: Do not initiate a reset until the procedure is complete.
2.5.2 EEPROM Security
The optional security feature, available only on ROM-based MCUs, protects the
EEPROM and RAM contents from unauthorized access. A program, or a key
portion of a program, can be protected against unauthorized duplication. To
accomplish this, the protection mechanism restricts operation of protected devices
to the single-chip modes. This prevents the memory locations from being
monitored externally because single-chip modes do not allow visibility of the
internal address and data buses. Resident programs, however, have unlimited
access to the internal EEPROM and RAM and can read, write, or transfer the
contents of these memories.
1. Erase the CONFIG register.
2. Program the new value to the CONFIG address.
3. Initiate reset.
An enhanced security feature which protects EPROM contents, RAM, and
EEPROM from unauthorized accesses is available in MC68S711E9. Refer to
Section 11. Ordering Information and Mechanical Specifications for the exact
part number.
M68HC11E Family — Rev. 5 Data Sheet
MOTOROLA Operating Modes and On-Chip Memory 61
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Operating Modes and On-Chip Memory
For further information, these engineering bulletins have been included at the back
of this data book:
• EB183 — Enabling the Security Feature on the MC68HC711E9 Devices
with PCbug11 on the M68HC711E9PGMR
• EB188 — Enabling the Security Feature on M68HC811E2 Devices with
PCbug11 on the M68HC711E9PGMR
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Data Sheet M68HC11E Family — Rev. 5
62 Operating Modes and On-Chip Memory MOTOROLA
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Data Sheet — M68HC11E Family
3.1 Introduction
The analog-to-digital (A/D) system, a successive approximation converter, uses an
all-capacitive charge redistribution technique to convert analog signals to digital
values.
Section 3. Analog-to-Digital (A/D) Converter
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cale Semiconductor,
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3.2 Overview
3.2.1 Multiplexer
The A/D system is an 8-channel, 8-bit, multiplexed-input converter. The converte r
does not require external sample and hold circuits because of the type of charge
redistribution technique used. A/D converter timing can be synchronized to the
system E clock or to an internal resistor capacitor (RC) oscillator.
The A/D converter system consists of four functional blocks: multiplexer, analog
converter, digital control, and result storage. Refer to Figure 3-1.
The multiplexer selects one of 16 inputs for conversion. Input selection is controlled
by the value of bits CD:CA in the ADCTL register. The eight port E pins are
fixed-direction analog inputs to the multiplexer, and additional internal analog
signal lines are routed to it.
Port E pins also can be used as digital inputs. Digital reads of port E pins are not
recommended during the sample portion of an A/D conversion cycle, when the
gate signal to the N-channel input gate is on. Because no P-channel devices are
directly connected to either input pins or reference voltage pins, voltages above
do not cause a latchup problem, although current should be limited according
V
DD
to maximum ratings. Refer to Figure 3-2, which is a functional diagram of an
input pin.
M68HC11E Family — Rev. 5 Data Sheet
MOTOROLA Analog-to-Digital (A/D) Converter 63
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Analog-to-Digital (A/D) Converter
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PE0
AN0
PE1
AN1
PE2
AN2
PE3
AN3
PE4
AN4
PE5
AN5
PE6
AN6
PE7
AN7
ANALOG
INPUT
PIN
8-BIT CAPACITIVE DAC
WITH SAMPLE AND HOLD
SUCCESSIVE APPROXIMATION
REGISTER AND CONTROL
ANALOG
MUX
ADR1 A/D RESULT 1 ADR2 A/D RESULT 2 ADR3 A/D RESULT 3 ADR4 A/D RESULT 4
RESULT
RESULT REGISTER INTERFACE
CCF
SCAN
MULTCDCCCBCA
ADCTL A/D CONTROL
Figure 3-1. A/D Converter Block Diagram
DIFFUSION/POLY
COUPLER
< 2 pF
INPUT
PROTECTION
DEVICE
+ ~20 V
– ~0.7 V
+ ~12V
– ~0.7V
DUMMY N-CHANNEL
OUTPUT DEVICE
ð 4 kΩ
400 nA
JUNCTION
LEAKAGE
*
~ 20 pF
CAPACITANCE
V
RL
V
RH
V
Rl
INTERNAL
DATA BU S
DAC
* THIS ANALOG SWITCH IS CLOSED ONLY DURING THE 12-CYCLE SAMPLE TIME.
Figure 3-2. Electrical Model of an A/D Input Pin (Sample Mode)
Data Sheet M68HC11E Family — Rev. 5
64 Analog-to-Digital (A/D) Converter MOTOROLA
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3.2.2 Analog Converter
Conversion of an analog input selected by the multiplexer occurs in this block. It
contains a digital-to-analog capacitor (DAC) array, a comparator, and a successive
approximation register (SAR). Each conversion is a sequence of eight comparison
operations, beginning with the most significant bit (MSB). Each comparison
determines the value of a bit in the successive approximation register.
The DAC array performs two functions. It acts as a sample and hold circuit during
the entire conversion sequence and provides comparison voltage to the
comparator during each successive comparison.
The result of each successive comparison is stored in the SAR. When a conversion
sequence is complete, the contents of the SAR are transferred to the appropriate
result register.
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A charge pump provides switching voltage to the gates of analog switches in the
multiplexer. Charge pump output must stabilize between 7 and 8 volts within up to
100 µs before the converter can be used. The charge pump is enabled by the
ADPU bit in the OPTION register.
Analog-to-Digital (A/D) Converter
Overview
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3.2.3 Digital Control
All A/D converter operations are controlled by bits in register ADCTL. In addition to
selecting the analog input to be converted, ADCTL bits indicate conversion status
and control whether single or continuous conversions are performed. Finally, the
ADCTL bits determine whether conversions are performed on single or multiple
channels.
3.2.4 Result Registers
Four 8-bit registers ADR[4:1] store conversion results. Each of these registers can
be accessed by the processor in the CPU. The conversion complete flag (CCF)
indicates when valid data is present in the result registers. The result registers are
written during a portion of the system clock cycle when reads do not occur, so there
is no conflict.
3.2.5 A/D Converter Clocks
The CSEL bit in the OPTION register selects whether the A/D converter uses the
system E clock or an internal RC oscillator for synchronization. When E-clock
frequency is below 750 kHz, charge leakage in the capacitor array can cause
errors, and the internal oscillator should be used. When the RC clock is used,
additional errors can occur because the comparator is sensitive to the additional
system clock noise.
M68HC11E Family — Rev. 5 Data Sheet
MOTOROLA Analog-to-Digital (A/D) Converter 65
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Analog-to-Digital (A/D) Converter
3.2.6 Conversion Sequence
A/D converter operations are performed in sequences of four conversions each. A
conversion sequence can repeat continuously or stop after one iteration. The
conversion complete flag (CCF) is set after the fourth conversion in a sequence to
show the availability of data in the result registers. Figure 3-3 shows the timing of
a typical sequence. Synchronization is referenced to the system E clock.
E CLOCK
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12 E CYCLES
SAMPLE ANALOG INPUT SUCCESSIVE APPROXIMATION SEQUENCE
WRITE TO ADCTL
CONVERT FIRST
CHANNEL, UPDATE
0 32 64 96 128 — E CYCLES
ADR1
CONVERT SECOND
CHANNEL, UPDATE
MSB
CYCLES
ADR2
BIT 6
4
CYC
2
Figure 3-3. A/D Conversion Sequence
3.3 A/D Converter Power-Up and Clock Select
Bit 7 of the OPTION register controls A/D converter power-up. Clearing ADPU
removes power from and disables the A/D converter system. Setting ADPU
enables the A/D converter system. Stabilization of the analog bias voltages
requires a delay of as much as 100 µs after turning on the A/D converter. When the
A/D converter system is operating with the MCU E clock, all switching and
comparator operations are inherently synchronized to the main MCU clocks. This
allows the comparator output to be sampled at relatively quiet times during MCU
clock cycles. Since the internal RC oscillator is asynchronous to the MCU clock,
there is more error attributable to internal system clock noise. A/D converter
accuracy is reduced slightly while the internal RC oscillator is being used
(CSEL = 1).
Address: $1039
Bit 7654321Bit 0
Read:
Write:
Reset:00010000
1. Can be written only once in first 64 cycles out of reset in normal modes or at any time in special modes
ADPU CSEL IRQE
= Unimplemented
BIT 5
BIT 4
2
CYC
ADR3
DLY
BIT 3
CYC
2
(1)
2
CYC
CONVERT THIRD
CHANNEL, UPDATE
(1)
BIT 2
BIT 1
LSB
2
2
CYC
CYC
CONVERT FOURTH
CHANNEL, UPDATE
CME CR1
2
CYC
ADR4
2
CYC
END
SET CC FLAG
REPEAT SEQUENCE, SCAN = 1
(1)
CR0
(1)
Figure 3-4. System Configuration Options Register (OPTION)
Data Sheet M68HC11E Family — Rev. 5
66 Analog-to-Digital (A/D) Converter MOTOROLA
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ADPU — A/D Power-Up Bit
0 = A/D powered down
1 = A/D powered up
CSEL — Clock Select Bit
0 = A/D and EEPROM use system E clock.
1 = A/D and EEPROM use internal RC clock.
Analog-to-Digital (A/D) Converter
Conversion Process
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IRQE — Configure IRQ
Refer to Section 5. Resets and Interrupts.
DLY — Enable Oscillator Startup Delay Bit
0 = The oscillator startup delay coming out of stop is bypassed and the MCU
1 = A delay of approximately 4000 E-clock cycles is imposed as the MCU is
CME — Clock Monitor Enable Bit
Refer to Section 5. Resets and Interrupts.
Bit 2 — Not implemented
Always reads 0
CR[1:0] — COP Timer Rate Select Bits
Refer to Section 5. Resets and Interrupts and Section 9. Timing System.
3.4 Conversion Process
The A/D conversion sequence begins one E-clock cycle after a write to the A/D
control/status register, ADCTL. The bits in ADCTL select the channel and the mode
of conversion.
An input voltage equal to V
converts to $FF (full scale), with no overflow indication. For ratiometric conversions
of this type, the source of each analog input should use V
and be referenced to V
3.5 Channel Assignments
The multiplexer allows the A/D converter to select one of 16 analog signals. Eight
of these channels correspond to port E input lines to the MCU, four of the channels
are internal reference points or test functions, and four channels are reserved.
Refer to Table 3-1.
for Edge-Sensitive Only Operation
resumes processing within about four bus cycles.
started up from the stop power-saving mode. This delay allows the
crystal oscillator to stabilize.
converts to $00 and an input voltage equal to VRH
RL
as the supply voltage
RH
.
RL
M68HC11E Family — Rev. 5 Data Sheet
MOTOROLA Analog-to-Digital (A/D) Converter 67
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Analog-to-Digital (A/D) Converter
Table 3-1. Converter Channel Assignments
Channel
Number
1AN0ADR1
2AN1ADR2
3AN2ADR3
4AN3ADR4
5AN4ADR1
6AN5ADR2
7AN6ADR3
8AN7ADR4
9 – 12 Reserved —
13
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1. Used for factory testing
14
15
16
3.6 Single-Channel Operation
The two types of single-channel operation are:
1. When SCAN = 0, the single selected channel is converted four consecutive
times. The first result is stored in A/D result register 1 (ADR1), an d the fourth
result is stored in ADR4. After the fourth conversion is complete, all
conversion activity is halted until a new conversion command is written to
the ADCTL register.
2. When SCAN = 1, conversions continue to be performed on the selected
cale Semiconductor,
channel with the fifth conversion being stored in register ADR1 (overwriting
the first conversion result), the sixth conversion overwriting ADR2, and so
on.
Channel
Signal
(1)
V
RH
(1)
V
RL
)/2
(V
RH
Reserved
(1)
(1)
Result in ADRx
if MULT = 1
ADR1
ADR2
ADR3
ADR4
Frees
3.7 Multiple-Channel Operation
The two types of multiple-channel operation are:
1. When SCAN = 0, a selected group of four channels is converted one time
each. The first result is stored in A/D result register 1 (ADR1), and the fourth
result is stored in ADR4. After the fourth conversion is complete, all
conversion activity is halted until a new conversion command is written to
the ADCTL register.
2. When SCAN = 1, conversions continue to be performed on the selected
group of channels with the fifth conversion being stored in register ADR1
(replacing the earlier conversion result for the first channel in the group), the
sixth conversion overwriting ADR2, and so on.
Data Sheet M68HC11E Family — Rev. 5
68 Analog-to-Digital (A/D) Converter MOTOROLA
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Analog-to-Digital (A/D) Converter
Operation in Stop and Wait Modes
3.8 Operation in Stop and Wait Modes
If a conversion sequence is in progress when either the stop or wait mode is
entered, the conversion of the current channel is suspended. When the MCU
resumes normal operation, that channel is resampled and the conversion
sequence is resumed. As the MCU exits wait mode, the A/D circuits are stable and
valid results can be obtained on the first conversion. However, in stop mode, all
analog bias currents are disabled and it is necessary to allow a stabilization period
when leaving stop mode. If stop mode is exited with a delay (DLY = 1), there is
enough time for these circuits to stabilize before the first conversion. If stop mode
is exited with no delay (DLY bit in OPTION register = 0), allow 10 ms for the A/D
circuitry to stabilize to avoid invalid results.
3.9 A/D Control/Status Register
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All bits in this register can be read or written, except bit 7, which is a read-only
status indicator, and bit 6, which always reads as 0. Write to ADCTL to initiate a
conversion. To quit a conversion in progress, write to this register and a new
conversion sequence begins immediately.
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Frees
Address: $1030
Bit 7654321Bit 0
Read: CCF
Write:
Reset: 0 0 Indeterminate after reset
= Unimplemented
Figure 3-5. A/D Control/Status Register (ADCTL)
CCF — Conversion Complete Flag
A read-only status indicator, this bit is set when all four A/D result registers
contain valid conversion results. Each time the ADCTL register is overwritten,
this bit is automatically cleared to 0 and a conversion sequence is started. In the
continuous mode, CCF is set at the end of the first conversion sequence.
Bit 6 — Unimplemented
Always reads 0
SCAN — Continuous Scan Control Bit
When this control bit is clear, the four requested conversions are performed
once to fill the four result registers. When this control bit is set, conversions are
performed continuously with the result registers updated as data becomes
available.
SCAN MULT CD CC CB CA
MULT — Multiple Channel/Single Channel Control Bit
When this bit is clear, the A/D converter system is configured to perform four
consecutive conversions on the single channel specified by the four channel
select bits CD:CA (bits [3:0] of the ADCTL register). When this bit is set, the A/D
M68HC11E Family — Rev. 5 Data Sheet
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Analog-to-Digital (A/D) Converter
system is configured to perform a conversion on each of four channels where
each result register corresponds to one channel.
NOTE: When the multiple-channel continuous scan mode is used, extra care is needed in
the design of circuitry driving the A/D inputs. The charge on the capacitive DAC
array before the sample time is related to the voltage on the previously converted
channel. A charge share situation exists between the internal DAC capacitance
and the external circuit capacitance. Although the amount of charge involved is
small, the rate at which it is repeated is every 64 µs for an E clock of 2 MHz. The
RC charging rate of the external circuit must be balanced against this charge
sharing effect to avoid errors in accuracy. Refer to M68HC11 Reference Manual,
Motorola document order number M68HC11RM/AD, for further information.
CD:CA — Channel Selects D:A Bits
Refer to Table 3-2. When a multiple channel mode is selected (MULT = 1), the
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two least significant channel select bits (CB and CA) have no meaning and the
CD and CC bits specify which group of four channels is to be converted.
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Table 3-2. A/D Converter Channel Selection
Channel Select
Control Bits
CD:CC:CB:CA
0000 AN0 ADR1
0001 AN1 ADR2
0010 AN2 ADR3
0011 AN3 ADR4
0100 AN4 ADR1
0101 AN5 ADR2
0110 AN6 ADR3
0111 AN7 ADR4
10XX Reserved —
1100
1101
1110
1111
1. Used for factory testing
Channel Signal
(1)
V
RH
(1)
V
RL
RH
)/2
(1)
(1)
(V
Reserved
Result in ADRx
if MULT = 1
ADR1
ADR2
ADR3
ADR4
Data Sheet M68HC11E Family — Rev. 5
70 Analog-to-Digital (A/D) Converter MOTOROLA
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Analog-to-Digital (A/D) Converter
A/D Converter Result Registers
3.10 A/D Converter Result Registers
These read-only registers hold an 8-bit conversion result. Writes to these registers
have no effect. Data in the A/D converter result registers is valid when the CCF flag
in the ADCTL register is set, indicating a conversion sequence is complete. If
conversion results are needed sooner, refer to Figure 3-3, which shows the A/D
conversion sequence diagram.
Register name: Analog-to-Digital Converter Result Register 1 Address: $1031
Bit 7654321Bit 0
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: Indeterminate after reset
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Register name: Analog-to-Digital Converter Result Register 2 Address: $1032
Bit 7654321Bit 0
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: Indeterminate after reset
Register name: Analog-to-Digital Converter Result Register 3 Address: $1033
Bit 7654321Bit 0
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: Indeterminate after reset
Register name: Analog-to-Digital Converter Result Register 4 Address: $1034
Bit 7654321Bit 0
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: Indeterminate after reset
= Unimplemented
Figure 3-6. Analog-to-Digital Converter
Result Registers (ADR1–ADR4)
Frees
M68HC11E Family — Rev. 5 Data Sheet
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Analog-to-Digital (A/D) Converter
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Data Sheet M68HC11E Family — Rev. 5
72 Analog-to-Digital (A/D) Converter MOTOROLA
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Data Sheet — M68HC11E Family
4.1 Introduction
Features of the M68HC11 Family include:
• Central processor unit (CPU) architecture
• Data types
Section 4. Central Processor Unit (CPU)
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4.2 CPU Registers
• Addressing modes
• Instruction set
• Special operations such as subroutine calls and interrupts
The CPU is designed to treat all peripheral, input/output (I/O), and memory
locations identically as addresses in the 64-Kbyte memory map. This is referred to
as memory-mapped I/O. There are no special instructions for I/O that are separate
from those used for memory. This architecture also allows accessing an operand
from an external memory location with no execution time penalty.
M68HC11 CPU registers are an integral part of the CPU and are not addressed as
if they were memory locations. The seven registers, discussed in the following
paragraphs, are shown in Figure 4-1.
M68HC11E Family — Rev. 5 Data Sheet
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Central Processor Unit (CPU)
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7070
15 0
4.2.1 Accumulators A, B, and D
AB
Accumulators A and B are general-purpose 8-bit registers that hold operands and
results of arithmetic calculations or data manipulations. For some instructions,
these two accumulators are treated as a single double-byte (16-bit) accumulator
called accumulator D. Although most instructions can use accumulators A or B
interchangeably, these exceptions apply:
• The ABX and ABY instructions add the contents of 8-bit accumulator B to
the contents of 16-bit register X or Y, but there are no equivalent instructions
that use A instead of B.
• The TAP and TPA instructions transfer data from accumulator A to the
condition code register or from the condition code register to accumulator A.
However, there are no equivalent instructions that use B rather than A.
8-BIT ACCUMULATORS A & B
D
IX
IY
SP
PC
70
Figure 4-1. Programming Model
OR 16-BIT DOUBLE ACCUMULATOR D
INDEX REGISTER X
INDEX REGISTER Y
STACK POINTER
PROGRAM COUNTER
CONDITION CODES
CVZNIHXS
CARRY/BORROW FROM MSB
OVERFLOW
ZERO
NEGATIVE
I-INTERRUPT MASK
HALF CARRY (FROM BIT 3)
X-INTERRUPT MASK
STOP DISABLE
• The decimal adjust accumulator A (DAA) instruction is used after
binary-coded decimal (BCD) arithmetic operations, but there is no
equivalent BCD instruction to adjust accumulator B.
• The add, subtract, and compare instructions associated with both A and B
(ABA, SBA, and CBA) only operate in one direction, making it important to
plan ahead to ensure that the correct operand is in the correct accumulator.
Data Sheet M68HC11E Family — Rev. 5
74 Central Processor Unit (CPU) MOTOROLA
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4.2.2 Index Register X (IX)
The IX register provides a 16-bit indexing value that can be added to the 8-bit offset
provided in an instruction to create an effective address. The IX register can also
be used as a counter or as a temporary storage register.
4.2.3 Index Register Y (IY)
The 16-bit IY register performs an indexed mode function similar to that of the IX
register. However, most instructions using the IY register require an extra byte of
machine code and an extra cycle of execution time because of the way the opcode
map is implemented. Refer to 4.4 Opcodes and Operands for further information.
4.2.4 Stack Pointer (SP)
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Central Processor Unit (CPU)
CPU Registers
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The M68HC11 CPU has an automatic program stack. This stack can be located
anywhere in the address space and can be any size up to the amount of memory
available in the system. Normally, the SP is initialized by one of the first instructions
in an application program. The stack is configured as a data structure that grows
downward from high memory to low memory. Each time a new byte is pushed onto
the stack, the SP is decremented. Each time a byte is pulled from the stack, the SP
is incremented. At any given time, the SP holds the 16-bit address of the next free
location in the stack. Figure 4-2 is a summary of SP operations.
When a subroutine is called by a jump-to-subroutine (JSR) or branch-tosubroutine (BSR) instruction, the address of the instruction after the JSR or BSR
is automatically pushed onto the stack, least significant byte first. When the
subroutine is finished, a return-from-subroutine (RTS) instruction is executed. The
RTS pulls the previously stacked return address from the stack and loads it into the
program counter. Execution then continues at this recovered return address.
When an interrupt is recognized, the current instruction finishes normally, the
return address (the current value in the program counter) is pushed onto the stack,
all of the CPU registers are pushed onto the stack, and execution continues at the
address specified by the vector for the interrupt.
At the end of the interrupt service routine, an return-from interrupt (RTI) instruction
is executed. The RTI instruction causes the saved registers to be pulled off the
stack in reverse order. Program execution resumes at the return address.
Certain instructions push and pull the A and B accumulators and the X and Y index
registers and are often used to preserve program context. For example, pushing
accumulator A onto the stack when entering a subroutine that uses accumulator A
and then pulling accumulator A off the stack just before leaving the subroutine
ensures that the contents of a register will be the same after returning from the
subroutine as it was before starting the subroutine.
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Central Processor Unit (CPU)
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JSR, JUMP TO SUBROUTINE
MAIN PROGRAM
PC
$9D = JSR
DIRECT
RTN
PC
INDEXED, X
RTN
PC
INDEXED, Y
RTN
PC
INDEXED, Y
BSR, BRANCH TO SUBROUTINE
RTS, RETURN FROM
SUBROUTINE
MAIN PROGRAM
PC
MAIN PROGRAM
PC
RTN
$8D = BSR
$39 = RTS
dd
NEXT MAIN INSTR.
MAIN PROGRAM
$AD = JSR
ff
NEXT MAIN INSTR.
MAIN PROGRAM
$18 = PRE
$AD = JSR
ff
NEXT MAIN INSTR.
MAIN PROGRAM
$BD = PRE
hh
ll
NEXT MAIN INSTR.
➩ SP–2
SP–1
SP+1
➩ SP+2
4.2.5 Program Counter (PC)
The program counter, a 16-bit register, contains the address of the next instruction
to be executed. After reset, the program counter is initialized from one of six
possible vectors, depending on operating mode and the cause of reset. See
Table 4-1.
STACK
70
➩ SP–2
SP–1
SP
STACK
70
RTN
SP
SP
RTN
STACK
70
RTN
RTN
RTN
H
RTN
L
LEGEND:
H
L
H
L
RTN = ADDRESS OF NEXT INSTRUCTION IN MAIN PROGRAM TO
RTN
RTN
Figure 4-2. Stacking Operations
RTI, RETURN FROM INTERRUPT
STACK
INTERRUPT ROUTINE
PC
$3B = RTI
SWI, SOFTWARE INTERRUPT
MAIN PROGRAM
PC
$3F = SWI
WAI, WAIT FOR INTERRUPT
MAIN PROGRAM
PC
$3E = WAI
BE EXECUTED UPON RETURN FROM SUBROUTINE
= MOST SIGNIFICANT BYTE OF RETURN ADDRESS
H
= LEAST SIGNIFICANT BYTE OF RETURN ADDRESS
L
➩ = STACK POINTER POSITION AFTER OPERATION IS COMPLETE
dd = 8-BIT DIRECT ADDRESS ($0000–$00FF) (HIGH BYTE ASSUMED
TO BE $00)
ff = 8-BIT POSITIVE OFFSET $00 (0) TO $FF (255) IS ADDED TO INDEX
hh = HIGH-ORDER BYTE OF 16-BIT EXTENDED ADDRESS
ll = LOW-ORDER BYTE OF 16-BIT EXTENDED ADDRESS
rr= SIGNED RELATIVE OFFSET $80 (–128) TO $7F (+127) (OFFSET
RELATIVE TO THE ADDRESS FOLLOWING THE MACHINE CODE
OFFSET BYTE)
70
SP
SP+1
SP+2
SP+3
SP+4
SP+5
SP+6
SP+7
SP+8
➩ SP+9
CCR
ACCB
ACCA
IX
H
IX
L
IY
H
IY
L
RTN
H
RTN
L
STACK
70
➩ SP–9
SP–8
SP–7
SP–6
SP–5
SP–4
SP–3
SP–2
SP–1
SP
CCR
ACCB
ACCA
IX
H
IX
L
IY
H
IY
L
RTN
RTN
H
L
Table 4-1. Reset Vector Comparison
Mode POR or RESET Pin Clock Monitor COP Watchdog
Normal $FFFE, F $FFFC, D $FFFA, B
Test or Boot $BFFE, F $BFFC, D $BFFA, B
Data Sheet M68HC11E Family — Rev. 5
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4.2.6 Condition Code Register (CCR)
This 8-bit register contains:
• Five condition code indicators (C, V, Z, N, and H),
Central Processor Unit (CPU)
CPU Registers
• Two interrupt masking bits (IRQ
• A stop disable bit (S)
In the M68HC11 CPU, condition codes are updated automatically by most
instructions. For example, load accumulator A (LDAA) and store accumulator A
(STAA) instructions automatically set or clear the N, Z, and V condition code flags.
Pushes, pulls, add B to X (ABX), add B to Y (ABY), and transfer/exchange
instructions do not affect the condition codes. Refer to Table 4-2, which shows
what condition codes are affected by a particular instruction.
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4.2.6.1 Carry/Borrow (C)
The C bit is set if the arithmetic logic unit (ALU) performs a carry or borrow during
an arithmetic operation. The C bit also acts as an error flag for multiply and divide
operations. Shift and rotate instructions operate with and through the carry bit to
facilitate multiple-word shift operations.
4.2.6.2 Overflow (V)
The overflow bit is set if an operation causes an arithmetic overflow. Otherwise, the
V bit is cleared.
4.2.6.3 Zero (Z)
The Z bit is set if the result of an arithmetic, logic, or data manipulation operation
is 0. Otherwise, the Z bit is cleared. Compare instructions do an internal implied
subtraction and the condition codes, including Z, reflect the results of that
subtraction. A few operations (INX, DEX, INY, and DEY) affect the Z bit and no
other condition flags. For these operations, only = and ≠ conditions can be
determined.
and XIRQ)
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4.2.6.4 Negative (N)
The N bit is set if the result of an arithmetic, logic, or data manipulation operation
is negative (MSB = 1). Otherwise, the N bit is cleared. A result is said to be negative
if its most significant bit (MSB) is a 1. A quick way to test whether the contents of a
memory location has the MSB set is to load it into an accumulator and then check
the status of the N bit.
4.2.6.5 Interrupt Mask (I)
The interrupt request (IRQ) mask (I bit) is a global mask that disables all maskable
interrupt sources. While the I bit is set, interrupts can become pending, but the
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Central Processor Unit (CPU)
operation of the CPU continues uninterrupted until the I bit is cleared. After any
reset, the I bit is set by default and can only be cleared by a software instruction.
When an interrupt is recognized, the I bit is set after the registers are stacked, but
before the interrupt vector is fetched. After the interrupt has been serviced, a
return-from-interrupt instruction is normally executed, restoring the registers to the
values that were present before the interrupt occurred. Normally, the I bit is 0 after
a return from interrupt is executed. Although the I bit can be cleared within an
interrupt service routine, "nesting" interrupts in this way should only be done when
there is a clear understanding of latency and of the arbitration mechanism. Refer
to Section 5. Resets and Interrupts.
4.2.6.6 Half Carry (H)
The H bit is set when a carry occurs between bits 3 and 4 of the arithmetic logic
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unit during an ADD, ABA, or ADC instruction. Otherwise, the H bit is cleared. Half
carry is used during BCD operations.
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4.2.6.7 X Interrupt Mask (X)
The XIRQ mask (X) bit disables interrupts from the XIRQ
set by default and must be cleared by a software instruction. When an XIRQ
interrupt is recognized, the X and I bits are set after the registers are stacked, but
before the interrupt vector is fetched. After the interrupt has been serviced , an RTI
instruction is normally executed, causing the registers to be restored to the va lues
that were present before the interrupt occurred. The X interrupt mask bit is set only
by hardware (RESET
instruction (TAP, where the associated bit of A is 0; or RTI, where bit 6 of the value
loaded into the CCR from the stack has been cleared). There is no hardware action
for clearing X.
4.2.6.8 STOP Disable (S)
Setting the STOP disable (S) bit prevents the STOP instruction from putting the
M68HC11 into a low-power stop condition. If the STOP instruction is encountered
by the CPU while the S bit is set, it is treated as a no-operation (NOP) instruction,
and processing continues to the next instruction. S is set by reset; STOP is
disabled by default.
4.3 Data Types
pin. After any reset, X is
or XIRQ acknowledge). X is cleared only by program
The M68HC11 CPU supports four data types:
1. Bit data
2. 8-bit and 16-bit signed and unsigned integers
3. 16-bit unsigned fractions
4. 16-bit addresses
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A byte is eight bits wide and can be accessed at any byte location. A word is
composed of two consecutive bytes with the most significant byte at the lower
value address. Because the M68HC11 is an 8-bit CPU, there are no special
requirements for alignment of instructions or operands.
Central Processor Unit (CPU)
Opcodes and Operands
4.4 Opcodes and Operands
The M68HC11 Family of microcontrollers uses 8-bit opcodes. Each opcode
identifies a particular instruction and associated addressing mode to the CPU.
Several opcodes are required to provide each instruction with a range of
addressing capabilities. Only 256 opcodes would be available if the range of values
were restricted to the number able to be expressed in 8-bit binary numbers.
A 4-page opcode map has been implemented to expand the number of
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instructions. An additional byte, called a prebyte, directs the processor from page
0 of the opcode map to one of the other three pages. As its name implies, the
additional byte precedes the opcode.
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A complete instruction consists of a prebyte, if any, an opcode, and zero, one, t wo,
or three operands. The operands contain information the CPU needs for executing
the instruction. Complete instructions can be from one to five bytes long.
4.5 Addressing Modes
Six addressing modes can be used to access memory:
•Immediate
•Direct
• Extended
• Indexed
• Inherent
•Relative
These modes are detailed in the following paragraphs. All modes except inherent
mode use an effective address. The effective address is the memory address from
which the argument is fetched or stored or the address from which execution is to
proceed. The effective address can be specified within an instruction, or it can be
calculated.
4.5.1 Immediate
In the immediate addressing mode, an argument is contained in the byte(s)
immediately following the opcode. The number of bytes following the opcode
matches the size of the register or memory location being operated on. There are
2-, 3-, and 4- (if prebyte is required) byte immediate instructions. The effective
address is the address of the byte following the instruction.
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Central Processor Unit (CPU)
4.5.2 Direct
In the direct addressing mode, the low-order byte of the operand address is
contained in a single byte following the opcode, and the high-order byte of the
address is assumed to be $00. Addresses $00–$FF are thus accessed directly,
using 2-byte instructions. Execution time is reduced by eliminating the additional
memory access required for the high-order address byte. In most applications, this
256-byte area is reserved for frequently referenced data. In M68HC11 MCUs, the
memory map can be configured for combinations of internal registers, RAM, or
external memory to occupy these addresses.
4.5.3 Extended
In the extended addressing mode, the effective address of the argument is
contained in two bytes following the opcode byte. These are 3-byte instructions (or
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4-byte instructions if a prebyte is required). One or two bytes are needed for the
opcode and two for the effective address.
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4.5.4 Indexed
4.5.5 Inherent
4.5.6 Relative
In the indexed addressing mode, an 8-bit unsigned offset contained in the
instruction is added to the value contained in an index register (IX or IY). The sum
is the effective address. This addressing mode allows referencing any memory
location in the 64-Kbyte address space. These are 2- to 5-byte instructions,
depending on whether or not a prebyte is required.
In the inherent addressing mode, all the information necessary to execute the
instruction is contained in the opcode. Operations that use only t he index registers
or accumulators, as well as control instructions with no arguments, are included in
this addressing mode. These are
1- or 2-byte instructions.
The relative addressing mode is used only for branch instructions. If the branch
condition is true, an 8-bit signed offset included in the instruction is added to the
contents of the program counter to form the effective branch address. Otherwise,
control proceeds to the next instruction. These are usually 2-byte instructions.
4.6 Instruction Set
Refer to Table 4-2, which shows all the M68HC11 instructions in all possible
addressing modes. For each instruction, the table shows the operand construction,
the number of machine code bytes, and execution time in CPU E-clock cycles.
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Central Processor Unit (CPU)
Instruction Set
Table 4-2. Instruction Set (Sheet 1 of 7)
Mnemonic Operation Description
ABA Add
ABX Add B to X I X + (0 0 : B) ⇒ IX INH 3A — 3 ————————
ABY Add B to Y I Y + (0 0 : B) ⇒ IY INH 18 3A — 4 ————————
ADCA (opr) Add with Carry
ADCB (opr) Add with Carry
ADDA (opr) Add Memory t o
ADDB (opr) Add Memory t o
ADDD (opr) Add 16-Bit to D D + (M : M + 1) ⇒ DIMM
ANDA (opr) AND A with
ANDB (opr) AND B with
ASL (opr) Arithmetic Shift
ASLA Arithmetic Shift
ASLB Arithmetic Shift
ASLD Arithmeti c Shift
ASR Arithmetic Shift
ASRA Arithmetic Shift
ASRB Arithmetic Shift
BCC (rel) Branch if Car ry
BCLR (opr)
BCS (rel) Branch if Carry
Accumulators
to A
to B
A
B
Memory
Memory
Left
Left A
Left B
Left D
Right
Right A
Right B
Clear
Clear Bit(s) M • (mm
(msk)
Set
A + B ⇒ AINH1B—2——∆ — ∆∆∆∆
A + M + C ⇒ AA IMM
B + M + C ⇒ BB IMM
A + M ⇒ A A IMM
B + M ⇒ BBIMM
A • M ⇒ AA IMM
B • M ⇒ BBIMM
b7 b0
C
b0
b7
C
b7 b0
C
b0
b7 b0
ABb7
C
b7 b0
b7 b0
b7 b0
? C = 0 REL 24 rr 3 ————————
) ⇒ M DIR
? C = 1 REL 25 rr 3 ————————
Addressing Instruction Condition Codes
Mode Opcode Operand Cycles S X H I N Z V C
89
ADIR
AEXT
AIND,X
AIND,Y
BDIR
BEXT
BIND,X
BIND,Y
ADIR
AEXT
AIND,X
AIND,Y
BDIR
BEXT
BIND,X
BIND,Y
DIR
EXT
IND,X
IND,Y
A DIR
A EXT
AIND,X
AIND,Y
BDIR
BEXT
BIND,X
BIND,Y
EXT
0
0
0
0
C
C
C
IND,X
IND,Y
A INH 48 — 2 ————∆∆∆∆
B INH 58 — 2 ————∆∆∆∆
INH 05 — 3 — — — — ∆∆∆∆
EXT
IND,X
IND,Y
A INH 47 — 2 ————∆∆∆∆
B INH 57 — 2 ————∆∆∆∆
IND,X
IND,Y
18 A9
18 E9
18 AB
18 EB
18 E3
18 A4
18 E4
18 68
18 67
18 1D
99
B9
A9
C9
D9
F9
E9
8B
9B
BB
AB
CB
DB
FB
EB
C3
D3
F3
E3
84
94
B4
A4
C4
D4
F4
E4
78
68
77
67
15
1D
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
hh ll
ff
ff
hh ll
ff
ff
dd mm
ff mm
ff mm
2
——∆ — ∆∆∆∆
3
4
4
5
2
——∆ — ∆∆∆∆
3
4
4
5
2
——∆ — ∆∆∆∆
3
4
4
5
2
——∆ — ∆∆∆∆
3
4
4
5
4
————∆∆∆∆
5
6
6
7
2
————∆∆0—
3
4
4
5
2
————∆∆0—
3
4
4
5
6
————∆∆∆∆
6
7
6
————∆∆∆∆
6
7
6
————∆∆0—
7
8
M68HC11E Family — Rev. 5 Data Sheet
MOTOROLA Central Processor Unit (CPU) 81
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Page 82
Central Processor Unit (CPU)
Mnemonic Operation Description
BEQ (rel) Branch if = Zero ? Z = 1 REL 27 rr 3 — — — — — — — —
BGE (rel) Branch if ∆ Zero ? N ⊕ V = 0 REL 2C rr 3 ————————
BGT (rel) Branch if > Zero ? Z + (N ⊕ V) = 0 REL 2E rr 3 ————————
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BHI (rel) Branch if
BHS (rel) Branch if
BITA (opr) Bit(s) Test A
BITB (opr) Bit(s) Test B
BLE (rel) Branch if ∆ Zero ? Z + (N ⊕ V) = 1 REL 2F rr 3 ————————
BLO (rel) Branch if Lower ? C = 1 REL 25 rr 3 ————————
BLS (rel) Branch if Lo wer
BLT (rel) Branch if < Zero ? N ⊕ V = 1 REL 2D rr 3 ————————
BMI (rel) Branch if Minus ? N = 1 REL 2B rr 3 ————————
BNE (rel) Branch if not =
BPL (rel) Branch if Plus ? N = 0 REL 2A rr 3 ————————
BRA (rel) Branch Always ? 1 = 1 REL 20 rr 3 ————————
BRCLR(opr)
(msk)
(rel)
BRN (rel) Branch Never ? 1 = 0 REL 21 rr 3 ————————
BRSET(opr)
(msk)
(rel)
BSET (opr)
(msk)
BSR (rel) Branch to
BVC (rel) Branch if
BVS (rel) Branch if
CBA Compare A to B A – B INH 11 — 2 — — — — ∆∆∆∆
CLC Clear Carry Bit 0 ⇒ C INH 0C — 2 ——————— 0
CLI Clear Interrupt
CLR (opr) Clear Memory
CLRA Clear
CLRB Clear
CLV Clear Overflow
Higher
Higher or Same
with Memory
with Memory
or Same
Zero
Branch if
Bit(s) Clear
Branch if Bit(s)
Set
Set Bit(s) M + mm ⇒ MDIR
Subroutine
Overflow Clear
Overflow Set
Mask
Byte
Accumulator A
Accumulator B
Flag
? C + Z = 0 REL 22 rr 3 ————————
? C + Z = 1 REL 23 rr 3 ————————
? M • mm = 0 DIR
? (M
See Figure 3–2 REL 8D rr 6 ————————
Freescale Semiconductor, Inc.
Table 4-2. Instruction Set (Sheet 2 of 7)
Addressing Instruction Condition Codes
Mode Opcode Operand Cycles S X H I N Z V C
? C = 0 REL 24 rr 3 ————————
A • M A IMM
B • M B IMM
? Z = 0 REL 26 rr 3 ————————
) • mm = 0 DIR
? V = 0 REL 28 rr 3 ————————
? V = 1 REL 29 rr 3 ————————
0 ⇒ I INH 0E — 2 ——— 0 ————
0 ⇒ MEXT
0 ⇒ A A INH 4F — 2 — — — — 0 1 0 0
0 ⇒ B B INH 5F — 2 — — — — 0 1 0 0
0 ⇒ V INH 0A — 2 ——————0—
ADIR
AEXT
AIND,X
AIND,Y
BDIR
BEXT
BIND,X
BIND,Y
IND,X
IND,Y
IND,X
IND,Y
IND,X
IND,Y
IND,X
IND,Y
85
95
B5
A5
18 A5
C5
D5
F5
E5
18 E5
13
1F
18 1F
12
1E
18 1E
14
1C
18 1C
7F
6F
18 6F
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
dd mm
rr
ff mm
rr
ff mm
rr
dd mm
rr
ff mm
rr
ff mm
rr
dd mm
ff mm
ff mm
hh ll
ff
ff
2
————∆∆0—
3
4
4
5
2
————∆∆0—
3
4
4
5
6
————————
7
8
6
————————
7
8
6
————∆∆0—
7
8
6
————0 1 0 0
6
7
Data Sheet M68HC11E Family — Rev. 5
82 Central Processor Unit (CPU) MOTOROLA
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Page 83
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Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Instruction Set
Table 4-2. Instruction Set (Sheet 3 of 7)
Mnemonic Operation Description
CMPA (opr) Compare A to
CMPB (opr) Compare B to
COM (opr) Ones
COMA Ones
COMB Ones
CPD (opr) Compare D to
CPX (opr) Compare X to
CPY (opr) Compare Y to
DAA Decimal Adjust AAdjust Sum to BCD INH 19 — 2 — — — — ∆∆∆∆
DEC (opr) Decrement
DECA Decrement
DECB Decrement
DES Decrement
DEX Decrement
DEY Decrement
EORA (opr) Exclusive OR A
EORB (opr) Exclusive OR B
FDIV Fractional
IDIV Integer Divide
Memory
Memory
Complement
Memory Byte
Complement
A
Complement
B
Memory 16-Bit
Memory 16-Bit
Memory 16-Bit
Memory Byte
Accumulator
A
Accumulator
B
Stack Pointer
Index Register
X
Index Register
Y
with Memory
with Memory
Divide 16 by 16
16 by 16
A – M A IMM
B – M B IMM
$FF – M ⇒ MEXT
$FF – A ⇒ AA INH 43 — 2————∆∆01
$FF – B ⇒ BB INH 53 — 2————∆∆01
D – M : M + 1 IMM
IX – M : M + 1 IMM
IY – M : M + 1 IMM
M – 1 ⇒ MEXT
A – 1 ⇒ AAINH 4A— 2————∆∆∆—
B – 1 ⇒ BBINH 5A— 2————∆∆∆—
SP – 1 ⇒ SP INH 34 — 3 —————— ——
IX – 1 ⇒ IX INH 09 — 3 — — — — — ∆ ——
IY – 1 ⇒ IY INH 18 09 — 4 — — — — — ∆ ——
A ⊕ M ⇒ A A IMM
B ⊕ M ⇒ B B IMM
D / IX ⇒ IX; r ⇒ D INH 03 — 41 —————∆∆∆
D / IX ⇒ IX; r ⇒ D INH 02 — 41 —————∆ 0 ∆
Addressing Instruction Condition Codes
Mode Opcode Operand Cycles S X H I N Z V C
ADIR
AEXT
AIND,X
AIND,Y
BDIR
BEXT
BIND,X
BIND,Y
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
IND,X
IND,Y
ADIR
AEXT
AIND,X
AIND,Y
BDIR
BEXT
BIND,X
BIND,Y
81
91
B1
A1
18 A1
C1
D1
F1
E1
18 E1
73
63
18 63
1A 83
1A 93
1A B3
1A A3
CD A3
8C
9C
BC
AC
CD AC
18 8C
18 9C
18 BC
1A AC
18 AC
7A
6A
18 6A
88
98
B8
A8
18 A8
C8
D8
F8
E8
18 E8
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
hh ll
ff
ff
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
2
————∆∆∆∆
3
4
4
5
2
————∆∆∆∆
3
4
4
5
6
————∆∆01
6
7
5
————∆∆∆∆
6
7
7
7
4
————∆∆∆∆
5
6
6
7
5
————∆∆∆∆
6
7
7
7
6
————∆∆∆—
6
7
2
————∆∆0—
3
4
4
5
2
————∆∆0—
3
4
4
5
M68HC11E Family — Rev. 5 Data Sheet
MOTOROLA Central Processor Unit (CPU) 83
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Page 84
Central Processor Unit (CPU)
Mnemonic Operation Description
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INC (opr) Increment
INCA Increment
INCB Increment
INS Increment
INX Increment
INY Increment
JMP (opr) Jump See Figure 3–2 EXT
JSR (opr) Jump to
LDAA (opr) Load
LDAB (opr) Load
LDD (opr) Load Double
LDS (opr) Load Stack
LDX (opr) Load Index
LDY (opr) Load Index
LSL (opr) Logical Shift
LSLA Logical Shift
LSLB Logical Shift
LSLD Logical Shift
Memory Byte
Accumulator
A
Accumulator
B
Stack Pointer
Index Register
X
Index Register
Y
Subroutine
Accumulator
A
Accumulator
B
Accumulator
D
Pointer
Register
X
Register
Y
Left
Left A
Left B
Left Double
M + 1 ⇒ MEXT
A + 1 ⇒ A A INH 4C — 2 — — — — ∆∆∆—
B + 1 ⇒ B B INH 5C — 2 — — — — ∆∆∆—
SP + 1 ⇒ SP INH 31 — 3 ————————
IX + 1 ⇒ IX INH 08 — 3 ————— ∆ ——
IY + 1 ⇒ IY INH 18 08 — 4 ————— ∆ ——
See Figure 3–2 DIR
M ⇒ A,M + 1 ⇒ BIMM
M : M + 1 ⇒ SP IMM
M : M + 1 ⇒ IX IMM
M : M + 1 ⇒ IY IMM
C
C
C
b7 b0ABb7
C
Freescale Semiconductor, Inc.
Table 4-2. Instruction Set (Sheet 4 of 7)
Addressing Instruction Condition Codes
Mode Opcode Operand Cycles S X H I N Z V C
IND,X
IND,Y
IND,X
IND,Y
EXT
IND,X
M ⇒ A A IMM
M ⇒ B B IMM
0
b0
b7
b7 b0
b7 b0
0
0
b0
0
IND,Y
A DIR
A EXT
A IND,X
A IND,Y
B DIR
B EXT
B IND,X
B IND,Y
DIR
EXT
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
EXT
IND,X
IND,Y
A INH 48 — 2 ————∆∆∆∆
B INH 58 — 2 ————∆∆∆∆
INH 05 — 3 — — — — ∆∆∆∆
7C
6C
18 6C
7E
6E
18 6E
9D
BD
AD
18 AD
86
96
B6
A6
18 A6
C6
D6
F6
E6
18 E6
CC
DC
FC
EC
18 EC
8E
9E
BE
AE
18 AE
CE
DE
FE
EE
CD EE
18 CE
18 DE
18 FE
1A EE
18 EE
78
68
18 68
hh ll
ff
ff
hh ll
ff
ff
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
hh ll
ff
ff
6
6
7
3
3
4
5
6
6
7
2
3
4
4
5
2
3
4
4
5
3
4
5
5
6
3
4
5
5
6
3
4
5
5
6
4
5
6
6
6
6
6
7
————∆∆∆—
————————
————————
————∆∆0—
————∆∆0—
————∆∆0—
————∆∆0—
————∆∆0—
————∆∆0—
————∆∆∆∆
Data Sheet M68HC11E Family — Rev. 5
84 Central Processor Unit (CPU) MOTOROLA
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Page 85
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Central Processor Unit (CPU)
Instruction Set
Table 4-2. Instruction Set (Sheet 5 of 7)
Mnemonic Operation Description
LSR (opr) Logical Shift
LSRA Logical Shift
LSRB Logical Shift
LSRD Logical Shift
MUL Multiply 8 by 8 A ∗ B ⇒ D INH 3D — 10 ———————∆
NEG (opr) Two’s
NEGA Two’s
NEGB Two’s
NOP No operation No Operation INH 01 — 2 — — — — — — — —
ORAA (opr) OR
ORAB (opr) OR
PSHA Push A onto
PSHB Push B onto
PSHX Push X onto
PSHY Push Y onto
PULA Pull A from
PULB Pull B from
PULX Pull X From
PULY Pull Y from
ROL (opr) Rotate Left EXT
ROLA Rotate Left A A INH 49 — 2 — — — — ∆∆∆∆
ROLB Rotate Left B B INH 59 — 2 — — — — ∆∆∆∆
ROR (opr) Rotate Right EXT
Right
Right A
Right B
Right Double
Complement
Memory Byte
Complement
A
Complement
B
Accumulator
A (Inclusive)
Accumulator
B (Inclusive)
Stack
Stack
Stack (Lo
First)
Stack (Lo
First)
Stack
Stack
Stack (Hi
First)
Stack (Hi
First)
0
b7 b0
0
b7 b0
0
b7 b0
0
b0
ABb7
b7 b0
0 – M ⇒ MEXT
0 – A ⇒ AAINH 40 — 2————∆∆∆∆
0 – B ⇒ BBINH 50 — 2————∆∆∆∆
A + M ⇒ A A IMM
B + M ⇒ B B IMM
A ⇒ Stk,SP = SP – 1 A INH 36 — 3 — — — — — — — —
B ⇒ Stk,SP = SP – 1 B INH 37 — 3 — — — — — — — —
IX ⇒ Stk,SP = SP – 2 INH 3C — 4 ————————
IY ⇒ Stk,SP = SP – 2 INH 18 3C — 5 ————————
SP = SP + 1, A ⇐ StkA INH 32 — 4 ————————
SP = SP + 1, B ⇐ StkB INH 33 — 4 ————————
SP = SP + 2, IX ⇐ Stk INH 38 — 5 ————————
SP = SP + 2, IY ⇐ Stk INH 18 38 — 6 ————————
b7 b0
C
b7 b0
C
b7
C
b7 b0
C
Addressing Instruction Condition Codes
Mode Opcode Operand Cycles S X H I N Z V C
EXT
IND,X
C
C
C
C
b0
IND,Y
A INH 44 — 2 ———— 0 ∆∆∆
B INH 54 — 2 ———— 0 ∆∆∆
INH 04 — 3 — — — — 0 ∆∆∆
IND,X
IND,Y
ADIR
AEXT
AIND,X
AIND,Y
BDIR
BEXT
BIND,X
BIND,Y
IND,X
IND,Y
IND,X
IND,Y
74
64
18 64
70
60
18 60
8A
9A
BA
AA
18 AA
CA
DA
FA
EA
18 EA
79
69
18 69
76
66
18 66
hh ll
ff
ff
hh ll
ff
ff
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
hh ll
ff
ff
hh ll
ff
ff
6
————0 ∆∆∆
6
7
6
————∆∆∆∆
6
7
————∆∆0—
2
3
4
4
5
————∆∆0—
2
3
4
4
5
6
————∆∆∆∆
6
7
6
————∆∆∆∆
6
7
M68HC11E Family — Rev. 5 Data Sheet
MOTOROLA Central Processor Unit (CPU) 85
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Central Processor Unit (CPU)
Mnemonic Operation Description
RORA Rotate Right A A INH 46 — 2 — — — — ∆∆∆∆
RORB Rotate Right B B INH 56 — 2 — — — — ∆∆∆∆
RTI Return from
RTS Return from
SBA Subtract B from
SBCA (opr) Subtract with
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I
SBCB (opr) Subtract with
SEC Set Carry 1 ⇒ C INH 0D — 2 ——————— 1
SEI Set Interrupt
SEV Set Overflow
STAA (opr) Store
STAB (opr) Store
STD (opr) Store
STOP Stop Internal
STS (opr) Store Stack
Interrupt
Subroutine
A
Carry from A
Carry from B
Mask
Flag
Accumulator
A
Accumulator
B
Accumulator
D
Clocks
Pointer
b7 b0
b7 b0
See Figure 3–2 INH 3B — 12 ∆↓∆∆∆∆∆∆
See Figure 3–2 INH 39 — 5 — — — — — — — —
A – B ⇒ A INH 10 — 2 ————∆∆∆∆
A – M – C ⇒ AA IMM
B – M – C ⇒ BB IMM
A ⇒ M, B ⇒ M + 1 DIR
SP ⇒ M : M + 1 DIR
cale Semiconductor,
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STX (opr) Store Index
STY (opr) Store Index
SUBA (opr) Subtract
SUBB (opr) Subtract
SUBD (opr) Subtract
Register X
Register Y
Memory from
A
Memory from
B
Memory from
D
IX ⇒ M : M + 1 DIR
IY ⇒ M : M + 1 DIR
A – M ⇒ AAIMM
B – M ⇒ BAIMM
D – M : M + 1 ⇒ DIMM
Freescale Semiconductor, Inc.
Table 4-2. Instruction Set (Sheet 6 of 7)
Addressing Instruction Condition Codes
Mode Opcode Operand Cycles S X H I N Z V C
C
C
82
ADIR
AEXT
AIND,X
AIND,Y
BDIR
BEXT
BIND,X
BIND,Y
1 ⇒ I INH 0F — 2 ——— 1 ————
1 ⇒ V INH 0B — 2 ——————1—
A ⇒ MADIR
B ⇒ MBDIR
— INH CF — 2 ————————
AEXT
AIND,X
AIND,Y
BEXT
BIND,X
BIND,Y
EXT
IND,X
IND,Y
EXT
IND,X
IND,Y
EXT
IND,X
IND,Y
EXT
IND,X
IND,Y
ADIR
AEXT
AIND,X
AIND,Y
ADIR
AEXT
AIND,X
AIND,Y
DIR
EXT
IND,X
IND,Y
18 A2
18 E2
18 A7
18 E7
18 ED
18 AF
CD EF
18 DF
18 FF
1A EF
18 EF
18 A0
18 E0
18 A3
92
B2
A2
C2
D2
F2
E2
97
B7
A7
D7
F7
E7
DD
FD
ED
9F
BF
AF
DF
FF
EF
80
90
B0
A0
C0
D0
F0
E0
83
93
B3
A3
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
dd
hh ll
ff
ff
dd
hh ll
ff
ff
dd
hh ll
ff
ff
dd
hh ll
ff
ff
dd
hh ll
ff
ff
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
2
————∆∆∆∆
3
4
4
5
2
————∆∆∆∆
3
4
4
5
3
————∆∆0—
4
4
5
3
————∆∆0—
4
4
5
4
————∆∆0—
5
5
6
4
————∆∆0—
5
5
6
4
————∆∆0—
5
5
6
5
————∆∆0—
6
6
6
2
————∆∆∆∆
3
4
4
5
2
————∆∆∆∆
3
4
4
5
4
————∆∆∆∆
5
6
6
7
Data Sheet M68HC11E Family — Rev. 5
86 Central Processor Unit (CPU) MOTOROLA
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Go to: www.freescale.com
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Central Processor Unit (CPU)
Instruction Set
Table 4-2. Instruction Set (Sheet 7 of 7)
Mnemonic Operation Description
SWI Software
TAB Transfer A to B A ⇒ B INH 16 — 2 ———— ∆∆0—
TAP Transfer A to
TBA Transfer B to A B ⇒ A INH 17 — 2 ———— ∆∆0—
TEST TEST (Only in
TPA Transfer CC
TST (opr) Test for Zero or
TSTA Test A for Zero
TSTB Test B for Zero
TSX Transfer Stack
TSY Transfer Stack
TXS Transfer X to
TYS Transfer Y to
WAI Wait for
XGDX Exchange D
XGDY Exchange D
Cycle
* Infinity or until reset occurs
** 12 cycles are used beginning with the opcode fetch. A wait state is entered which remains in effect for an int eger number of MPU E-clock
cycles (n) until an interrupt is recognized. Finally, two additional cycles are used to fetch the appropriat e interrupt vector (14 + n total).
Operands
dd = 8-bit direct address ($0000–$00FF) (high byte assumed to be $00)
ff = 8-bit positive offset $00 (0) to $FF (255) (is added to index)
hh = High-order byte of 16-bit extended address
ii = One byte of immediate data
jj = High-order byte of 16-bit immediate data
kk = Low-order byte of 16-bit immediate data
ll = Low-order byte of 16-bit extended address
mm = 8-bit mask (set bits to be affected)
rr = Signed relative offset $80 (–128) to $7F (+127)
Interrupt
CC Register
Test Modes)
Register to A
Minus
or Minus
or Minus
Pointer to X
Pointer to Y
Stack Pointer
Stack Pointer
Interrupt
with X
with Y
(offset relative to address following machine code offset byte))
See Figure 3–2 INH 3F — 14 — — — 1 — — — —
A ⇒ CCR INH 06 — 2 ∆↓∆∆∆∆∆∆
Address Bus Counts INH 00 — * — — — — — — — —
CCR ⇒ A INH 07 — 2 ————————
M – 0 EXT
A – 0 A INH 4D — 2 — — — — ∆∆00
B – 0 B INH 5D — 2 — — — — ∆∆00
SP + 1 ⇒ IX INH 30 — 3 ——— ——— ——
SP + 1 ⇒ IY INH 18 30 — 4 ————————
IX – 1 ⇒ SP INH 35 — 3 ————————
IY – 1 ⇒ SP INH 18 35 — 4 ————————
Stack Regs & WAIT INH 3E — ** — — — — — — — —
IX ⇒ D, D ⇒ IX INH 8F — 3 ————————
IY ⇒ D, D ⇒ IY INH 18 8F — 4 ————————
Addressing Instruction Condition Codes
Mode Opcode Operand Cycles S X H I N Z V C
7D
IND,X
IND,Y
6D
18 6D
hh ll
ff
ff
6
————∆∆00
6
7
Operators
( ) Contents of register shown inside parentheses
⇐ Is transferred to
⇑ Is pulled from stack
⇓ Is pushed onto stack
• Boolean AND
+ Arithmetic addition symbol except where used as inclusive-OR symbol
in Boolean formula
⊕ Exclusive-OR
∗ Multiply
: Concatenation
– Arithmetic subtraction symbol or negation symbol (two’s complement)
Condition Codes
— Bit not changed
0 Bit always cleared
1 Bit always set
∆ Bit cleared or set, depending on operation
↓ Bit can be cleared, cannot become set
M68HC11E Family — Rev. 5 Data Sheet
MOTOROLA Central Processor Unit (CPU) 87
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Page 88
Central Processor Unit (CPU)
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Data Sheet M68HC11E Family — Rev. 5
88 Central Processor Unit (CPU) MOTOROLA
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Data Sheet — M68HC11E Family
Section 5. Resets and Interrupts
5.1 Introduction
Resets and interrupt operations load the program counter with a vector that points
to a new location from which instructions are to be fetched. A reset immediately
stops execution of the current instruction and forces the program counter to a
known starting address. Internal registers and control bits are initialized so the
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MCU can resume executing instructions. An interrupt temporarily suspends normal
program execution while an interrupt service routine is being executed. After an
interrupt has been serviced, the main program resumes as if there had been no
interruption.
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5.2 Resets
The four possible sources of reset are:
• Power-on reset (POR)
• External reset (RESET
• Computer operating properly (COP) reset
• Clock monitor reset
POR and RESET
reset each has its own vector.
5.2.1 Power-On Reset (POR)
A positive transition on V
for power-up conditions. POR cannot be used to detect drops in power supply
voltages. A 4064 t
active allows the clock generator to stabilize. If RESET
4064 t
The POR circuit only initializes internal circuitry during cold starts. Refer to
Figure 1-7. External Reset Circuit.
NOTE: It is important to protect the MCU during power transitions. Most M68HC11
systems need an external circuit that holds the RESET
below the minimum operating level. This external voltage level detector, or other
external reset circuits, are the usual source of reset in a system.
CYC
)
share the normal reset vector. COP reset and the clock monitor
generates a power-on reset (POR), which is used only
DD
(internal clock cycle) delay after the oscillator becomes
CYC
is at logical 0 at the end of
, the CPU remains in the reset condition until RESET goes to logical 1.
pin low whenever VDD is
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Resets and Interrupts
5.2.2 External Reset (RESET)
The CPU distinguishes between internal and external reset conditions by sensing
whether the reset pin rises to a logic 1 in less than two E-clock cycles after an
internal device releases reset. When a reset condition is sensed, the RESET
driven low by an internal device for four E-clock cycles, then released. Two E-clock
cycles later it is sampled. If the pin is still held low, the CPU assumes that an
external reset has occurred. If the pin is high, it indicates that the reset was initiated
internally by either the COP system or the clock monitor.
CAUTION: Do not connect an external resistor capacitor (RC) power-up delay circuit to the
reset pin of M68HC11 devices because the circuit charge time constant can cause
the device to misinterpret the type of reset that occurred.
pin is
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5.2.3 Computer Operating Properly (COP) Reset
The MCU includes a COP system to help protect against software failures. When
the COP is enabled, the software is responsible for keeping a free-running
watchdog timer from timing out. When the software is no longer being executed in
the intended sequence, a system reset is initiated.
The state of the NOCOP bit in the CONFIG register determines whether the COP
system is enabled or disabled. To change the enable status of the COP system,
change the contents of the CONFIG register and then perform a system reset. In
the special test and bootstrap operating modes, the COP system is initially
inhibited by the disable resets (DISR) control bit in the TEST1 register. The DISR
bit can subsequently be written to 0 to enable COP resets.
The COP timer rate control bits CR[1:0] in the OPTION register determine the COP
timeout period. The system E clock is divided by 2
factor shown in Table 5-1. After reset, these bits are 0, which selects the fastest
timeout period. In normal operating modes, these bits can be written only once
within 64 bus cycles after reset.
Table 5-1. COP Timer Rate Select
XTAL = 4.0 MHz
By
Timeout
– 0 ms, + 32.8 ms
CR[1:0]
Divide
15
E/2
XTAL = 8.0 MHz
Timeout
– 0 ms, + 16.4 ms
15
and then further scaled by a
XTAL = 12.0 MHz
Timeout
– 0 ms, + 10.9 ms
XTAL = 16.0 MHz
Timeout
– 0 ms, + 8.2 ms
0 0 1 32.768 ms 16.384 ms 10.923 ms 8.19 ms
0 1 4 131.072 ms 65.536 ms 43.691 ms 32.8 ms
1 0 16 524.28 ms 262.14 ms 174.76 ms 131 ms
1 1 64 2.098 s 1.049 s 699.05 ms 524 ms
E = 1.0 MHz 2.0 MHz 3.0 MHz 4.0 MHz
Data Sheet M68HC11E Family — Rev. 5
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Address $103A
Read:
Write:
Reset: 0
Figure 5-1. Arm/Reset COP Timer Circuitry Register (COPRST)
Complete this 2-step reset sequence to service the COP timer:
1. Write $55 to COPRST to arm the COP timer clearing mechanism.
2. Write $AA to COPRST to clear the COP timer.
Performing instructions between these two steps is possible as long
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5.2.4 Clock Monitor Reset
as both steps are completed in the correct sequence before the timer times out.
Resets and Interrupts
Resets
Bit 7654321Bit 0
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0000000
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The clock monitor circuit is based on an internal resistor capacitor (RC) time delay.
If no MCU clock edges are detected within this RC time delay, the clock monitor
can optionally generate a system reset. The clock monitor function is enabled or
disabled by the CME control bit in the OPTION register. The presence of a timeout
is determined by the RC delay, which allows the clock monitor to operate without
any MCU clocks.
Clock monitor is used as a backup for the COP system. Because the COP needs
a clock to function, it is disabled when the clock stops. Therefore, the clock monitor
system can detect clock failures not detected by the COP system.
Semiconductor wafer processing causes variations of the RC timeout values
between individual devices. An E-clock frequency below 10 kHz is detected as a
clock monitor error. An E-clock frequency of 200 kHz or more prevents clock
monitor errors. Using the clock monitor function when the E-clock is below 200 kHz
is not recommended.
Special considerations are needed when a STOP instruction is executed and the
clock monitor is enabled. Because the STOP function causes the clocks to be
halted, the clock monitor function generates a reset sequence if it is enabled at the
time the stop mode was initiated. Before executing a STOP instruction, clear the
CME bit in the OPTION register to 0 to disable the clock monitor. After recovery
from STOP, set the CME bit to logic 1 to enable the clock monitor. Alternatively,
executing a STOP instruction with the CME bit set to logic 1 can be used as a
software initiated reset.
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Resets and Interrupts
5.2.5 System Configuration Options Register
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Address: $1039
Read:
Write:
Reset: 0
1. Can be written only once in first 64 cycles out of reset in normal mode or at any time in special modes
Figure 5-2. System Configuration Options Register (OPTION)
ADPU — Analog-to-Digital Converter Power-Up Bit
Refer to Section 3. Analog-to-Digital (A/D) Converter.
CSEL — Clock Select Bit
Refer to Section 3. Analog-to-Digital (A/D) Converter.
Bit 7654321Bit 0
ADPU CSEL IRQE
0010000
= Unimplemented
(1)
DLY
(1)
CME CR1
(1)
CR0
(1)
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IRQE — Configure IRQ
0 = IRQ
1 = IRQ
DLY — Enable Oscillator Startup Delay Bit
Refer to Section 2. Operating Modes and On-Chip Memory and Section 3.
Analog-to-Digital (A/D) Converter.
CME — Clock Monitor Enable Bit
This control bit can be read or written at any time and controls whether or not
the internal clock monitor circuit triggers a reset sequence when the system
clock is slow or absent. When it is clear, the clock monitor circuit is disabled, and
when it is set, the clock monitor circuit is enabled. Reset clears the CME bit.
0 = Clock monitor circuit disabled
1 = Slow or stopped clocks cause reset
Bit 2 — Unimplemented
Always reads 0
CR[1:0] — COP Timer Rate Select Bit
The internal E clock is first divided by 2
system. These control bits determine a scaling factor for the watchdog timer.
See Table 5-1 for specific timeout settings.
is configured for level-sensitive operation.
is configured for edge-sensitive-only operation.
for Edge-Sensitive-Only Operation Bit
15
before it enters the COP watchdog
Data Sheet M68HC11E Family — Rev. 5
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5.2.6 Configuration Control Register
Address: $103F
Read:
Write:
Reset: 0
EE[3:0] — EEPROM Mapping Bits
EE[3:0] apply only to MC68HC811E2. Refer to Section 2. Operating Modes
and On-Chip Memory.
Bit 7654321Bit 0
EE3 EE2 EE1 EE0 NOSEC NOCOP ROMON EEON
Figure 5-3. Configuration Control Register (CONFIG)
Resets and Interrupts
Effects of Reset
0001111
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NOSEC — Security Mode Disable Bit
NOCOP — COP System Disable Bit
ROMON — ROM (EPROM) Enable Bit
EEON — EEPROM Enable Bit
5.3 Effects of Reset
When a reset condition is recognized, the internal registers and control bits are
forced to an initial state. Depending on the cause of the reset and the operating
mode, the reset vector can be fetched from any of six possible locations. Refer to
Table 5-2.
Refer to Section 2. Operating Modes and On-Chip Memory.
0 = COP enabled (forces reset on timeout)
1 = COP disabled (does not force reset on timeout)
Refer to Section 2. Operating Modes and On-Chip Memory.
Refer to Section 2. Operating Modes and On-Chip Memory.
Table 5-2. Reset Cause, Reset Vector, and Operating Mode
Cause of Reset
POR or RESET
Normal Mode
Vector
pin $FFFE, FFFF $BFFE, $BFFF
Special Test
or Bootstrap
Clock monitor failure $FFFC, FFFD $BFFC, $BFFD
COP Watchdog Timeout $FFFA, FFFB $BFFA, $BFFB
These initial states then control on-chip peripheral systems to force them to known
startup states, as described in the following subsections.
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Resets and Interrupts
5.3.1 Central Processor Unit (CPU)
5.3.2 Memory Map
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After reset, the central processor unit (CPU) fetches the restart vector from the
appropriate address during the first three cycles and begins executing instructions.
The stack pointer and other CPU registers are indeterminate immediately after
reset; however, the X and I interrupt mask bits in the condition code register (CCR)
are set to mask any interrupt requests. Also, the S bit in the CCR is set to inhibit
stop mode.
After reset, the INIT register is initialized to $01, mapping the RAM at $00 and the
control registers at $1000.
For the MC68HC811E2, the CONFIG register resets to $FF. EEPROM mapping
bits (EE[3:0]) place the EEPROM at $F800. Refer to the memory map diagram for
MC68HC811E2 in Section 2. Operating Modes and On-Chip Memory.
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5.3.3 Timer
During reset, the timer system is initialized to a count of $0000. The prescaler bits
are cleared, and all output compare registers are initialized to $FFFF. All input
capture registers are indeterminate after reset. The output compare 1 mask
(OC1M) register is cleared so that successful OC1 compares do not affect any I/O
pins. The other four output compares are configured so that they do not affect any
I/O pins on successful compares. All input capture edge-detector circuits are
configured for capture disabled operation. The timer overflow interrupt flag and all
eight timer function interrupt flags are cleared. All nine timer interrupts are disabled
because their mask bits have been cleared.
The I4/O5 bit in the PACTL register is cleared to configure the I4/O5 function as
OC5; however, the OM5:OL5 control bits in the TCTL1 register are clear so OC5
does not control the PA3 pin.
5.3.4 Real-Time Interrupt (RTI)
The real-time interrupt flag (RTIF) is cleared and automatic hardware interrupts are
masked. The rate control bits are cleared after reset and can be initialized by
software before the real-time interrupt (RTI) system is used.
5.3.5 Pulse Accumulator
The pulse accumulator system is disabled at reset so that the pulse accumulator
input (PAI) pin defaults to being a general-purpose input pin.
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5.3.6 Computer Operating Properly (COP)
The COP watchdog system is enabled if the NOCOP control bit in the CONFIG
register is cleared and disabled if NOCOP is set. The COP rate is set for the
shortest duration timeout.
5.3.7 Serial Communications Interface (SCI)
The reset condition of the SCI system is independent of the operating mode. At
reset, the SCI baud rate control register (BAUD) is initialized to $04. All transmit
and receive interrupts are masked and both the transmitter and receiver are
disabled so the port pins default to being general-purpose I/O lines. The SCI frame
format is initialized to an 8-bit character size. The send break and receiver wakeup
functions are disabled. The TDRE and TC status bits in the SCI status register
(SCSR) are both 1s, indicating that there is no transmit data in either the transmit
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data register or the transmit serial shift register. The RDRF, IDLE, OR, NF, FE, PF,
and RAF receive-related status bits in the SCI control register 2 (SCCR2) are
cleared.
Resets and Interrupts
Effects of Reset
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5.3.8 Serial Peripheral Interface (SPI)
The SPI system is disabled by reset. The port pins associated with this function
default to being general-purpose I/O lines.
5.3.9 Analog-to-Digital (A/D) Converter
The analog-to-digital (A/D) converter configuration is indeterminate after reset. The
ADPU bit is cleared by reset, which disables the A/D system. The conversion
complete flag is indeterminate.
5.3.10 System
The EEPROM programming controls are disabled, so the memory system is
configured for normal read operation. PSEL[3:0] are initialized with the value
%0110, causing the external IRQ
pin is configured for level-sensitive operation (for wired-OR systems). The
IRQ
RBOOT, SMOD, and MDA bits in the HPRIO register reflect the status of the
MODB and MODA inputs at the rising edge of reset. MODA and MODB inputs
select one of the four operating modes. After reset, writing SMOD and MDA in
special modes causes the MCU to change operating modes. Refer to the
description of HPRIO register in Section 2. Operating Modes and On-Chip
Memory for a detailed description of SMOD and MDA. The DLY control bit is set
to specify that an oscillator startup delay is imposed upon recovery from stop
mode. The clock monitor system is disabled because CME is cleared.
pin to have the highest I-bit interrupt priority. The
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Resets and Interrupts
5.4 Reset and Interrupt Priority
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Resets and interrupts have a hardware priority that determines which reset or
interrupt is serviced first when simultaneous requests occur. Any maskable
interrupt can be given priority over other maskable interrupts.
The first six interrupt sources are not maskable. The priority arrangement for these
sources is:
1. POR or RESET
2. Clock monitor reset
3. COP watchdog reset
4. XIRQ
5. Illegal opcode interrupt
6. Software interrupt (SWI)
The maskable interrupt sources have this priority arrangement:
1. IRQ
2. Real-time interrupt
3. Timer input capture 1
4. Timer input capture 2
5. Timer input capture 3
6. Timer output compare 1
7. Timer output compare 2
8. Timer output compare 3
9. Timer output compare 4
10. Timer input capture 4/output compare 5
11. Timer overflow
12. Pulse accumulator overflow
13. Pulse accumulator input edge
14. SPI transfer complete
15. SCI system (refer to Figure 5-7)
Any one of these interrupts can be assigned the highest maskable interrupt priority
by writing the appropriate value to the PSEL bits in the HPRIO register. Otherwise,
the priority arrangement remains the same. An interrupt that is assigned highest
priority is still subject to global masking by the I bit in the CCR, or by any associated
local bits. Interrupt vectors are not affected by priority assignment. To avoid race
conditions, HPRIO can be written only while I-bit interrupts are inhibited.
pin
interrupt
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5.4.1 Highest Priority Interrupt and Miscellaneous Register
Address: $103C
Read:
Write:
Reset:
Single chip:00000110
Expanded: 00100110
Bootstrap:11000110
Special test:01110110
1. The values of the RBOOT, SMOD, and MDA reset bits depend on the mode selected at the
RESET pin rising edge. Refer to Table 2-1. Hardware Mode Select Summary.
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Resets and Interrupts
Reset and Interrupt Priority
Bit 7654321Bit 0
RBOOT
(1)
Figure 5-4. Highest Priority I-Bit Interrupt
(1)
SMOD
and Miscellaneous Register (HPRIO)
MDA
(1)
IRVNE PSEL2 PSEL2 PSEL1 PSEL0
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RBOOT — Read Bootstrap ROM Bit
Has meaning only when the SMOD bit is a 1 (bootstrap mode or special test
mode). At all other times this bit is clear and cannot be written. Refer to Section
2. Operating Modes and On-Chip Memory for more information.
SMOD — Special Mode Select Bit
This bit reflects the inverse of the MODB input pin at the rising edge of reset.
Refer to Section 2. Operating Modes and On-Chip Memory for more
information.
MDA — Mode Select A Bit
The mode select A bit reflects the status of the MODA input pin at the rising
edge of reset. Refer to Section 2. Operating Modes and On-Chip Memory for
more information.
IRVNE — Internal Read Visibility/Not E Bit
The IRVNE control bit allows internal read accesses to be available on the
external data bus during operation in expanded modes. In single-chip and
bootstrap modes, IRVNE determines whether the E clock is driven out an
external pin. For the MC68HC811E2, this bit is IRV and only controls internal
read visibility. Refer to Section 2. Operating Modes and On-Chip Memory for
more information.
PSEL[3:0] — Priority Select Bits
These bits select one interrupt source to be elevated above all other I- bit-related
sources and can be written only while the I bit in the CCR is set (interrupts
disabled).
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Resets and Interrupts
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Table 5-3. Highest Priority Interrupt Selection
PSEL[3:0] Interrupt Source Promoted
0 0 0 0 Timer overflow
0 0 0 1 Pulse accumula to r overflow
0 0 1 0 Pulse accumulator input edge
0 0 1 1 SPI serial transfer complete
0 1 0 0 SCI serial system
0 1 0 1 Reserved (default to IRQ
0 1 1 0 IRQ
0 1 1 1 Real-time interrupt
1 0 0 0 Timer input capture 1
1 0 0 1 Timer input capture 2
1 0 1 0 Timer input capture 3
1 0 1 1 Timer output compare 1
1 1 0 0 Timer output compare 2
1 1 0 1 Timer output compare 3
1 1 1 0 Timer output compare 4
1 1 1 1 Timer input capture 4/output compare 5
(external pin or parallel I/O)
)
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5.5 Interrupts
The MCU has 18 interrupt vectors that support 22 interrupt sources. The 15
maskable interrupts are generated by on-chip peripheral systems. These interrupts
are recognized when the global interrupt mask bit (I) in the condition code register
(CCR) is clear. The three non-maskable interrupt sources are illegal opcode trap,
software interrupt, and XIRQ
sources and vector assignments for each source.
For some interrupt sources, such as the SCI interrupts, the flags are automatically
cleared during the normal course of responding to the interrupt requests. For
example, the RDRF flag in the SCI system is cleared by the automatic clearing
mechanism consisting of a read of the SCI status register while RDRF is set,
followed by a read of the SCI data register. The normal response to an RDRF
interrupt request would be to read the SCI status register to check for receive
errors, then to read the received data from the SCI data register. These steps
satisfy the automatic clearing mechanism without requiring special instructions.
pin. Refer to Table 5-4, which shows the interrupt
Data Sheet M68HC11E Family — Rev. 5
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Table 5-4. Interrupt and Reset Vector Assignments
Resets and Interrupts
Interrupts
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Vector Address Interrupt Source
FFC0, C1 – FFD4, D5 Reserved — —
SCI serial system
• SCI receive data register full
FFD6, D7
FFD8, D9 SPI serial transfer complete I SPIE
FFDA, DB Pulse accumulator input edge I PAII
FFDC, DD Pulse accumulator overflow I P AOVI
FFDE, DF Timer overflow I TOI
FFE0, E1 Timer input capture 4/output compare 5 I I4/O5I
FFE2, E3 Timer output compare 4 I OC4I
FFE4, E5 Timer output compare 3 I OC3I
FFE6, E7 Timer output compare 2 I OC2I
FFE8, E9 Timer output compare 1 I OC1I
FFEA, EB Timer input capture 3 I IC3I
FFEC, ED Timer input capture 2 I IC2I
FFEE, EF Timer input capture 1 I IC1I
FFF0, F1 Real-time interrupt I RTII
FFF2, F3 IRQ
FFF4, F5 XIRQ
FFF6, F7 Software interrupt None None
FFF8, F9 Illegal opcode trap None None
FFFA, FB COP failure None NOCOP
FFFC, FD Clock monitor fail None CME
FFFE, FF RESET
• SCI receiver overrun
• SCI transmit data register empty
• SCI transmit complete
• SCI idle line detect
(external pin) I None
pin X None
CCR
Mask Bit
I
None None
Local
Mask
RIE
RIE
TIE
TCIE
ILIE
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Resets and Interrupts
5.5.1 Interrupt Recognition and Register Stacking
An interrupt can be recognized at any time after it is enabled by its local mask, if
any, and by the global mask bit in the CCR. Once an interrupt source is recognized,
the CPU responds at the completion of the instruction being executed. Interrupt
latency varies according to the number of cycles required to complete the current
instruction. When the CPU begins to service an interrupt, the contents of the CPU
registers are pushed onto the stack in the order shown in Table 5-5. After the CCR
value is stacked, the I bit and the X bit, if XIRQ is pending, are set to inhibit further
interrupts. The interrupt vector for the highest priority pending source is fetched
and execution continues at the address specified by the vector. At the end of the
interrupt service routine, the return-from-interrupt instruction is executed and the
saved registers are pulled from the stack in reverse order so that normal program
execution can resume. Refer to Section 4. Central Processor Unit (CPU).
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Table 5-5. Stacking Order on Entry to Interrupts
Memory Location CPU Registers
SP–1 PCH
SP–2 IYL
SP–3 IYH
SP–4 IXL
SP–5 IXH
SP–6 ACCA
SP–7 ACCB
SP–8 CCR
5.5.2 Non-Maskable Interrupt Request (XIRQ
Non-maskable interrupts are useful because they can always interrupt CPU
operations. The most common use for such an interrupt is for serious system
problems, such as program runaway or power failure. The XIRQ
updated version of the NMI
Upon reset, both the X bit and I bit of the CCR are set to inhibit all maskable
interrupts and XIRQ
bit by a TAP instruction, enabling XIRQ
the X bit. Thus, an XIRQ
operation of the I-bit-related interrupt structure has no effect on the X bit, the
internal XIRQ
interrupt has a higher priority than any source that is maskable by the I bit. All
I-bit-related interrupts operate normally with their own priority relationship.
pin remains unmasked. In the interrupt priority logic, the XIRQ
. After minimum system initialization, software can clear the X
SP PCL
)
input is an
(non-maskable interrupt) input of earlier MCUs.
interrupts. Thereafter, software cannot set
interrupt is a non-maskable interrupt. Because the
When an I-bit-related interrupt occurs, the I bit is automatically set by hardware
after stacking the CCR byte. The X bit is not affected. When an X-bit-related
interrupt occurs, both the X and I bits are automatically set by hardware after
Data Sheet M68HC11E Family — Rev. 5
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