Page 1
8 Mbit (512K x16) 3.0V Asynchronous SRAM
FEATURES SUMMARY
■ SUPPLY VOLTAGE : 2.7 to 3.6V
■ 512K x 16 bits SRAM with OUTPUT ENABLE
■ EQUAL CYCLE and ACCESS TIMES: 55, 70ns
■ LOW STANDBY CURRENT
■ LOW V
■ TRI-STATE COMMON I/O
■ AUTOMATIC POWER DOWN
DATA RETENTION: 1.5V
CC
M68AW512D
Figure 1. Packages
BGA
TFBGA48 (ZB)
8 x 10 mm
1/18November 2002
Page 2
M68AW512D
TABLE OF CONTENTS
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 3. TFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4. Block Diagr am . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
MAXIMUM RATING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DC and AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 6. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. DC Character i stics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. Address Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . 9
Figure 9. Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms . . . . . . . . . . . . . . . . . . 9
Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 10. Write En a ble Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 11. Chip Enable Controlled, Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 12. UB/LB Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figu r e 1 3 . E1 Con trolled, Lo w VCC Data R e t e n tion A C Wav e fo r ms . . . . . . . . . . . . . . . . . . . . . . . 14
Figu r e 1 4 . E2 Cont r o l led, Lo w VCC Da ta R e tent io n AC Wav e fo r ms . . . . . . . . . . . . . . . . . . . . . . . 14
Table 9. Low VCC Data Retention Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
TFBGA48 8x10mm - 6x8 ball array, 0.75 mm pitch, Bottom View Package Outline. . . . . . . . . . . . 15
TFBGA48 8x10mm - 6x8 ball array, 0.75 mm pitch, Package Mechanic al Data . . . . . . . . . . . . . . . 15
PART NUMBERING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 11. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 12. Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2/18
Page 3
SUMMARY DESCRIPTION
The M68AW512D is an 8 Mbit (8,388,608 bit)
CMOS SRAM, organized as 524,288 words by 16
bits. The device features fully static operation requiring no external clocks or timing strobes, with
equal address access and cycle times. It requires
a single 2.7 to 3.6V supply. This device has a Chip
it is active (E2 high) the device has an auto matic
power-down feature, reducing the power consumption by over 99%.
The M68AW512D is available in TFBGA48 (0.75
mm ball pitch) package.
Select pin (E2) for easy memory expansion; when
Figure 2. Logic Diagram Table 1. Signal Names
A0-A18 Address Inputs
DQ0-DQ15 Data Input/Output
V
CC
E1
Chip Enable
M68AW512D
A0-A18
W
E1
E2
UB
LB
19
16
DQ0-DQ15
M68AW512D
G
V
SS
AI04800b
E2 Chip Select
G
W
UB
LB
V
CC
V
SS
NC Not Connected
DU Don’t Use as Internally Connected
Output Enable
Write Enable
Upper Byte Enable Input
Lower Byte Enable Input
Supply Voltage
Ground
3/18
Page 4
M68AW512D
Figure 3. TFBGA Connections (Top view through package)
654321
A
B
C
D
E
F
G
H
DQ8
DQ9
V
SS
V
CC
DQ14
DQ15
UB
DQ10
DQ11
DQ12
DQ13
NC
A0GLB
A17
V
A14
A9
SS
A1
A4 E1
A6A5
A7
A16
A15
A13
A10
A2 E2
DQ3
DQ4
DQ5
DQ0A3
DQ2DQ1
V
CC
V
SS
DQ6
DQ7WA12
DUA11A8A18
4/18
AI03960
Page 5
Figure 4. Block Diagram
A18
A8
ROW
DECODER
M68AW512D
MEMORY
ARRAY
DQ15
UB
E1
E2
UB
LB
Ex
W
G
DQ0
LBLB
MAXIMUM RATI N G
Stressing the device above the rating l isted in t he
Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress
ratings only and operation of the device at t hese or
any other conditions ab ove those i ndicated in t he
Operating sections of this specificat ion is not im-
(8)
(8)
(8)
UB
(8)
LB
I/O CIRCUITS
COLUMN
DECODER
A0 A7
AI05452
plied. Exposure to Absolute Maximum Rating conditions for periods greater than 1 sec may affect
device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality
documents.
Table 2. Absolute Maximum Ratings
Symbol Parameter Value Unit
T
A
T
STG
V
CC
(1)
V
IO
P
D
Note: 1. Up to a maximu m operatin g VCC of 3.6V only.
Ambient Operating Temperature –55 to 125 °C
Storage Temperature –65 to 150 °C
Supply Voltage –0.5 to 4.6 V
Input or Output Voltage
–0.5 to V
CC
+0.5
Power Dissipation 1 W
V
5/18
Page 6
M68AW512D
DC AND AC PARAMETERS
This section summarizes the operat ing and measurement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the M easure-
Table 3. Operating and AC Measurement Conditions
Parameter M68AW512D
Supply Voltage
V
CC
Ambient Operating Temperature
Load Capacitance (C
Output Circuit Protection Resis tance (R
Load Resistance (R
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Output Transition Timing Ref. Voltages
)
L
)
1
)
2
ment Conditions listed i n the relevant tables. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
2.7 to 3.6V
Range 1 0 to 70°C
Range 6 –40 to 85°C
30pF
3.0k
Ω
3.1k
Ω
1ns/V
≤
0 to V
CC
V
/2
CC
V
= 0.3VCC; VRH = 0.7V
RL
CC
Figure 5. AC Measurement I/O Waveform Figure 6. AC Measurement Load Circuit
V
CC
I/O Timing Reference Voltage
V
CC
0V
Output Transition Timing Reference Voltage
V
CC
0V
VCC/2
0.7V
0.3V
AI04831
DEVICE
UNDER
TEST
R
CC
CC
CL includes probe and 1 TTLcapacitance
R
1
OUT
C
L
2
AI05832
6/18
Page 7
M68AW512D
Table 4. Capacitance
Symbol
C
C
OUT
Note: 1. Sampled only, not 100% tested.
2. At T
Input Capacitance on all pins (except DQ)
IN
Output Capacitance
= 25°C, f = 1 MHz, VCC = 3.0V.
A
Parameter
(1,2)
Table 5. DC Characteristics
Symbol Parameter Test Condition Min Typ Max Unit
V
(1,2)
I
CC1
I
CC2
I
I
V
V
V
V
Note: 1. Average AC current, cycling at t
Operating Supply Current
(3)
Operating Supply Current
Standby Supply Current CMOS
SB
I
Input Leakage Current
LI
Output Leakage Current
LO
Input High Voltage 2.2
IH
Input Low Voltage –0.3 0.6 V
IL
Output High Voltage
OH
Output Low Voltage
OL
= VILAND E2 = V
2. E1
3. E1
≤ 0.2V AND E2 ≥ V
4. Outpu t disabled.
LB OR/AND UB = VIL, VIN = VIL OR VIH.
IH,
–0.2V, LB OR/AND UB ≤ 0.2V, V
CC
AVAV
minimum.
= 3.6V, f = 1/t
CC
I
V
V
E1
≥
= 0mA
OUT
= 3.6V, f = 1MHz,
CC
I
OUT
V
= 3.6V, f = 0,
CC
–0.2V or E2 ≤
CC
LB
=UB ≥
0V≤ V
V
0V
≤
OUT
I
= –1.0mA
OH
I
= 2.1mA
OL
≤ 0.2V OR VIN≥ V
IN
AVAV
= 0mA
V
CC
V
≤
IN
V
≤
,
0.2V or
–0.2V
CC
(4)
CC
Test
Condition
V
= 0V
IN
V
= 0V
OUT
Min Max Unit
8pF
10 pF
70ns 35 mA
55ns 40 mA
4mA
120µA
–1 1 µA
–1 1 µA
V
+ 0.3
CC
2.4 V
0.4 V
–0.2V .
CC
V
7/18
Page 8
M68AW512D
OPERATION
The M68AW512D has a Chip Enable power down
feature which invokes an automatic standby mode
whenever Chip Enable is de-asserted (E1
or Chip Select is asserted (E2 = Low), or UB
are de-asserted (UB/LB = High). An Output Enable (G
) signal provides a high speed tri-state con-
Table 6. Operating Modes
Operation E1 E2 W G LB UB DQ0-DQ7 DQ8-DQ15 Power
Deselected
Deselected X
Deselected XXXX
Lower Byte Read
Lower Byte Write
Output Disabled
Upper Byte Read
Upper Byte Write
Word Read
Word Write
Note: 1. X = VIH or VIL.
V
V
V
V
V
V
V
V
XXXXX Hi-Z Hi-Z
IH
V
IL
V
IL
IH
V
IL
IH
V
IL
IH
V
IL
IH
V
IL
IH
V
IL
IH
V
IL
IH
= High)
/LB
XXXX Hi-Z Hi-Z
V
V
IH
IL
V
V
V
V
V
V
X
IL
V
IH
IH
V
IH
IL
X
IL
V
IH
IL
X
IL
trol, allowing fast read/write cycles to be achieved
with the common I/O data bus. Operational modes
are determined by device control inputs W
and UB as summarized in the Operating Modes table (see Table 6).
Standby (I
Standby (I
V
V
IH
IH
V
V
IL
IH
V
V
IL
IH
Hi-Z Hi-Z
Data Output Hi-Z
Data Input Hi-Z
X X Hi-Z Hi-Z
V
V
IH
IL
V
V
IH
IL
V
V
IL
IL
V
V
IL
IL
Hi-Z Data Output
Hi-Z Data Input
Data Output Data Output
Data Input Data Input
Standby (I
Active (I
Active (I
Active (I
Active (I
Active (I
Active (I
Active (I
, E1, LB
)
SB
)
SB
)
SB
)
CC
)
CC
)
CC
)
CC
)
CC
)
CC
)
CC
Read Mode
The M68AW512D, when Chip Select (E2) is High,
is in the read mode whenever Write Enable (W
High with Output Enable (G
able (E1
) is asserted. This provides access to data
) Low, and Chip En-
) is
from eight or sixte en, depending on the status of
the signal UB
and LB, of the 8,388,608 locations in
the static memory array, specified by the 19 address inputs. Valid data will be available at the
eight or sixteen output pins within t
last stable address, providing G
Low and E2 is High. If Chip Enable or Output Enable access times are not met, data access will be
measured from the limiting parameter (t
t
GLQV
may be indeterminate at t
but data lines will always be valid at t
Figure 7. Address Controlled, Read Mode AC Waveforms
tAVAV
A0-A18
tAVQV tAXQX
DQ0-DQ7 and/or DQ8-DQ15
Note: E1 = Low, E2 = High, G = Low, W = High, UB = Low and/or LB = Low.
VALID
or t
BLQV
DATA VALID
after the
AVQV
is Low and E1 is
) rather than the address. Data out
ELQV
ELQX
, t
GLQX
AVQV
AI05839
and t
.
BLQX
,
,
8/18
Page 9
Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms
tAVAV
M68AW512D
A0-A18
E1
E2
G
DQ0-DQ15
UB, LB
Note: Write Enable (W) = High
VALID
tAVQV tAXQX
tELQV
tELQX
tGLQV
tGLQX
VALID
tBLQV
tBLQX
tGHQZ
tBHQZ
AI05981
tEHQZ
Figure 9. Chi p E nable or UB/LB Controlled, Standby Mode AC Waveforms
E1, UB, LB
E2
I
I
CC
SB
tPU
50%
tPD
AI05497
9/18
Page 10
M68AW512D
Table 7. Read and Standby Mode AC Characteristics
Symbol Parameter
M68AW512D
Unit
55 70
t
AVAV
t
AVQV
t
AXQX
t
BHQZ
t
BLQV
t
BLQX
t
EHQZ
t
ELQV
t
ELQX
t
GHQZ
t
GLQV
t
GLQX
(4)
t
PD
(4)
t
PU
Note: 1. Test conditions as s u m e t ransit i on timing reference level = 0.3VCC or 0.7VCC.
2. At any gi ven temperature and voltage condition, t
3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
4. Testested initially and af ter any design or proces s c hanges that ma y affect these parameters.
Read Cycle Time Min 55 70 ns
Address Valid to Output Valid Max 55 70 ns
(1)
Data hold from address change Min 5 5 ns
(2,3,4)
Upper/Lower Byte Enable High to Output Hi-Z Max 20 25 ns
Upper/Lower Byte Enable Low to Output Valid Max 55 70 ns
(1)
Upper/Lower Byte Enable Low to Output Transition Min 5 5 ns
(2,3,4)
Chip Enable High to Output Hi-Z Max 20 25 ns
Chip Enable Low to Output Valid Max 55 70 ns
(1)
Chip Enable Low to Output Transition Min 5 5 ns
(2,3,4)
Output Enable High to Output Hi-Z Max 20 25 ns
Output Enable Low to Output Valid Max 25 35 ns
(1)
Output Enable Low to Output Transition Min 5 5 ns
Chip Enable or UB/LB High to Power Down Max 0 0 ns
Chip Enable or UB/LB Low to Power Up Min 55 70 ns
any given de vice.
voltage lev el s.
is less than t
GHQZ
GLQX
, t
BHQZ
is less than t
BLQX
and t
EHQZ
is less than t
ELQX
for
10/18
Page 11
Write Mode
The M68AW512D, when Chip Select (E2) is High,
is in the Write Mode whenev er the W
Low. Either the Chip Enable Input (E1
Enable input (W
) must be de-asserted during Ad-
and E1 are
) or the Write
dress transitions for subsequent write cycles.
When E1
cycle begins on the W
or W is Low, and UB or LB is Low, write
or E1 falling edge. When E1
and W are Low, and UB = LB = High, write cycle
begins on the first falling edge of UB
or LB. Therefore, address setup time is referenced to Write Enable, Chip Enables and UB
t
respectively, and is det ermined by the latter
AVBL
/LB as t
AVWL
, t
AVEL
and
occurring falling edge.
The Write cycle can be terminated by the earlier
rising edge of E1
If the Output is enabled (E1
Low, LB
puts to high impedance within t
edge. Care must be taken to avoid bus contention
in this type of operation. Data input must be valid
for t
DVWH
or for t
before the rising edge of UB/LB, whichever
VBH
occurs first, and remain valid for t
t
BHDX
Figure 10. Write Enable Controlled, Write AC Waveforms
tAVAV
M68AW512D
, W, UB and LB.
= Low, E2 = High, G =
or UB = Low), then W will return the out-
of its fall ing
WLQZ
before the rising edge of Write Enable,
before the rising edge of E1 or for t
DVEH
, t
respectively.
WHDX
EHDX
D-
and
A0-A18
tAVEL
E1
E2
tAVWL
W
tWLQZ
DQ0-DQ15
UB, LB
Note: 1. During this period DQ0- DQ15 are in output state and input sig nal s should not be applied.
VALID
tAVWH
tELWH
tWLWH
tWHDX
DATA INPUT
tDVWH
tBLBH
tWHAX
tWHQX
AI05982
11/18
Page 12
M68AW512D
Figure 11. Chip Enable Controlled, Write AC Waveforms
tAVAV
A0-A18
E1
E2
W
DQ0-DQ15
UB, LB
Figure 12. UB
VALID
tAVEH
tAVEL
tAVWL
tWLEH
tBLBH
/LB Controlle d, Write AC Waveforms
tELEH
tEHAX
tEHDX
DATA INPUT
tDVEH
AI05983
tAVAV
A0-A18
E1
E2
tAVWL
W
tWLQZ tBHDX
(1)
DQ0-DQ15
UB, LB
Note: 1. During this period DQ0- DQ15 are in output state and input sig nal s should not be applied.
DATA
tAVBL
VALID
tAVBH
tWLBH
DATA INPUT
tDVBH
tBLBH
tBHAX
AI05984
12/18
Page 13
Table 8. Write Mode AC Characteristics
Symbol Parameter
M68AW512D
M68AW512D
Unit
55 7 0
t
AVAV
t
AVBH
t
AVBL
t
AVEH
t
AVEL
t
AVWH
t
AVWL
t
BHAX
t
BHDX
t
BLBH
t
BLEH
t
BLWH
t
DVBH
t
DVEH
t
DVWH
t
EHAX
t
EHDX
t
ELBH
t
ELEH
t
ELWH
t
WHAX
t
WHDX
t
WHQX
t
WLBH
t
WLEH
(1,2,3)
t
WLQZ
t
WLWH
Note: 1. At any given tem perature and voltage conditi on, t
2. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
3. Testested initially and af ter any design or proces s c hanges that ma y affect these parameters.
Write Cycle Time Min 55 7 0 ns
Address Valid to LB, UB High Min 45 60 ns
Addess Valid to LB, UB Low Min 0 0 ns
Address Valid to Chip Enable High Min 45 60 ns
Address valid to Chip Enable Low Min 0 0 ns
Address Valid to Write Enable High Min 45 60 ns
Address Valid to Write Enable Low Min 0 0 ns
LB, UB High to Address Transition Min 0 0 ns
LB, UB High to Input Transition Min 0 0 ns
LB, UB Low to LB, UB High Min 45 60 ns
LB, UB Low to Chip Enable High Min 45 60 ns
LB, UB Low to Write Enable High Min 45 60 ns
Input Valid to LB, UB High Min 25 30 ns
Input Valid to Chip Enable High Min 25 30 ns
Input Valid to Write Enable High Min 25 30 ns
Chip Enable High to Address Transition Min 0 0 ns
Chip enable High to Input Transition Min 0 0 ns
Chip Enable Low to LB, UB High Min 45 60 ns
Chip Enable Low to Chip Enable High Min 45 60 ns
Chip Enable Low to Write Enable High Min 45 60 ns
Write Enable High to Address Transition Min 0 0 ns
Write Enable High to Input Transition Min 0 0 ns
(1)
Write Enable High to Output Transition Min 5 5 ns
Write Enable Low to LB, UB High Min 45 60 ns
Write Enable Low to Chip Enable High Min 45 60 ns
Write Enable Low to Output Hi-Z Max 20 20 ns
Write Enable Low to Write Enable High Min 40 50 ns
voltage lev el s.
is less than t
WLQZ
for any given device.
WHQX
13/18
Page 14
M68AW512D
Figure 13. E1 Controlled, Low VCC Data Retention AC Waveforms
3.6V
VCC 2.7V
VDR> 1.5V
E1 or UB/LB
Figure 14. E2 Controlled, Low V
3.6V
VCC 2.7V
VDR> 1.5V
E2
DATA RETENTION MODE
tCDR
E1 ≥ VDR– 0.2V or UB = LB ≥ VDR – 0.2V
Data Retention AC Waveforms
CC
DATA RETENTION MODE
tCDR
E2< 0.2V
tR
AI05985
tR
AI05986B
Table 9. Low V
Data Retention Characteristics
CC
Symbol Parameter Test Condition Min Typ Max Unit
V
CC
= LB ≥
–0.2V or
V
–0.2V,
CC
510µA
I
CCDR
(1)
Supply Current (Data Retention)
= 1.5V, E1 ≥
V
CC
E2 ≤ 0.2V or UB
f = 0
Chip Deselected to Data
(1,2)
t
CDR
t
R
V
DR
Note: 1. All other Inputs at V
Retention Time
(2)
Operation Recovery Time
V
E1
≥
–0.2V or E2 ≤ 0.2V or
CC
V
= LB ≥
CC
≤ 0.2V.
IL
UB
(1)
Supply Voltage (Data Retention)
≥ V
–0.2V or V
IH
2. Tested initiall y and after an y design or process that may affect t hese parame ters.
3. No input may exceed V
CC
CC
+0.2V.
–0.2V, f = 0
t
AVAV
0ns
t
AVAV
1.5 V
is Read cycle time.
ns
14/18
Page 15
M68AW512D
PACKAGE MECHANICAL
Figure 15. TFBGA48 8x10mm - 6x8 ball array, 0.75 mm pitch, Bottom View Packag e Outl ine
D
BALL "A1"
Note: Drawing is not to scale.
E1E
FD
FE
A
D1
SD
SE
eb
A2
A1
ddd
BGA-Z28
Table 10. TFBGA48 8x10mm - 6x8 ball array, 0.75 mm pitch, Package Mech anical Data
Symbol
A 1.200 0.0472
A1 0.260 0.0102
A2 0.900 0.0354
b 0.350 0.450 0.0138 0.0177
D 8 .000 7.900 8.100 0.3150 0.3110 0.3189
D1 3.750 – – 0.1476 – –
ddd 0.100 0.0039
E 10.000 9.900 10.100 0.3937 0.3898 0.3976
E1 5.250 – – 0.2067 – –
e 0.750 – – 0.0295 – –
FD 2.125 – – 0.08 37 – –
FE 2.375 – – 0.0935 – –
SD 0.375 – – 0.0148 – –
SE 0.375 – – 0.01 48 – –
Typ Min Max Typ Min Max
millimeters inches
15/18
Page 16
M68AW512D
PART NUMBERING
Table 11. Ordering Information Scheme
Example: M68AW512 D L 55 ZB 6 T
Device Type
M68
Mode
A = Asynchronous
Operating Voltage
W = 2.7 to 3.6V
Array Organization
512 = 8 Mbit (512K x16)
Option 1
D = 2 Chip Enable; Write and Standby from UB
Option 2
L = L-Die
N = N-Die
and LB
Speed Class
55 = 55ns
70 = 70ns
Package
ZB = TFBGA48: 0.75 mm pitch
Operative Temperature
1 = 0 to 70 °C
6 = –40 to 85 °C
Shipping
T = Tape & Reel Packing
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
16/18
Page 17
REVISION HIST ORY
Table 12. Document Revision History
Date Version Revision Details
July 2001 -01 First Issue
06-Feb-2002 -02 70ns Speed Class added, Commercial Temperature Range added
M68AW512D
14-Mar-2002 -03
17-Jun-2002 -04
09-Oct-2002 4.1
25-Nov-2002 4.2 Figure 14, E2 Controlled, Low VCC Data Retention AC Waveforms, corrected.
Document status moved to Datasheet
Tables 6, 7 and 9 clarified
Figures 8, 9, 10, 11 and 12 clarified
Block Diagram clarified (Figure 4)
clarified (Table 5)
I
SB
I
clarified (Table 9)
CCDR
Revision numbering modified: a minor revision will be indicated by incrementing the
digit after the dot, and a major revision, by incrementing the digit before the dot
(revision version 04 equals 4.0).
Part number modified.
17/18
Page 18
M68AW512D
Information furnished is believed to be accurate and reliabl e. However, STMicroelectronics assumes no responsibili t y for the cons equences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or o therwise under any patent or patent rights of S T M i croelectronics. Specificat i ons menti oned in thi s publicat i on are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authoriz ed for use as cri t i cal components in life support dev i ces or systems without express wri t ten approval of STMic roelectronics.
The ST logo i s registered trademark of STMicroelectronics
All other na m es are the property of the i r respective owners.
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18/18
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