8 Mbit (512K x16) 1.8V Asynchronous SRAM
FEATURES SUMMARY
■ SUPPLY VOLTAGE: 1.65 to 1.95V
■ 512K x 16 bits SRAM with OUTPUT ENABLE
■ EQUAL CYCLE and ACCESS TIMES: 70ns
■ SINGLE BYTE READ/W R ITE
■ LOW STANDBY CURRENT
■ LOW V
■ TRI-STATE COMMON I/O
■ AUTOMATIC POWER DOWN
■ DUAL CHIP ENABLE for EASY DEPTH
EXPANSION
DATA RETENTION: 1.0V
CC
M68AR512D
Figure 1. Packages
BGA
TFBGA48 (ZB)
6 x 7mm
BGA
TFBGA48 (ZB)
8 x 10mm
1/19October 2002
M68AR512D
TABLE OF CONTENTS
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 3. TFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 4. Block Diagr am . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
MAXIMUM RATING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DC and AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 6. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. DC Character i stics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. Address Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . 9
Figure 9. Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms . . . . . . . . . . . . . . . . . . 9
Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 10. Write En a ble Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 11. Chip Enable Controlled, Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 12. UB/LB Controlled, Writ e AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 13. E1 Controlled, Low V
Figure 14. E2 Controlled, Low V
Data R e t e n tion A C Wavefo r ms . . . . . . . . . . . . . . . . . . . . . . . . 1 4
CC
Data R e t e n tion A C Wavefo r ms . . . . . . . . . . . . . . . . . . . . . . . . 1 4
CC
Table 9. Low VCC Data Retention Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PACKAGE MECHANICAL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
TFBGA48 6x7mm - 6x8 ball array, 0.75 mm pitch, Bottom View Package Outline. . . . . . . . . . . . . 15
TFBGA48 6x7mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data. . . . . . . . . . . . . . . . 15
TFBGA48 8x10mm - 6x8 ball array, 0.75 mm pitch, Bottom View Package Outline. . . . . . . . . . . . 16
TFBGA48 8x10mm - 6x8 ball array, 0.75 mm pitch, Package Mechanic al Data . . . . . . . . . . . . . . . 16
PART NUMBERING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 12. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 13. Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2/19
SUMMARY DESCRIPTION
The M68AR512D is an 8 Mbit (8,388,608 bit)
CMOS SRAM, organized as 524,288 words by 16
bits. The device features fully static operation requiring no external clocks or timing strobes, with
equal address access and cycle times. It requires
a single 1.8V (
±150mV) supply. This device has a
Chip Select pin (E2) for easy memory ex pansion;
matic power-down feature, reducing the power
consumption by over 99%.
The M68AR512D is available in TFBGA48
(6x7mm and 8x10mm, 6x8 active ball array, 0.75
mm ball pitch) package. See the Ordering Information Scheme (Table 12) for details.
when it is active (E2 high) the device has an auto-
Figure 2. Logic Diagram Table 1. Signal Names
A0-A18 Address Inputs
M68AR512D
A0-A18
W
E1
E2
UB
LB
V
CC
19
M68AR512D
G
V
SS
16
DQ0-DQ15
AI03953C
DQ0-DQ15 Data Input/Output
, E2 Chip Enable
E1
G
W
UB
LB
V
CC
V
SS
NC Not Connected
DU Don’t Use as Internally Connected
Output Enable
Write Enable
Upper Byte Enable Input
Lower Byte Enable Input
Supply Voltage
Ground
3/19
M68AR512D
Figure 3. TFBGA Connections (Top view through package)
654321
A
B
C
D
E
F
G
H
DQ8
DQ9
V
SS
V
CC
DQ14
DQ15
UB
DQ10
DQ11
DQ12
DQ13
NC
A0GLB
A17
V
A9
SS
A1
A4 E1
A6A5
A7
A16
A15
A13
A10
A2 E2
DQ3
DQ4
DQ5A14
DQ0A3
DQ2DQ1
V
CC
V
SS
DQ6
DQ7WA12
DUA11A8A18
4/19
AI03960
Figure 4. Block Diagram
A18
A8
ROW
DECODER
M68AR512D
MEMORY
ARRAY
DQ15
UB
E1
E2
UB
LB
Ex
W
G
DQ0
LBLB
MAXIMUM RATIN G
Stressing the device above the rating l isted in t he
Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress
ratings only and operation of the device at t hese or
any other conditions ab ove those i ndicated in t he
Operating sections of this specificat ion is not im-
(8)
(8)
(8)
UB
(8)
LB
I/O CIRCUITS
COLUMN
DECODER
A0 A7
AI05452
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents.
Table 2. Absolute Maximum Ratings
Symbol Parameter Value Unit
(1)
I
O
T
A
T
STG
V
CC
(2)
V
IO
P
D
Note: 1. One output at a time, not to exceed 1 second durati on.
2. Up to a maximum operating V
Output Current 20 mA
Ambient Operating Temperature –55 to 125 °C
Storage Temperature –65 to 150 °C
Supply Voltage –0.5 to 2.5 V
Input or Output Voltage
–0.5 to V
CC
+0.5
Power Dissipation 1 W
of 1.95 V only.
CC
V
5/19
M68AR512D
DC AND AC PARAMETERS
This section summarizes the operat ing and measurement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the M easure-
Table 3. Operating and AC Measurement Conditions
Parameter M68AR5 12D
Supply Voltage
V
CC
Ambient Operating Temperature
ment Conditions listed i n the relevant tables. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
1.65 to 1.95V
Range 1 0 to 70°C
Range 6 –40 to 85°C
Load Capacitance (C
Output Circuit Protection Resis tance (R
Load Resistance (R
)
L
)
1
)
2
30pF
15.3kΩ
11.3kΩ
Input Rise and Fall Times 1ns/V
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Output Transition Timing Ref. Voltages
V
RL
0 to V
CC
V
/2
CC
= 0.3VCC; VRH = 0.7V
Figure 5. AC Measurement I/O Waveform Figure 6. AC Measurement Load Circuit
V
CC
I/O Timing Reference Voltage
V
CC
0V
Output Timing Reference Voltage
V
CC
0V
VCC/2
0.7V
0.3V
AI04831
DEVICE
UNDER
TEST
R
CC
CC
CL includes probe and 1TTL capacitance
R
1
OUT
C
L
2
CC
6/19
AI03853
M68AR512D
Table 4. Capacitance
Symbol
C
C
OUT
Note: 1. Sampled only, not 100% tested.
2. At T
Input Capacitance on all pins (except DQ)
IN
Output Capacitance
= 25°C, f = 1 MHz, VCC = 1.8V.
A
Parameter
(1,2)
Table 5. DC Characteristics
Symbol Parameter Test Condition Min Typ Max Unit
V
(1,2)
I
CC1
I
CC2
I
LO
I
SB
V
V
V
V
Note: 1. Average AC current, cycling at t
Operating Supply Current
(3)
Operating Supply Current
I
Input Leakage Current
LI
(4)
Output Leakage Current
(3)
Standby Supply Current CMOS
Input High Voltage 1.4
IH
Input Low Voltage –0.5 0.4 V
IL
Output High Voltage
OH
Output Low Voltage
OL
= VIL, E2 = VIH, UB or/and LB = VIL, VIN = VIH or VIL.
2. E1
≤ 0.2V or E2 ≥ VCC –0.2V, LB or/and UB ≤ 0.2V, VIN≤ 0.2V or V
3. E1
4. Out put disabled.
AVAV
minimum.
= 1.95V, f = 1/t
CC
I
= 0mA
OUT
V
= 1.95V, f = 1MHz,
CC
I
= 0mA
OUT
0V ≤ V
IN
0V
≤ V
OUT
= 1.95V,
V
CC
E1 ≥ VCC–0.2V or
E2 ≤ 0.2V or
=LB ≥ V
UB
I
= –100µA
OH
I
= 100µA
OL
CC
≤ V
≤ V
–0.2V, f = 0
CC
IN
CC
AVAV
≥ V
,
CC
–0.2V.
Test
Condition
V
= 0V
IN
V
= 0V
OUT
Min Max Unit
6pF
8pF
12 mA
2mA
–1 1 µA
–1 1 µA
115µA
V
+ 0.4
CC
1.5 V
0.2 V
V
7/19
M68AR512D
OPERATION
The M68AR512D has a Chip Enable power down
feature which invokes an automatic standby mode
whenever Chip Enable is de-asserted (E1
or Chip Select is asserted (E2 = Low), or UB
are de-asserted (UB/LB = High). An Output Enable (G
) signal provides a high speed tri-state con-
Table 6. Operating Modes
Operation E1 E2 W G LB UB DQ0-DQ7 DQ8-DQ15 Power
Deselected/Power-down
V
Deselected/Power-down X
Deselected/Power-down XXXX
Lower Byte Read
Lower Byte Write
Output Disabled
Upper Byte Read
Upper Byte Write
Word Read
Word Write
Note: X = VIH or VIL.
V
V
V
V
V
V
V
XXXXX Hi-Z Hi-Z
IH
V
IL
V
IL
IH
V
IL
IH
V
IL
IH
V
IL
IH
V
IL
IH
V
IL
IH
V
IL
IH
= High)
/LB
XXXX Hi-Z Hi-Z
V
V
IH
IL
V
V
V
V
V
X
IL
V
X
IH
V
IH
IL
X
IL
V
IH
IL
X
IL
trol, allowing fast read/write cycles to be achieved
with the common I/O data bus. Operational modes
are determined by device control inputs W
and UB as summarized in the Operating Modes table (see Table 6).
Standby (I
Standby (I
V
IH
V
IL
V
IL
X
V
IH
V
IH
V
IL
V
IL
V
IH
V
IH
V
IH
Hi-Z Hi-Z
Data Output Hi-Z
Data Input Hi-Z
X Hi-Z Hi-Z
V
IL
V
IL
V
IL
V
IL
Hi-Z Data Output
Hi-Z Data Input
Data Output Data Output
Data Input Data Input
Standby (I
Active (I
Active (I
Active (ICC)
Active (I
Active (I
Active (I
Active (I
, E1, LB
)
SB
)
SB
)
SB
)
CC
)
CC
)
CC
)
CC
)
CC
)
CC
Read Mode
The M68AR512D, when Chi p S elect (E2) i s High,
is in the read mode whenever Write Enable (W
High with Output Enable (G
able (E1
) is asserted. This provides access to data
) Low, and Chip En-
) is
from eight or sixte en, depending on the status of
the signal UB
and LB, of the 8,388,608 locations in
the static memory array, specified by the 19 address inputs. Valid data will be available at the
eight or sixteen output pins within t
last stable address, providing G
Low. If Chip Enable or Output Enable access
times are n ot met, data access will be m easured
from the limiting parameter (t
rather than the address. Data out may be inde terminate at t
will always be v alid at t
Figure 7. Address Controlled, Read Mode AC Waveforms
tAVAV
A0-A18
tAVQV tAXQX
DQ0-DQ7 and/or DQ8-DQ15
Note: E1 = Low, E 2 = High, G = Low, W = High, UB = Low and/or LB = Low.
VALID
, t
ELQX
DATA VALID
GLQX
and t
AVQV
AVQV
is Low and E1 is
, t
ELQV
GLQV
, but data lines
BLQX
.
AI03961
after the
or t
BLQV
)
8/19
Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms
tAVAV
M68AR512D
A0-A18
E1
E2
G
DQ0-DQ15
UB, LB
Note: Write Enable (W) = High
VALID
tAVQV tAXQX
tELQV
tELQX
tGLQV
tGLQX
VALID
tBLQV
tBLQX
tGHQZ
tBHQZ
AI05994
tEHQZ
Figure 9. Chi p E nable or UB/LB Controlled, Standby Mode AC Waveforms
E1, UB, LB
E2
I
CC
I
SB
tPU
50%
tPD
AI05990
9/19
M68AR512D
Table 7. Read and Standby Mode AC Characteristics
Symbol Parameter
t
AVAV
t
AVQV
t
AXQX
t
BHQZ
t
BLQV
t
BLQX
t
EHQZ
t
ELQV
t
ELQX
t
GHQZ
t
GLQV
t
GLQX
(4)
t
PD
(4)
t
PU
Note: 1. Test con di tions assume transit i on timing reference level = 0. 3V
2. At any given temperature and voltage cond i tion, t
3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
4. T ested initiall y and after any design or proc ess changes t hat may affect these parameters.
Read Cycle Time Min 70 ns
Address Valid to Output Valid Max 70 ns
(1)
Data hold from address change Min 5 ns
(2, 3)
Upper/Lower Byte Enable High to Output Hi-Z Max 25 ns
Upper/Lower Byte Enable Low to Output Valid Max 70 ns
(1)
Upper/Lower Byte Enable Low to Output Transition Min 5 ns
(2, 3)
Chip Enable High to Output Hi-Z Max 25 ns
Chip Enable Low to Output Valid Max 70 ns
(1)
Chip Enable Low to Output Transition Min 5 ns
(2, 3)
Output Enable High to Output Hi-Z Max 25 ns
Output Enable Low to Output Valid Max 35 ns
(1)
Output Enable Low to Output Transition Min 5 ns
Chip Enable High to Power Down Max 0 ns
Chip Enable Low to Power Up Min 70 ns
any given de vice.
voltage lev el s.
is less than t
GHQZ
CCQ
to 0.7V
GLQX
, t
CCQ
BHQZ
.
is less than t
M68AR512D
and t
BLQX
is less than t
EHQZ
70
Unit
ELQX
for
10/19
Write Mode
The M68AR512D, when Chi p S elect (E2) i s High,
is in the Write Mode whenev er the W
Low. Either the Chip Enable Input (E1
Enable input (W
) must be de-asserted during Ad-
and E1 are
) or the Write
dress transitions for subsequent write cycles.
When E1
cycle begins on the W
or W is Low, and UB or LB is Low, write
or E1 falling edge. When E1
and W are Low, and UB = LB = H igh, write cycle
begins on the first falling edge of UB
or LB. Therefore, address setup time is referenced to Write Enable, Chip Enables and UB
t
respectively, and is det ermined by the latter
AVBL
/LB as t
AVWL
, t
AVEL
and
occurring falling edge.
The Write cycle can be terminated by the earlier
rising edge of E1
If the Output is enabled (E1
Low, LB
puts to high impedance within t
edge. Care must be taken to avoid bus contention
in this type of operation. Data input must be valid
for t
DVWH
or for t
before the rising edge of UB/LB, whichever
VBH
occurs first, and remain valid for t
t
BHDX
Figure 10. Write Enable Controlled, Write AC Waveforms
tAVAV
M68AR512D
, W, UB and LB.
= Low, E2 = High, G =
or UB = Low), then W will return the out-
of its fall ing
WLQZ
before the rising edge of Write Enable,
before the rising edge of E1 or for t
DVEH
, t
respectively.
WHDX
EHDX
D-
and
A0-A18
E1
E2
W
DQ0-DQ15
UB, LB
tAVEL
tAVWL
tWLQZ
VALID
tAVWH
tELWH
tWLWH
tBLBH
tWHAX
tWHQX
tWHDX
DATA INPUT
tDVWH
AI05995
11/19
M68AR512D
Figure 11. Chip Enable Controlled, Write AC Waveforms
tAVAV
A0-A18
E1
E2
W
DQ0-DQ15
UB, LB
Figure 12. UB
VALID
tAVEH
tAVEL
tAVWL
tWLEH
tBLBH
/LB Controlled, Write AC Waveforms
tELEH
tEHAX
tEHDX
DATA INPUT
tDVEH
AI05996
tAVAV
A0-A18
E1
E2
tAVWL
W
tWLQZ tBHDX
(1)
DQ0-DQ15
UB, LB
Note: 1. Duri ng this period DQ0-DQ15 ar e i n output state and input signal s should not be applied.
DATA
tAVBL
VALID
tAVBH
tWLBH
DATA INPUT
tDVBH
tBLBH
tBHAX
AI05997
12/19
M68AR512D
Table 8. Write Mode AC Characteristics
Symbol Parameter
t
AVAV
t
AVBH
t
AVBL
t
AVEH
t
AVEL
t
AVWH
t
AVWL
t
BHAX
t
BHDX
t
BLBH
t
BLEH
t
BLWH
t
DVBH
t
DVEH
t
DVWH
t
EHAX
t
EHDX
t
ELBH
t
ELEH
t
ELWH
t
WHAX
t
WHDX
t
WHQX
t
WLBH
t
WLEH
t
WLQZ
t
WLWH
Note: 1. At any gi ven temperature and vol t age condition, t
2. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage lev el s.
Write Cycle Time Min 70 ns
Address Valid to LB, UB High Min 60 ns
Address Valid to LB, UB Low Min 0 ns
Address Valid to Chip Enable High Min 60 ns
Address valid to Chip Enable Low Min 0 ns
Address Valid to Write Enable High Min 60 ns
Address Valid to Write Enable Low Min 0 ns
LB, UB High to Address Transition Min 0 ns
LB, UB High to Input Transition Min 0 ns
LB, UB Low to LB, UB High Min 60 n s
LB, UB Low to Chip Enable High Min 60 ns
LB, UB Low to Write Enable High Min 60 ns
Input Valid to LB, UB High Min 30 n s
Input Valid to Chip Enable High Min 30 ns
Input Valid to Write Enable High Min 30 ns
Chip Enable High to Address Transition Min 0 ns
Chip enable High to Input Transition Min 0 ns
Chip Enable Low to LB, UB High Min 60 ns
Chip Enable Low to Chip Enable High Min 60 ns
Chip Enable Low to Write Enable High Min 60 ns
Write Enable High to Address Transition Min 0 ns
Write Enable High to Input Transition Min 0 ns
(1)
Write Enable High to Output Transition Min 5 ns
Write Enable Low to LB, UB High Min 60 ns
Write Enable Low to Chip Enable High Min 60 ns
(1, 2)
Write Enable Low to Output Hi-Z Max 20 ns
Write Enable Low to Write Enable High Min 60 ns
WHQZ
is less than t
for any given device.
WLQX
M68AR512D
70
Unit
13/19
M68AR512D
Figure 13. E1 Controlled, Low VCC Data Retention AC Waveforms
1.95V
VCC 1.8V
VDR> 1.0V
E1
Figure 14. E2 Controlled, Low V
1.95V
VCC 1.65V
VDR> 1.0V
E2
DATA RETENTION MODE
tCDR
E1 ≥ VDR– 0.2V
Data Retention AC Waveforms
CC
DATA RETENTION MODE
tCDR
E2 ≤ 0.2V
tR
AI05455
tR
AI05475
Table 9. Low V
Data Retention Characteristics
CC
Symbol Parameter Test Condition M in Typ Max Unit
V
= 1.0V, E1 ≥ VCC–0.2V or
(1)
I
CCDR
t
CDR
t
R
V
DR
Supply Current (Data Retention)
Chip deselected to Data
(2)
Retention Time
(2)
Operation Recovery Time
(1)
Supply Voltage (Data Retention)
CC
E2 ≤ 0.2V or
/LB ≥ VCC–0.2V, f = 0
UB
E1
≥ VCC–0.2V or
E2 ≤ 0.2V or
/LB ≥ VCC–0.2V,
UB
(3)
0.1 8 µA
0ns
t
AVAV
1.0 V
f=0
Note: 1. All other Inputs at VIH≥ VCC–0.2V or VIL≤ 0.2V.
2. T ested initiall y and after any design or proc ess changes t hat may affect these parameters.
3. No input may exceed V
CC
+0.3V.
t
is Read cycle time.
AVAV
ns
14/19
M68AR512D
PACKAGE MECHANICAL
Figure 15. TFBGA48 6x7mm - 6x8 ball array, 0.75 mm pitch, Bottom View Package Outline
D
FD
FE
D1
SD
SE
E1E
BALL "A1"
e
eb
A
A2
A1
BGA-Z43
Note: Drawing is not to scale.
Table 10. TFBGA48 6x7mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data
Symbol
Typ Min Max Typ Min Max
A 1.200 0.0472
millimeters inches
ddd
A1 0.250 0.400 0.0098 0.0157
A2 0.790 0.0311
b 0 .400 0.350 0.450 0.0157 0.0138 0.0177
D 6 .000 5.900 6.100 0.2362 0.2323 0.2402
D1 3 .750 0.1476
ddd 0.100 0.0039
E 7.000 6.900 7.100 0.2756 0.2717 0.2795
E1 5.250 0.2067
e 0 .750 – – 0.0295 – –
FD 1.125 0.0443
FE 0 .875 0.0344
SD 0.375 – – 0.0148 – –
SE 0.375 – – 0.0148 – –
15/19
M68AR512D
Figure 16. TFBGA48 8x10mm - 6x8 ball array, 0.75 mm pitch, Bottom View Packag e Outl ine
D
BALL "A1"
Note: Drawing is not to scale.
E1E
FD
FE
A
D1
SD
SE
eb
A2
A1
ddd
BGA-Z28
Table 11. TFBGA48 8x10mm - 6x8 ball arra y, 0.75 mm pitch, Packag e Mech anical Data
Symbol
A 1.200 0.0472
A1 0.260 0.0102
A2 0.900 0.0354
b 0.350 0.450 0.0138 0.0177
D 8 .000 7.900 8.100 0.3150 0 .3110 0.3189
D1 3 .750 – – 0.1476 – –
ddd 0.100 0.0039
E 1 0.000 9.900 10.1 00 0.3937 0.3898 0.3976
E1 5.250 – – 0.2067 – –
e 0 .750 – – 0.0295 – –
FD 2.125 – – 0.0837 – –
FE 2 .375 – – 0.0935 – –
SD 0.375 – – 0.0148 – –
SE 0.375 – – 0.0148 – –
Typ Min Max Typ Min Max
millimeters inches
16/19
PART NUMBERING
Table 12. Ordering Information Scheme
Example: M68AR512 D N 70 ZB 6 T
Device Type
M68
Mode
A = Asynchronous
Operating Voltage
R = 1.65 to 1.95V
Array Organization
512 = 8 Mbit (512K x16)
Option 1
D = 2 Chip Enable; Write and Standby from UB
Option 2
L = L-Die
N = N-Die
and LB
M68AR512D
Speed Class
70 = 70 ns
Package
ZB = TFBGA48, 6x7mm, 6x8 ball array 0.75 mm pitch
ZB = TFBGA48, 8x10mm, 6x8 ball array 0.75 mm pitch
Operative Temperature
1 = 0 to 70 °C
6 = –40 to 85 °C
Shipping
T = Tape & Reel Packing
Note: 1. TFB GA 48, 6x7mm is avai l able only for the M 68AR512D N part.
2. TFBGA48, 8x10mm is available only for the M 68A R512DL part.
(1)
(2)
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
17/19
M68AR512D
REVISION HIST ORY
Table 13. Document Revision History
Date Version Revision Details
August 2001 -01 First Issue
08-Oct-2001 -02 Document status moved to Preliminary Data
Document status moved to Data Sheet
18-Mar-2002 -03
17-May-2002 -04 Document globally revised
02-Oct-2002 4.1
09-Oct-2002 4.2
Temperature range 1 (0 to 70°C) added
Tables 3, 5, 6, 7, 8 and 9 clarified
Figures 7, 8, 9, 10, 11 and 12 clarified
Revision numbering modified: a minor revision will be indicated by incrementing the
digit after the dot, and a major revision, by incrementing the digit before the dot
(revision version 04 equals 4.0).
Part number changed.
Part number changed and new salestype added
TFBGA48 8x10mm package added (Figure 16, Table 11)
18/19
M68AR512D
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or oth erwise under any patent or patent rights of STMicroe l ectronics. Specificati ons mentioned in this publication are subject
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19/19
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