Datasheet M66252P, M66252FP Datasheet (Mitsubishi)

MITSUBISHI 〈DIGITAL ASSP〉

MITSUBISHI 〈DIGITAL ASSP〉

DESCRIPTION

The M66252P/FP is a high-speed line memory with a FIFO
(First In First Out) structure of 1 152-word × 8-bit configuration
which uses high-performance silicon gate CMOS process
technology.
It has separate clock, enable and reset signals for write and
read and is most suitable as a buffer memory between
devices with different data processing throughput.

FEATURES

• Memory construction........................................................

............................. 1152words x 8bits (dynamic memory)

• High-speed cycle............................................ 50ns (min.)

• High-speed access........................................ 40ns (max.)

• Output hold....................................................... 5ns (min.)

• Fully independent, asynchronous write and read opera-

tions

• Variable-length delay bit

• Output.................................................................... 3-state

M66252P/FP

1152 x 8-BIT LINE MEMORY (FIFO)

1152 x 8-BIT LINE MEMORY (FIFO)

PIN CONFIGURATION (TOP VIEW)

24
23
22

M66252P/FP

21
20
19
18
17
16
15
14
13

24P4Y
24P2W-A

Data output

Read enable input

Read reset input

Read clock input

Data output

RRES

GND

RCK

Q
Q
Q
Q

RE

Q
Q
Q
Q

0
1
2
3

4

10

5

11

6

12

7

Outline

1

2
3
4
5
6

7
8
9

M66252P/FP

D

0

D

1

Data input

D

2

D

3

Write enable input

WE
WRES

Write reset input

V

CC

WCK

Write clock input

4

D
D

5

Data input

D

6

D

7

APPLICATION

Digital photocopiers, high-speed facsimiles, laser beam print­ers.

BLOCK DIAGRAM

Data input



D

0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

Write
enable input

Write
reset input

WE

WRES

24 23 22 21

20

19

16 15 14 13

Input buffer

Memory array

(1152 x 8 bits)

Data output



12349

Output buffer

10 11 12

5

6

Read

RE

enable input

RRES

Read
reset input

Write
clock input

WCK

Vcc

17

18

Write control circuit

Write address counter

Read address counter

Read control circuit

8

7

clock input

GND

1

Read

RCK

MITSUBISHI 〈DIGITAL ASSP〉

M66252P/FP

1152 x 8-BIT LINE MEMORY (FIFO)

FUNCTION

When the status of write enable input WE is “L,” data on D
thru D7 are written on the memory synchronously with write
clock input WCK rise edges. At this time, write address
counter executes counting.
The following write-related operations are also performed
synchronously with WCK rise edges.
When WE is “H,” writing on memory is inhibited, and write ad­dress counter stops counting.
When write reset input WRES is “L,” write address counter is
initialized.

When read enable input RE is “L,” data on memory are out-

0

put to Q
rise edges. At this time, read address counter executes
counting.
The following read-related operations are also performed
synchronously with RCK rise edges.
When RE is “H,” reading from memory is inhibited, and read
address counter stops counting. The status of Q
comes high-impedance.
When read reset input RRES is “L,” read address counter is
initialized.

ABSOLUTE MAXIMUM RATINGS (Ta = –20 ~ 70°C unless otherwise noted)

Symbol
VCC
VI
VO
Pd
Tstg

Note 1: Ta ≥ 62°C are derated at –8.8mW/°C (24P4Y)

Ta ≥ 51°C are derated at –7.5mW/°C (24P

Supply voltage
Input voltage
Output voltage
Power dissipation
Storage temperature

Parameter

Reference pin: GND

Ta = 25°C

2W)

RECOMMENDED OPERATIONAL CONDITIONS

VCC
GND
Topr

Symbol

Supply voltage
Supply voltage
Ambient temperature

Parameter

Min.

4.5

–20

0 thru Q7 synchronously with read clock input RCK

0 thru Q7 be-

Conditions

Limits

Typ.

Max.
5
0

5.5

70

Ratings

–0.5 ~ +7.0
–0.5 ~ VCC + 0.5
–0.5 ~ VCC + 0.5

550 (Note 1)

–65 ~ 150

Unit

V
V

°C

Unit

V
V
V

mW

°C

ELECTRICAL CHARACTERISTICS (Ta = –20 ~ 70°C, VCC = 5V±10%, GND = 0V)

VIH
VIL
VOH
VOL

IIH

IIL

IOZH
IOZL

ICC
CI

CO

Symbol

“H” input voltage
“L” input voltage
“H” output voltage
“L” output voltage

“H” input current

“L” input current

“H” output current under “off” condition
“L” output current under “off” condition

Average supply current during operation
Input capacitance

Output capacitance under “off” condition

Parameter

Test conditions

IOH = –4mA
IOL = 4mA

VI = VCC

VI = GND

VO = VCC
VO = GND
VI = VIH, VIL, Outputs are open

tWCK, tRCK = 100ns
f = 1MHz
f = 1MHz

WE, WRES, WCK, RE,
RRES, RCK
D0~D7

WE, WRES, WCK, RE,
RRES, RCK
D0~D7

2.0

VCC – 0.8

Limits

Typ.Min.

Max.

0.8

0.55

1.0

–1.0

5.0

–5.0

100

10
15

Unit

V
V
V
V

µA

µA

µA
µA

mA

pF
pF

2

SWITCHING CHARACTERISTICS (Ta = –20 ~ 70°C, VCC = 5V±10%, GND = 0V)

tAC
tOH
tOEN
tODIS

Symbol

Access time
Output hold time
Output enable time
Output disable time

Parameter

TIMING CHARACTERISTICS (Ta = –20 ~ 70°C, VCC = 5V±10%, GND = 0V)

Symbol

tWCK
tWCKH
tWCKL
tRCK
tRCKH
tRCKL
tDS
tDH
tRESS
tRESH
tNRESS
tNRESH
tWES
tWEH
tNWES
tNWEH
tRES
tREH
tNRES
tNREH
tr, tf
tH

Note 1. The following conditions should be met for each line access:

WE “H” level period ≤ 20ms - 1152 · t
RE “H” level period ≥ 20ms - 1152 · t

2. Perform reset operation after turning on power supply.

Write clock (WCK) cycle time
Write clock (WCK) “H” pulse width
Write clock (WCK) “L” pulse width
Read clock (RCK) cycle time
Read clock (RCK) “H” pulse width
Read clock (RCK) “L” pulse width
Input data setup time (in response to WCK)
Input data hold time (in response to WCK)
Reset setup time (in response to WCK and RCK)
Reset hold time (in response to WCK and RCK)
Reset non-select setup time (in response to WCK and RCK)
Reset non-select hold time (in response to WCK and RCK)
WE setup time (in response to WCK)
WE hold time (in response to WCK)
WE non-select setup time (in response to WCK)
WE non-select hold time (in response to WCK)
RE setup time (in response to RCK)
RE hold time (in response to RCK)
RE non-select setup time (in response to RCK)
RE non-select hold time (in response to RCK)
Input pulse rise time and fall time
Data hold time (Note 1)

WCK - WRES “L” level period

RCK - RRES “L” level period

Parameter

MITSUBISHI 〈DIGITAL ASSP〉

M66252P/FP

1152 x 8-BIT LINE MEMORY (FIFO)

50
25
25
50
25
25
15

15

15

15

15

15

15

Limits

Typ.Min.

5
5
5

Limits

Typ.Min.

5

5

5

5

5

5

5

Max.

40

40
40

Max.

35
20

Unit

ns
ns
ns
ns

Unit

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

ms

3

TEST CIRCUIT

Qn

L

=30pF : tAC, t

C

OH

MITSUBISHI 〈DIGITAL ASSP〉

M66252P/FP

1152 x 8-BIT LINE MEMORY (FIFO)

Vcc

RL=1kΩ

SW1

Qn

SW2

L=5pF : tOEN, tODIS

C

L

=1kΩ

R

Input pulse level: 0 ~ 3V
Input pulse rise time and fall time: 3ns

Parameter

Measurement reference level, input: 1.3V
Measurement reference level, output:1.3V (Note: t

ODIS (LZ) is tested at 10% output

amplitude, and t

ODIS (HZ) is tested at 90%

output amplitude.)

Load capacitance CL includes floating capacitance and probe input capacitance.

TEST CONDITIONS FOR OUTPUT DISABLE TIME tODIS AND OUTPUT ENABLE TIME tOEN

RCK

RE

Qn

1.3V 1.3V

ODIS(HZ)

t

90%

t

OEN(ZH)

tODIS(LZ)
tODIS(HZ)
tOEN(ZL)
tOEN(ZH)

1.3V

SW1
Closed
Open
Closed
Open

SW2
Open
Closed
Open
Closed

3V

GND

3V

GND

OH

V

t

ODIS(LZ)

Qn

4

10%

t

OEN(ZL)

1.3V
V

OL

TIMING CHARTS

• Write Cycles

WCK

WE

MITSUBISHI 〈DIGITAL ASSP〉

M66252P/FP

1152 x 8-BIT LINE MEMORY (FIFO)

Cycle n Cycle(n+1) Cycle(n+2) Disable cycles Cycle(n+3) Cycle(n+4)

t

t

WCK

t

WCKHtWCKLtWEHtNSES

NWEH

t

WES

Dn

• Write Reset Cycles

WCK

DStDH

t

(n) (n+2)(n+1) (n+3) (n+4)

Cycle(n–1)

WCKtNRESHtRESS

t

Cycle n

tDSt

DH

Reset cycles

WRES=“H”

Cycle 0 Cycle 1 Cycle 2

t

RESH

t

NRESS

WRES

Dn

t

DH

DS

t

t

DH

t

DS

(n –1) (n) (0) (1) (2)

WE=“L”

5

• Matters that needs attention when WCK stops

n cycle n+1 cycle n cycle Disable cycle

WCK

tWCK

WE

tDS tDH tDS tDH

t

NWES

MITSUBISHI 〈DIGITAL ASSP〉

M66252P/FP

1152 x 8-BIT LINE MEMORY (FIFO)

n

D

(n)

Period for writing data (n)
into memory

(n)

Period for writing data (n)
into memory

WRES = “H”

Input data of n cycle is read at the rising edge after WCK of n cycle and writing operation starts in the WCK low-level period of
n+1 cycle. The writing operation is complete at the falling edge after n+1 cycle.
To stop reading write data at n cycle, enter WCK before the rising edge after n+1 cycle.
When the cycle next to n cycle is a disable cycle, WCK for a cycle requires to be entered after the disable cycle as well.

6

• Read Cycles

RCK

MITSUBISHI 〈DIGITAL ASSP〉

M66252P/FP

1152 x 8-BIT LINE MEMORY (FIFO)

Cycle n Cycle(n+1) Cycle(n+2) Cycle(n+3) Cycle(n+4)Disable cycles

RE

Qn

• Read Reset Cycles

RCKtRCKH

t

tRCKLtREHtNRES

t

ODIS

(n) (n+1) (n+2) (n+3) (n+4)

t

NREHtRES

HIGH-Z

t

OEN

t

AC

RRES=“H”

t

OH

RCK

RRES

Qn

Cycle(n–1) Cycle n Cycle 0 Cycle 1 Cycle 2Reset cycles

t

RCK

t

NRESH

t

RESS

(n–1) (n) (0) (0) (0) (1) (2)

t

RESH

t

NRESS

t

AC

t

OH

RE=“L”

7

MITSUBISHI 〈DIGITAL ASSP〉

M66252P/FP

1152 x 8-BIT LINE MEMORY (FIFO)

VARIABLE-LENGTH DELAY BITS

• 1-line (1152-bit) delay
A write input data is written into memory at the second rise edge of WCK in the cycle, and a read output data is output from
memory at the first rise edge of RCK in the cycle, so that 1-line delay can be made easily.

Cycle 0 Cycle 1 Cycle 2

WCK
RCK

RESStRESH

t

WRES
RRES

tDSt

DH

Dn

(0) (1) (2)

1152 cycles

Qn

• n-bit delay 1
(Making a reset at a cycle corresponding to delay length)

Cycle

1150

Cycle

1151

Cycle 0’

tDSt

Cycle 1’

DH

Cycle 2’

(1149) (1150) (1151) (0’) (1’) (2’)

t

t

AC

OH

(0) (1) (2)

WE, RE=“L”

WCK
RCK

WRES
RRES

Dn

Qn

Cycle 0 Cycle 1 Cycle 2

t

RESStRESH

t

DS

t

DH

Cycle

(n–2)

(1)(0) (2) (n–3) (n–2) (n–1) (0’) (1’) (2’) (3’)

m cycles t

Cycle

(n–1)

t

RESStRESH

Cycle 0’

AC

Cycle 1’

t

DS

t

DH

t

OH

(0) (1) (2) (3)

Cycle 2’

Cycle 3’

WE, RE=“L”
m ≥ 3

8

• n-bit delay 2
(Sliding WRES and RRES at a cycle corresponding to delay length)

MITSUBISHI 〈DIGITAL ASSP〉

M66252P/FP

1152 x 8-BIT LINE MEMORY (FIFO)

WCK
RCK

WRES

RRES

Dn

Qn

Cycle 0(W) Cycle 1(W) Cycle 2(W)

t

RESS

t

RESH

tDSt

DH

(0) (1) (2) (n–2) (n–1) (n) (n+1) (n+2) (n+3)

m cycles

Cycle

(n–1)(W)

t

RESS

Cycle n(W)

Cycle 0(R)

t

RESH

t

DS

t

AC

Cycle(n+1)(W)

Cycle 1(R)

t

DH

t

DH

(0) (1) (3)(2)

Cycle(n+2)(W)

Cycle 2(R)

WE, RE=“L”
m ≥ 3

Cycle(n+3)(W)

Cycle 3(R)

• n-bit delay 3
(Disabling RE at a cycle corresponding to delay length)

Cycle 0(W) Cycle 1(W) Cycle 2(W)

WCK
RCK

t

RESH

t

RESS

WRES
RRES

RE

tDSt

DH

Dn

Qn

(0) (1) (2) (n–2) (n–1) (n) (n+1) (n+2) (n+3)

m cycles

HIGH-Z

Cycle

(n–1)(W)

t

t

NREH

Cycle n(W)

RES

Cycle 0(R)

t

DS

AC

t

Cycle(n+1)(W)

Cycle 1(R)

t

DH

t

OH

Cycle(n+2)(W)

Cycle 2(R)

Cycle(n+3)(W)

Cycle 3(R)

(0) (1) (2) (3)

WE, RE=“L”
m ≥ 3

9

MITSUBISHI 〈DIGITAL ASSP〉

M66252P/FP

1152 x 8-BIT LINE MEMORY (FIFO)

• Shortest read of data “n” written in cycle n
Cycle n–1 on read side should be started after end of cycle n+1 on write side

When the start of cycle n–1 on read side is earlier than the end of cycle n+1 on write side, output Qn of cycle n becomes invalid.
In the figure shown below, the read of cycle n–1 is invalid.

Cycle n Cycle n+1 Cycle n+2 Cycle n+3

WCK

D

n

RCK

Q

n

(n) (n + 1) (n + 2) (n + 3)

Cycle nCycle n – 1Cycle n – 2

(n)invalid

• Longest read of data “n” written in cycle n: 1-line delay
Cycle n <1>* on read side should be started when cycle n <2>* on write is started

Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1>* and the start of writing side n cycle <2>* over­lap each other.

WCK

Cycle n 〈1〉

∗

Cycle 0 〈2〉

∗

Cycle n 〈2〉

∗

10

D

n

RCK

Q

n

(n – 1)〈1〉

(n – 1)〈0〉

∗

Cycle n 〈0〉

∗

∗

(n)〈0〉

(n)〈1〉

∗

∗

Cycle 0 〈1〉

(0)〈2〉

∗

∗

(0)〈1〉

∗

∗

(n – 1)〈2〉

Cycle n 〈1〉

∗

(n – 1)〈1〉

〈0〉∗, 〈1〉∗ and 〈2〉

indicates a line value.

∗

(n)〈2〉

∗

∗

(n)〈1〉

∗

APPLICATION EXAMPLE

Laplacian Filter Circuit for Correction of Resolution in the Secondary Scanning Direction.

MITSUBISHI 〈DIGITAL ASSP〉

M66252P/FP

1152 x 8-BIT LINE MEMORY (FIFO)

B

Line (n+1)

image data

M66252

D

0

~

D

7

1-line
delay

M66252

D

0

~

D

7

1-line
delay

Q
Q

Q
Q

0

~

7

0

~

7

A

Line (n–1)

image data

×2

Adder

Line n image data

A+B

N

2N–(A+B)

Subtractor

×K

{2N–(A+B)}

Adder

N+K

Corrected
image data

Primary scanning

direction

Secondary scanning

direction

A
N
B

Line (n–1)
Line n
Line (n+1)

N' = N+K {(N–A)+(N–B)}

= N+K {2N–(A+B)}
K :

Laplacean coefficient

11