Datasheet M65761FP Datasheet (Mitsubishi)

SPECIFICATION OF INTEGRATED CIRCUIT

)

MITSUBISHI ICs (LSI)

M65761FP

QM-CODER

1. TYPE NO.

2. FUNCTION

2.1 CIRCUIT FUNCTION

2.2 BLOCK DIAGRAM

3. APPLICATION

4. OUTLINE

4.1 PACKAGE

4.2 OUTLINE DRAWING

M65761FP

QM-Coder

see the third page

FAX, PPC etc

100 Pin Plastic Molded Quad Flat Package (Fine Pitch)
[100P6S-A]

G465181

5. CIRCUIT DIAGRAM
DRAWING

6. PIN DIAGRAM

7. OTHER SPECIFICATIONS

see the next page (2page

see cover page of specification

PIN CONFIGURATION(TOP VIEW

)

MITSUBISHI ICs (LSI)

M65761FP

QM-CODER

GND

PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9

PD10

V

GND
PD11
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21

V

GND
PD22
PD23
PD24

VCC

TEST0

TEST1

TOUT1

TOUT2

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

1
2
3
4
5
6
7
8

9
10
11
12

CC

CC

13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

GND

PXCKO

VCCD15

M65761FP

D14

D13

D12

GND

VCCD11

D10D9D8

GND

CC

V

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

D7
D6
D5
D4
GND

CC

V
D3
D2
D1
D0
GND

CC

V
RESET

A3
A2
A1
A0
BHE
CS
MCLK
GND

CC

V
WR
RD
DMAAK
BUS16
DMARQ
INTR
XCLK
GND

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

CC

V

PD25

PD26

PD27

PD28

PD29

PD30

PD31

PDRQ

GND

PDRD

PDAK

PDWR

RVID

PRDY

SVID

Outline 100P6S-A

PTIM

PXCK

CC

V

XWAIT

BLOCK DIAGRAM

MITSUBISHI ICs (LSI)

M65761FP

QM-CODER

100

RESET

CS

68

62

–

A0

64

–––––

BHE

A3

WR

58

63

67

SWITCH

––––

D0

RD

71

57

CONTEXT TABLE RAM

CONTEXT GENERATION

D4

D3

77

74

QM-CODER

D7
80

D8
83

D11
86

HOST BUS I/F

TABLE RAM PROBABILITY ESTIMATION

D12
89

D15

92

DMARQ

DMAAK

56

54

INTR
53

BUS16
55

MCLK
61

TEST1
98

TEST0
99

Leave TOUT1 and TOUT2 open.

97
96

TOUT1,2

94

70 76 82 88
60

GND

51

14 27 40
1

TYPICAL PREDICTION

PIXEL DATA

–

28

–

PD22

LINE MEMORY

37

PD31

PD0-11=CX0-11

PD15=PEUPE

38

PDRQ

43

PDAK

41

PDRD

42

PDWR

45

PRDY

IMAGE DATA • CONTEXT I/F

47

PTIM

(=XRDY)

VCC

13 26 39 50 59 69 75 81 87 93

12

PD10

–

15

–

PD11

25

PD21

2

PD 0

–

–

CONTEXT DATA

48

PXCK

(=XTIM)

46

95

SVID

PXCKO

44

RVID

(=SPIX)

52

XCLK

(=RPIX)

49

XWAIT

9. CODING SPECIFICATION

(1) Coding Algorithm

• QM-Coder
(JBIG Standard Arithmetic Coding System)

(2) Context

(i) Built-in Context Mode

a) Template Model

• 2 or 3 line 10 pixel template (See Fig9. 1)
(This agrees with the template used with the minimum resolution of JBIG)

NOTE:The coding efficiency of the 3-line template is better than that of the 2-line template by several %.

b) Adaptive Template (AT)

• It is possible to move up to 127pixcels on the coding line.
(The position of ATgiven instruction by the MPU)

Note:It is possible to improve the coding effeciency against the dither image

by the use of AT.

• It is posible to change the position of AT line by line in the middle of coding

and decoding.
Note:It is not possible to change the template at the time when change the

position of the AT pixels.

(ii) Extenal Context Mode

• It is possible to input any context up to 12 bits.

(It is possible to interface with JBIG Progressive Coding and the Arithmatic Coding of JPEG Option Function)

X

A

A

MITSUBISHI ICs (LSI)

M65761FP

QM-CODER

XXX
XXXX?A
XX

XXXXX?A
XXX

Fig. 9. 1 Template (X, A)

(Top : 3line, Bottom : 2line)

XXX
XXXX
X?X

MAX127

X
X

X

MAX127

Fig. 9. 2 Adaptive template (A)

XXX
X?X

X

(3) Typical Prediction

• Agreement with the Typical Prediction of the lowest resolution of JBIG.
The pseudo-pixcel (SLNTP) is geneated by the symbol LNTPwhich shows whether the coding/decoding process agree with the directly
before line.If they agree, the line is not coding/decoding .
This makes it possible to shorten the time of process and rejection of the code data.
SLNTPy =! ( LNTPy + LNTPy-1 ) (y:line number, LNTPy=1; LNTPy-1=1)

(4) Deterministic Prediction

• This LSI is not equipped with the Typical Prediction.However,the DP function is realized when the DP pixels are identified and
eliminated by the extenal circuits during the external context mode.

(5) Coding Data Format

• The Stripe Data Entity (SDE)
(=Stripe coded data with byte stuffing (PSCD) + end marker (SDNORM/ SDRST)) Coding/decoding of one stripe portion os
perfformed.In case of the multi-striped (construct the multi stripes) stripes are activated one at a time.

(6) Marker Code

• The SDE end marker is supported.(SDNORM=02h, SDRST=03h, ABORT=04h)
(During coding the marker code previously set in the register is outputted.During decoding ,the marker code detected by requesting an
interrupt to MPU when the marker is detected is read out od register.)

(7) Rough Estimate of Coding and Decoding Time(T1:M65761FP as a whole,T2;Processing Time of the arithmetic coding section alone)

• The total number of clocks needed for coding and decoding 1 page (stripe)is calculates roughly using the following equations.

T1= (p ∗ Lp) + (9/8 ∗ C) + (α∗Lp)

- S ∗ ((1 - β) ∗ p ∗ Ltp - Lp) [clock]

T2= (p ∗ Lp) + (9/8 ∗ C)

- S ∗ ((p ∗ Ltp) - Lp)) [clock]

p : Number of pixcels/line β : about 0.3
Lp : Number of lines/page

Ltp : Number of TP line /page
C : Number of coded data bits/page

S= 1: TP exists 0: No TP α : about 10

10. FUNCTIONAL DESCRIPTION OF PINS

MITSUBISHI ICs (LSI)

M65761FP

QM-CODER

Classification Pin name I/O Function

RESET
CS
A0-3
BHE

Host Bus I/F

Parallel

Image data
I/F

Serial

Context I/F

WR
RD
D0-15
DMARQ
DMAAK
INTR
BUS16

PD0-31
PDRQ
PDAK
PDRD
PDWR

PRDY
PTIM
PXCK
PXCKO
SVID
RVID

CX0-11
PEUPE
SPIX
RPIX
XCLK
XWAIT
XRDY
XTIM

I
I
I
I
I
I
IO
O
I
O
I

IO
O
I
I
I

O
I
I
O
I
O

I
I
I
O
O
I
O
I

BUF

S

H/W reset signal
Chip select signal
Internal register address select signal
High-order(D8-15)access signal

S

Write strobe signal

S

Read strobe signal

8

I/O data signal (D0-7 used on 8-bit bus)

2

Code data DMA request signal

US

Code data DMA acknowledge signal

2

Interrupt request signal

U

8-bit bus (D0-7)and 16-bit bus(D0-15)function select bus.

U2

Parallel image I/O bus (PD0-15 used on 16-bit bus)

2

Image data DMA request signal

US

Image data DMA acknowledge signal

US

Image data read strobe signal

US

Image data write strobe signal

2

Image data 1-line I/O start ready signal

US

Image data 1-line transfer section signal

US

Image data transfer clock signal

4

Image data transfer sync clock signal

U

Image data input signal

2

Image data output signal

U

Context input (CX0 can be fed back inside LSI) (=PD0-11)

U

PE RAM update enable (learning function ON/OFF) (=PD15)

U

Coded image data input signal (=SVID)

2

Decoded image data output signal (=RVID)

4

Context data transfer clock signal

US

Context data transfer wait signal

2

Context data 1-stripe I/O start ready signal (=PRDY)

US

Context data 1-stripe transfer section signal (=PTIM)

MCLK

Others

Notes:Most of the context I/F signals are used in conjunction with the image data I/F signals.
∗ The input buffers of the input terminals (I and IO) are at TTL level.

Options are as follows.

(U:with pull-up resistors,D:with pull-down resistors,S:Schmitt trigger)

∗ Numbers (2,4,8) of the BUF column of the output terminals (O and IO) indicate current value. (one of 2,4,or 8mA)

TEST0-1
Vcc/GND

I
I
–

Master clock input signal

DS

Test signal (should be connected to GND when normally used).

–

Power supply (+5V)/ground

11. REGISTER CONFIGURATION

11. 1 List of registers

Address Register Name R/W Description

• LSI H/W reset

• Coding/decoding/image data through mode selection

• Context selection(internal context/external context)

0

1

2

System setting

Parameter setting

Command

R/W

R/W

W

• Byte swap ON/OFF of coded/image data on host bus

• Bit swap ON/OFF of coded/image data on host bus

• Image data I/O I/F(parallel I/F,serial I/F)

• Image data bus bit width selection(32bits/16bits)

• Template selection (2-line/3-line template)

• Setting of AT pixel position (up to 127)(IF O is set,AT becomes
non-existent (default position))

• Latch input/through input selection in external context input mode

• Context table RAM initialization command

• Coding (decoding,through) start/end command

• Start/stop command for R/W of context table RAM

• Selection of temporary stop and terminating end

MITSUBISHI ICs (LSI)

M65761FP

QM-CODER

2

3

4,5

6,7

8,9

A,B

A,B

C

C

Status

Interrupt enable setting

Pixel count setting

Line count setting

Processed line count

Data write buffer

Data read buffer

Marker code setting

Marker code read

R

R/W

R/W

R/W

R

W

R

W

R

• Processing status (in process/end of processing)

• Coded data read/write ready (ready/busy)

• Marker code detection (SDNORM,SDRST,ABORT,others)

• Interrupt request status

• SC counter over flow

• Processing mode (stop temporary/terminating end)

• Interrupt enable setting correspondence to each of bits positions of
status register

• Setting the number of pixels on one line (in multiples of 16or32,up to
10240 pixels)

• Setting the number of lines to be coded/decoded(up to 65535 lines)

• Setting the number of coded/decoded lines (up to 65535 lines)

• Buffer for writing coded data/image data/context table RAM data from
MPU into LSI (DMA transferable)(RAM address is automatically
incremented each time data is written.)

• Buffer for reading coded data/image data/context table RAM data from
LSI into MPU (DMA transferable)(RAM address is automatically
incremented each time data is read).

• Setting a terminal marker code in coding (SDNORM/SDRST)

• Reading a marker code in decoding (SDNORM,SDRST,ABORT,others)

• Reduction in coding (1/2 reduction in horizontal and vertical directions,
horizontal OR processing)

D

Notes:When the 8bit bus is used for the data read/write buffer,use Address A only.

Scaling

Incase of the 16-bit buffer,only the word access is possible.

(The byte access is not possible).

R/W

• Magnification during decoding ( × 2 lengthwise and width)

• Select throwing away the leading 1byte of the coded data read when
decoding

• Selecting the typical prediction

• Selection of prohibiting line memory initialization

11. 2 Description of Registers

(1) System Set Up Register (W/R) (address : 0)

d0(HR) : H/W reset (0:Active, 1:Reset state)

To make a H/W reset ,set this bit to 1 then to 0.
Reset initializes the entire LSI including the group of register and Line Memory. However, the context table RAM is not
initialized.

d1-2(MOD) :This sets up the operating modes.

(d2=0,d1=0:coding, d2=1,d1=0:iage data through (Iage data I/F→Host I/F),
d2=0,d1=1:decoding, d2=1,d1=1:Iage data through (Host I/F→Iage data I/F))

d3(CX) :Context select (0:internal context, 1:Image data through)

NOTE:The internal context should be selected when the image data through mode is used.

When initializing or processing R/W of the Context table RAM and coding /decoding,

This bit must be set the same.(Because RAM configration changes depending on internal/external modes.)
d4(BS) :Select data bit swap of the host bus. (0:MSB(d7)first, 1:LSB(d0)first)
d5(BX) :Select data byte swap of the host bus.(0:Lower byte(A)first, 1:Upper byte(B)first)

NOTE:BX is valid only when the host bus is 16 bits.(BUS16=HIGH)

Table 11. 2 The coed data and image data line-up on the Host bus

Bus width
BUS16

1

16bit

0

8bit

d6(PI) :Selects the image data I/O I/F (0:Serial /F, 1:ParallelI/F)
d7(PB) :Selects the bit width of the iamge data bus (0:32bit bus (PD0-31), 1:16bit bus(PD0-15))

Table 11. 3 The image data line-up on the image data parallel bus

bit width

PB=0
PB=1

Swap

BX BS

0

0

0

1

1

0

1

1

––0

1

PD31 • • • • • • PD16
p0 • • • • • • p15

Upper address(B) Lower address(A)

d15 • • • • • • d8

b8 • • • • • • b15
b15 • • • • • • b8
b0 • • • • • • b7
b7 • • • • • • b0

–
–

PD15 • • • • • • PD0
p16 • • • • • • p31

–

p0 • • • • • • p15

d7 • • • • • • d0
b0 • • • • • • b7

b7 • • • • • • b0
b8 • • • • • • b15
b15 • • • • • • b8

b0 • • • • • • b7
b7 • • • • • • b0

SYS_REG :

p0 is the image data on the left-hand on the screen.
p31is the image data on the right-hand on the screen.

MITSUBISHI ICs (LSI)

M65761FP

QM-CODER

d7(MSB) d0

PB PI BX BS CX MOD HR

b0 is the first coded data on the time
series/the left-hand side image data on the
screen.
b15 is the last coded data on the time
series/the right-hand image data on the
screen.

(2) Parameter Setup Register (W/R) (Address:1)

d7

1) External Context Mode

d6 (LC) :Condition of taking in the input from the external context are selected.

(0:through onput, 1:latch input)

When this bit is set to 1,the CX0 to CX11 of the context input is latched once using the transfer clock.("XCLK")

d7 (C0) : When this bit is set to 1,CX0 is selected.

(0:CX0 external input, 1:CX0 internal feedback)

2) Internal Context Mode

d0-4 (AT<0>-AT<4>) :ATpixel position Lower 5bits. (See Fig.9. 2)
d5 (TM) :Template select (0:3line template, 1:2line template)
d6 -7(AT<5>-AT<6>) :AT pixel position upper 2bits (the 6th and 7th bits)

d7

Example : 3line template,AT=4 :

2line template,AT=48 :

NOTE) The AT pixel position at time of the internal context mode is set up by using all the AT<6:0> (0 to 127)

When the default position (when the AT pixels are not used) is used, At is set to 0.
When the 2-line templsate is used, AT should not be set to 1 to 4. In case of the 3-line template,
AT=1 to 2 is not allowed.

0 0 0 0 0 1 0 0

d7

0 1 1 1 0 0 0 0

d4

d4

PARA_REG :

PARA_REG :

d0

d0

C0 LC 0 0

d5

d6

d7

AT TM AT

d4

d4

d0

d0

MITSUBISHI ICs (LSI)

M65761FP

QM-CODER

(3) Command Register (W) (address : 2)

CMD_REG :

d0 (IC) :This command starts initialization of Context Table RAM (1:start initialization)

When this bit goes 1,the Context Rable RAM initialization starts.This bit returns to 0 automatically when the initialization is
completed.

d1 (JC) :Processing (Coding/Decoding/Through) start /end command (1:start processing, 0:end processing)

When this bit goes 1,processing(coding/decoding/through)starts.
This bit returns to 0 automatically when processing of the number of set lines is finished during the selection of end of
termination.
And if this JC bit is made 0 and inputting the image data is stopped during the coding porocess,the coding is stopped (flushed)
even if the set lines are not filled.Mreover,if this bit made 0 during decoding and no more coded data is coming in,it is
assumed that the '00'of the coded data came in and the preset lines have been processed.However,in case of the multi­striped coding ,processing should not end by making this bit "0" except in case of last stripe.

d2 (RC) :This command starts and stops R/W of Context Table RAM. (1:R/W start, 0:R/W end)

The Context Table RAM is read out or written in by making this bit to "1".
When reading/writing is finished,this bit must have "0" on it.

d3 (JP) :This selectd temporary stop and the end of termination of coding/decoding/through processing.

(1:Temporary stop selected, 0:End of processing selected)
When the process start command d1(JC)is issued by making this JP bit to 1,the processing stops temporarily when the set
number of lines have been processed. Then, if the process satart command d1(JC) is issued,processing restarts.(See 11.4(3))

d7

d3

0 JP RC JC IC

d0

(4) Status Register (R) (address : 2)

d0 (JS) :This register indicates the status of processing in initialization,coding,decoding and through.

(0:Processing in progress(being initialized),1:End of processing)
This JS bit goes to "1"when the initialization is completed as RAM initialization command is issued.
(IC=1) This JS bit goes to "1"when all coded data has been read out during coding in case when the process start command
of the processing end is issued.(JC=1,JP=0) This JS bit goes to "1" when reading all the image data has been completed
during the image data through and decoding. Moreover,this JS bit stays "0" even when the set number of lines have been
processed when the command to start processing the process which has been stopped temporarily has been issued (JC=1,
JP=1). (However,interrupts are issued during the temporary stops.)

d1 (DS) :This is used for read and write ready of coded data.(In case of the through mode,this is used for the image data.)(1:Ready,

0:Reading no possible)
It is possible to do R/W of data by the way of the data write/read buffer when this bit is 1.

d2 (MS) :This detects the marker code during decoding.(0:not detected, 1:detected)

This bit goes to "1" if any marker is detected during decoding.
d3 (IS) :This indicates the status of the interrupt request.(0:No request, 1:Request exists)
d4(SC) :This shows the SC count over error during coding.(0:Normal, 1:There is a SC counter overflow)

NOTE:The SC counter counts the "FF" data bytes which occur duriing coding.Coding continues even when the SC counter

overflows.this means correct coding data will not be outputted.(Coding error)

d5(PS) :processing modes (Stopped temporary /End of trailer)(1:Process temporaryily stopped, 0:End of processing)

This PS bit corresponds to the temporary stop and end of processing of d3 bit (JP) processing of the command register.

STAT_REG :

d7

d5

0 PS SC IS MS DS JS

d0

MITSUBISHI ICs (LSI)

M65761FP

QM-CODER

(5) Interrupt Enable Register (W/R) (address : 3)

IENB_REG :

d0 (JE) :Temporary stop/End of trailer interrupt of initialization/coding/decoding/through .

(0:interrupt mask, 1:interrupt enable)

d1 (DE) :Coded data(Image data)read out/write in ready interrupt.

(0:interrupt mask, 1:interrupt enable)
d2 (ME) :Marker code detection interrupt during decoding. (0:interrupt mask, 1:interrupt enable)
d3 (SE) :SC count over error interrupt during coding.(0:interrupt mask, 1:interrupt enable))

This bit sets to 1 beforehand, it occurs the interruption when the SC counter is overflow during coding. Processing of coding

continues, but the correct coded data is not output.

NOTE:Bits,d0-d3,are for interrupt enable of bits d0-d2 and d4 of the Status Register.

The interrupt request signal(INTR) is asserted when any one of the status bit set in the interrupt enable (D0(JE)generates

interrupts even during the temporary stop),the status goes to "0" due to H/W reset or the INTR signal is negated when the

interrupt mask causes factors for interrupt to be lost. Moreever, the status register will not be cleared by the generation of

interrupts or the R/W of the interrupt enable register.
d7 (MP) :This specified the marker code detection time halt. (0:Continue/restart, 1:temporary halt)

Decoding will stop temporarily when the marker code is detected if this MP bit is preset to "1"during decoding. (it occures

interruption when the marker code is detected, if the ME bit preset to "1".)

if decoding is not completed during the temporary halt,it is possible to reset the line number setup

register. Next, if this MP bit is set to "0",decoding is restarted(Decoding continues to the line number set.)

d7

MP 0 SE ME DE JE

d3

d0

(6) Register used to set the number of pixels (W/R)

(address:4)

(address:5)
d0-7 (PEL_L) :Number of pixels/line is set (Lower byte)
d0-5 (PEL_H):Number of pixels/line is set (Upper byte)

It is possible to set up 8192 pixels maximum when 3-line template is used. It is used to set up 10240 pixels maximum when 2-line
template is used. The number of pixels actually coded (or decoded)should be set when reducing(or expanding).When the image
bus uses 16bits(or 32bits)in parallel I/F,multiples of 16 (or 32) should be set. In case of serial I/F,multiples of 8 should be used.

(7) Line Number Setting Register (W/R)

(Address:6)
(Address:7)

d0-7 (LSET_L):This sets the number of lines to be processed. (Lower bytes)

(1 to 65535, 0 line not used)

d0-7 (LSET_H):This sets the number of lines to be processed. (Upper bytes)

When reducing(magnification)the actual number of lines to be coded (decoded) should be set.The number of lines (relative number of
lines)from the process start command to be issued from now the immediately following temporary stop/end of trailer should be set. This
register should be set to the value specified before the process star command is issued. Moreover,this register can be rewritten during
processing as long as the following conditions are met:

• If the maximum value, (65535), is set before the process start command is issued,it can be reset once during processing.

• If a value other than maximum value (65535) is set before the process start command is issued and if resetting becomes necessary
during processing,the maximum value (65535) has to be reset once and desired value should the reset.

PEL_REG_L :

PEL_REG_H :

LSET_REG_L :

LSET_REG_H :

d7

PEL_L

d7 d0

d7

d5

PEL_H0

LSET_L
LSET_H

d0

d0

MITSUBISHI ICs (LSI)

M65761FP

QM-CODER

(8) Number of Lines to be Processed Specified (R)

(address:8)

(address:9)
d0-7 (LINE_L):The number of lines actually processed is read out (Lower bytes) (0 to 65535)
d0-7 (LINE_H):The number of lines actually processed is read out (Upper bytes)

When the number of lines processed≥number of lines set,coding/decoding/through stops temporarily/end of processing
∗ NOTE:The number of lines to be processed by this processing is cleared to 0 by the issuance of process start command.

(9) Data write in buffer (W) (See Note1)

(address:A)

(address:B)
d0-7 (DWR_L):This writes in the coded data/image data/context table RAM data (Lower bytes)
d0-7 (DWR_H):This writes in the coded data/image data/context table RAM data (Upper bytes)

(10) Data read out buffer (R) (See Note1)

(address:A)

(address:B)
d0-7 (DRD_L) :This read out the coded data/image data/context table RAM data. (Lower bytes)
d0-7 (DRD_H) :This read out the coded data/image data/context table RAM data. (Upper bytes)

∗ NOTE1:Address A is used with 8bit bus. In case of the 16 bit bus, only the word access is possible.

(Not byte access). If the number of coded data bytes is an odd number during coding, an one byte pad ("00") is attached after the
end marker is issued in order to use it as a word boundary.
See Table 11.2 for the bit arrangement used during the coded data/image data. In case of the context table RAM data, only the
lower byte becomes valid data regardless of the bus width of the host bus (BUS16).

LIN_REG_L :
LIN_REG_H :

DWR_BUF_L :

DWR_BUF_H :

DRD_BUF_L :

d7

LINE_L
LINE_H

d7

DWR_L
DWR_H

d7 d0

DRD_L
DRD_HDRD_BUF_H :

d0

d0

Table 11. 4 Context data line-up

Host I/F
Bus Width

8bit

16bit

(11) Marker code set up register (W) (address:C)

d0-7 (MSET):The end marker code used during coding is set.(SDNORM=02h, SDRST=03h)

(12) Marker code read out register (R) (address:C)

d0-7 (MDET):The marker codes detected during decoding are read out.

Upper address (B) Lower address (A)

d15 • • • • • • • d8 d7

–
–

The byte set to this register is outputted as the end marker during coding.

(SDNORM=02h, SDRST=03h, ABORT=04h etc)
The marker codes detected during decoding read out as is.

d6 • • • • • d0

mps

s6 • • • • • s0

mps

s6 • • • • • s0

mps:Superior symbol MPS (expected value ∗o/1)
s6-0:Status number ST (0 to 112)

MSET_REG : MSET

MDET_REG : MDET

d7

d7

d0

d0

MITSUBISHI ICs (LSI)

M65761FP

QM-CODER

(13) This register sets up various functions (W/R)

(address:D)

d0 (VE):Selects expansion in lengthwise direction during decoding. (0:Equal dimension, 1:∗2 expansion)
d1 (HE):Selects expansion sideways during decoding. (0:Equal dimension, 1:∗2 expansion)

∗d0 and d1 are possible only during decoding.

d2 (VR):Selects reduction in lengthwise direction during coding. (0:Equal dimension, 1:1/2 reduction)
d3 (HR):Selects sideways reduction during coding. (0:Equal dimension, 1:1/2 reduction)

∗d2 and d3 are possible only during coding.

d4 (HO):Selects thinning in sideways direction during coding. (0:simple thinning, 1:OR processing)

This reduction is valid only during coding.
Note 1:This lengthwise 1/2 reduction during coding is used for the simple thinning. (Odd lines are skipped)
Note 2: The number of lines for image data to be inputs when VR=1 for coding must be twice the value set by the register which

sets the number of lines.

Note 3:The number of lines for image data to be outputs when VE=1 for decoding must be twice the value set by the register which

sets the number of lines.

d5(OB):This selects if the leading 1 byte is discarded during decoding. (0:Normal processing (No discarding),

1:The leading 1 byte is discarded)
If a command to start processing the first the stripe decoding is issued during decoding while OB is set to "1", the leading 1 byte
of the input data is discarded. (Not used for decoding) If OB=0,the one of byte discarding process is not used. (Normal decoding
used) For example, this function is used by the Host 16 bits bus when the leading 1 byte of the input data word is an invalid data.

Note :Selecting this function is valid in case of the Host 8 bits bus and the external context mode also.

d6 (LI):Line memory initialization is prohibited. (0:Initialization specified, 1:Initialization prohibited)

When a command to start processing coding/decoding of the first stripe is issued, if L1=1, the initialization of the internal line
memory is prohibited. (The last image data of the immediately prior coding/decoding left in the line memory is used as the
leading reference line data o the next coding/ decoding.) When LI=0, the internal line memory is initialized. (All white (0) data is
used as the leading reference line data of the next coding /decoding.)In case when the previous stripe ended with SDNORM
during coding/decoding of multi-stripe by setting this bit in the initialization prohibit (1).

Note :Even when LI=1is set, this LI bit is cleared (0) and the internal line memory will be initialized the same line

the H/W reset is written into the external reset terminal or the system set up register.

d7 (TP):This selects the Typical prediction when coding and decoding. (0:Typical prediction off, 1:Typical prediction ON)

d7 d0

TP LI OB HO HR VR HE VECONV_REG :

due to the fact that

11. 3 Initialization of register

Each register is initialized as shown in the table below by writing H/W reset to the external RESET terminals or the system set up registers.
Table 11. 5 Initialization values for registers

Initialization valuesRegisters

System set up
Parameter set up
Command
Status
Interrupt enable
Number of pixels set up
Set up number of lines
Number of lines processed
Data buffer
Marker code set up
Marker code read out
Various functions set up

00h Notes
00h
00h
00h
00h
00h
00h
00h
Inderfinite
00h
00h
00h

Note:When writing H/W RESET into the System

Setup Register,the value written into is set
up in the System Setup Register.

MITSUBISHI ICs (LSI)

j

M65761FP

QM-CODER

11. 4 Sequence of setting up registers

(1) Initialization sequence of the internal line memory and context table RAM

This sequence starts with the initialization set up (See Note) of internal line memory by the H/W RESET. It is followed by the
initialization of the Context table RAM. (Clear)

1

H/W Reset
Context mode set up

Context table RAM
Initialization command issued

Interrupt enable set up

[During this time,the context table RAM is initialized.]

The number of clocks needed for initialization is as follows,

When the internal text mode is used, 1024 + α [clocks]
When the external text mode is used, 4096 + α [clocks]

(Interrupt generation)

Set up interrupt enable

SYS_REG:

SYS_REG:

CMD_REG:

IENB_REG:

IENB_REG:

d7 d0

0 0 0 0 0 0 0 1

0 0 0 0 C 0 0 0

∗ The ON time for H/W RESET bit (The time from d0="1" is

written in to the time when d0="0" is written in)should be 100ns more.
0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 1

d7 d0

0 0 0 0 0 0 0 1

;H/W reset bit ON
;H/W reset bit OFF

;C=Context mode set up

;Context table initialized

;Process ens interrupt enable

;Interrupt disable

Status register read out

(Check if procesing finished)

= 1 ?

Y

End of initialization command

to 2

Note: Initialization of the line memory by H/W RESET is provided for for the start of coding and decoding by preparing the all white (0) data

as a reference line. At the same time,it initializes the LNTP bit to LNTP=1 for the Typical Prediction .

N

(Error)

STAT_REG

CMD_REG:

– – – – – – – J

0 0 0 0 0 0 0 0

;j=End of processing

;End of initialization

(2) Coding/decoding of stripes (No change in the AT pixel position)/Image data through processing sequence

j

2

System set up
(LSI mode set up)

Parameter set up
(Template,context)

Set up number of pixels

d7 d0

SYS_REG:

∗

∗

PARA_REG:

PEL_REG_L:

PEL_REG_H:

b p x s C m m 0

c/a l/a t a a a a a

pel_l

0 0

pel_h

;mm=operating mode(Coding/decoding)
;C=context selection(Internal/external)
;s,x=Bit,byte swap
;p,b=Image data I/F, bit width

;aa,aaaaa=AT pixel position
;t=Template selection
;l=Conditions to take in external context
;c=External context CX0 selects

;pel_l,pel_h=Number of pixels per line

MITSUBISHI ICs (LSI)

M65761FP

QM-CODER

Set up number of lines

Set up marker code
(Note:Coding only)

Set up functions

Note:Set Li to "0" when it is the leading stripe of

Process start command
(Coding/decoding/through)

Set up interrupt enable

∗ When the external context mode is used,it is not necessary to set the position of AT pixels,number of

pixels,number of lines,and expansion,reduction/typical prediction/line memory initialization selection.
(They will be invalid)

[Coding and decoding are performed during this time]– – –I/O of image data and code data is performed.

(Interrupt is generated)

Interrupt disable is set up

∗

∗

single or multi stripe.

LSET_REG_L:

LSET_REG_H:

MSET_REG:

CONV_REG:

CMD_REG:

IENB_REG:

IENB_REG:

Tp Li Ob Ho Hr Vr He Ve

0 0 0 0 0 0 1 0

0 0 0 0 0 0 0 1

(Coding and decoding of stripe is performed.)

d7 d0

0 0 0 0 0 0 0 0

lset_l

lset_h

mset

;lset_l,lset_h=Number of lines processed

;mset=marker code byte set up
(SDNORM=02h,SDRST=03h)

;Ve,He=Select expansion during decoding
;Vr,Hr,Ho=Select reduction during coding
;Ob=Select discarding leading 1 byte during decoding
;Tp=ON/OFF of typical prediction function
;Li=Select prohibiting initialization of line memory

;End of trailer processing (Coding/decoding/through)

start command

;Processing end interrupt enable

;Interrupt disable

Status register is read out
(Check end of processing)

N

= 1 ?

Y

Decoded?

Y

(Decoded)

m=1?

Y

(Marker detected)

Marker code read out
Note:only for decoding

End

(Error)

N

(Coded)

N

(Marker not yet detected)

(Error)

STAT_REG:

MDET_REG:

– – – s – m – j

s = 0 ?

Y

End

mdet

;j=End of processing
;m=Marker detection
;s=SC counter overflow

N (SC counter overflow)

(Error)

;mdet=marker code read out

MITSUBISHI ICs (LSI)

(3) Processing sequence of coding/decoding of stripes (Internal context mode and AT pixel position may change)

2

System set up
(LSI mode set up)

Parameter set up
(Template,At pixel position)

SYS_REG:

PARA_REG:

d7 d0

b p x s C m m 0

a a t a a a a a

;mm=operating mode(Coding/decoding)
;C=0 Internal context selected
;s,x=Bit and byte swap
;p,b=Image data I/F, bit width

;aa,aaaaa=AT pixel position
;t=Template selection

M65761FP

QM-CODER

Set up number of pixels

Set up number of lines

Set up marker code
(Note:Coding only)

Set up various functions

Note:Set Li to "0" when the leading stripe of

single or multi stripe is used.

Process start command
(Stop processing temporarily)

Set up interrupt enable

[Coding /decoding go on during this time] – – – I/O of the first image data and code data take place.
Note:During the first processing,if it is coding,(the number of lines of the input image data)=

(the value set in the register which sets the number of lines)+1
During decoding,(number of lines of the output image data)=(the value set in the register which sets the number of lines)-1

PEL_REG_L:

PEL_REG_H:

LSET_REG_L:

LSET_REG_H:

MSET_REG:

CONV_REG:

CMD_REG:

IENB_REG:

0 0

Tp Li Ob Ho Hr Vr He Ve

0 0 0 0 1 0 1 0

0 0 0 0 0 0 0 1

pel_l

lset_l

lset_h

mset

pel_h

;pel_l,pel_h=Number of pixels per 1 line

;lset_l,lset_h=Number of lines process
Note:The number of lines up to the point

where AT pixel position is changed is set.

;mset=marker code byte set up
(SDNORM=02h,SDRST=03h)

;Ve,He=Expansion selection for decoding
;Vr,Hr,Ho=Select reduction during coding
;Ob=Select discarding leading 1 byte when coding
;Tp=ON/OFF of typical prediction function
;Li=Select prohibiting initialization of line memory. Note

;Stop processing temporarily (Coding/decoding)

;Processing stop interrupt enable

Interrupt disable is set up

Status register is read out

Middle of set up

to Next page

(Interrupt is generated)

Set up the last AT

Set up AT pixel position

Set up number of lines

IENB_REG:

STAT_REG:

Last set up

PARA_REG:

LSET_REG_L:

LSET_REG_H:

d7 d0

0 0 0 0 0 0 0 0

– – p – – – – j

Go to 3

a' a' t a' a' a' a' a'

lset_l
lset_h

;Interrupt disable

;Status check
;j=0,p=1;temporary check

;AT pixel change set up (a'a'a'a'a'a'a')
∗ Template not to be changed

;lset_l,lset_h=Number of lines process
Note:Set up the number of lines to be processed from
the time processing restarted to the position where
next the next AT pixel is changed.

j

(To previous page)

MITSUBISHI ICs (LSI)

M65761FP

QM-CODER

Process start command
(Temporary stop command)

Set up interrupt enable

[Coding and decoding are performed during this time] – – – I/O of image data and code data is performed.

This routine is repeated the (AT move -1) times

Note:During the above processing the following is true.

(Interrupt is generated)

Interrupt disable is set up

CMD_REG:

IENB_REG:

During coding,

(The number of lines of the input image data) = (Number of lines set in the line number setting register)

During decoding,

(Number of lines of the output image data) = ( Number of lines set in the line number setting register)

IENB_REG:

0 0 0 0 1 0 1 0

0 0 0 0 0 0 0 1

d7 d0

0 0 0 0 0 0 0 0

;Command to restart processing which stopped
temporarily (Coding/decoding)

;Processing end interrupt enable

;Interrupt disable

Status register is read out
(Check end of processing)

= 1 ?

Y

Decoded?

(Decoded)

Y

m=1?

(Marker detected)Y

Marker code read out
Note:only for decoding

End

STAT_REG:

N

(Error)

(Coded)N

(Marker not yet detected)

N

(Error)

MDET_REG:

– – – s – m – j

s=0?

Y

End

mdet

;j=End of processing
;m=Marker detection
;s=SC counter overflow

N (SC counter overflow)

(Error)

;mdet=marker code read out

(4) Read out /write in sequence of context table RAM

This sequence dies R/W of context table RAM.

MITSUBISHI ICs (LSI)

M65761FP

QM-CODER

d7 d0

Set context mode

Start command for R/W

of RAM

[Reading (writing) of Context table RAM continues during this time.]

RAM data is outputted (inputted) by way of data read (write) buffer.
The RAM address is automatically incremented every time 1 byte is read out (write in)

(Note) It I not possible to mix reading and writing.

End of R/W command of RAM

Note:The assignment of address for context table RAM is as follows.

Internal context mode:Address 0 to 1023 of (LSB:0, MSB:9) as shown below.
External context mode:Address 0 to 4095 of (LSB:CX0, MSB:CS11)

3-line template 2-line template

SYS_REG:

CMD_REG:

CMD_REG:

876

54329

?01

01

– – – – C – – 0

0 0 0 0 0 1 0 0

0 0 0 0 0 0 0 0

54329

8

7

;H/Wreset bit OFF
;C=Context mode set

;Start of R/W context table RAM

;End of R/W command of RAM

This does not end automatically.
Be sure to write the end of R/W command.

?6

(AT pixel is MSB:9)

MITSUBISHI ICs (LSI)

(5) Overall sequence of multi-stripe coding/decoding

The image whose 1page is composed of multiple stripes must perform (2) or (3) by stripes after the initialization of (1).

(Note1) When 16 bit bus is used for the host-bus during coding , in
multi-stripe
coding/decoding

Internal memory & context
table RAM are initialized.
(1) processing

Coding/decoding of 1st stripe

(2) or (3) processing

order to use the word boundary, he pad byte ("00") 1byte long tends

to follow behind the end marker code of each stripe.This must be

eliminated externally.

(Note2) When starting decoding of each stripe (during decoding),

inputting must start from the leading coded data of SDE (Stripe data

entity). If necessary, the leading 1 byte is discarded. (In case when

the leading portion of coded data of the next stripe is already

inputted in LSI (FIFO) or when it is not lined up with the lead

boundary during decoding of each stripe ends,external management

is needed.

M65761FP

QM-CODER

This routine is repeated(Number of stripes -1)

All stripes
process ended?

N

Is the previous
stripe SDNORM?

(SDNORM)

Y

Stripe coding/decoding
(Line memory initialization

prohibited:Li=1,AT pixel=
the value of previous stripe

[(2)or (3) is processed]

Y

End of page

N (SDRST)

Initialization of internal
line memory and Context table
RAM

(1) processing

stripe coding/decoding
process (line memory
initialization is specified
by Li=0, AT pixel =default
position(0)

[ (2) or (3) is processed]

(Note3) Management of marker codes (AT MOVE,
NEWLEN, etc) processing (Insertion at the time of coding
and detection/removing at the time of decoding) should be
done externally.

(Description)
If the end marker of the stripe one before is SDNORM,
do not initialize the line memory nor the Context table
RAM. The AT pixel position will use the last value of
the previous stripe and starts processing next stripe.
In case of SDRST,initialization takes place first and
then the AT pixel position is returned to the default
position. Then the processing of the next stripe begins.

MITSUBISHI ICs (LSI)

M65761FP

12. ABSOLUTE MAXIMUMRATINGS(Ta=–20 to +70°C unless otherwise noted)

Symbol Parameter Conditions Ratings Unit

V

CC

Supply voltage

-0.3 to +7.0

QM-CODER

V

VI

VO

Tstg

Pd

Note : All of the voltage is reference the GND terminal of the circuit .

Maximum value and minimum value are expression of absolute value.

Input voltage

Output voltage

Storage temperature

Power dissipation

Ta=25°C
When single IC is used

13. RECOMMEND O PERATING CONDITIONS

Symbol

VCC

GND

VI

Supply voltage

GND voltage

Input voltage

Parameter

Test conditions

-0.3 to VCC+0.3

0 to VCC

-65 to +150

1380

Limits

Min Typ Max

5.55.04.5

0

V

CC0

V

V

°C

mW

Unit

V

V

V

T

CL

opr

Operating temperature range

Output capacitance(against IC)

50

+70-20

°C

pF

14. ELECTRICAL CHARACTERISTICS(Ta=-20 to +70°C, VCC=5V±10% unless otherwise noted)

MITSUBISHI ICs (LSI)

M65761FP

QM-CODER

Symbol

VIH

VIL
VIH

VIL

VT+

VT-

VH
VOH

VOL
VOH

VOL
VOH

VOL

Parameter

"H"input voltage

"L"input voltage
"H"input voltage

"L"input voltage

Positive
threshold voltage

Negative
threshold voltage

Hysteresis width
"H"output voltage

"L"output voltage
"H"output voltage

"L"output voltage
"H"output voltage

"L"output voltage

PD<31:0>,A<3:0>,
D<15:0>,SVID,
BUS16,CS,BHE

MCLK,PXCK

PDRD,DMAAK,
PDAK,PTIM
XWAIT,PDWR,
TEST1,TEST0,
RD,WR,RESET

D<15:0>

XCLK,PXCKO

PD<31:0>,INTR,
DMARQ,PDRQ,
PRDY,RVID

Test conditions

IOH=-8mA

OH=8mA

I

OH=-4mA

I

OH=4mA

I
IOH=-2mA

OH=2mA

I

Limits

Min Typ Max

2.0

4.5

0.6

0.2

CC-0.8

V

V

CC-0.8

VCC-0.8

0.8

0.0

2.4

0.55

0.55

0.55

Unit

V

V
V

V

V

V

V
V

V
V

V
V

V

IIH

IIL

IOZH

"H"Input current

"L"Input current

"H"output current
in OFF state

A<3:0>,
D<15:0>,RD,WR,
MCLK,BHE,
RESET,CS

D<15:0>

"L"output current

IOZL

in OFF state
Pull up Resister VCC=5.5V, VI=0V

RU

PD<31:0>,PDRD,
PDWR,PDAK,
SVID,PTIM,
PXCK,XWAIT,
BUS16,DMAAK

RD

Dynamic consumption VCC=5.5V, VI=VCC, GND

ICCA

∗ The value of register is 50kΩ buffer's value.

VCC=5.5V, VI=5.5V

V

CC=5.5V, VI=0V

VCC=5.5V, VI=5.5V

V

CC=5.5V, VI=0V

VCC=5.5V, VI=5VPull down Resister TEST1,TEST0

-1.0

1.0

-5.0

5.0

25∗ 100∗

21∗ 100∗

100

µA

µA

µA

µA

kΩ

kΩ

mA

15. TIMING CHARACTERISTICS(Ta=-20 to +70°C, VCC=5V±10% unless otherwise noted)

1) Host Bus I/F

Symbol Parameter

tPZL
(RD-D0 to 15)

PZH

t
(RD-D0 to 15)

tPLZ
(RD-D0 to 15)

PHZ

t
(RD-D0 to 15)

PHL

t
(DMAAK-DMARQ)

D0 to 15 output define time
for RD assert

D0 to 15 output hold time for RD assert

DMARQ negate time for DMAAK assert

Test
conditions

CL=50pF 0

Min Typ Max

0

0

0

Limits

MITSUBISHI ICs (LSI)

M65761FP

QM-CODER

ns

ns

ns

ns

ns

Test
circuit

1

Unit

30

30

30

30

20

2) Image data I/F

Symbol Parameter

tPLH
(PTIM-PRDY)

tPHL
(PXCK-RVID)

tPLH
(PXCK-RVID)

tPHL
(PXCK-PXCKO)

tPLH
(PXCK-PXCKO)

tPHL
(PXCKO-RVID)

tPLH
(PXCKO-RVID)

tPLH
(PTIM-RVID)

tPHL
(PDAK-PDRQ)

tPZL
(PDRD-PD0 to 31)

tPZH
(PDRD-PD0 to 31)

tPLZ
(PDRD-PD0 to 31)

tPHZ
(PDRD-PD0 to 31)

PRDY negate time for PTIM assert

RVID output define time
for the fall of PXCK

PXCKO delay time for PXCK

RVID output define time
for the fall of PXCKO

RVID negate time for PTIM negate

PDRQ negate time for PDAK assert

PD0 to 31 output define time
for PDRD assert

PD0 to 31 hold time for PDRD negate

Test
conditions

CL=50pF

Limits

Min Typ Max

30 ns

25 ns

25 ns

15 ns

15 ns

10 ns

10 ns

0ns

20 ns

0

0

0

0

30

30

30

30

Unit

Test
circuit

1

ns

ns

ns

ns

3) Context I/F

Symbol Parameter

tPLH
(XTIM-XRDY)

tPLH
(XCLK-RPIX)

tPHL
(XCLK-RPIX)

tPLH
(MCLK-XCLK)

tPHL
(MCLK-XCLK)

XRDY negate time for XTIM assert time

RPIX output define time
for the fall of XCLK

XCLK delay time for MCLK

Test
conditions

CL=50pF

MITSUBISHI ICs (LSI)

Limits

Min Typ Max

30 ns

0

30 ns

30 ns

30 ns

30 ns

M65761FP

QM-CODER

Unit

Test
circuit

10

16. TIMING CHARACTERISTICS(Ta=-20 to +70°C, VCC=5V±10% unless otherwise noted)

1) Host Bus I/F

Symbol Parameter

t

w(RESET) RESET assert time

Test
conditions

Min Typ Max

100 ns

Limits

MITSUBISHI ICs (LSI)

M65761FP

QM-CODER

Unit

Test
circuit

th(RD-CS)

tsu(RD-A0 to 3)

tsu(RD-BHE)

tw(RD)

th(RD-A0 to 3)

th(RD-BHE)

tsu(WR-CS)

th(WR-CS)

tsu(WR-A0 to 3)

tsu(WR-BHE)

CS set up time for RD asserttsu(RD-CS)

CS hold time for RD negate

A0 to 3 set up time for RD assert

BHE set up time for RD assert

RD assert time

A0 to 3 hold time for RDnegate

BHE hold time for RD negate

CS set up time for WR assert

CS hold time for WR negate

A0 to 3 set up time for WR assert

A0 to 3 set up time for WR assert

C

L=50pF

20 ns

20 ns

20 ns

20 ns

30 ns

20 ns

20 ns

20 ns

20 ns

20 ns

20 ns

1

tw(WR)

th(WR-A0 to 3)

th(WR-BHE)

tsu(WR-D0 to 15)

th(WR-D0 to 15)

tsu(RD-DMAAK)

th(RD-DMAAK)

tsu(WR-DMAAK)

th(WR-DMAAK)

WR assert time

A0 to 3 hold time for WR negate

BHE hold time for WR negate

D0 to 15 input set up time for WR negate

D0 to 15 input hold time for WR negate

DMAAK set up time for RD assert

DMAAK hold time for RD negate

DMAAK set up time for WR assert

DMAAK hold time for WR negate

30 ns

20 ns

20 ns

20 ns

20 ns

20 ns

20 ns

20 ns

20 ns

2) Image Data I/F

Symbol Parameter

Test
conditions

MITSUBISHI ICs (LSI)

Limits

Min Typ Max

M65761FP

QM-CODER

Unit

Test
circuit

t

ci(MCLK)

twi+(MCLK)

twi-(MCLK)

tri(MCLK)

tfi(MCLK)

tsu(PXCK-PTIM)

th(PXCK-PTIM)

tw+(PXCK)

tw-(PXCK)

tc(PXCK)

tsu(PXCK-SVID)

MCLK period(Mx)
when used image data I/F

MCLK high level time(Mh)
when used image data I/F

MCLK low level time(Ml)
when used image data I/F

MCLK rising time
when used image data I/F

MCLK falling time
when used image data I/F

PTIM set up time for the fall of PXCK

PTIM hold time for the rise of PXCK

PXCK high time

PXCK low time

PXCK period

SVID set up time for the fall of PXCK

CL=50pF

50 ns

20 ns

20 ns

20 ns

20 ns

20 ns

20 ns

20 ns

20 ns

50 ns

1

10 ns

th(PXCK-SVID)

tsu(PDRD-PDAK)

th(PDRD-PDAK)

tw(PDRD)

tsu(PDWR-PDAK)

th(PDWR-PDAK)

tw(PDWR)

tsu(PDWR-PD0 to 31)

th(PDWR-PD0 to 31)

SVID set up time for the fall of PXCK

PDAK set up time for PDRD assert

PDAK hold time for PDRD negate

PDRD assert time

PDAK set up time for PDWR assert

PDAK hold time for PDWR negate

PDWR assert time

PD0 to 31 input set up time
for PDWR negate

PD0 to 31 input hold time
for PDWR negate

10 ns

20 ns

20 ns

30 ns

20 ns

20 ns

20 ns

20 ns

20 ns

3) Context I/F

Symbol Parameter

Test
conditions

MITSUBISHI ICs (LSI)

Limits

Min Typ Max

M65761FP

QM-CODER

Unit

Test
circuit

t

cc(MCLK)

twc+(MCLK)

twc-(MCLK)

trc(MCLK)

tfc(MCLK)

tsu(MCLK-XTIM)

th(XCLK-XTIM)

tw+(XCLK)

tw-(XCLK)

tc(XCLK)

th(XCLK-XWAIT)

tsul(XCLK-CX0 to 11)

MCLK period(Mx)
when used context I/F

MCLK high level time(Mh)
when used context I/F

MCLK low level time(Ml)
when used context I/F

MCLK rising time
when used context I/F

MCLK falling time
when used context I/F

XTIM assert time for the rise of MCLK

XTIM negate time for the rise of XCLK

XCLK high time

XCLK low time

XCLK period

XWAIT negate time for the rise of XCLK

CX0 to 11 set up time
for the rise of XCLK

CL=50pF

100 ns

40 ns

40 ns

20 ns

20 ns

20 ns

20 ns

Mh ns

Ml ns

Mx ns

0ns

20

10

1

ns

tsul(XCLK-PEUPE)

tsul(XCLK-SPIX)

thl(XCLK-CX0 to 11)

thl(XCLK-PEUPE)

thl(XCLK-SPIX)

tsut(XCLK-CX0 to 11)

tsut(XCLK-SPIX)

tht(XCLK-CX0 to 11)

tht(XCLK-SPIX)

tk(XCLK-PEUPE)

PEUPE set up time for the rise of XCLK

SPIX set up time for the rise of XCLK

CX0 to 11 hold time for the rise of XCLK

PEUPE hold time for the rise of XCLK

SPIX hold time for the rise of XCLK

CX0 to 11 set up time
for the rise of XCLK

SPIX set up time for the rise of XCLK

CX0 to 11 hold time for the rise of XCLK

SPIX hold time for the rise of XCLK

PEUPE input define time
for the rise of XCLK

20 ns

20 ns

20 ns

20 ns

20 ns

70 ns

70 ns

20 ns

20 ns

20

ns

17. TEST CIRCUIT

G

O

S

SW2CLG

)

(MCLK)

(MCLK)

(MCLK)

(MCLK)

1

MITSUBISHI ICs (LSI)

M65761FP

QM-CODER

P

Parameter

tPLH, tPHL

tPLZ

Input

50Ω

SW1 SW2

Open
Close

Open
Open

VCC

DUT

ND

utput V CC

RL=1kΩ

W1

R

L=1kΩ

(1) characteristic of pulse generation (PG) (10% to 90%)

t

r=3ns, tf=3ns

Master clock

MCLK

tPHZ
tPZL

tPZH

Open
Close
Open

t

wi+

twc+(MCLK)

Close
Open
Close

ci

t
tcc(MCLK)

(2) Capacitance CL includes stray wiring capacitance

and probe input capacitance.

t

fi

t

wi-

twc-(MCLK)

tfc(MCLK)

90% 90%

10% 10%

tri(MCLK
trc(MCLK)

HOST BUS I/F

(RD)

(WR)

CS

(RD)

(WR)

Q

(1) MPU access

MITSUBISHI ICs (LSI)

M65761FP

QM-CODER

RESET

A0 to 3

BHE

RD

WR

D0 to 15

D0 to 15

t

w

(RESET)

su

t
(RD-CS)

su

t
(RD-A0 to 3)

tsu
(RD-BHE)

PZL

t
(RD-D0 to 15)

t

PZH

(RD-D0 to 15)

t

h

(RD-CS)

t

w

h

t
(RD-A0 to 3)

t

h

(RD-BHE)

PLZ

t
(RD-D0 to 15)

su

t
(WR-A0 to 3)

t

su

(WR-BHE)

50%

10%

t

PHZ

90%

(RD-D0 to 15)

t

su

(WR-CS)

t

tsu
(WR-D0 to 15)

w

50%

h

t
(WR-A0 to 3)

t

h

(WR-BHE)

Input

t

h

(WR-CS)

t

h

(WR-D0 to 15)

(2) DMA access

DMAR

DMAAK

RD

WR

D0 to 15

D0 to 15

su

t
(RD-DMAAK)

PZL

t
(RD-D0 to 15)

PZH

t
(RD-D0 to 15)

50%

PHL

t
(DMAAK-DMARQ)

t

w

50%

90%

50%

th
(RD-DMAAK)

PLZ

t
(RD-D0 to 15)

10%

PHZ

t
(RD-D0 to 15)

tsu
(WR-DMAAK)

t

w

su

t
(WR-D0 to 15)

th
(WR-DMAAK)

th
(WR-D0 to 15)

Input

IMAGE DATA I/F

(PXCK)

)

)

(PXC

O)

)

)

)

CKO

S

Q

)

(

)

(1) Serial image data I/F

MITSUBISHI ICs (LSI)

M65761FP

QM-CODER

PRDY

PXCK

PX

PTIM

PVID

su

t
(PXCK-PTIM)

tPHL
(PXCK-RXCKO)

tPHL (PXCKO-RVID
tPHL (PXCK-RVID

t

su

(PXCK-SVID)

50%

PLH

t
(PTIM-PRDY)

tw+(PXCK

PLH

t

50% 50%

t

h

(PXCK-SVID)

t

c

K-RXCK
tPLH (PXCKO-RVID

PLH

t
(PXCK-RVID)

tw-(PXCK

th
(PXCK-PTIM)

t

PLH

(PTIM-RVID)

50%

VID

(2) Pallarell Image Data

PDR

PDAK

tsu
(PDRD-PDAK) tw(PDRD

PDRD

PDWR

PD0 to 31

t

PZL

(PDRD-PD0 to 31)

50%

tPHL
(PDAK-PDRQ)

50%

th
(PDRD-PDAK)

t

su

(PDWR-PDAK)

PLZ

t
(PDRD-PD0 to 31)

10%

w

PDWR

t

t

su

(PDWR-PD0 to 31)

th
(PDWR-PDAK)

t

h

(PDWR-PD0 to 31)

t

PZH

(PDRD-PD0 to 31)

50%

90%

t

PHZ

(PDRD-PD0 to 31)

Input

CONTEXT I/F

C

C

S

(XCLK)

(1) Latch input mode

MITSUBISHI ICs (LSI)

M65761FP

QM-CODER

XRDY

XTIM

M

LK

XWAIT

XCLK

50%

PLH

t
(XTIM-XRDY)

t

su

(MCLK-XTIM)

tw-
(XCLK)

w+

t
(XCLK)

PHL

t
(MCLK-XCLK)

c

t

t

PLH

(MCLK-XCLK)

t

h

(XCLK-XWAIT)

h

t
(XCLK-XTIM)

X0 to 11

PEUPE

PIX

RPIX

sul

t
(XCLK-CX0 to 11)

t

sul

(XCLK-PEUPE)
t

sul

(XCLK-SPIX)

t

hl

(XCLK-CX0 to 11)
t

hl

(XCLK-PEUPE)
t

hl

(XCLK-SPIX)

tPHL
(XCLK-SPIX)

50%

PLH

t
(XCLK-SPIX)

50%

(2) Through input mode

(XCLK)

C

C

C

S

MITSUBISHI ICs (LSI)

M65761FP

QM-CODER

XRDY

XTIM

M

LK

XWAIT

X

LK

50%

t

PLH

(XTIM-XRDY)

su

t
(MCLK-XTIM)

tw-
(XCLK)

PHL

t
(MCLK-XCLK)

t

c

t

w+

(XCLK)

t

PLH

(MCLK-XCLK)

h

t
(XCLK-XWAIT)

t

h

(XCLK-XTIM)

X0 to 11

PIX

PEUPE

RPIX

sut

t
(XCLK-CX0 to 11)

t

sut

(XCLK-SPIX)

ht

t
(XCLK-CX0 to 11)

ht

t
(XCLK-SPIX)

k

t
(XCLK-PEUPE)

t

PLH

(XCLK-RPIX)

50%

PHL

t
(XCLK-RPIX)

50%