Page 1
×
×
∗
∗
MITSUBISHI ICs (TV)
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
DESCRIPTION
The M65667FP is a NTSC PIP (Picture in Picture) signal
processing LSI, whose sub and main-picture inputs are composite
and Y/C separated signals, respectively. The built-in field memory
(96k-bit RAM) ,V-chip data slicer and analog circuitries lead the PIP
system low cost and small size.
FEATURES
•
Built-in 96k-bit field memory (sub-picture data storage)
•
Internal V-chip data slicer (for sub-picture)
•
Vertical filter for sub-picture (Y signal )
•
Single sub-picture (selectable picture size : 1/9 , 1/16)
•
Sub-picture processing sepecification (1/9 size / 1/16 size) :
Quantization bits Y, B-Y, R-Y : 6bits
Horizontal sampling 171 pixels (Y) , 28.5 pixels (B-Y, R-Y)
Vertical lines 69/ 52 lines
•
Frame (sub-picture) on/off
•
Built-in analog circuits :
Two 8-bit A/D converters (main and sub-picture signals)
Two 8-bit D/A converters (Y and C sub-picture signals)
Sync-tip-clump, VCXO, Analog switch ... etc.
2
I
C BUS control (parallel/serial control) :
•
PIP on/off , Sub-picture size(1/9 or 1/16), Frame on/off
(programmable luma level), PIP position (4 corners fixed
position), Picture freeze , Y delay adjustment, Chroma level, Tint,
Black level, Contrast ... etc.
M65667FP
PICTURE-IN-PICTURE SIGNAL PROCESSING
APPLICATION
NTSC color TV
RECOMMENDED OPERATING CONDITION
Supply voltage range........................................................3.1 to 3.5V
Operating frequency.........................................................14.32 MHz
Operating temperature....................................................-20 to 75 ° C
Input voltage (CMOS interface)"H"........................V
"L".............................0 to V
Output current (output buffer)........................................ ± 4mA (MAX)
Output load capacitance............................................20pF (MAX)
Circuit current.........................................................................160mA
NOTICE: Connect a 0.1 µ F or larger capacitor between V
pins.
1 : Include pin capacitance (7pF)
DD
0.7 to V
DD
DD
and V
DD
0.3V
SS
V
1
PIN CONFIGURATION (TOP VIEW)
C-PIP
48
NC
49
50
TEST8
51
Y-PIP
TEST9
52
53
Yin
Cin
(VCXO)
FILTER
BIAS
(VCXO)
54
55
56
57
58
59
60
61
62
63
64
1
Vin (m)
TESTEN
AVss (ana)
AVss3
VCXO out
VCXO in
AVdd3
AVdd2 (m)
AVdd2 (m)
AVdd4 (da)
47
2
Vrt (m)
AVdd4 (da)
AVdd4 (da)
46
454443
3
4
Vrb (m)
AVss2 (m)
(da)
C-PIPin
AVss4
AVss4 (da)
42
M65667FP
5
6
7
AVdd1 (s)
AVdd1 (s)
AVss2 (m)
Outline 64P6N-A
Y-PIPin
ADJ-Ysub
41
403938
8
9
Vrt (s)
Vin (s)
Yout-sub
ADJ-Csub
101112
Vrb (s)
AVss1 (s)
Cout-sub
DVss3
37
363534
131415
RESET
AVss1 (s)
DVdd3
LOCK/TEST7
DVss1
DVdd1
NC
33
NC
32
VD/CSYNC/TEST6
31
HD/TEST5
30
29
SWM/TEST4
MCK
28
27
fsc/TEST3
26
BGP (m)/TEST2
25
DVdd2 (ram)
DVss2 (ram)
24
23
CLK
22
DATA
21
ACK
20
CSYNC (s)/TEST1
19
SCK
18
BGP (s)/TEST0
17
NC
16
NC
NC : NO CONNECTION
1
Page 2
MITSUBISHI ICs (TV)
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
BLOCK DIAGRAM
Yin
Sync tip
Cin
Vdd / Vss
for test
DATA
CLK
ACK
Vin(s)
Vrt(m)
Vrb(m)
ADJ-Ysub
Yout-sub
Cout-sub
ADJ-Csub
Vin(m)
Vrt(m)
Vrb(m)
15
3
3
2
HD
2
Clamp
Sync tip
Clamp
D/A
8bit
D/A
8bit
Bias
I2C
I/F
Bias
A/D
8bit
2
C )
( I
A/D
8bit
HPLL
SCK
V-chip
data slicer
Y/C SEP
(LPF,BPF)
Phase
Select
4fsc
Delay
fsc
Encode
Burst Data
Sampling
Y
Level
Detect
CSYNC(s)
/TEST1
C
Delay
Luma
Clamp
Sync
Sep
Demod
MIX
M65667FP
PICTURE-IN-PICTURE SIGNAL PROCESSING
BGP(s)
/TEST0
RAM(1H)
Bias
C
Y6
Timing Gen
(Decode)
B-Y
R-Y
6Y
B-Y
6
R-Y
6
6
6
VCXO
Driver
Demux
Vert-filter
&
MUX
Y
B-Y
R-Y
RAM
96Kbits
Back Porch
Clamp
Timing Gen
(Memory
Cont)
4fsc
VCXO
Delay
AFC
Tint
Delay
LPF
&MPY
Phase
Detect
Lock/Free-run
via I
2
Y- PIP
C- PIP
C- PIPin
Y- PIPin
SWMG
/TEST7
VD
/CSYNC
/TEST6
HD
/TEST5
FILTER
BIAS
VCXO in
VCXO out
RESET
MCK
BGP(m)
/TEST2
fsc
/TEST3
SWM
/TEST4
2
Page 3
MITSUBISHI ICs (TV)
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
PICTURE-IN-PICTURE SIGNAL PROCESSING
M65667FP
DESCRIPTION OF PIN
Pin No. Name I/O Function Remarks
1 Vin (m) I Chroma signal input (main-picture)
2 Vrt (m) O A/D Vref+ (main-picture)
3 Vrb (m) O A/D Vref- (main-picture)
4 AVss2 (m) GND Connect to analog GND
5 AVss2 (m) GND Connect to analog GND
6 AVdd1 (s) Vdd Connect to analog power supply
7 AVdd1 (s) Vdd Connect to analog power supply
8 Vin (s) I Composite video signal input (sub-picture)
9 Vrt (s) O A/D Vref+ (sub-picture)
10 Vrb (s) O A/D Vref- (sub-picture)
11 AVss1 (s) GND Connect to analog GND
12 AVss1 (s) GND Connect to analog GND
13 RESET I Power on reset input signal ("L" reset)
14 DVss1 GND Connect to digital GND
15 DVdd1 Vdd Connect to digital power supply
16 NC
17 NC
18
BGP(s)/TEST0
(I/)O For test non connect
19 SCK I For test (connect to digital GND) connect to GND
20
21 ACK O
22 DATA I
23 CLK I
CSYNC(s)/TEST1
I(/O) For test (connect to digital GND) pull down 15k Ω
2
I
C bus-data/Acknowledge output signal
2
I
C bus-data input signal
2
I
C bus-clock input signal
24 DVss2(ram) GND Connect to digital GND
25 DVdd2(ram) Vdd Connect to digital power supply
26
BGP(m)/TEST2
(I/)O For test non connect
27 fsc/TEST3 I(/O) For test (pull down to digital GND by resistor 15k Ω ) pull down 15k Ω
28 MCK I For test (connect to digital GND) connect to GND
29 SWM/TEST4 (I/)O For test non connect
30 HD/TEST5 I(/O) Horizontal sync input signal (Positive going edge is used)
31
VD/CSYNC
/TEST6
I(/O) Vertical sync input signal (active "H")
32 NC
33 NC
34
SWMG/TEST7
I(/O) Enable input signal to display sub picture ("H" enable) pull up 15k Ω
35 DVdd3 Vdd Connect to digital power supply
36 DVss3 GND Connect to digital GND
37 Cout-sub O D/A output signal (Chroma signal of sub-picture)
38 ADJ-Csub I D/A adjust for chroma signal (sub-picture)
39 Yout-sub O D/A output signal (Luma signal of sub-picture)
40 ADJ-Ysub I D/A adjust for luma signal (sub-picture)
41 Y-PIPin I PIP luma signal re-input
42 AVss4 (da) GND Connects to analog GND
43 AVss4 (da) GND Connects to analog GND
44 C-PIPin I PIP chroma signal re-input
45 AVdd4 (da) Vdd Connect to analog power supply
46 AVdd4 (da) Vdd Connect to analog power supply
47 AVdd4 (da) Vdd Connect to analog power supply
48 C-PIP O PIP chroma signal output
49 NC
50 TEST8 I For test (connect to analog GND) pull up 15k Ω
51 Y-PIP O PIP luma signal output
52 TEST9 I For test (connect to analog GND) connect to GND
100k Ω to V
,10 µ F to GND
DD
3
Page 4
∗
( ∗
−
MITSUBISHI ICs (TV)
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
DESCRIPTION OF PIN
(cont.)
PICTURE-IN-PICTURE SIGNAL PROCESSING
M65667FP
Pin No. Name I/O Function Remarks
53 Yin I Luma input signal (main-picture)
54 TESTEN I For test (connect to analog GND) connect to GND
55 Cin I Chroma input signal (main-picture)
56 AVss (ana) GND Connect to analog GND
57 AVss3
(VCXO)
GND Connects to analog GND
58 VCXO out O VCXO output signal
59 VCXO in I VCXO input signal
60 FILTER I Filter
61 BIAS O Bias
62 AVdd3
(VCXO)
Vdd Connect to analog power supply
63 AVdd2 (m) Vdd Connect to analog power supply
64 AVdd2 (m) Vdd Connect to analog power supply
SS
(V
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter
V
DD3
V
I
V
O
O
I
P
d
T
opr
T
stg
1: Output current per output terminal. But P
Supply voltage (3.3V) -0.3 4.6 V
Input voltage -0.3
Output voltage -0.3
Output current
1)
Power dissipation
Operating temperature -20 75 ° C
Storage temperature -50 125 ° C
d
=0V)
limits all current.
Limits
Min. Max.
DD3
V
+0.3
DD3
V
+0.3
−
I
=20
OL
I
=-26
OH
−
1400 mW
Unit
V
V
mA
4
Page 5
−
−
MITSUBISHI ICs (TV)
−
−
−
|
−
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
DC CHARACTERISTICS
(Ta=25 ° C, unless otherwise noted, V
Symbol Parameter Test conditions
V
IL
V
IH
V
-
T
V
+ + 1.4
T
V
H
OL
V
OH
V
OL
I
OH
I
IH
I
IL
I
IOZL
IOZH HVDD=3.6V, VO=3.6V -1 − 1 µA
Input voltage
(CMOS interface)
Input voltage schmitt trigger
(CMOS interface)
Output voltage
Output current
Input current
Output leakage current
LV
HV
=2.7V 0
DD
=3.6V 2.52
DD
–
V
=3.3V
DD
Hysteresis
L
H 3.25
LV
HV
LV
HV
DD
V
DD
DD
DD
DD
=3.3V, | I
=3.0V , V
=3.0V , V
=3.6V , V
=3.6V , V
LVDD=3.6V , V O=0V -1 − 1 µA
CI Input pin capacitance
CO Output pin capacitance − 7 15 pF
f=1MHz, VDD=0V
PICTURE-IN-PICTURE SIGNAL PROCESSING
SS
=0V)
O
<1 µ A
OL
=0.4V 4
OH
=2.6V
I
=0V -1
I
=3.6V -1
M65667FP
Limits
Min. Typ. Max.
0.81 V
3.6 V
0.5
0.3
−−
−−
− 7 15 pF
1.65 V
2.4 V
1.2 V
0.05 V
−−
−−
-4 mA
1 µ A
− 1 µA
CIO Bidirectional pin capacitance − 7 15 pF
IDD Operating current
3.3V supply
−− 140 mA
Unit
V
mA
TYPICAL CHARACTERISTICS
THERMAL DERATING (MAXIMUM RATING)
2000
1600
1280
1200
800
400
POWER DISSIPATION Pd (mW)
0
0 25 75 125
AMBIENT TEMPERATURE Ta (°C)
50
100
5
Page 6
MITSUBISHI ICs (TV)
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
APPLICATION EXAMPLE
Ana.
PIP Luma signal output
Luma signal input
(main-picture)
Chroma input signal
(main-picture)
330104
103
10µ
Ana.
3.3µ
103
2k
51
100k
104
104
14p
470k
15k
PICTURE-IN-PICTURE SIGNAL PROCESSING
Ana.
68p
Ana.
PIP Chroma signal output
10µ
103
104 103
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
12345678910111213141516
Ana.
150p
103
104
M65667FP
470
360
Sub-picture displaying on/off
Dig
10µ
103
Vertical sync input signal (main-picture)
32
31
30
29
28
15k
27
26
25
24
103
23
22
21
20
19
18
17
M65667FP
Horizontal sync input signal (main-picture)
C BUS Clock
2
I
100
10k
100
560
input signal
SCL
SDA
100
10µ
Dig
Dig5V
Dig5V
10k
12k
47k
12k
47k
330
C BUS DATA
2
I
input /output signal
104
103
Ana.
Digital +3.3V
power supply
Digital GND
Analog +3.3V
power supply
Analog GND
Ana.
103
10µ
103
Ana.
SYNC SEP
103103
10µ
103
104
CIRCUIT
Composite video
input signal
(sub-picture)
(OPTIONAL)
Separate Y/C signals by using LC-tank circuit or LPF,BPF for Y/C signals level adjust.
And then mix both signals for sub-picture input video signal.
100k
10µ
Dig
Units Resistance : Ω
Capacitance : F
6
Page 7
MITSUBISHI ICs (TV)
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
PIP TV SYSTEM BLOCK DIAGRAM
(BASIC)
Composite
Video Signal
Y/C Separated
Video Signal
Y/C
Separation
Y
C
Y
C
Y
C
CV
M65667FP
PICTURE-IN-PICTURE SIGNAL PROCESSING
M65667FP
BLPLL
B-LD
PIP Signal
Processing
Y
C
Y
C
Video
Signal
Processing
Deflection
Unit
HD VD
Yoke
(Driving Method and Operating Specification for
Serial Interface Data)
(1) Serial data transmission completion and start
A low-to-high transition of the DATA (serial data) line while the CLK
(serial clock) is high, that completes the serial transmission and
makes the bus free.
A high-to-low transition of the DATA line while the CLK is high, that
starts the serial transmission and waits for the following CLK and
DATA inputs.
(2) Serial data transmission
The data are transmitted in the most significant bit (MSB) first by
one-byte unit on the DATA line successively. One-byte data
transmission is completed by 9 clock cycles, the f ormer 8 cycles are
for address/data and the latter one is for acknowledge detection. (In
reading state, ACK is 'H' under these two conditions ; 1) the
coincidence of two address data for the address data transmission,
2) the completion of 8-bit setting data transfer. In writing state, ACK
is 'H' with the address coincidence and ACK is 'L' for detecting
acknowledge input from the master (micro processor) after sending
8-bit setting data.)
For address/data transmission, DATA must change while CLK is 'L'.
(The data change while CLK is 'H' or the simultaneous change of
CLK and DATA, that will be a false operation because of
undistinguished condition from the completion/start of serial data
transfer).
After the beginning of serial data transmission, the total number of
data bytes that can be transferred are not limited.
(3) The byte format of data transmission (The sequence of data
transmission)
1. The byte format during data setting to M65667FP are shown as
follows.
In right after the forming of serial data transmitting state, the slave
address 24h (00100100b) is transferred. Afterwards, the internal
register address (1 byte) and setting data (by 1 byte unit) are
transferred successively. Several bytes of setting data can be
handled in the one transmission. In this operation, the setting data
are written into the address register whose address is increased
one in initially transferred internal register address. (The next
address of 7Fh, it returns to 00h).
2. The byte format during data reading from M65667FP are shown
as follows.
Before data reading from M65667FP, whose internal address need
to be set by the data reading/transmitting. After the data reading/
transmitting, the operation of "serial data transmission completion
and start" (described in (1)) is necessar y. Continuously, the slave
address 25h (00100101b) is sent, and then the inverted read out
data are available on ACK. Several bytes of writing data can be
handled in the one transmission, too. In this operation, the setting
data also are written into the address register whose address is
increased one in initially transferred internal register address. (The
next address of 7Fh, it returns to 00h).
7
Page 8
MITSUBISHI ICs (TV)
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
(The examples of serial byte transmission format)
(1) The writing operation of the setting data (AAh) into M65667FP internal address of 00h
Transmission
Activation
Confirmation
of bus free
(DATA='H')
no
is applied
on CLk for the
release of
output state
(2) The writing operation of the setting data (FFh, 80h, EEh) into M65667FP internal address of 04h to 06h
yes
S 24h A 00h A AAh A D E
S : Operation of serial transmission start
A : Acknowledge detection
D : Dummy clock feed for the release of
acknowledge output state
E : Operation of serial transmission completion
PICTURE-IN-PICTURE SIGNAL PROCESSING
M65667FP
Transmission
Activation
Confirmation
of bus free
(DATA='H')
no
is applied
on CLk for the
release of
output state
yes
S 24h A 04h A FFh
(3) The reading operation of the setting data from M65667FP internal address of 00h
Transmission
Activation
Confirmation
of bus free
(DATA='H')
no
is applied
on CLk for the
release of
output state
yes
S 24h A 00h A
A’ : Bus free operation by the
master (micro processor)
DES
A 80h A EEh
25h A $$h
ADE
A’
8
Page 9
MITSUBISHI ICs (TV)
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
(4) The reading operation of the setting data from M65667FP internal address of 04h to 06h
Transmission
Activation
Confirmation
of bus free
(DATA='H')
no
is applied
on CLk for the
release of
output state
yes
S 24h A 04h A
A’’ : Output ‘L’ operation by the
master (micro processor)
TIMING DIAGRAM
123456
PICTURE-IN-PICTURE SIGNAL PROCESSING
DES
25h A SSh
7
891
M65667FP
A’’
A’’
SSh SSh
A’
CLK
DATA
ACK
_ Acknowledge
ACK
_ Readout data
Bit7
(MSB)
Bit7
(MSB)
Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit6 Bit5 Bit4
Bit3 Bit2 Bit1
(LSB)
Bit0
(LSB)
ACK
Detec.
Bit7
(MSB)
Bit7
(MSB)
9
Loading...