Datasheet M59BW102 Datasheet (SGS Thomson Microelectronics)

1 Mbit (64Kb x16, Burst) Low Voltage Flash Memory

■ 2.7 to 3. 6V SUPPLY VOLTAGE f or PROGRAM,

ERASE and READ OPERATIONS

■ SEQUENTIAL CYCLE TIME: 25ns

■ RANDOM ACCESS TIME

■ PROGRAMMING TIME: 10µs typical

■ INTERLEAVED ACCESS TIME: 16ns

■ CONTINUOUS MEMORY INTERLEAVING

– Unlimited Linear Access Data Output

■ PROGRAM/ERASE CONTROLLER (P/E.C.)

– Program Word-by-Word
– Status Register bits

■ LOW POWER CONSUMPTION

– Stand-by and Automatic Stand-by

■ 100,000 PROGRAM/ERASE CYCL ES

■ 20 YEARS DATA RETENTI ON

– Defectivity below 1ppm/year

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h
– Device Code: C1h

DESCRIPTION

The M59BW102 is a non-volatile memory that may
be erased electrically at the chip level and pro­grammed in-system on a Word-by-Word basis us­ing only a single 3V V
Erase operations the necessary high voltages are
generated internally. The de vice can also be pro­grammed in standard programmers.

The device can be programmed and erased over
100,000 cycles.

Instructions for Read/Reset, Auto Select for read­ing the Electronic Signature, Programming and
Chip Erase are written to the device in cycles of
commands to a Command Interface using stan­dard microprocessor write timings. The
M59BW102 features an interleaved access mo­dality which allows extremely fast access time.
The device is offered in TSOP40 (10 x 14mm)
package.

supply. For Program and

CC

TSOP40 (N)

10 x 14mm

Figure 1. Logic Diagram

V

CC

16

A0-A15

W

E

G

ALE

M59BW102

V

SS

M59BW102

PRELIMINARY DATA

16

DQ0-DQ15

AI02763B

March 2000

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

1/24

M59BW102

Figure 2. TSOP Connections

A9
A10
A11
A12
A13
A14
A15

ALE

W

V

CC
NC

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

DQ9
DQ8

1

10

M59BW102

11

E

20 21

AI02764B

40

31
30

V

SS

A8
A7
A6
A5
A4
A3
A2
A1
A0
G
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
V

SS

Organization

The M59BW102 is organized as 64K x16 bits. The
memory uses the addre ss inputs A0-A 15 and the
Data Inputs/Outputs DQ0-DQ15. Memory control
is provided by Chip Enable E
Address Latch Enable ALE and Write Enable W

, Output Enable G,

in-

puts.
Erase and Program operations are controlled by

an internal Program/Erase Controller (P/E.C.).
Status Register data output on DQ7 provides a
Data Polling signal, and DQ6 and DQ2 provide
Toggle signals to indicat e the state of the P/E.C
operations.

Bus Operations

The following operations can be performed using
the appropriate bus cycles: Read (Array, Electron­ic Signature), Write command, Output Disable,
Standby. See Tables 3 and 4.

Table 1. Signal Names

A0-A15 Address Inputs
DQ0-DQ7 Data Inputs/Outputs, Command Inputs
DQ8-DQ15 Data Inputs/Outputs
E
G
W
ALE Address Latch Enable
V

CC

V

SS

NC Not Connected Internally

Chip Enable
Output Enable
Write Enable

Supply Voltage
Ground

Command Interface

Instructions, made up of commands wri tten in cy­cles, can be given to the Program/Erase Controller
through a Command Interface (C.I.). For added
data protection, program or erase execution starts
after 4 or 6 cycles. The first, second, fourth and
fifth cycles are used to input Coded c ycles to the
C.I. This Coded sequence is the same for all Pro­gram/Erase Controller instructions. The ’Com­mand’ itself and its confirmation, when applicable,
are given on the third, fourth or sixt h cycles. Any
incorrect command or any improper command se­quence will reset the device to Read Array mode.

Instructions

Four instructions are de fined to perform Rea d Ar­ray, Auto Select (to read the Electronic Signature),
Program, Chip Erase. The internal P/E.C. auto­matically handles all tim ing and verification of t he
Program and Erase operations. The Status Regis­ter Data Polling, Toggle and Error bits may be read
at any time, during programming or erase, to mon­itor the progress of the operation.

Instructi ons a re co mpose d of up to si x cycles. The
first two cycles input a Coded sequence to the
Command Interface which is common to all in­structions (s ee Tab le 7). The third cycl e i nput s th e
instruction set-up command. Subsequent cycles
output the addressed data or Electronic Signature
for Read operations. In order to give additional
data protection, the instructions for Program and
Chip Erase require further command inputs. For a
Program instruction, the fourth command cycle in­puts the address and data to be programmed. For
an Erase instruction, the fourth and fifth cycles in­put a further Coded sequence before the com­mand confirmatio n on the sixth cycle.

2/24

M59BW102

Table 2. Absolute Maximum Ratings

(1)

Symbol Parameter Value Unit

T

A

T

BIAS

T

STG

(2)

V

IO

V

CC

V

(A9, E, G)

Note: 1. Except for the ratin g "Operati ng Temperature Range" , stresses above those listed i n t he Table "Absolute M aximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indi cated in t he Operating sect i ons of thi s specifi cation i s not impl i ed. Exposure to Absolute M aximum Rating c ondi­tions for extended per iods may aff ect device reliabilit y. Refer also to the STMicroel ectronics SURE Program an d other relevan t qual ­ity docum en ts .

2. Mini m um Voltage may undershoot to –2V duri ng transit i on and for less than 20ns.

Table 3. User Bus Operations

Operation E

Non Linear
Access Mode

Linear Access
Cycle

Write Word
Output Disable
Standby

Note: 1. X = VIL or VIH.

Ambient Operating Temperature

Temperature Under Bias –50 to 125 °C
Storage Temperature –65 to 150 °C

Input or Output Voltage –0.6 to 5 V
Supply Voltage –0.6 to 5 V

(2)

A9, E, G Voltage –0.6 to 13.5 V

(1))

G W ALE A0 A1 A6 A9 A12 A15 DQ15-DQ0

V

V

V
V

V

V

IL

Rising

IL

Edge

V

IL

V

IL

IH

X X X X X X X X X Hi-Z

V

IL

IH

IH

Pulse X X X X X X Data Output

IH

V

V

V

V

IH

IL

IH

IL

V

IH

V

IH

X

A0 A1 A6 A9 A12 A15 Data Input

X X X X X X Hi-Z

X

X X X X Data Output

0 to 70 °C

Table 4. Read Electronic Signature (following AS instruction or with A9 = VID)

Code E

Manufact. Code
Device Code

V

IL

V

IL

G W A0 A1

V

IL

V

IL

V

IH

V

IH

SIGNAL DESCRIPTIONS

See Figure 1 and Table 1.
Address Inputs (A0-A15). The address inputs

for the memory array are latched during a write op­eration on the falling edge of Chip Enable E
Write Enable W

. When A9 is raised to VID, either a

or

Read Electronic Signature Manufacturer or Device
Code is enabled depending on the combination of
levels on A0 and A1.

Data Inputs/Outputs (DQ0-DQ15). The input is
data to be programm ed in the memory array or a
command to be written to the C.I. Both are latched
on the rising edge of Chip Enable E
able W

. The output is data from the Memory Array,

or Write En-

V

IL

V

IH

V

IL

V

IL

the Electronic Signature Manufa cturer or Device
codes, the Status register Data Polling bit DQ7,
the Toggle Bits DQ6 and DQ2, the Error bit DQ5
or the Erase Timer bit DQ3. Outputs are valid
when Chip Enable E
tive. The output is high imped ance when the chip
is deselected or the outputs are disabled.

Chip Enable (E

vates the memory control logic, input buffers, de­coders and sense amplifiers. E
memory and reduces the power consumption to
the standby level. E
writing to the command register and to the memo­ry array, while W

Other

Address

Don't Care 00h 20h
Don't Care 00h C1h

and Output Enable G are ac-

). The Chip Enable input acti-

can also be u sed to control

remains at a low level.

DQ15-DQ8 DQ7-DQ0

High deselects the

3/24

M59BW102

Table 5. Commands

Hex Code Command

00h Invalid/Reserved

10h Chip Erase Confir m

20h Rese r ved

80h Set-up Erase

90h Read Electronic Signature

A0h Program

F0h Read Array/Reset

Output Enable (G

). The Output Enable gates the

outputs through the data buffers during a read op­eration. When G

and ALE are bot h High the ou t-

puts are High impedance.

Write Enable (W

). This input controls writing to

the Command Register and Address and Data
latches.

Address Latch Enable (ALE). This input con­trols the latching of address for reading. When
pulsed, the device operates in the random or non
linear access mode.

Supply Voltage. The power supply for all

V

CC

operations (Read, Program and Erase).

V

Ground. VSS is the reference for all voltage

SS

measurements.

DEVICE OPERATIONS

See Tables 3 and 4.

Read (Non Linear Access Mode and Linear Ac­cess Cycle). The device is internally organized in

two memory banks (named Even and Odd bank).
A0 address bit is asserted as "priority" bit, so that
when A0 = 0 the even bank is the current memory
array under selection and the odd bank is masked.
When A0 = 1 the odd bank is the current array un­der selection and even bank is masked.

To begin a random (or Non Linear) access mode
(NLA), ALE is pulsed high and E

is asser ted low.

Two internal 15 bit counters store the current ad­dress for the odd and e ven banks a nd increment
alternatively, under the priority bit control, during
each subsequent cycle called sequential (or Lin­ear) address cycle (LA). The linear cycle (LA) can
be terminated if a new NLA starts or if E

is assert­ed high, putting the device in stand-by mode. In
this last case the linear cycle can be resumed if E
is asserted low again and ALE is low.

During the LA mode all the memory can be swept,
as there is no phy sical limits to the linear access
output. When the last address of the me mory is

reached by the counters they start again from the
first memory address and continue. The
M59BW102 will provide data output during the LA
cycle determined by G

Each time ALE signal is pulsed and G

signal.

signal is
High, while the current address is loaded into the
counters, the output bu ffers are put in Hi-Z condi­tion and remain in this condit ion until the f irst new
valid data comes. The M59BW102 operation in LA
and NLA modes is explained in Figure 3 and the
block diagram is shown in Figure 4.

Write. Write operations are used to give I nstruc­tion Commands to the memory or to latch input
data to be programmed. A write operation is initi­ated when Address Latch Enable (ALE) is high,
Chip Enable E
with Out p ut E n ab l e G
on the falling edge of W

is Low and Write Enable W is Low

High. Addresses are latched

or E whichever occurs
last. Commands and Input Data are latched on the
rising edge of W

or E whichever occurs first.

Output Disa bl e . The data outputs are high im­pedance when the Output Enable G

and the Ad­dress Latch Enable (ALE) are both High with Write
Enable W

High.

Standby. The mem ory is in standby when C hip
Enable E

is High and the P/E.C. is idle. The power
consumption is reduced to the sta ndby level and
the outputs are high impedanc e, independent of
the Output Enable G
(ALE) or the Write Enable W

, the Address Latch Enable

inputs.

Electronic Signature. Tw o codes identifying the
manufacturer and the device can be read from the
memory. The manufacturer’s code for
STMicroelectronics is 20h, the device code is C1h.
These codes allow programming equipment or ap­plications to automat ically match their interface to
the characteristics of the M59B W102. The Elec­tronic Signature is output by a Read operation
when the voltage applied to A9 is at VID and ad­dress inputs A1 is Low. The manufacturer c ode is
output when the Address input A0 is Low and the
device code when this input is High. Other Ad­dress inputs are ignored. The codes are output on
DQ0-DQ7.

The Electronic Signature can also be read, without
raising A9 to V

, by giving the memory the In-

ID

struction AS. The codes are output on DQ0-DQ7
with DQ8-DQ15 at 00h.

Tabl e 6. Polling and Toggle Bi ts

Mode DQ7 DQ6 DQ2

Program DQ7
Erase 0 T oggle Toggle

Toggle 1

4/24

Figure 3. Non Linear and Linear Access Cycle Timing Diagram

M59BW102

OddEven

ADDR + 1 ADDR + 2

Odd

ADDRESS (Odd)ADDRESS (Even)

ADDR+3

ADDR + 2

RESUME

(LINEAR)

AI02766B

14 14

CLKOUT

ALE

E

G

ADDR + 1 ADDR + 2 ADDR + 3

A0-A15

EvenEven Odd Odd

DQ0-DQ15

ADDRESS (Even) ADDR + 2 ADDR + 4 ADDR + 1

Cntr even

ADDR + 1 ADDR + 3 ADDRESS (Odd)Cntr odd

NON LINEAR LINEAR LINEAR LINEAR NON LINEAR

5/24

M59BW102

Figure 4. Block Diagram

DQ0-DQ15

A1-A15

A0

G

LOGIC

E

ALE

EVEN COUNTER OUTPUT BUFFER ODD COUNTER

MULTIPLEXER

EVEN MATRIX

(16 x 32K)

ODD MATRIX

(16 x 32K)

INSTRUCTIONS AND COMMANDS

The Command Interface latches c ommands writ­ten to the memory. Instructions are made up from
one or more commands to perform Read Memory
Array, Read Electronic Signature, Program, Ch ip
Erase. Commands are made of address and data
sequences. The instructions require from 1 to 6 cy­cles, the first or first three of which are always write
operations used to initiate the instruction. They are
followed by either further write cycles to confirm
the first command or execute the command imme­diately. Command sequencing must be followed
exactly. Any invalid combination of commands will
reset the device to Read Array. The increased
number of cycles has been chosen to assure max­imum data security. Instructions are initialised by
two initial Coded cycles which unlock the Com­mand Interface. In addition, f or Erase, instruction
confirmation is again preceded by the two Co ded
cycles.

Status Register Bits

P/E.C. status is indicated during execution by Data
Polling on D Q7, detection of T oggle on DQ6 and

AI02765

DQ2, or Error on DQ5 and E ras e T imer DQ3 bits.
Any read attempt from any address during Pro­gram or Erase command execution will automati­cally output these five Status Register bits. The P/
E.C. automatically sets bits DQ2, DQ3, DQ5, DQ6
and DQ7. Other bits (DQ0, DQ1 and DQ4) are re­served for future use and should be masked. See
Table 8.

Data Polling Bit (DQ7). When Program ming op­erations are in progress, this bit out puts the com­plement of the bit being programmed on DQ7.
During Erase operation, it outputs a ’0’. After com­pletion of the operation, DQ7 will output the bit last
program me d or a ’1 ’ after er asi ng. Data Pollin g is
valid and only effective during P/E.C. operation,
that is after the fourth W
after the six th W

pulse for erase. See Figure 11 for

pulse for programming or

the Data Polling waveforms and Figure 12 for the
Data Polling flowcha rt. A Valid Address is t he ad­dress being programmed or any address while
erasing the chip.

Toggle Bit (DQ6). When Programming or Eras­ing operations are in progress, successive at­tempts to read DQ6 will output complementary

6/24

M59BW102

Table 7. Instructions

Mne. Instr . Cyc. 1st Cyc. 2nd Cyc. 3r d Cyc. 4th Cyc. 5th Cyc. 6th Cyc. 7th Cyc.

Read/Reset

(2,4)

RD

AS

Note: 1. Commands not interpreted in this table will default to read array mode.

Memor y Array

(4)

Auto Select 3+

PG Program 4

CE Chip Erase 6

2. A wait of 10µs is necessary after a Read/Reset command if the memory was in an Erase or Program mode before starting any new

operation.

3. X = Don't Care.

4. The f i rst cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the com­mand cycl e s.

5. Sig nat ure Addres s bits A0, A1, at V
code.

6. For C oded cycles address inputs A11-A16 are don't care.

7. Rea d Data Polling, Toggle bi ts until Erase comple t es.

(1)

1+

3+

(3,6)

Addr.
Data

(3,6)

Addr.
Data

(3,6)

Addr.
Data

(3,6)

Addr.

Data

(3,6)

Addr.
Data

will output Manufacturer code (20h). Address bits A0 at VIH and A1, at VIL will out put De vice

IL

X

Read Memory Array until a new write cycle is initiated.

F0h

555h 2AAh X

AAh 55h F0h

555h 2AAh 555h

AAh 55h 90h

555h 2AAh 555h

AAh 55h A0h

555h 2AAh 555h 555h 2AAh 555h

AAh 55h 80h AAh 55h 10h

Read Memory Array until a new write
cycle is initiated.

Read Electronic Signature until a new
write cycle is initiated. See Note 5.

Program

Address

Program

Data

Read Data Polling or Toggle
Bit until Program completes.

Note 7

data. DQ6 will toggle following toggling of either G,
or E

when G is low. The operation is completed
when two successive reads yield the same output
data. The next read will output the bit last pro­grammed or a ’1’ after erasing. The toggle bit DQ6
is valid only during P/E.C. op erations, that is after
the fourth W
sixth W

pulse for programming or after the

pulse for Erase. See Figure 13 for Togg le
Bit flowchart and Figure 14 f or Toggle Bit wave­forms .

Toggle Bit (DQ2). This toggle bit, together with
DQ6, can be used to det ermine the d evice status
during the Erase operations. During Chip Erase a
read operation will cause DQ2 to toggle since chip
is being erased. DQ2 will be set to ’1’ during pro­gram operation and when erase is complete.

Error Bit (DQ5). This bit is set to ’1’ by the P/E.C.
when there is a failure of programming or chip
erase that results in invalid data in the memory. In
case of an error in program, the ch ip must b e dis­carded. The DQ5 failure condition will also appear
if a user tries to program a ’1’ to a location that is

previously programmed to ’0’. The error bit resets
after a Read/Reset (RD) instruction. In case of
success of Pr ogram or Eras e, t he er ror b it w ill b e
set to ’0’.

Erase Timer Bit (DQ3). This bi t is s et to ’ 0’ by th e
P/E.C. when the Erase command has been en­tered to the Comm and Interface and it is awaiting
the Erase start. When the erase timeout period is

finished, after 50µs to 120µs, DQ3 returns to '1'.

Coded Cycles

The two Coded cycles unlock the Command Inter­face. They are followed by an input command or a
confirmation command. The Coded cycles consist
of writing the data AAh at address 555h during the
first cycle. During the second cycle the Coded cy­cles consist of writing the data 55h at address
2AAh. Address lines A0 to A10 are valid; other ad­dress lines are 'don't care'. The Coded cycl es hap­pen on first and second cycles of the command
write or on the fourth and fifth cycles.

7/24

M59BW102

Table 8. Status Register Bits

DQ Name L ogic Level Defi nition Note

’1’ Erase Complete

Data

7

Polling

’0’ Erase On-going
DQ Program Complete
DQ

Program On-going

Indicates the P/E.C. status, check during
Program or Erase, and on completion before
checking bits DQ5 for Program or Erase
Success.

’-1-0-1-0-1-0-1-’ Erase or Program On-going Successive reads output complementary

6 Toggle Bit

5 Error Bit

4 Reserved

Erase

3

Time Bit

2 Toggle Bit

1 Reserved
0 Reserved

Note: Logic leve l ’1’ is High, ’0’ is Low. -0-1 -0-0-0-1-1-1-0- represent bit value in successive R ead operations.

Instructions

See Table 7.
Read/Reset (RD) Instruction. The Read/Reset

instruction consists of one write cycle giving the
command F0h. It can be optionally preceded by
the two Coded cycles. Subsequent read opera­tions will r ead the memory array a ddressed and
output the data read. Read/Reset is not accepted
in Program/Erase operation unless a fail occurred.

Auto Select (AS) Instruction. This instruction
uses the two Coded cycles followed by one write
cycle giving the command 90h to address 555h for
command set-up. A subsequent read will output
the manufacturer code and the device code de­pending on the levels of A0 and A1. The manufac­turer code, 20h, is output when the addresses

DQ Program Complete

’-1-1-1-1-1-1-1-’ Erase Complete

’1’ Program or Erase Error

’0’ Program or Erase On-going

’1’ Erase Timeout Period Expired P/E.C. Erase operation has started.

’0’

’-1-0-1-0-1-0-1-’ Chip Erase

’1’

Erase Timeout Period On­going

Program On-going or Erase
Complete

lines A0 and A1 are Low, t he de vice c ode, C1h is
output when A0 is High with A1 Low.

Program (PG) Instruction. This ins truction uses
four write cycles. The Program command A0h is
written to address 555h on the third cycle after two
Coded cycles. A fourth write operation latches the
Address on the falling edge of W
to be written on the rising edge and starts the P/
E.C. Read operations o utput the Status Register
bits after the programming has started. Memory
programming is made only by writing ’0’ in place of
’1’. Status bits DQ6 and DQ7 determine if pro­gramming is on-going and DQ5 allows verification
of any possible error.

Chip Erase (CE) Instructi on. This instruction uses
six write cycles. The Set-up command 80h is writ-

data on DQ6 while Programming or Erase
operations are on-going. DQ6 remains at
constant level when P/E.C. operations are
completed.

This bit is set to ’1’ in the case of
Programming or Erase failure.

Indicates the erase status.

or E and the Data

8/24

M59BW102

Table 9. AC Measurement Conditions

Load Capacitance (CL)
Input Rise and Fall Times ≤ 10ns
Input Pulse Voltages
Input and Output Timing Ref. Voltages 1.5V

30pF

0 to 3V

Figure 6. AC Testing Load Circuit

1.3V

1N914

3.3kΩ

Figure 5. AC Testing Input Output Waveform

DEVICE
UNDER

TEST

3V

1.5V

0V

AI01417

Table 10. Capacitance

Symbol Parameter Test Condition Min Max Unit

C

IN

C

OUT

Note: 1. Sampled only, not 100% tested.

Input Capacitance
Output Capacitance

(1)

(TA = 25 °C, f = 1 MHz)

V

CL includes JIG capacitance

V

= 0V

IN

= 0V

OUT

CL = 30pF

6pF

12 pF

OUT

AI01119

ten to address 555h on the third cycle afte r the two
Coded cycles. The Chip Erase Confirm command
10h is similarly written on the sixth cycle after an­other two Coded cycles. If the second command
given is not an erase confirm or if the Coded cy­cles are wrong, the instruction aborts an d the de­vice is reset to Read Array. It is not necessary to
program the array with 0000h first as the P/E.C.
will automatically do this before erasing it to
FFFFh. Read operations after the sixth rising edge

or E output the Status Register bits. During

of W
the execution of the erase by the P/E.C., Data
Polling b i t D Q7 retur ns ' 0', then '1' on c o m p let io n.
The Toggle bits DQ2 and DQ6 toggle during erase
operation and stop when erase is completed. After
completion the Status Register bit DQ5 returns '1'
if there has been an Erase Failure.

POWE R SU PPLY
Power Up

The memory Command Interface is reset on pow­er up to Read Array. Either E
V

during Power Up to allow m aximum security

IH

or W must be tied to

and the possibility to write a command on the first
rising edge of E
blocked when V

and W. Any write cycle initiation is

is below V

CC

LKO

.

Supply Rails

Normal precautions must be taken for supply volt­age decoupling; each device in a system should
have the V
close to the V
widths should be sufficient to carry the V

rail decoupled with a 0.1µF capacitor

CC

and VSS pins. The PCB trace

CC

CC

pro-

gram and erase currents required.

9/24

M59BW102

Table 11. DC Characteristics

(T

= 0 to 70°C; VCC = 3.0V to 3.6V)

A

Symbol Parameter Test Condition Min Max Unit

I

Input Leakage Current

LI

I

I

CC1

I

CC2

I

CC3

V

V
V
V

V

V

LKO

Note: 1. Sampled only, not 100% tested.

Output Leakage Current

LO

Supply Current (Read)
Supply Current (Standby)

(1)

Supply Current (Program or Erase)

Input Low Voltage –0.5 0.8 V

IL

Input High Voltage

IH

Output Low Voltage

OL

Output High Voltage

OH

A9, E, G High Voltage 11.5 12.5 V

ID

I

A9, E, G High Current

ID

Supply Voltage (Erase and Program

(1)

lock-out)

0V ≤ V

0V

E

= VIL, G = VIH, f = 6MHz

ALE, E

≤ V

IN

CC

≤ V

≤ V

OUT

= VCC ± 0.2V

CC

Byte program or

Chip Erase in progress

I

= 1.8mA

OL

I

= –100µA VCC – 0.4V

Oh

A9, E

, G = V

ID

2V

1.8 2.3 V

Table 12. Sequential Read Mode AC Characteristics
(T

= 0 to 70°C)

A

Symbol Alt Parameter Test Condition

t

CYCLE

t

GHGL

t

GLGH

t

GHEL

t

GHEH

t

EHALH

t

GHALH

t

GHQV

t

ELQV

t

EHQZ

t

ALHQZ

Note: 1. This timing refers to a Load Capacitance (CL) of 30pF. If CL is higher, add 1 ns for each ex tra 10pF.

(1)

(1)

t

CY

t

GW

t

GL

t

ATT

t

SBY

t

AV

t

GS

t

GACC

t

EACC

t

EDF

t

ADF

Sequential Cycle
Output Enable High to Output Enable Low G = Pulse 13 ns
Output Enable Low to Output Enable High G = Pulse 12 ns
Output Enable High to Chip Enable Low –2 ns
Output Enable High to Chip Enable High –2 ns
Chip Enable High to Address Latch Enable

High
Output Enable High to Address Latch

Enable High (following cycle)
Output Enable High to Output Valid 20 ns

Chip Enable Low to Output Valid 20 ns
Chip Enable High to Output Hi-Z 12 ns

Address Latch Enable High to Output Hi-Z 20 ns

E

= VIL, ALE = V

V

CC

Min Typ Max

25 ns

IL

3ns

0ns

±1 µA
±1 µA
10 mA

100 µA

20 mA

+ 0.3

CC

0.45 V

100 µA

M59BW102

25

= 3.0V to 3.6V

V

V

Unit

10/24

Table 13. Random Read Mode AC Characteristics
(T

= 0 to 70°C)

A

M59BW102

M59BW102

Symbol Alt Parameter Test Condition

V

Min Typ Max

t

ALHALLtALW

t

ELALL

t

AXALL

t

EHALH

t

ALLGL

t

GHALH

t

GHGL

t

GLGH

(1)

(1)

t
t

t

GLQV

t

ELQV

t

GHEL

t

EHQZ

t

ALHQZ

t

QVGH

t

GHEH

t

ELGL

t

EHQV

t

ALLAX

Note: 1. This timing refers to a Load Capacitance (CL) of 30pF. If CL is higher, add 1ns for each ex tra 10pF.

Address Latch Enable High to Address
Latch Enable Low

Chip Enable Low to Address Latch Enable

t

E

Low
Address Transition to Address Latch

t

AS

Enable Low
Chip Enable High to Address Latch Enable

t

ELV

High
Address Latch Enable Low to Output

t

AG

Enable Low
Output Enable High to Address Latch

t

QP

Enable High

t

Output Enable High to Output Enable Low G = Pulse 14 ns

GW

t

Output Enable Low to Output Enable High 48 ns

GL

Output Enable Low to Output Valid 30 ns

GACC

Chip Enable Low to Output Valid 55 ns

EACC

t

Output Enable High to Chip Enable Low –2 ns

GE

t

Chip Enable High to Output Hi-Z 12 ns

EDF

t

Address Latch Enable High to Output Hi-Z 20 ns

ADF

t

Output Valid to Output Enable High 10 ns

QV

t

Output Enable High to Chip Enable High 0 ns

GE

t

Chip Enable Low to Output Enable Low 13 ns

EGL

ALE = Pulse

10 ns

10 ns

6ns

3ns

7.5 ns

0ns

Chip Enable High to Data Hold 0 ns
Address Latch Enable Low to Address

Transition

30 ns

25

= 3.0V to 3.6V

CC

Unit

11/24

M59BW102

Figure 7. Sequential Cycle Waveforms

ALE

E

tGHGL

G

tELQV

A0-A15

tGHQV

DQ0-DQ15

Figure 8. Random Mode Waveform s

tCYCLE

tGLGH

tGHEH

tGHALH

tEHALH

tEHQZtGHEL

tEHQV

tALHQZ

AI02767B

ALE

E

G

A0-A15

DQ0-DQ15

tALLAX

tALHALL

tGHGL

tELGL

tGHALH

tGHEL tGHEH

tAXALL

tALLGL

tGLGH

tGLQV

tELALL

tELQV

tEHALH

tQVGH

tEHQZ

tEHQV

tALHQZ

AI02768B

12/24

Table 14. Write AC Characteristics, Write Enable Controlled

(T

= 0 to 70°C)

A

M59BW102

M59BW102

Symbol Alt Parameter

t

AVAV

t

ELWL

t

WLWH

t

DVWH

t

WHDX

t

WHEH

t

WHWL

t

AVWL

t

WLAX

t

GHWL

t

VCHEL

t

WHGL

t

WC

t

CS

t

WP

t

DS

t

DH

t

CH

t

WPH

t

AS

t

AH

t

VCS

t

OEH

Address Valid to Next Address Valid 55 ns
Chip Enable Low to Write Enable Low 0 ns
Write Enable Low to Write Enable High 30 ns
Input Valid to Write Enable High 25 ns
Write Enable High to Input Transition 0 ns
Write Enable High to Chip Enable High 0 ns
Write Enable High to Write Enable Low 20 ns
Address Valid to Write Enable Low 0 ns
Write Enable Low to Address Transition 35 ns

Output Enable High to Write Enable Low 0 ns
VCC High to Chip Enable Low

Write Enable High to Output Enable Low 0 ns

Figure 9. Write AC Waveforms, W Controlled

25

= 3.0V to 3.6V

V

CC

Min Max

50 µs

Unit

tAVAV

A0-A15

tAVWL

E

tELWL

G

W

DQ0-DQ15

V

CC

tVCHEL

Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W; ALE must be High.

VALID

tWLWHtGHWL

tDVWH

tWLAX

tWHEH

tWHGL

tWHWL

tWHDX

VALID

AI02769

13/24

M59BW102

Table 15. Write AC Characteristics, Chip Enable Controlled

(T

= 0 to 70°C)

A

M59BW102

Symbol Alt Parameter

t

AVAV

t

WLEL

t

ELEH

t

DVEH

t

EHDX

t

EHWH

t

EHEL

t

AVEL

t

ELAX

t

GHEL

t

VCHWL

t

EHGL

t

WC

t

WS

t
t
t

t

WH

t

CPH

t
t

t

VCS

t

OEH

Address Valid to Next Address Valid 55 ns
Write Enable Low to Chip Enable Low 0 ns
Chip Enable Low to Chip Enable High 30 ns

CP

Input Valid to Chip Enable High 25 ns

DS

Chip Enable High to Input Transition 0 ns

DH

Chip Enable High to Write Enable High 0 ns
Chip Enable High to Chip Enable Low 20 ns
Address Valid to Chip Enable Low 0 ns

AS

Chip Enable Low to Address Transition 35 ns

AH

Output Enable High to Chip Enable Low 0 ns
VCC High to Write Enable Low

Chip Enable High to Output Enable Low 0 ns

Figure 10. Write AC Waveforms, E Controlled

25

= 3.0V to 3.6V

V

CC

Min Max

50 µs

Unit

tAVAV

A0-A15

tAVEL

W

tWLEL

G

E

DQ0-DQ15

V

CC

tVCHWL

Note: Address are latched on the falling edge of E, Data is latc hed on the rising edge of E; A LE must be High.

VALID

tELEHtGHEL

tDVEH

tELAX

tEHWH

tEHGL

tEHEL

tEHDX

VALID

AI02770

14/24

M59BW102

Table 16. Write AC Characteristics, Write Enable Controlled and Address Latch Enable Pulsed

(T

= 0 to 70°C)

A

M59BW102

Symbol Alt Parameter

t

AVAV

t

ELWL

t

WLWH

t

DVWH

t

WHDX

t

WHEH

(1)

t

WHWL

t

GHWL

t

VCHEL

t

WHGL

t

ALHWL

t

AVALL

t

ELALL

t

ALLAX

(1)

t

WHALL

t

EHGL

Note: 1. These pa rameters are applicable only if the following cycle is for the same devi ce.

t

WC

t

CS

t

WP

t

DS

t

DH

t

CH

t

WPH

t

VCS

t

OEH

Address Valid to Next Address Valid 55 ns
Chip Enable Low to Write Enable Low 0 ns
Write Enable Low to Write Enable High 30 ns
Input Valid to Write Enable High 25 ns
Write Enable High to Input Transition 0 ns
Write Enable High to Chip Enable High 0 ns

Write Enable High to Write Enable Low 20 ns
Output Enable High to Write Enable Low 0 ns

V

High to Chip Enable Low

CC

Write Enable High to Output Enable Low 0 ns
Address Latch Enable High to Write Enable Low 10 ns
Address Valid to Address Latch Enable Low 5 ns
Chip Enable Low to Address Latch Enable Low 10 ns
Address Latch Enable Low to Address Transition 35 ns

Write Enable High to Address Latch Enable Low 50 ns
Chip Enable High to Output Enable Low 10 ns

V

25

= 3.0V to 3.6V

CC

Min Max

50 µs

Unit

Figure 11. Write AC Waveforms, W Controlled and Address Latch Enabl e Pulsed

tAVAV

A0-A15

E

G

W

DQ0-DQ15

V

CC

tVCHEL

ALE

tAVALL

tELWL

tELALL

tALHWL tWHALL

VALID

tWLWHtGHWL

tDVWH

tALLAX

tWHEH

tWHGL

tEHGL

tWHWL

tWHDX

VALID

AI03041B

Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W.

15/24

M59BW102

Table 17. Suspend and Resume Last Linear Cycle Characteristics

(T

= 0 to 70°C)

A

M59BW102

Symbol Alt Parameter

t

ALLEL

Address Latch Enable Low to Chip Enable Low 15 ns

Figure 12. Suspend and Resume Linear Cycle Wave forms wi th Bus Idle

ALE

tEHALH tALLEL

E

tGHEH

G

A0-A15

Fetch Idle Fetch Idle Fetch Idle

25

= 3.0V to 3.6V

V

CC

Min Max

Unit

DQ0-DQ15

Odd EvenOddEven

AI03248

16/24

Table 18. Suspend and Resume Next Linear Cycle Characteristics

(T

= 0 to 70°C)

A

M59BW102

M59BW102

Symbol Alt Parameter

V

t

ALLEL

Address Latch Enable Low to Chip Enable Low 15 ns

Figure 13. Suspend and Resume Linear Cycle Waveforms without Bus Idle

ALE

tEHALH tALLEL

E

tGHEH

G

A0-A15

Fetch

Fetch

Fetch FetchIdleIdleIdle

25

= 3.0V to 3.6V

CC

Min Max

Unit

DQ0-DQ15

Odd OddEvenEven

AI03249

17/24

M59BW102

Table 19. Data Polling and Toggle Bit AC Characteristics

(TA = 0 to 70°C)

Symbol Parameter

t

WHQ7V

t

EHQ7V

t

Q7VQV

t

WHQV

t

EHQV

Note: 1. All other timings are defined in Read AC Characteristics table.

Write Enable High to DQ7 Valid (Program, W Controlled) 10 2400 µs

Write Enable High to DQ7 Valid (Chip Erase, W

Controlled) 1 30 sec
Chip Enable High to DQ7 Valid (Program, E Controlled) 10 2400 µs
Chip Enable High to DQ7 Valid (Chip Erase, E

Controlled) 1 30 sec
DQ7 Valid to Output Valid (Data Polling) 25 ns
Write Enable High to Output Valid (Program) 10 2400 µs
Write Enable High to Output Valid (Chip Erase) 1 30 sec
Chip Enable High to Output Valid (Program) 10 2400 µs
Chip Enable High to Output Valid (Chip Erase) 1 30 sec

(1)

M59BW102

25

= 3.0V to 3.6V

V

CC

Min Max

Unit

18/24

Figure 14. Data Polling DQ7 AC Waveform

M59BW102

AI02771

ARRAY

READ CYCLE

DATA OUTPUT VALID

ADDRESS

tELQV

tAVQV

tEHQ7V

tGLQV

VALID

DQ7

tWHQ7V

VALID

tQ7VQV

IGNORE

DATA POLLING (LAST) CYCLE MEMORY

A0-A15

READ CYCLES

DATA POLLING

PROGRAM

OR ERASE

CYCLE OF

LAST WRITE

E

G

W

DQ7

DQ0-DQ6/

DQ8-DQ15

INSTRUCTION

Note: AL E must be high.

19/24

M59BW102

Figure 15. Da t a P olling Flowcha rt

START

READ DQ5 & DQ7

at VALID ADDRESS

DQ7

DATA

NO

DQ5

READ DQ7

DQ7

DATA

FAIL PASS

= 1

YES

=

NO

YES

YES

=

NO

Figure 16. Data Toggle Flowchart

START

READ

DQ2, DQ5 & DQ6

DQ2, DQ6

=

TOGGLE

NO

DQ5

= 1

READ DQ2, DQ6

DQ2, DQ6

=

TOGGLE

FAIL PASS

NO

YES

YES

NO

YES

AI01369B

AI01873

Table 20. Program, Erase Times and Program , Erase End urance Cycl es

(T

= 0 to 70°C; VCC = 3.0V to 3.6V)

A

M59BW102

Parameter

Min Typ

Typical after

100k W/E Cycles

Chip Erase (Preprogrammed) 0.7 0.7 sec
Chip Erase 1.5 1.5 sec
Chip Program 0.7 0.7 sec
Word Program 10 10 µs

Program/Erase Cycles 100,000 cycles

Unit

20/24

Figure 17. Data Toggle DQ6, DQ2 AC Waveforms

M59BW102

AI02772

VALID

tEHQV

tAVQV

tELQV

tGLQV

VALID

tWHQV

STOP TOGGLE

VALID

IGNORE

READ CYCLE

MEMORY ARRAY

READ CYCLE

DATA TOGGLE

A0-A15

DATA

TOGGLE

READ CYCLE

OF ERASE

PROGRAM

CYCLE OF

LAST WRITE

DQ6,DQ2

DQ0-DQ1,DQ3-DQ5,DQ7/

E

G

W

DQ8-DQ15

INSTRUCTION

Note: All other timin g are as a norma l Read cycle; AI LE m ust be high.

21/24

M59BW102

Table 21. Ordering Information Scheme

Example: M59BW102 25 N 1 T

Device Type

M59

Architecture

B = Burst Mode

Operating Voltage

W = V

Device Function

102 = 1 Mbit (64Kb x16)

Speed

25 = 25 ns sequential cycle time, 55 ns random access time

= 2.7 to 3.6V

CC

Package

N = TSOP40: 10 x 14 mm

Temperature Range

1 = 0 to 70 °C

Option

T = Tape & Reel Packing

For a list of available options (Speed, Pac kage, etc...) or for furthe r information on any aspect of this de­vice, please contact the ST Sales Office nearest to you.

22/24

M59BW102

Table 22. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 14 mm, Package Mechanical Data

Symb

Typ Min Max Typ Min Max

A 1.20 0.0472
A1 0.05 0.15 0.0020 0.0059
A2 0.95 1.05 0.0374 0.0413

B 0.17 0.27 0.0067 0.0106

C 0.10 0.21 0.0039 0.0083

D 13.80 14.20 0.5433 0.5591
D1 12.30 12.50 0.4843 0.4921

E 9.90 10.10 0.3898 0.3976

e0.50 – – 0.0197 – –

L 0.50 0.70 0.0197 0.0276
α 0° 5° 0° 5°
N40 40

CP 0.10 0.0039

mm inches

Figure 18. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Packag e Outline

A2

1 N

e

E

B

N/2

D1

D

DIE

A

CP

C

TSOP-a

Drawing is not to scale.

LA1 α

23/24

M59BW102

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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or otherwise under any patent or patent rights of STMi croelectr onics. Specifications mentioned in thi s publicati on are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
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24/24