Datasheet M58LW032C Datasheet (SGS Thomson Microelectronics)

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32 Mbit (2Mb x16, Uniform Block, Burst)

FEATURES SUMMARY

■ WIDE x16 DATA BUS for HIGH BANDWIDTH

■ SUPPLY VOLTAGE

= 2.7 to 3.6V core supply voltage for Pro-

–V

gram, Erase and Read operations

–V

■ SYNCHRONOUS/ASYNCHRONOUS READ

– Synchronous Burst read – Asynchronous Random Read – Asynchronous Address Latch Controlled

– Page Read

■ ACCESS TIME

– Synchronous Burst Read up to 56MHz – Asynchronous Page Mode Read 90/25ns,

– Random Read 90ns, 110ns

■ PROGRAMMING TIME

– 16 Word Write Buffer – 12µs Word effective programming time

■ 32 UNIFORM 64 KWord MEMORY BLOCKS

■ ENHANCED SECURITY

– Block Protection/ Unprotection – Smart Protection: irreversible block locking

–V – 128 bit Protection Register with 64 bit Unique

■ PROGRAM and ERASE SUSPEND

■ COMMON FLASH INTERFACE

■ 100,000 PROGRAM/ERASE CYCLES per

BLOCK

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 0020h – Device Code M58LW032C : 8822h

= 1.8 to VDD for I/O B u ffers

DDQ

Read

110/25ns

system

signal for Program Erase Enable

PEN

Code in OTP area

M58LW032C

3V Supp l y Fl ash Memory

Figure 1. Packages

TSOP56 (N)

14 x 20 mm

TBGA

TBGA64 (ZA)

10 x 13 mm

1/61April 2003

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M58LW032C

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. TSOP56 Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4. TBGA64 Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 5. Block Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Address Inputs (A1-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1

Data Inputs/Outputs (DQ0-DQ15 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Reset/Power-Down (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Clock (K).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Valid Data Ready (R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Status/(Ready/Busy) (STS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Program/Erase Enable (VPEN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

DDQ

Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

SSQ

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Address Latch.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Power-Down.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 2. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

READ MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Asynchronous Read Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Asynchronous Latch Controlled Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Asynchronous Random Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Asynchronous Page Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Synchronous Read Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Synchronous Burst Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Single Synchronous Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

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CONFIGURATION REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Read Select Bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

X-Latency Bits (CR13-CR11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Internal Clock Divider Bit (CR10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Y-Latency Bit (CR9). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Valid Data Ready Bit (CR8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6

Burst Type Bit (CR7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Valid Clock Edge Bit (CR6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Burst Length Bit (CR2-CR0).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 3. Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 4. Burst Type Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 6. Burst Configuration X-1-1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 7. Burst Configuration X-2-2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Read Memory Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Read Electronic Signature Comma nd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Read Query Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Write to Buffer and Program Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Program/Erase Suspend Comm and . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Set Configuration Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Block Protect Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Blocks Unprotect Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Configure STS Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2

Table 5. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 6. Configuration Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 7. Read Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 8. Read Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 8. Protection Register Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 9. Program, Erase Times and Program Erase Endurance Cy cles . . . . . . . . . . . . . . . . . . . 25

STATUS REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Program/Erase Controller Status Bit (SR7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Erase Suspend Status Bit ( SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Erase Status Bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Program Status Bit (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Status Bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

PEN

Program Suspend Status Bit (SR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Block Protection Status Bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

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Reserved (SR0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 10. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 11. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 12. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 9. AC Measurement Input Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 10. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 13. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 14. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 11. Asynchronous Bus Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 15. Asynchronous Bus Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 12. Asynchronous Latch Controlled Bus Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . 33

Table 16. Asynchronous Latch Controlled Bus Read AC Characteristics. . . . . . . . . . . . . . . . . . . 33

Figure 13. Asynchronous Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 17. Asynchronous Page Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 14. Asynchronous Write AC Waveform, Write Enable Controlled . . . . . . . . . . . . . . . . . . . 35

Figure 15. Asynchronous Latch Controlled Write AC Waveform, Write Enable Controlled. . . . . . 35

Table 18. Asynchronous Write and Latch Controlled Write AC Characteristics, Write Enable

Controlled.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 16. Asynchronous Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . 37

Figure 17. Asynchronous Latch Controlled Write AC Waveforms, Chip Enable Controlled . . . . . 37

Table 19. Asynchronous Write and Latch Controlled Write AC Characteristics, Chip Enable

Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 18. Synchronous Burst Read AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 19. Synchronous Burst Read - Continuous - Valid Data Ready Output. . . . . . . . . . . . . . . 40

Table 20. Synchronous Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 20. Reset, Power-Down and Power-up AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 21. Reset, Power-Down and Power-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 41

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 21. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Outline . . . . . . . 42

Table 22. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Mechanical Data 42

Figure 22. TBGA64 10x13mm - 8x8 ball array, 1mm pitch, Package Outline . . . . . . . . . . . . . . . . 43

Table 23. TBGA64 10x13mm - 8x8 ball array, 1mm pitch, Package Mechanical Data. . . . . . . . . 43

PART NUMBERING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 24. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

APPENDIX A. BLOCK ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 25. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

APPENDIX B. COMMON FLASH INTERFACE - CFI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 26. Query Structure Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

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Table 27. CFI - Query Address and Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 28. CFI - Device Voltage and Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 29. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 30. Block Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 31. Extended Query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

APPENDIX C. FLOW CHARTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 23. Write to Buffer and Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 50

Figure 24. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . 51

Figure 25. Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 26. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . 53

Figure 27. Block Protect Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 28. Blocks Unprotect Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 29. Protection Register Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 56

Figure 30. Command Interface and Program Erase Controller Flowchart (a). . . . . . . . . . . . . . . . 57

Figure 31. Command Interface and Program Erase Controller Flowchart (b). . . . . . . . . . . . . . . . 58

Figure 32. Command Interface and Program Erase Controller Flowchart (c). . . . . . . . . . . . . . . . 59

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 32. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5/61

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M58LW032C

SUMMARY DESCRIPTION

M58LW032C is a 32 M bit (2Mb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7V t o 3.6V) core supply. On power-up the memory defaults to Read mode with an asynchronous bus where it can be read in the same way as a non-burst Flash memory.

The memory is divided into 32 blocks of 1Mbit that can be erased i ndependently so it is poss ible to preserve valid data while old data is erased. P rogram and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a Program or Erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards.

The device supports synchronous burst read and asynchronous read from all blocks of the memory array; at power-up the device is configured for asynchronous read. In asynchronous mode an Address Latch input can be used to latch addresses in Latch Controlled mode. In synchronous burst mode, data is output on each clock cycle at frequencies of up to 56MHz.

The Write Buffer allows the microprocessor to program from 1 to 16 Words in parallel, both speeding up the programming and freeing up the microprocessor to perform other work. A Word Program command is available to program a single Word.

Erase can be suspended in order to perform either Read or Program in any other block and then resumed. Program ca n be s uspended to Read data in any other block and then resum ed. Eac h block can be programmed and erased over 100,000 cycles.

The M58LW032C has several security features to increase data protection.

■ Block Protection, where each block can be

individually protected against p r ogram or eras e operations. All blocks are protected during power-up. The protection of the blocks is nonvolatile; after power-up the protection status of each block is restored to the state when power was last removed.

■ Program Erase Enable i nput V

, program or

PEN

erase operations are not possible when the Program Erase Enable input V

■ Smart Protection, which allows protected blocks

PEN

is low.

to be permanently locked. This feature is not described in the datasheet for security reasons. Please contact STMicroelectronics for further details.

■ 128 bit Protection Regi ster, divided in to two 64

bit segments: the f irst con tains a unique device number written by ST, the second is user programmable. The user programmable segment can be protected.

The Reset/Power-Down pin is used to apply a Hardware Reset to the memory and to set the device in power-down mode.

The device features an Auto Low Power mode. If the bus becomes inactive during Asynchronous Read operations, the device automatically enters Auto Low Power mode. In this mode the power consumption is reduced to the Auto Low Power supply current.

The STS signal is an open drain output that can be used to identify the Program/Erase Controller status. It can be configured in two modes: Ready/ Busy mode where a static signal indicates the status of the P/E.C, and Status mode where a pulsing signal indicates the end of a Program or Block Erase operation. In Status mode it can be used as a system interrupt signal, useful for saving CPU time.

The memory is available in TSOP56 (14 x 20 mm) and TBGA64 (10 x 13mm, 1mm pitch) packages.

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Page 7

Figure 2. Logi c D iag ram Table 1. Si gn a l Nam es

A1-A21 Address inputs

DDQ

DQ0-DQ15 Data Inputs/Outputs

M58LW032C

A1-A21

PEN

W E

DQ0-DQ15

M58LW032C

STS R

SSQ

AI06208

G K Clock L R Valid Data Ready STS Status/(Ready/Busy) RP

PEN

W V

DDQ

SSQ

NC Not Connected Internally

Chip Enable Output Enable

Latch Enable

Reset/Power-Down Program/Erase Enable Write Enable Supply Voltage Input/Output Supply Voltage Ground Input/Output Ground

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M58LW032C

Figure 3. TSOP56 Connections

A21 A20 A19 A18 A17 A16

DD A15 A14 A13 A12

PEN

RP A11 A10

A9 A8

A7 A6 A5 A4 A3 A2 A1

M58LW032C

28 29

43 42

NC W

G STS

DQ15 DQ7 DQ14 DQ6 V

DQ13 DQ5 DQ12 DQ4 V

DDQ

SSQ

DQ11 DQ3 DQ10 DQ2 V

DQ9 DQ1 DQ8 DQ0 NC K NC L

8/61

AI06209

Page 9

Figure 4. TBGA64 Connections (Top view through package)

M58LW032C

87654321

B RA19A2

D A16

A4 A5

DQ0

A6 V

A7A3

A10 A12

A11

DQ10

DQ2

PEN

EA9

DDQ

A13

A14

A15

NC NC

DQ5V

DQ6

A20

DQ15 STSDQ9DQ8 DQ1 DQ4DQ3

DQ14

NCA18

A21

A17

GDQ12DQ11

DQ13

SSQ

DQ7

AI06210b

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Page 10

M58LW032C

Figure 5. Block Addresses

Word (x16) Bus Width

1FFFFFh

1F0000h

1EFFFFh

1E0000h

Total of 32

1 Mbit Blocks

01FFFFh

010000h

00FFFFh

000000h

Note: Also see Appendix A, T able 25 for a full li st i ng of the Block Addresses.

1 Mbit or

64 KWords

1 Mbit or

64 KWords

1 Mbit or

64 KWords

1 Mbit or

64 KWords

AI06254

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Page 11

SIGNAL DESCRIPTIONS

See Figure 2, Logic Diagram and Table 11, Signal Names, for a brief overview of the signals connected to this device.

Address Inputs (A1-A21). The Address Inputs are used to select the cells to access in the memory array during Bus Read operations either to read or to program data to. During Bus Write operations they control the commands sent to the Command Interface of the internal state m ac hine. Chip Enable and Latch Enable must be low when selecting the addresses.

The address inputs are latched on the rising edge of Chip Enable, Write Enable or Latch Enable, whichever occurs first in a Write operation. The address latch is transparent when Latch Enable is low, V

. The address is internally latched in an

Erase or Program operation. Data Inputs/Outputs (DQ0-DQ15). The Data In-

puts/Outputs output the data stored at the selected address during a Bus Read operation, or are used to input the data during a program operation. During Bus Write operations they repres ent the commands sent to the Command Interface of the internal state machine. When used to input data or Write commands they are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first.

When Chip Enable and Output Enable are both low, V

, the data bus outputs data from the mem-

ory array, the Electronic Signature, the Block Protection status, the CFI Information or the contents of the Status Register. The data bus is high impedance when the chip is deselected, Output E nable is high, V low, V

or the Reset/Power-Down signal is

IH,

. When the Program/Erase Controller is

active the Ready/Busy status is given on DQ7.

Chip Enable (E

). The Chip Enable, E, input acti-

vates the memory control logic, input buffers, decoders and sense amplifiers. Chip Enable, E V

deselects the memory and reduces the power

consumption to the Standby level, I

Output Enable (G

). The Output Enable, G, gates

DD1

, at

the outputs through the data output buffers during a read operation. When Output Enable, G

, is at V

the outputs are high impedance. Output Enable, G

, can be used to inhibit the data ou tput during a

burst read operation.

Write Enable (W

). The Write Enable input, W,

controls writing to the Command Interface, Input Address and Data latches. Both addresses and data can be latched on the rising edge of Write Enable (also see Latch Enable, L

Reset/Power-Down (RP

). The Reset/PowerDown pin can be used to apply a Hardware Reset to the me mory.

M58LW032C

A Hardware Reset is achieved by holding Reset/ Power-Down Low, V Reset/Power-Down is Low, V ter information is c leared and t he power consumption is reduced to power-down level. The device is deselected and outputs are high impedance. If Reset/Power-Down goes low, V Erase, a Write to Buffe r and Program or a Block Protect/Unprotect the operation is aborted and the data may be corrupted. In this case the Ready/ Busy pin stays low, V t

PLPH

+ t

until the completion of the Reset/

PHRH,

Power-Down pulse. After Reset/Power-Down goes High, V

memory will be ready for Bus Read and Bus Write operations after t does not fall during a reset , s ee Rea dy /Busy Ou tput section.

In an application, it is recommended to associate Reset/Power-Down pin, RP of the microprocessor. Otherwise, if a reset operation occurs while the memory is performing an Erase or Program operation, the memory may output the Status Register information inst ead of being initialized to the default Asynchronous Random Read.

Latch Enable (L

ured to latch the Address Inputs on the rising edge of Latch Enable, L the address is latched on the active edge of the Clock when Latch Enable is Low, V ing of Latch Enable, whichever occurs first. Once latched, the addresses may change without affecting the address used by the memory. When Latch Enable is Low, V

Clo c k (K). The Clock, K, is used to synchronize the memory with the external bus during Synchronous Bus Read operations. The Clock can be configured to have an active rising or falling edge. Bus signals are latched on the active edge of the Clock during synchronous bus operations. In Synchronous Burst Read m ode the address is latched on the first active clock edge when Latch Enable is low, VIL, or on the rising edge of Latch Enable, whichever occurs first.

During asynchronous bus operations the Clock is not used.

Valid Data Ready (R). The Valid Data Ready output, R, is an open drain output that can be used to identify if the memory is ready to output data or not. The Valid Data Ready output is only active during Synchronous Burst Read operat ions when the Burst Length is set to Continuous. The Valid Data Ready output can be configured to be active on the clock edge of the invalid data read cycle or one cycle before. Valid Data Ready Low, V

, for at least t

, for a ma ximum timin g of

. Note that Ready/Busy

PHQV

, the Status Regis-

,during a Block

PLPH

. When

, the

, with the reset sig nal

). The Bus Interface is config-

. In synchronous bus operations

or on the ris-

, the latch is transparent.

, in-

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Page 12

M58LW032C

dicates that the data is not, or will not be valid. Valid Data Ready in a high-impedance state indicates that valid data is or will be available.

Unless Synchronous Burst Read has been selected, Valid Data Ready is high-impedance. It may be tied to other components with the same Valid Data Ready signal to create a unique System Ready signal.

The Valid Data Ready, R, output has an internal pull-up resistor of approximately 1 MΩ powered from V

, designers should use an external pull-

DDQ

up resistor of the correct value to meet the external timing requirements for Valid Data Ready rising. Refer to Figure 19.

Status/(Ready/Busy) (STS). The STS signal is an open drain output t hat can be used to id entify the Program/Erase Controller status. It can be configured in two modes:

■ Ready/Busy - the pin is Low, V

, during

Program and Erase operations and high impedance when the memory is ready for any Read, Program or Erase operation.

■ Status - the pin gives a pulsing signal to indicate

the end of a Program or Block Erase operation.

After power-up or reset the STS pin i s configured in Ready/Busy mode. T he pin can be co nfigured for Status mode using the Configure STS command.

When the Program/Erase Controller is idle, or suspended, STS can float High through a pul l-up resistor. The use of an open-drain output allows the STS pins from several memo ries to be c onnect ed to a single pull-up resistor (a Low will indicate that one, or more, of the memories is busy).

STS is not Low during a reset unless the reset was applied when the Program/Erase controller was active. Ready/Busy can rise before Reset/PowerDown rises.

Program/Erase Enable (V

Erase Enable input, V

PEN,

). The Program/

PEN

is used to protect all blocks, preventing Program and Erase operations from affecting their data.

Program/Erase Enable must be kept High during all Program/Erase Controller operations, otherwise the operations is not guaranteed to suc ceed and data may become corrupt.

Supply Voltage. VDD provides the power

supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program and Erase).

Supply Voltage. V

DDQ

provides the power

DDQ

supply to the I/O pins and enables all Outputs to

. V

be powered independently from V tied to V

or can use a separate supply.

DDQ

can be

It is recommended to power-up and power-down V

and V

together to avoid any condition that

DDQ

would result in data corruption.

Ground. Ground, V

is the reference for

SS,

the core power supply. It must be connected to the system ground.

Ground. V

SSQ

the input/output circuitry driven by V

ground is the reference for

SSQ

DDQ

. V

SSQ

must be connected to VSS.

Note: Each device in a system should have V

and V

decoupled with a 0.1µF ceramic

DDQ

capacitor close to the pin (high frequency, inherently low inductance ca pacitors should b e as close as possible to the package). See Figure 10, AC Measurement Load Circuit.

12/61

Page 13

BUS OPERATIONS

There are six standard bus operations that control the device. These are Address Latch, B us Read, Bus Write, Output Disable, Power-Down and Standby. See Table 2, Bus Operations, for a summary.

Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect Bus Write operations.

Address Latch. Address latch operations input valid addresses.

A valid bus operation i nvolves set ting the des ired address on the Address Inputs, setting Chip Enable and Latch Enable Low, V Enable High, V

; the address is latched on the ris-

and keeping Write

ing edge of Address Latch. Bus Read. Bus Read operations are used to out-

put the contents of the Memory Array, the Electronic Signature, the Status Register, the Common Flash Interface and the Block Protection Status.

A valid bus operation i nvolves set ting the des ired address on the Address Inputs, applying a Low signal, V Latch Enable and keeping Write Enable High, V

, to Chip Enable, Output Enable and

The data read depends on the previous command written to the memory (see Command Interface section). See Figures 11, 12, 13, 18 and 19 Read AC Waveforms, and Tables 15, 16, 17 and 20 Read AC Characteristics, for details of when the output becomes valid.

Bus Write. Bus Write operations write Commands to the memory or latch addresses and input data to be programmed.

M58LW032C

A valid Bus Write operation begin s by setting the desired address on the Address Inputs and setting Latch Enable Low, V latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, V the Bus Wr ite operation.

See Figures 14, 15, 16 and 17, Write AC Waveforms, and Tables 18 and 19, Write AC Characteristics, for details of the timing requirements.

Output Disa bl e . The The Data Inputs/Outputs are high impedance when the Out put Enable i s at

Power-Down. The memory is in Power-Down mode when Reset/Power-Down, RP power consumption is reduced to the Power-Down level, I

, and the out puts are high impedance,

DD2

independent of Chip Enable, Output Enable or Write Enable.

Standby. Stan dby disables most of the inte rnal

circuitry, allowing a substantial reduction of the current consumption. The memory is in standby when Chip Enable is at V tion is reduced to the standby level I outputs are set to high impedance, independently from the Output Enable or Write Enable inputs.

If Chip Enable switches to V erase operation, the d ev ice en ters Standby mode when finished.

. The Address Inputs are

, is Low. The

. The power consump-

during a program or

DD1

, during

and the

Table 2. Bus Operations

Operation E G W RP L A1-A21 DQ0-DQ15

Address Latch

Bus Read Bus Write

Output Disable

Power-Down X X X

Standby

Note: 1. X = Don’t Care VIL or VIH.

2. Depends on G

X X High Z X X High Z X X High Z

Address Address Data Output Address Data Input

Data Output or Hi-Z

(2)

13/61

Page 14

M58LW032C

READ MODES

Read operations can be performed in two different ways depending on the settings in the Configura-

tion Register. If the clock signal is ‘d on’t care’ for the data output, the read operation is asynchronous; if the data output is synchronized with clock, the read operation is synchronous.

The read mode and f ormat of the data output are determined by the Configuration Register. (See Configuration Register section for details).

On Power-up or after a Hardware Reset the memory defaults to Asynchronous Read mode.

Asynchronous Read Modes

In Asynchronous Read operations the clock signal is ‘don’t care’. The device outpu ts the dat a corresponding to the address latched, that is the mem ory array, Status Register, Common Flash Interface, Electronic Signature or Block Protection Status depending on the comma nd issued. CR15 in the Configuration Register must be set to ‘1’ for asynchronous operations.

During Asynchronous Read operations, if the bus is inactive for a time equivalent to t vice automatically enters Auto Low Power mode. In this mode the internal supply current is reduced to the Auto Low Power supply current, I Data Inputs/Outputs will still output data if a Bus Read operation is in progress.

Automatic Low Power is only available in Asynchronous Read modes.

Asynchronous Read operations can be performed in three different ways, Asynchronous Latch Controlled Read, Asynchronous Random Read and Asynchronous Page Read.

Asynchronous Latch Controlled Read.

In Asynchronous Latch Controlled Read operations read the address is latched in the me mory before the value is output on the data bus, allowing the address to change during the cycle without affecting the address that the memory uses.

A valid bus operation i nvolves set ting the des ired address on the Address Inputs, setting Chip Enable and Latch Enable Low, V Enable High, V

; the address is latched on the ris-

and keeping Write

ing edge of Address L atch. Once latched, the Address Inputs can change. Set Output Enable Low,

, to read the data on the Data Inputs/Outputs;

see Figure 12, Asynchronous Latch Controlled Read AC Waveforms and Table 16, Asynchronous Latch Controlled Read AC Characteristics for details on when the output becomes valid.

See Figures 12, Asynchronous Latch Controlled Read AC Waveforms, and Table 16, Asynchronous Latch Controlled Read AC Characteristics, for details.

AVQV

, the de-

. The

DD5

Asynchro nous Random R ead. As th e Lat ch En able input is transparent when set Low, V

, Asyn-

chronous Random Read operations can be performed by holding Latch Enable Low, V throughout the bus operation.

See Figures 11, Asynchronous Random Read AC Waveforms, and Table 15, Asynchronous Random Read AC Characteristics, for details.

Asynchro nous Page Read . In Asynchronous Page Read mode a Page of data is internally read and stored in a Page Buffer. Each memory page is 4 Words and has th e same A3-A22, only A 1 and A2 may change.

The first read operation within the Page has the normal access time (t

), subsequent reads

AVQV

within the same Page have much sho rter access times (t

). If the Page changes then the nor-

AVQV1

mal, longer timings apply again. See Figures 13, Asynchronous Page Read AC

Waveforms, and Table 17, Asynchronous Page Read AC Characteristics, for details.

Synchronous Read Mo de s

In Synchronous Read mode the data output is synchronized with the clock. CR15 in the Configuration Register must be set to ‘0’ for synchronous operations.

Synchronous Burst Read. In Synchronous Burst Read mode the data is output in bursts synchronized with the clock. It is possible to perform burst reads across bank boundaries.

Synchronous Burst Read mode can onl y be used to read the memory array. For other read operations, such as Read Status Register, Read CFI, Read Electronic Signature and Block Protection Status, Single Synchronous Read or Asynchronous Read must be used.

In Synchronous Burst Read mode the flow o f the data output depends on param eters that are configured in the Configuration Register.

A valid Synchronous Burst Read operation begins when the address is set on the Address Inputs, Write Enable is High, V Latch Enable are Low, V

, and Chip Enable and

, during the active edge

of the Clock. The address is latched on the first active clock edge when Latch Enable i s low, or on the rising edge of Latch Enable, whichever occurs first. The data becomes available for output after the X-latency specified in the Burst Control Register has expired. The output buffers are activated by setting Output Enable Low, V

. See Figures 6

and 7 for examples o f Synchronous Burst Read operations.

The number of Words to be out put during a Synchronous Burst Read operation can be configured as 4 Words, 8 Words or Continuous (Burst Length

14/61

Page 15

M58LW032C

bits CR2-CR0). In Synchronous Continuous Burst Read mode one Burst Read operation can access the entire memory sequ entially. If the starting address is not associated with a page (4 Word) boundary the Valid Data Ready, R, output goes Low, V

, to indicate that the data will not be ready

in time and additional wait-states are required. The Valid Data Ready output timing (bit CR8) can be changed in the Configuration Register.

The order of the data output can be modified through the Burst Type bit in the Configuration

See Table 20, Synchronous Read AC Characteristics and Figure 18 a nd 19, Synchronous Burst Read AC Waveform for details.

Single Synchronous Read. Single Synchronous Read operations are similar to S ync hronous Burst Read operations except that only the first data output after the X latency is valid. Single Synchronous Reads are used to read the Status Register, CFI, Electronic Signature and Block Protection Status.

15/61

Page 16

M58LW032C

CONFIGURATION REGISTER

The Configuration Register is used to configure the type of bus access that the memory will perform. The Configuration Register bits are described in Table 3. They specify the selection of the burst length, burst type, burst X and Y latencies and the Read operation. See figures 6 and 7 for examples of Synchronous Burst Read configurations.

The Configuration Register is set through the Command Interface and will retain its information until it is re-configured, the device is reset, or the device goes into Reset/Power-Down mode. The Configuration Register is read using the Read Electronic Signature Command at address 05h.

Read Select Bit (CR15). The Read Select bit, CR15, is used to switch between asynchronous and synchronous Bus Read operations. When the

Read Select bit is set to ’1’, Bus Read operations are asynchronous; when the Read Select but is set to ’0’, Bus Read operations are synchronous.

On reset or power-up the Read Select bit is set to ’1’ for asynchronous access.

X-Latency Bits (CR13-CR11). The X-Latency bits are used during Synchronous Bus Read operations to set the number of clock cy cles between the address being latched and the first data becoming available. For correct operation the X-Latency bits can only assume the values in Table 3, Configuration Register.

Internal Clock Divider Bit (CR10). The Internal Clock Divider Bit is used to divide the internal clock by two. When CR10 is set to ‘1’ the internal clock is divided by two, which effectively means that the X and Y-Latency values are multiplied by two, that is the number of clock cycles between the address being latched and the first data becoming available will be twice the value set in CR13-CR11, and the number of clock cycles between consecutive reads will be twice the value set in CR9. For example 8-1-1-1 will be come 16-2-2-2. When C R10 is set to ‘0’ the internal clock runs normally and the X and Y-Latency values are those set in CR13-CR11 and CR9.

Y-Latency Bit (CR9). The Y-Latency bit is used during Synchronous Bus Read operations to set

the number of clock cycles between consecutive reads. The Y-Latency value depends on both the X-Latency value and the setting in CR9.

When the Y-Latency is 1 the data changes each clock cycle; when the Y-Latency is 2 the data changes every seco nd clock cycle. See Tab le 3, Configuration Register for valid combinations of the Y-Latency, the X-Latency and the Clock frequency.

Valid Data Ready Bit (CR8). The Valid Data Ready bit controls the timing of the Valid Data Ready output pin, R. When the Valid Data Ready bit is ’0’ the Valid Data Ready output pin is driven Low for the active clock edge when invalid data is output on the bus. When the Valid Data Ready bit is ’1’ the Valid Data Ready output pin is driven Low one clock cycle prior to invalid data being output on the bus.

Burst Type Bit (CR7). The Burst Type bit is used to configure the sequence of addresses read as sequential or interleaved. When the Burst Type bit is ’0’ the memory outputs from interleaved addresses; when the Burst Type bit is ’1’ the memory outputs from sequential addresses. See Tables 4, Burst Type Definition, for the sequence of addresses output from a given starting address in each mode.

Valid Clock Edge Bit (CR6). The Valid Clock Edge bit, CR6, is used to configure the active edge of the Clock, K, during Synchronous Burst Read operations. When the Valid Clock Edge bit is ’0’ the falling edge of the Clock is the active edge; when the Valid Clock Edge bit is ’1’ the rising edge of the Clock is active.

Burst Length Bit (CR2-CR0). The Burst Length bits set the maximum number of Words that can be output during a Synchronous Burst Read operation.

Table 3, Configuration Register gives the valid combinations of the Burst Length bits that the memory accepts; Tables 4, Burst Type Definition, give the sequence of addresses output from a given starting address for each length.

CR5 CR4 and CR3 are reserved for future use.

16/61

Page 17

Table 3. Configuration Register

Address

Bit

Mnemonic Bit Name

16 CR15 Read Select 1

15 CR14 Reserved

Reset

Value

Value Description

0 Synchronous Burst Read 1 Asynchronous Bus Read (default at power-up)

001 Reserved 010

X-Latency = 4, 4-1-1-1 (use only with Y-Latency = 1)

M58LW032C

(1)

CR13-CR11

X-Latency

(2)

XXX

011 100 101

X-Latency = 5, 5-1-1-1, 5-2-2-2 X-Latency = 6, 6-1-1-1, 6-2-2-2 X-Latency = 7, 7-1-1-1, 7-2-2-2

110 X-Latency = 8, 8-1-1-1, 8-2-2-2

X and Y-Latencies remains as set in CR13-CR11 and

11 CR10

Internal

Clock Divider

CR9

1 Divides internal clock, X and Y-Latencies multiplied by 2

10 CR9

9CR8

Y-Latency

Valid Data Ready

(3)

0 Y-Latency = 1 1 Y-Latency = 2 0 R valid Low during valid Clock edge 1 R valid Low one cycle before valid Clock edge 0 Interleaved

8 CR7 Burst Type X

1 Sequential

7CR6

Valid Clock Edge

0 Falling Clock edge 1 Rising Clock edge

6 to 4 CR5-CR3 Reserved

CR2-CR0 Burst Length XXX

Note: 1. 4 - 2 - 2 - 2 (represents X-Y-Y-Y) is not allowed.

2. X latencies can be calculated as: (t

is the clock period).

3. Y latencies can be calculated as: t

4. t

SYSTEM MARGIN

is the time m argin requir ed for the calculation.

AVQV

KHQV

– t

LLKH

+ t

SYSTEM MARGIN

001 4 Words 010 8 Words 111 Continuous

+ t

) + t

QVKH

SYSTEM MARGIN

+ t

QVKH

< Y t

< (X - 1) t

is an integer number from 4 to 8 and t

K. (X

17/61

Page 18

M58LW032C

Tabl e 4. Burst Type Definit ion

Starting

Addressx4Sequentialx4Interleaved

Sequential

Interleaved

Continuous

0 0-1-2-3 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10.. 1 1-2-3-0 1-0-3-2 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 1-2-3-4-5-6-7-8-9-10-11..

2 2-3-0-1 2-3-0-1 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 2-3-4-5-6-7-8-9-10-11-12.. 3 3-0-1-2 3-2-1-0 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 3-4-5-6-7-8-9-10-11-12-13..

4 – – 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-11-2-13-14..

5 – – 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 5-6-7-8-9-10-11-12-13-14..

6 – – 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 6-7-8-9-10-11-12-13-14-15.. 7 – – 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 7-8-9-10-11-12-13-14-15-16..

8 – – – – 8-9-10-11-12-13-14-15-16-17..

Figure 6. Burst Configuration X-1-1-1

0123456789

ADD VALID

4-1-1-1

5-1-1-1

6-1-1-1

7-1-1-1

8-1-1-1

VALID

VALIDVALIDVALIDVALID

VALIDVALIDVALID

VALID

VALIDVALIDVALIDVALID

VALID

VALIDVALID

AI05512

18/61

Page 19

Figure 7. Burst Configuration X-2-2-2

0123456789

M58LW032C

ADD

5-2-2-2

6-2-2-2

7-2-2-2

8-2-2-2

VALID

NV=NOT VALID

VALID

NVNV

AI05513

19/61

Page 20

M58LW032C

COMMAND INTERFACE

All Bus Write operations t o the me mory are in terpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. The Commands are summarized in Table 5, Commands. Refer to Table 5 in conjunction with the text descriptions below.

After power-up or a Reset operation the memory enters Read mode.

Synchronous Read operations and Latch Controlled Bus Read operations can only be used to read the memory array. The Electr onic Sign ature, CFI or Stat us Register will b e read in asynchro nous mode or single synchronous burst mode. Once the memory returns to Read Memory Array mode the bus will resume the setting in the Configuration Register automatically.

Read Memory A rray Command. The Read Memory Array command returns the memory to Read mode. One Bus Write cycle is required to issue the Read Memory Array command and return the memory to Read mode. Once the command is issued the memory remains in Read mode until another command is issued. From Read mode Bus Read commands will access the memory array.

While the Program/Erase Controller is executing a Program, Erase, Block Protec t, Blocks Unprotect or Protection Register Program operation the memory will not accept the Read Mem ory Array command until the operation completes.

Read Electr onic S ignature C ommand. The Read Electronic Signature command is used to read the Manufacturer Code, the Device Code, t he Block Protection Status, the Configuration Register and the Protect ion Registe r. One Bu s Write cycl e is required to issue the Read Electronic Signature command. Once the command is issued subsequent Bus Read operations read the Manufacturer Code, the Device Code, the Block Prote ction Status, the Configuration Register or the Protection Register until another command is issued. Refer to Table 7, Read Electronic Signature, Table 8, Read Protection Register and Figure 8, Prot ection Register Memory Map for information on the add re sses.

Read Query Command. The Read Query Command is used to read data from the Common Flash Interface (CFI) Memory Area. One Bus Write cycle is required to issue the Read Query Command. Once the command is issued subsequent Bus Read operations read from the Common Flash Interface Memory Area. See Appendix B, Tables 26, 27, 28, 29, 30 and 31 for details on the information contained in the Common Flash Interface (CFI) memory area.

Read Statu s Registe r Co mm an d . The Read Status Register command is used to read the Status

Register. One Bus Write cycle is required to issue the Read Status Register command. Once the command is issued subsequent Bus Read operations read the Status Register until another command is issued.

The Status Register information is present on the output data bus (DQ1-DQ 7) when both Chip Enable and Output Enable are low, V

See the section on the Status Reg ister and Table 10 for details on the definitions of the Status Register bits

Clear Status Register Command. The Clear Status Register command can be used to res et bits SR1, SR3, SR4 and SR5 in the Status Register to

‘0’. One Bus Write is required to issue the Clear Status Register command.

The bits in the Status Register are stic ky and do not automatically return to ‘0’ when a new Write to Buffer and Program, Erase, Block Protect, Block Unprotect or Protection Register Program command is issued. If any error occurs then it is essential to clear any error bits in the Status Register by issuing the Clear Status Register command before attempting a new Program, Erase or Resume command.

Block Erase Command. The Block Erase command can be used to e rase a block. I t sets all of the bits in the block to ‘1’. All previous data in the block is lost. If the block is protected then the Erase operation will abort, the data in the block will not be changed and the Status Register will output the error.

Two Bus Write operations are required to issue the command; the second Bus Write cycle latches the block address in the internal state machine and starts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits.

During the Erase operation the memory will only accept the Read Status Register command and the Program/Erase Su spend command. All ot her commands will be ignored. Typical Erase times are given in Table 9.

See Appendix C, Figure 25, Block Erase Flowchart and Pseudo Code, for a suggested flowchart on using the Block Erase command.

Word Program Command. The Word Program command is used to p rogram a single word in the memory array. Two Bus Write operations are required to issue the command; the first write cycle sets up the Word Program command, the second write cycle latches the address and data to be programmed in the internal state machi ne and s tarts the Program/Erase Controller.

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Page 21

M58LW032C

If the block being program m ed i s prote cted an error will be set in the Status Register and the operation will abort without affecting the data in the memory array. The block must be unprotected using the Blocks Unprotect command.

Write to Buffer and Program Command. The Write to Buffer and Program comm and is used to program the memory array.

Up to 16 Words can be loaded into the Write Buffer and programmed into the memory. Each Write Buffer has the same A5-A21 addresses.

Four successive steps are required to issue the command.

1. One Bus Write operation is required to set up the Write to Buffer and Program Comm and. Issue the set up command with the selected memory Block Address where the program operation should occur (any address in the block where the values will be programmed can be used). Any Bus Read operations will start to output the Status Register after the 1st cycle.

2. Use one Bus Write operation to write the same block address along with the value N on the Data Inputs/Output, where N+1 is the number of Words to be programmed.

3. Use N+1 Bus Write operations to load the address and data for each Word into the Write Buffer. See the constraints on the address c ombinations listed below. The addresses must have the same A5-A21.

4. Finally, use one Bus Write operation to issue the final cycle to confirm the command and start the Program operation.

Invalid address combinations or failing to follow the correct sequence of Bus Write cycles will set an error in the Status Register and abort the operation without affecting the data in the memory array. The Status Register should be cleared before re-issuing the command.

See Appendix C, Figure 23, Write to Buffer and Program Flowchart and Pseudo Code, for a suggested flowchart on using the W rite to Buf fer and Program command.

Program/Erase Suspend Command. The Program/Erase Suspend command is used to pause a Word Program, Write to Buffer and Program or Erase operation. The command will only be accepted during a Program or an Erase operation. It can be issued at any tim e during an Erase operation but will only be accepted during a Word Pro-

gram or Write to Buf fer and P rogram comman d if the Program/Erase Controller is running.

One Bus Write cycle is required to i ssue the P rogram/Erase Suspend command and pause the Program/Erase Controller. Once the command is issued it is necessary to poll the Program/Erase Controller Status bit (SR7) to find out when the Program/Erase Controller has paused; no other commands will be accepted until the Program/ Erase Controller has paused. After the Program/ Erase Controller has paused, the memory will continue to output the Status Register until another command is issued.

During the polling period between issuing the Program/Erase Suspend command and the Program/ Erase Controller pausing it is possible for the operation to complete. Once the Program/Erase Controller Status bit (SR7) indicates that the Program/Erase Controller is no longer active, the Program Suspend Status bit (SR2) or the Erase Suspend Status bit (SR6) can be used to determine if the operation has completed or is suspended. For timing on the delay between issuing the Program/Erase Suspend command and the Program/Erase Controller pausing see Table 9.

During Program/Erase Suspend the Read Memory Array, Read Status Register, Read Elect ronic Signature, Read Query and Program/Erase Resume commands will be accepted by the Command Interface. Additionally, if the suspended operation was Erase then the W rite to B uffer and Program, and the Program Suspend commands will also be ac cepted. W hen a program o peration is completed inside a Block Erase Suspend the Read Memory Array command m ust be issued to reset the device in Read mode, then the Erase Resume command can be issued to complete the whole sequence. Only the blocks not being erased may be read or programmed correctly.

See Appendix C, Figure 24 , Program Suspend & Resume Flowchart and Pseudo Code, and Figure 26, Erase Suspend & Resume Flowchart and Pseudo Code, for suggested flowcharts on using the Program/Erase Suspend command .

Program / Erase Resum e Command. The Program/Erase Resume command can be used to restart the Program/Erase Controller after a Program/Erase Suspend operat ion h as paused it. One Bus Write cycle is required to i ssue the P rogram/Erase Resume command. Once the command is issued subsequ ent Bus Read operations read the Status Register.

Set Conf ig uration Regis te r Com m and. Th e Set Configuration Register command is used to write a new value to t he B urst Configurat ion Control Register which defines the burst length, type, X and Y latencies, Synchronous/Asynchronous

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M58LW032C

Read mode and the valid Clock edge configuration.

Two Bus Writ e cycles a re required to i ssue the Set Configuration Register command. Once the command is issued the memory returns to Read mode as if a Read Memory Array command had been issued.

The value for the Configuration Register is presented on A1-A16. CR0 is on A1, CR1 on A2, etc.; the other address bits are ignored.

Block Protect Command. The Block Protect command is used to protec t a block and prevent Program or Erase operations from changing the data in it. Two Bus Write cycles are required to issue the Block Protect command; the second Bus Write cycle latches the block address in the internal state machine and sta rts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits.

During the Block Protect operation the memory will only accept the Read Sta tus Register command. All other commands will be ignored. Typical Block Protection times are given in Table 9.

The Block Protection bits are non-volatile, once set they remain set through reset and powerdown/power-up. They ar e cleared by a Blocks Unprotect command.

See Appendix C, Figure 27, Block Protect Flowchart and Pseudo Code, for a suggested flowchart on using the Block Protect command.

Blocks Unprotect Command. The Blocks Unprotect command is used to unprotect all of the blocks. Two Bus Write cycles are requir ed to issue the Blocks Unprotect command ; the second Bus Write cycle starts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Stat us Register for details on the definitions of the Status Register bits.

During the Block Unprotect operation the memory will only accept the Read Status Register command. All other commands will be ignored. Typical Block Protection times are given in Table 9.

See Appendix C, Figure 28, Block Unprotect Flowchart and Pseudo Code, for a suggested flowchart on using the Block Unprotect command.

Protectio n Register Program Comm and. The Protection Register Program c omm and is used to Program the 64 bit user segment of the Protection Register. The segment is programmed 16 bits at a

time. Two write cycles are required to issue the Protection Register Program command.

■ The first bus cycle sets up the Protection

■ The second latches the Address and the Data to

be written to the Protection Register and starts the Program/Erase Controller.

Read operations output the Status Register content after the programming has started.

The user-programmable segment can be locked by programming bi t 1 of the Protection Register

Lock location to ‘0’ (see Table 8). Bit 0 of the Protection Register Lock location locks the factory programmed segment and is programmed to ‘0’ in the factory. The locking of the Protec tion Regi ster is not reversible, once the lock bits are programmed no further changes c an be m ade to the values stored in the Protection Register, see Figure 8, Protection Register Memory Map. Attemp ting to program a previously protected Protection Register will result in a Status Register error.

The Protection Register Program cannot be suspended. See Appendix C, Figure 29, Protection Register Program Flowchart and Pseudo Code, for the flowchart for using the P rotection Regi ster Program command.

Configure STS Command.

The Configure STS command is used to configure the Status/(Ready/Busy) pin. After power-up or reset the STS pin is configured in Ready/Busy mode. The pin can be configured in Status mode using the Configure STS command (refer to Status/(Ready/Busy) section for more details.

Two write cycles are required to issue the Configure STS command.

■ The first bus cycle sets up the Configure STS

command.

■ The second specifies one of the four possible

configurations (refer to Table 6, Configuration Codes):

– Ready/Busy mode – Pulse on Erase complete mode – Pulse on Program complete mode – P ulse on E rase or Program complete mode

The device will not accept the Configure STS command while the Program/Erase controller is busy or during Program/Erase Suspend. When STS pin is pulsing it remains Low for a typical time of 250ns. Any invalid Configuration Code will set an error in the Status Register.

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Page 23

Table 5. Commands

Bus Operations

Command

Cycles

Read Memor y Array

2 Write X FFh Read RA RD

≥

Read Electronic Signature ≥ 2 Write X 90h Read

Read Status Register 2 Write X 70h Read X SRD

Read Query

2 Write X 98h Read

≥

Clear Status Register 1 Write X 50h

Block Erase 2 Write X 20h Write BA D0

Word Program 2 Write X

Write to Buffer and

Program

4 + N Write BA E8h Write BA N Write PA PD Write X D0h

Program/Erase Suspend 1 Write X B0h

Program/Erase Resume 1 Write X D0h

Set Configuration Register 2 Write X 60h W rite BCR 03h

Block Protect 2 Write X 6 0h Write BA 01h

Blocks Unprotect 2 Write X 60h Write X D0h

1st Cycle 2nd Cycle Subsequent Final

Op. Addr. Data Op. Addr. Data Op. Addr. Data Op. Addr. Data

(3)

(4)

IDD

40h

Write PA PD

10h

ID A

M58LW032C

(3)

(4)

Protection Register

Program

2 Write X C0h Write PRA PRD

Configure STS command 2 Write X B8h Write X CC

Note: 1. X Don’t Care; RA Read Address, RD Read Data, IDA Identifier Address, IDD Identifier Data, SRD Status Register Data, PA Program

Address; PD Prog ram Data, QA Qu ery Add ress, Q D Q uery Dat a, BA A ny address in the Block, BC RConfigur at ion Re gi ster v al ue, CC Configuration Code.

2. Base Address, refer to Fi gure 8 and Tabl e 8 f or more inform at i on.

3. For Identifier addres ses and data refer to table 7, Rea d Electronic Signature.

4. For Query A ddress and Data refer to Appendix B, CFI.

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Page 24

M58LW032C

Table 6. Configuration Codes

Configuration

Code

00h 0 0 Ready/Busy

01h 0 1

02h 1 0

03h 1 1

Note: 1. DQ2-DQ7 are reserved

2. When STS pin is pulsing it remains Low for a typical time of 250ns.

Table 7. Read Electronic Signature

Manufacturer Code 000000h 0020h

DQ1 DQ2 Mode STS Pin Description

during P/E

Pulse on Erase complete

Pulse on Program complete

Pulse on Erase or Program complete

operations Hi-Z when the memory is ready

Pulse Low then High when operation

completed

(2)

The STS pin is Low during Program and Erase operations and high impedance when the memory is ready for any Read, Program or Erase operation.

Supplies a system interrupt pulse at the end of a Block Erase operation.

Supplies a system interrupt pulse at the end of a Program operation.

Supplies a system interrupt pulse at the end of a Block Erase or Program operation.

Code Address (A21-A1) Data (DQ15-DQ0)

Device Code 000001h 8822h

Block Protection Status SBA+02h

0000h (Block Unprotected)

0001h (Block Protected)

Configuration Register 000005h BCR Protection Register

Note: 1. SBA i s t he Start Base Ad dress of each block, BCR is Configu ration Regist er data, PRD is Protection Regi ster Data.

2. Base Address, refer to Fi gure 8 and Table 8 for more information.

000080h

(2)

PRD

Table 8. Read Protection Register

Word Use A8A7A6A5A4A3A2A1

Lock Factory, User 1 0 000000

0 Factory (Unique ID) 1 0 000001 1 Factory (Unique ID) 1 0 000010 2 Factory (Unique ID) 1 0 000011 3 Factory (Unique ID) 1 0 000100 4 User 10000101 5 User 10000110 6 User 10000111 7 User 10001000

24/61

Page 25

Figure 8. Prot ect i on Register Mem o ry Map

WORD

ADDRESS

88h

User Programmable

85h 84h

81h 80h

Unique device number

Protection Register Lock 1 0

Table 9. Program , Erase Times and Program Erase Endurance Cycles

Parameters

Min

Block (1Mb) Erase 1.2 Chip Program (Write to Buffer) 24 Chip Erase Time 37 Program Write Buffer

M58LW032C

(1,2)

Typ

(3)

192

Max

4.8 72

110 576

M58LW032C

(2)

(4)

AI05501

Unit

s s s

µs

Word/Byte Program Time (Word/Byte Program command)

Program Suspend Latency Time 1 Erase Suspend Latency Time 1 Block Protect Time 18 Blocks Unprotect Time 0.75

20 25 30

1.2

(4)

(5)

µs

µs µs µs

(5)

Program/Erase Cycles (per block) 100,000 cycles Data Retention 20 years

Note: 1. Typical values m easured at room temperature and nominal voltages.

2. Sampled, but not 100% tested.

3. Effective byte programming time 6µs, effective word prog ram m i ng time 12µ s.

4. Maximu m value measured at worst case conditions for bot h temperatu re and V

5. Maximu m value measured at worst case conditions for bot h temperatu re and V

after 100,000 program/erase cycles.

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M58LW032C

STATUS REGISTER

The Status Register provides information on the current or previous Program, Erase, Block Protect or Blocks Unprotect operation. The various bits in the Status Register convey information and errors on the operation. They are output on DQ7-DQ0.

To read the Status Register the Read Status Register command can be issued. The Status Register is automatically read after Program, Erase, Block Protect, Blocks Unprotect and Program/Erase Resume commands. The Status Register can be read from any address.

The Status Register can only be read using Asynchronous Bus Read or Single Synchronous Read operations. Once the memory returns to Read Memory Array mode the bus will resume the setting in the Configuration Register automatically.

The contents of the Status Register can be updated during an Erase or Program operation by toggling the Output Enable pin or by dis-activating (Chip Enable, V able and Output Enable, V

Status Register bits SR 5, S R4, SR 3 and SR1 are associated with various error conditions and can only be reset with the Clear Status Register command. The Status Register bits are summarized in Table 10, Status Register Bits. Refer to Table 10 in conjunction with the following text descriptions.

Program/Erase Controller Status Bit (SR7). The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is act ive or inactive. When the Program/Erase Controller Status bit is Low, V is active and all other Status Register bits are High Impedance; when the bit is High, V gram/Erase Controller is inactive.

The Program/Erase Controller Status is Low immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is High.

During Program, Erase, Block Protect and Blocks Unprotect operations the Program/Erase Controller Status bit can be polled to find the end of the operation. The other bits in the Status Register should not be tested until the Program/Erase Controller completes the operation and the bit is High.

After the Program/Erase Cont roller completes its operation the Erase S tatus, Program Status and Block Protection Status bits should be tested for errors.

Erase Suspend Status Bit ( SR6). The Erase Suspend Status bit indicates that an Erase operation has been suspended and is waiting to be resumed. The Erase Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller

) and then reactivating (Chip En-

, the Program/Erase Controller

) the device.

, the Pro-

inactive); after a Program/Erase Suspend command is issued the memory may still complete the operation rather than entering the Suspend mode.

When the Erase Suspend Statu s bit is Low, V

the Program/Erase Controller is active or has completed its operation; when the bit is High, V

, a Program/Erase Suspend com mand has been issued and the memory is waiting for a Program/ Erase Resume command.

When a Program/Erase Re sume command is issued the Erase Suspend Status bit returns Low.

Erase Status Bit (SR5). The Erase Status bit can be used to identify if the memory has failed to verify that the block has erased correctly or that all blocks have been unprotected successfully. The Erase Status bit should be read once the Program/ Erase Controller Status bit is High (Program/Erase Controller inactive).

When the Erase St atu s bit i s Low, V

, the mem-

ory has successfully verified that the block has erased correctly or all blocks have been unprotected successfully. When the Erase Status bit is High, V

, the erase operation has failed. De-

pending on the cause of the failure othe r Status Register bits may also be set to High, V

■ If only the Erase Status bit (SR5) is set High,

then the Program/Erase Controller has

OH,

applied the maximum number of pulses to the block and still failed to verify that the block has erased correctly or that all the blocks have been unprotected successfully.

■ If the failure is due to an erase or blocks

unprotect with V bit (SR3) is also set High, V

■ I f the failure is due to an erase on a protected

low, VOL, then V

PEN

Status

PEN

block then Block Protection Status bit (SR1) is also set High, V

■ If the failure is due to a program or erase

incorrect command sequence then Program Status bit (SR4) is also set High, V

Once set High, the Erase Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail.

Program Status Bit (SR4). The Program Status bit is used to identify a Program or Block Protect failure. The Program Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive).

When the Program Status bit is Low, V

, the memory has successfully verified that the Write Buffer has programmed correc tly or the block is protected. When the Program Status bit is High, V

, the program or block protect operation has

26/61

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M58LW032C

failed. Depending on the cause of the failure other Status Register bits may also be set to High, V

■ If only the Program Status bit (SR4) is set High,

then the Program/Erase Controller has

OH,

applied the maximum number of pulses to the byte and still failed to verify that the Write Buffer has programmed correctly or that the Block is protected.

■ If the failure is due to a program or block protect

with V is also set High, V

■ If the failure is due to a program on a protected

low, VOL, then V

PEN

Status bit (SR3)

PEN

block then Block Protection Status bit (SR1) is also set High, V

■ If the failure is due to a program or erase

incorrect command sequence then Erase Status bit (SR5) is also set High, V

Once set High, the Program Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail.

Status Bit (SR3). The V

PEN

Status bit can

PEN

be used to identify if a Program, Erase, Block Protection or Block Unprotection operation has b een attempted when V

When the V

PEN

is Low, VIL.

PEN

Status bit is Low, VOL, no Program, Erase, Block Protection or Block Unprotection operations have been attempted with V

PEN

Low, VIL, since the last Clear S tatus Register command, or hardware reset. When the V bit is High, V

, a Program, Erase, Block Protec-

PEN

Status

tion or Block Unprotection operation has been a ttempted with V

Once set High, the V

Low, VIL.

PEN

Status bit can only be re-

PEN

set by a Clear Status Register command or a hardware reset. If set High it should be reset befo re a new Program, Erase, Block Protection or Block Unprotection command is issued, otherwise the new command will appear to fail.

Program Suspend Status Bit (SR2). The Program Suspend Status bit indicates that a Program

operation has been sus pended and is waiting to be resumed. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive); after a Program/Erase Suspend command is issued the memory may still complete the operation rather than entering the Suspend mode.

When the Program Suspend Status bit is Low,

, the Program/Erase Controller is active or has

completed its operation; when the bit is High, V a Program/Erase Suspend command has been issued and the memory is waiting for a Program/ Erase Resume command.

When a Program/Erase Re sume command is issued the Program Suspend Status bit returns Low.

Block Protection Status Bit (SR1). The Block Protection Status bit can be used to identify if a Program or Erase operation has tried to modify the contents of a protected block.

When the Block Protection Status bit is Low, V no Program or Erase operations have been attempted to protected blocks since the last Clear Status Register command or hardware reset; when the Block Protection Status bit is High, V a Program (Program St atus bit SR4 set High) or Erase (Erase Status bit SR5 set High) operation has been attempted on a protected block.

Once set High, the Block Protection Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail.

Reserved (SR0). SR0 of the Status Register is reserved. Its value should be masked.

27/61

Page 28

M58LW032C

Table 10. Status Register Bits

OPERATION SR7 SR6 SR5 SR4 SR3 S R2 SR1 RB

Program/Erase Controller active 0 Hi-Z Write Buffer not ready 0 Hi-Z Write Buffer ready 1 000000Hi-Z 80h Write Buffer ready in Erase Suspend 1 100000Hi-Z C0h Program suspended 1 000010Hi-Z 84h Program suspended in Erase Suspend 1 100010Hi-Z C4h Program/Block Protect complete d

successfully Program completed successfully in Erase

Suspend Program/Block protect failure due to

incorrect command sequence Program failure due to incorrect command

sequence in Erase Suspend Program/Block Protect failure due to

error

PEN

Program failure due to V

error in Erase

PEN

Suspend

1000000Hi-Z 80h

1100000Hi-Z C0h

1011000Hi-Z B0h

1111000Hi-Z F0h

1001100Hi-Z 98h

1101100Hi-Z D8h

Result

(Hex)

N/A N/A

Program failure due to Block Protection 1 001001Hi-Z 92h Program failure due to Block Protection in

Erase Suspend Program/Block Protect failure due to cell

failure Program failure due to cell failure in Erase

Suspend

1101001Hi-Z D2h

1001000Hi-Z 90h

1101000Hi-Z D0h

Erase Suspended 1 100000Hi-Z C0h Erase/Blocks Unprotect completed

successfully Erase/Blocks Unprotect failure due to

incorrect comman d sequence Erase/Blocks Unprotect failure due to

error

PEN

1000000Hi-Z 80h

1011000Hi-Z B0h

1010100Hi-Z A8h

Erase failure due to Block Protection 1 010001Hi-Z A2h Erase/Blocks Unprotect failure due to

failed cells in Block

1010000Hi-Z A0h

28/61

Page 29

MAXIMUM RATING

Stressing the device above the ratings listed in Table 11, Absolute Maximum Ratings, may cause permanent damage to the device. These are stress ratings only and operation of the dev ice at these or any other conditions above those indicated in the Operating sections of this specification is

Table 11. Absolute Maximum Ratings

Symbol Parameter

M58LW032C

not implied. Exposure to Absol ute Maxim um Ra ting conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.

Value

Unit

Min Max

BIAS

STG

, V

DDQ

Temperature Under Bias –40 125 °C

Storage Temperature –55 150 °C

Input or Output Voltage –0.6 Supply Voltage –0.6 5.0 V

DDQ

+0.6

29/61

Page 30

M58LW032C

DC AND AC PARAMETERS

This section summarizes the operat ing and measurement conditions, and the DC and AC characteristics of the device. The parameters in t he DC and AC characteristics Tables that follow, are derived from tests performed under the Measure-

Table 12. Operating and AC Measurement Conditions

Parameter

Supply Voltage (V Input/Output Supply Voltage (V

Ambient Temperature (T

Load Capacitance (C Clock Rise and Fall Times 3 ns Input Rise and Fall Times 4 ns Input Pulses Voltages Input and Output Timing Ref. Voltages

)

DDQ

)

ment Conditions summarized in Table 12, Operating and AC Measurem ent Conditions. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.

M58LW032C

90, 110

Min Max

2.7 3.6 V

1.8

Grade 1 0 70 °C

Grade 6 –40 85 °C

0 to V

0.5 V

30 pF

DDQ

Units

V V

Figure 9. AC Me asurement In put Ou t put Waveform

DDQ

0.5 V

DDQ

AI00610

Figure 10. AC Measurement Lo a d Cir c ui t

1.3V

DDQ

DEVICE UNDER

TEST

0.1µF

0.1µF CL includes JIG capacitance

Table 13. Capacitance

Symbol Parameter Test Condition Typ Max Unit

OUT

= 0V

68pF 812pF

OUT

Note: 1. TA = 25°C, f = 1 MHz

2. Sampled only, not 100% tested.

Input Capacitance Output Capacitance

1N914

3.3kΩ

AI03459

30/61

Page 31

M58LW032C

Table 14. DC Characteristics

Symbol Parameter Test Condition Min Max Unit

DDB

DD1

DD5

DD2

DD3

Input Leakage Curren t

Output Leakage Current

Supply Current (Random Read)

Supply Current (Burst Read) Supply Current (Standby) Supply Current (Auto Low-Power) Supply Current (Reset/Power-Down) Supply Current (Program or Erase,

Block Protect, Block Unprotect)

0V≤ V

= VIL, G = VIH, f

E E

Program or Erase operation in

≤ V

DDQ

≤

≤V

OUT

DDQ

add

clock

= VIH, RP = V = VIL, RP = V

= V

progress

= 6MHz = 50MHz

±1 µA ±5 µA 20 mA 30 mA 40 40 40 µA

30 mA

V V

DD4

LKO

Supply Current (Erase/Program Suspend)

Input Low Voltage –0.5

Input High Voltage

Output Low Voltage Output High Voltage

= V

= 100µA

= –100µA V

VDD Supply Voltage (Erase and Program lockout)

DDQ

x 0.7 V

–0.2

40 µA

x 0.3

DDQ

+ 0.5

DDQ

0.2 V

V V

31/61

Page 32

M58LW032C

Figure 11. Asynchronous Bus Read AC Waveforms

tAVAV

A1-A21

tELQV

VALID

tAXQXtELQX

tGLQV

tGLQX

tAVQV

DQ0-DQ15

Note: As ynchronous Re ad CR15 = 1

Table 15. Asynchronous Bus Read AC Characteristics .

Symbol Parameter

AVAV

AVQV

ELQX

ELQV

GLQX

GLQV

EHQX

GHQX

AXQX

EHQZ

GHQZ

Address Valid to Address Valid Min 90 110 ns Address Valid to Output Valid Max 90 110 ns Chip Enable Low to Output Transition Min 0 0 ns Chip Enable Low to Output Valid Max 90 110 ns Output Enable Low to Output Transition Min 0 0 ns Output Enable Low to Output Valid Max 25 25 ns Chip Enable High to Output Transition Min 0 0 ns Output Enable High to Output Transition Min 0 0 ns Address Transition to Output Transition Min 0 0 ns Chip Enable High to Output Hi-Z Max 25 25 ns Output Enable High to Output Hi-Z Max 20 20 ns

tEHQZ tEHQX

tGHQZ tGHQX

OUTPUT

AI06255

M58LW032C

Unit

90 1 10

32/61

Page 33

Figure 12. Asynchronous Latch Controlled Bus Read AC Waveforms

M58LW032C

A1-A21

tAVLL

DQ0-DQ15

Note: Asynchronous Read CR15 = 1

tAVLH

VALID

tELLL

tLLLH tELLH

tGLQV tGLQX

tLLQX tLLQV

tLHAX

tEHLXtLHLL

tEHQZ tEHQX

OUTPUT

Table 16. Asynchronous Latch Controlled Bus Read AC Characteris tics

Symbol Parameter

AVLL

AVLH

LHLL

LLLH

ELLL

ELLH

LLQX

LLQV

LHAX

GLQX

GLQV

EHLX

Note: Fo r other timings see Table 15, A synchronous Bus Read Characteristics.

Address Valid to Latch Enable Low Min 0 0 ns Address Valid to Latch Enable High Min 10 10 ns Latch Enable High to Latch Enable Low Min 10 10 ns Latch Enable Low to Latch Enable High Min 10 10 ns Chip Enable Low to Latch Enable Low Min 0 0 ns Chip Enable Low to Latch Enable High Min 10 10 ns Latch Enable Low to Output Transition Min 0 0 ns Latch Enable Low to Output Valid Min 90 110 ns Latch Enable High to Address Transition Min 6 6 ns Output Enable Low to Output Transition Min 0 0 ns Output Enable Low to Output Valid Max 25 25 ns Chip Enable High to Latch Enable Transition Min 0 0 ns

90 110

tGHQZ

tGHQX

AI06256b

M58LW032C

Unit

33/61

Page 34

M58LW032C

Figure 13. Asynchronous Page Read AC Waveforms

A1-A2

A3-A21

tAVQV

DQ0-DQ15

Note: As ynchronous Re ad CR15 = 1

VALID VALID

VALID

tELQV tELQX

tGLQV

tGLQX

OUTPUT OUTPUT

Table 17. Asynchronous Page Read AC Characteristics

Symbol Parameter

AXQX1

AVQV1

Note: Fo r other timings see Table 15, A synchronous Bus Read Characteristics.

Address Transition to Output Transition Min 6 ns Address Valid to Output Valid Max 25 ns

tAVQV1

tAXQX1

tAXQX

tEHQZ

tEHQX

tGHQZ tGHQX

AI06257

M58LW032C

Unit

90, 110

34/61

Page 35

Figure 14. Asynchronous Write AC Waveform, Write Enable Controlled

M58LW032C

A1-A21

DQ0-DQ15

PEN

tELWL

tGHWL

tAVWH

tVPHWH

VALID

tWLWH

tDVWH

tWHEH

INPUT

tWHAX

tWHDX

tWHBL

tWHWL

tWHGL

Figure 15. Asynchronous Lat ch C on t rol le d W ri te AC Waveform, Write Ena bl e Cont ro ll ed

AI06258

A1-A21

DQ0-DQ15

PEN

tELLL

tELWL

tAVLH

VALID

tLLLH

tWLLH

tLHWH

tWLWH

tDVWH

tVPHWH

INPUT

tLHAX

tWHEH

tWHDX

tWHBL

tWHWL

tLHGL

tWHGLtGHWL

AI06259

35/61

Page 36

M58LW032C

Table 18. Asynchronous Write and Latch Controlled Write AC Characteristics, Write Enable Controlled.

Symbol Parameter

AVLH

AVWH

DVWH

ELWL

ELLL

LHAX

LHGL

LHWH

LLLH

LLWH

VPHWH

WHAX

WHBL

WHDX

WHEH

GHWL

WHGL

WHWL

WLWH

WLLH

Address Valid to Latch Enable High Min 10 ns Address Valid to Write Enable High Min 50 ns Data Input Valid to Write Enable High Min 50 ns Chip Enable Low to Write Enable Low Min 0 ns Chip Enable Low to Latch Enable Low Min 0 ns Latch Enable High to Address Transition Min 6 ns Latch Enable High to Output Enable Low Min 95 ns Latch Enable High to Write Enable High Min 0 ns Latch Enable low to Latch Enable High Min 10 ns Latch Enable Low to Write Enable High Min 50 ns Program/Erase Enable High to Write Enable High Min 0 ns Write Enable High to Address Transition Min 0 ns Write Enable High to Ready/Busy low Max 500 ns Write Enable High to Input Transition Min 0 ns Write Enable High to Chip Enable High Min 0 ns Output Enable High to Write Enable Low Min 20 ns Write Enable High to Output Enable Low Min 35 ns Write Enable High to Write Enable Low Min 30 ns Write Enable Low to Write Enable High Min 70 ns Write Enable Low to Latch Enable High Min 10 ns

M58LW032C

90, 110

Unit

36/61

Page 37

Figure 16. Asynchronous Write AC Waveforms, Chip Enable Controlled

M58LW032C

A1-A21

DQ0-DQ15

PEN

tWLEL

tAVEH

VALID

tELEH

tDVEH

tVPHEH

INPUT

tEHAX

tEHWH

tEHDX

tEHBL

tEHEL

tEHGLtGHEL

Figure 17. Asynchronous Latch Controlled Write AC Waveforms, Chip Enable Controlled

AI06260

A1-A21

DQ0-DQ15

PEN

tWLLL

tWLEL

tGHEL

tAVLH

tAVEH

VALID

tLLLH

tELLH

tELEH

tDVEH

tVPHEH

INPUT

tLHAX

tEHAX

tLHEH

tEHWH

tEHDX

tEHBL

tEHEL

tLHGL

tEHGL

AI06261

37/61

Page 38

M58LW032C

Table 19. Asynchronous Write and Latch Controlled Write AC Characteristics, Chip Enable Controlled

Symbol Parameter

AVLH

AVEH

DVEH

EHAX

EHBL

EHDX

EHWH

EHGL

EHEL

ELEH

ELLH

GHEL

LHAX

LHGL

LHEH

LLLH

LLEH

VPHEH

WLEL

WLLL

Address Valid to Latch Enable High Min 10 ns Address Valid to Chip Enable High Min 50 ns Data Input Valid to Chip Enable High Min 50 ns Chip Enable High to Address Transition Min 0 ns Chip Enable High to Ready/Busy low Max 500 ns Chip Enable High to Input Transition Min 0 ns Chip Enable High to Write Enable High Min 0 ns Chip Enable High to Output Enable Low Min 35 ns Chip Enable High to Chip Enable Low Min 30 ns Chip Enable Low to Chip Enable High Min 70 ns Chip Enable Low to Latch Enable High Min 10 ns Output Enable High to Chip Enable Low Min 20 ns Latch Enable High to Address Transition Min 6 ns Latch Enable High to Output Enable Low Min 35 ns Latch Enable High to Chip Enable High Min 0 ns Latch Enable low to Latch Enable High Min 10 ns Latch Enable Low to Chip Enable High Min 50 ns Program/Erase Enable High to Chip Enable High Min 0 ns Write Enable Low to Chip Enable Low Min 0 ns Write Enable Low to Latch Enable Low Min 0 ns

M58LW032C

Unit

90, 110

38/61

Page 39

Figure 18. Synchronous Burst Read AC Waveform

M58LW032C

AI06262

X+2Y+1 X+2Y+2

X+2YX+YX

X-1

tKHAX

tLHAX

tEHQX

tEHQZ

tGHQZ

tGHQX

tGLKH

Q2 Q3

tKHQX

tQVKH

tKHQV

tKHLL

Note: Vali d Clock Edge = Ri sing (CR6 = 1)

VALID

A1-A21

tLLKH

tLLLH

tELLH

tELKH

tAVLH

tAVKH

DQ0-DQ15

39/61

Page 40

M58LW032C

Figure 19. Synchronous Burst Read - Continuous - Valid Data Ready Output

(2)

Output

Note: 1. Valid Data Ready = Valid Low during valid clock edge (CR8 = 0)

2. V= Valid output, NV= Not Valid output.

3. R is an open drain out put with an interna l pull up re sistor of 1MΩ. Depend ing on t h e Va lid Da ta R eady pin c apac ita nce load an external pul l up resistor must b e chosen accor di ng to the system clock period.

V V NV NV V V

tRLKH

(3)

Table 20. Synchronous Burst Read AC Characteristics

Symbol Parameter

AVKH

AVLH

ELKH

ELLH

GLKH

KHAX

KHLL

KHLH

KHQX

LLKH

LLLH

KHQV

QVKH

RLKH

Note: Fo r other timings see Table 15, A synchronous Bus Read Characteristics.

Address Valid to Active Clock Edge Min 7 ns Address Valid to Latch Enable High Min 10 ns Chip Enable Low to Active Clock Edge Min 10 ns Chip Enable Low to Latch Enable High Min 10 ns Output Enable Low to Valid Clock Edge Min 20 ns Valid Clock Edge to Address Transition Min 5 ns Valid Clock Edge to Latch Enable Low Min 0 ns Valid Clock Edge to Latch Enable High Min 0 ns Valid Clock Edge to Output Transition Min 3 ns Latch Enable Low to Valid Clock Edge Min 6 ns Latch Enable Low to Latch Enable High Min 7 ns Valid Clock Edge to Output Valid Max 15 ns Output Valid to Active Clock Edge Min 5 ns Valid Data Ready Low to Valid Clock Edge Min 5 ns

M58LW032C Unit

90, 110

AI05510

40/61

Page 41

Figure 20. Reset, Power-Down and Power-up AC Waveform

E, G

DQ0-DQ15

tPHQV

tVDHPH tPLPH

VDD, VDDQ

M58LW032C

tPLRH

Power-Up and Reset

Table 21. Reset, Power-Down and Power-u p AC Charac teris tics

Symbol Parameter

PHQV

PLPH

PLRH

VDHPH

Reset/Power-Down High to Data Valid Max 130 150 ns Reset/Power-Down Low to Reset/Power-Down High Min 100 100 ns Reset/Power-Down Low to Ready High Max 30 30 µs

Supply Voltages High to Reset/Power-Down High Min 0 0 µs

Reset during Program or Erase

AI05521

M58LW032C

Unit

90 110

41/61

Page 42

M58LW032C

PACKAGE MECHANICAL

Figure 21. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Outline

1 N

N/2

DIE

TSOP-a

Note: Drawing is not to scale.

LA1 α

Table 22. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package M echa nical Data

Symbol

Typ Min Max Typ Min Max

A 1.20 0.0472 A1 0.05 0.15 0.0020 0.0059 A2 0.95 1.05 0.0374 0.0413

B 0.17 0.27 0.0067 0.0106

C 0.10 0.21 0.0039 0.0083 D 19.80 20.20 0.7795 0.7953

mm inches

D1 18.30 18.50 0.7205 0.7283

E 13.90 14.1 0 0.5472 0.5551

e 0.50 – – 0.0197 – –

L 0.50 0.70 0.0197 0.0276

N56 56

CP 0.10 0.0039

42/61

0° 5° 0° 5°

Page 43

Figure 22. TBGA64 10x13mm - 8x8 ball array, 1mm pitch, Pac kage Outline

M58LW032C

ddd

BGA-Z23

Note: Drawing is not to scale.

E1E

BALL "A1"

Table 23. TBGA64 10x13mm - 8x8 ball array, 1mm pitch, Package Mec han ica l Data

Symbol

Typ Min Max Typ Min Max

A 1.20 0 0.0472 A1 0.300 0.200 0.350 0.01 18 0.0079 0.0138 A2 0.850 0.0335

b 0.400 0.500 0.0157 0 .0197

D 1 0.000 9.900 10.100 0.3937 0.3898 0.3976

millimeters inches

D1 7 .000 – – 0.2756 – –

ddd 0.100 0.0039

e 1 .000 – – 0.0394 – –

E 13.000 1 2.900 13.1 00 0.5118 0.5079 0.5157 E1 7.000 – – 0.2756 – – FD 1.500 – – 0.0591 – – FE 3 .000 – – 0.1181 – – SD 0.500 – – 0.0197 – – SE 0.500 – – 0.0197 – –

43/61

Page 44

M58LW032C

PART NUMBERING

Table 24. Ordering Information Scheme

Example: M58LW032C 110 N 1 T

Device Type

M58

Architecture

L = Page Mode, Burst

Operating Voltage

W = V

Device Function

032C = 32 Mbit (x16), Uniform Block

Speed

90 = 90ns 110 = 110ns

= 2.7V to 3.6V; V

DDQ

= 1.8 to V

Package

N = TSOP56: 14 x 20 mm ZA = TBGA64: 10 x 13mm, 1mm pitch

Temperature Range

1 = 0 to 70 °C 6 = –40 to 85 °C

Option

Blank = Standard Packing T = Tape & Reel Packing E = Lead-free Package, Standard Packing F = Lead-free Package, Tape & Reel Packing

Note: Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Pac kage, etc...) or for furthe r information on any aspect of this de-

vice, please contact the ST Sales Office nearest to you.

44/61

Page 45

APPENDIX A. BLOCK ADDRESS TABLE

Table 25. Block Addresses

Block

Number

32 1F0000h-1FFFFFh 31 1E0000h-1EFFFFh 30 1D0000h-1DFFFFh 29 1C0000h-1CFFFFh 28 1B0000h-1BFFFFh 27 1A0000h-1AFFFFh 26 190000h-19FFFFh 25 180000h-18FFFFh 24 170000h-17FFFFh 23 160000h-16FFFFh 22 150000h-15FFFFh 21 140000h-14FFFFh

Address Range (x16 Bus Width)

M58LW032C

20 130000h-13FFFFh 19 120000h-12FFFFh 18 110000h-11FFFFh 17 100000h-10FFFFh 16 0F0000h-0FFFFFh 15 0E0000h-0EFFFFh 14 0D0000h-0DFFFFh 13 0C0000h-0CFFFFh 12 0B0000h-0BFFFFh 11 0A0000h-0AFFFFh 10 090000h-09FFFFh

9 080000h-08FFFFh 8 070000h-07FFFFh 7 060000h-06FFFFh 6 050000h-05FFFFh 5 040000h-04FFFFh 4 030000h-03FFFFh 3 020000h-02FFFFh 2 010000h-01FFFFh 1 000000h-00FFFFh

45/61

Page 46

M58LW032C

APPENDIX B. COMMON FLASH INTERFACE - CFI

The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to det ermine various electrical and t iming parameters, density information and functions supported by the memory. The system can interface easily with the de-

Table 26. Query Structure Overview

Offset Sub-section Name Description

00h Manufacturer Code 01h Device Code 10h CFI Query Identification String Command set ID and algorithm data offset

1Bh System Interface Information Device timing and voltage information

27h Device Geometry Definition Flash memory layout

(1)

P(h)

A(h)

(SBA+02)h Block Status Register Block-related Information

Note: 1. Offs et 15h defines P whi ch points to the Primary Algor i thm Extended Qu ery Address Ta bl e.

2. Offset 19h defines A whic h poi nts to the Alternate Algorithm Extended Query Addre ss T abl e.

3. SBA is the S t art Base Address for each bloc k.

Primary Algorithm-specific Extended Query Table

(2)

Alternate Algorithm-specific Extended Query Table

vice, enabling the software to upgrade itself when necessary.

When the CFI Query C ommand (RCFI) is issued the device enters CFI Query mode and the data structure is read from the memory. Tables 26 , 27, 28, 29, 30 and 31 show the addresses used to retrieve the data.

Additional information specific to the Primary Algorithm (optional)

Additional information specific to the Alternate Algorithm (optional)

Table 27. CFI - Query Address and Data Output

Address

Note: 1. Query Data are always presented on DQ7-DQ0. DQ15-DQ8 are set to ’0’.

2. Offset 19h defines A which points to the Alternate Algorithm Exten ded Query Address Table.

A21-A1

10h 51h "Q" 11h 52h "R" 12h 59h "Y" 13h 01h 14h 00h 15h 31h 16h 00h 17h 00h 18h 00h 19h 00h

(2)

1Ah

Data Instruction

51h; "Q" Query ASCII String 52h; "R"

Primary Vendor: Command Set and Control Interface ID Code

Primary algorithm extended Query Address Table: P(h)

Alternate Vendor: Command Set and Control Interface ID Code

Alternate Algorithm Extended Query address Table

00h

59h; "Y"

46/61

Page 47

Table 28. CFI - Device Voltage and Timing Specification

Address A21-A1

1Bh 1Ch 1Dh

1Eh

1Fh

20h 08h

21h 0Ah

22h

23h

24h 04h

25h 04h

26h

Note: 1. Bits are coded in Binary Code Decim al , bit7 to bit4 are s caled in Volts and bi t3 to bit0 in mV.

2. Bit7 to bit 4 are coded in Hexadecimal and scaled in Volts whi l e bit3 to bit0 are i n Binary Code Dec i mal and scale d i n 100mV.

3. Not supported.

Data Description

(1)

27h 36h

(2)

00h

04h

00h

04h 2

(3)

00h

VDD Min, 2.7V

(1)

VDD max, 3.6V VPP min – Not Available

(2)

VPP max – Not Available 2n µs typical time-out for Word, DWord prog – Not Available

µs, typical time-out for max buffer write

ms, typical time-out for Erase Block

(3)

2n ms, typical time-out for chip erase – Not Available

x typical for Word Dword time-out max – Not Available

x typical for buffer write time-out max

x typical for individual block erase time-out maximum

2 2n x typical for chip erase max time-out – Not Available

M58LW032C

Table 29. Device Geometry Definition

Address

A21-A1

27h 16h

28h 01h Device Interface

29h 00h Organization Sync./Async. 2Ah 05h 2Bh 00h 2Ch 01h Bit7-0 = number of Erase Block Regions in device 2Dh 1Fh 2Eh 00h

2Fh 00h

30h 02h

Data Description

n where 2

Maximum number of bytes in Write Buffer, 2

is number of bytes memory Size

Number (n-1) of Erase Blocks of identical size; n=64

Erase Block Region Information x 256 bytes per Erase block (128K bytes)

47/61

Page 48

M58LW032C

Table 30. Block Status Register

Address A21-A1 Data Selected Block Information

bit0

(BA+2)h

Note: 1. BA sp ecifies the b lo ck address location, A21-A17.

2. Not Supp orted.

(1)

bit1

bit7-2 0 Reserved for future features

0 Block UnProtected 1 Block Protected 0

Last erase operation ended successfully Last erase operation not ended successfully

(2)

48/61

Page 49

Table 31. Extended Query information

Address

offset

(P)h 31h 50h "P"

(P+2)h 33h 49h "I" (P+3)h 34h 31h Major version number (P+4)h 35h 31h Minor version number

Address

A21-A2

Data (Hex)

x16 Bus Width

Query ASCII string - Extended Table(P+1)h 32h 52h "R"

M58LW032C

Description

(P+5)h 36h CEh Optional Feature: (1=yes, 0=no) (P+6)h 37h 01h (P+7)h 38h 00h

bit0, Chip Erase Supported (0=no) bit1, Suspend Erase Supported (1=yes) bit2, Suspend Program Supported (1=yes) bit3, Protect/UnProtect Supported (1=yes) bit4, Queue Erase Supported (0=no) bit5, Instant Individual Block locking (0=no)

(P+8)h 39h 00h

bit6, Protection bits supported (1=yes) bit7, Page Read supported (1=yes) bit8, Synchronous Read supported (1=yes) bits 9 to 31 reserved for future use

Function allowed after Suspend:

(P+9)h 3Ah 01h

Program allowed after Erase Suspend (1=yes) Bit 7-1 reserved for future use

(P+A)h 3Bh

01h

(P+B)h 3Ch 00h

(P+C)h 3Dh 33h (P+D)h 3Eh 00h

Block Status Register bit0, Block Protect Bit status active (1=yes) bit1, Block Lock-Down Bit status active (not available) bits 2 to 15 reserved for future use

OPTIMUM Program/Erase voltage conditions

(P+E)h 3Fh 01h OTP protection: No. of protection register fields

(P+F)h 40h 80h Protection Register’s start address, least significant bits

(P+10)h 41h 00h Protection Register’s start address, most significant bits (P+11)h 42h 03h

(P+12)h 43h 03h (P+13)h 44h 03h

n where 2 n where 2 Page Read: 2

is number of factory reprogrammed bytes

is number user programmable bytes

Bytes (n = bits 0-7)

(P+14)h 45h 03h Synchronous mode configuration fields (P+15)h 46h 01h

(P+16)h 47h 02h

n where 2 n where 2

n+1

is the number of Words for the burst Length = 4

n+1

is the number of Words for the burst Length = 8

(P+17)h 48h 07h Burst Continuous

Note: 1. Bit7 to bit4 are coded in Hexadecimal and scaled in Volt while bit3 to bit0 are in Binary Code Decimal and scaled in mV.

49/61

Page 50

M58LW032C

APPENDIX C. FLOW CHARTS

Figure 23. Write to Buffer and Program Flowchart and Pseudo Code

Start

Write to Buffer E8h

Command, Block Address

Read Status

Note 1: N+1 is number of Words

to be programmed

SR7 = 1

YES

(1)

Write N

Block Address

Write Buffer Data,

Start Address

Write to Buffer

Timeout

YES

Try Again Later

Note 2: Next Program Address must

have same A5-A21.

Note 3: A full Status Register Check must be

done to check the program operation's

success.

X = 0

X = N

Write Next Buffer Data, Next Program Address

X = X + 1

Program Buffer to Flash

Confirm D0h

Read Status

YES

(3)

SR7 = 1

Full Status

YES

(2)

50/61

End

AI06263b

Page 51

Figure 24. Program Suspend & Resume Flowchart and Pseudo Code

Start

Write B0h

M58LW032C

Write 70h

Read Status

SR7 = 1

YES

SR2 = 1

YES

Write FFh

Read data from

another block

Write D0h

Program Continues

Program Complete

Write FFh

Read Data

Program/Erase Suspend Command: – write B0h – write 70h

do: – read status register

while SR7 = 1

If SR2 = 0, Program completed

Read Memory Array command: – write FFh – one or more data reads from other blocks

Program Erase Resume Command: – write D0h to resume erasure – if the program operation completed then this is not necessary. The device returns to Read Array as normal (as if the Program/Erase Suspend command was not issued).

AI00612b

51/61

Page 52

M58LW032C

Figure 25. Erase Flowchart and Pseudo Code

Start

Write 20h

Write D0h to

Block Address

Read Status

SR7 = 1

YES

SR3 = 0

YES

SR4, SR5 = 0

YES

SR5 = 0

Suspend

Invalid

PEN

Error (1)

Command

Sequence Error

Erase

Error (1)

YES

Suspend

Loop

Erase command: – write 20h – write D0h to Block Address (A12-A17) (memory enters read Status Register after the Erase command)

do: – read status register – if Program/Erase Suspend command given execute suspend erase loop

while SR7 = 1

If SR3 = 1, V – error handler

If SR4, SR5 = 1, Command Sequence error: – error handler

If SR5 = 1, Erase error: – error handler

invalid error:

PEN

YES

SR1 = 0

End

Note: 1. If an error is found, the Status Register must be cleared (Clear Statu s Register Com m and) befo re further P rogram or Erase oper -

ations.

YES

Erase to Protected

Block Error

If SR1 = 1, Erase to Protected Block Error: – error handler

AI00613C

52/61

Page 53

Figure 26. Erase Suspend & Resume Flowchart and Pseudo Code

Start

Write B0h

M58LW032C

Write 70h

Read Status

SR7 = 1

YES

SR6 = 1

YES

Write FFh

Read data from

another block

or Program

Write D0h

Erase Continues

Erase Complete

Write FFh

Read Data

Program/Erase Suspend Command: – write B0h – write 70h

do: – read status register

while SR7 = 1

If SR6 = 0, Erase completed

Read Memory Array command: – write FFh – one or more data reads from other blocks

Program/Erase Resume command: – write D0h to resume the Erase operation – if the Program operation completed then this is not necessary. The device returns to Read mode as normal (as if the Program/Erase suspend was not issued).

AI00615b

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Page 54

M58LW032C

Figure 27. Block Protect Flowchart and Pseudo Code

Start

Write 60h

Block Address

Write 01h

Block Address

Block Protect Command – write 60h, Block Adress – write 01h, Block Adress

Read Status Register

SR7 = 1

YES

SR3 = 1

SR4, SR5 = 1,1

SR4 = 1

Write FFh

YES

Invalid Error

PEN

Invalid Command

Sequence Error

Block Protect

Error

do: – read status register

while SR7 = 1

If SR3 = 1, V

If SR4 = 1, SR5 = 1 Invalid Command Sequence

If SR4 = 1, Block Protect Error

Read Memory Array Command: – write FFh

PEN

Invalid Error

Error

54/61

Block Protect

Sucessful

AI06157b

Page 55

Figure 28. Blocks Unprotect Flowchart and Pseudo Code

Start

M58LW032C

Write 60h

Write D0h

Read Status Register

SR7 = 1

YES

SR3 = 1

SR4, SR5 = 1,1

YES

Invalid Error

PEN

Invalid Command

Sequence Error

Blocks Unprotect Command – write 60h, Block Adress – write D0h, Block Adress

do: – read status register

while SR7 = 1

If SR3 = 1, V

If SR4 = 1, SR5 = 1 Invalid Command

Sequence Error

PEN

Invalid Error

SR5 = 1

Write FFh

Blocks Unprotect

Sucessful

YES

Blocks Unprotect

Error

If SR5 = 1, Blocks Unprotect Error

Read Memory Array Command: – write FFh

AI06158b

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M58LW032C

Figure 29. Protection Register Program Flowchart and Pseudo Code

Start

Write C0h

Write

PR Address, PR Data

Read Status Register

SR7 = 1

YES

SR3, SR4 = 1,1

SR1, SR4 = 0,1

YES

PEN

Protection Register

Invalid Error

Program Error

Protection Register Program Command – write C0h – write Protection Register Address, Protection Register Data

do: – read status register

while SR7 = 1

If SR3 = 1, SR4 = 1 V

If SR1 = 0, SR4 = 1 Protection Register

Program Error

PEN

Invalid Error

SR1, SR4 = 1,1

Write FFh

PR Program

Sucessful

Note: PR = Protection Register

56/61

YES

Protection Register

Program Error

If SR1 = 1, SR4 = 1 Program Error due to

Protection Register Protection

Read Memory Array Command: – write FFh

AI06159b

Page 57

Figure 30. Command Interface and Program E rase Con trolle r Flowchart (a)

WAIT FOR

COMMAND

WRITE

90h

YES

M58LW032C

READ

SIGNATURE

98h

YES

CFI

QUERY

70h

YES

READ

STATUS

50h

CLEAR

STATUS

PROGRAM COMMAND

ERROR

YES

PROGRAM

BUFFER

E8h

LOAD

D0h

YES

20h

YES

ERASE

SET-UP

D0h

YES

READ

ARRAY

(1)

FFh

YES

ERASE

COMMAND

ERROR

Note 1. The Erase command (20h) can only be issued if the flash is not already in Erase Suspend.

AI03618

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M58LW032C

Figure 31. Command Interface and Program E rase Con trolle r Flowchart (b)

WAIT FOR

COMMAND

WRITE

READ

ARRAY

YES

FFh

ERASE

SUSPENDED

YES

READ

STATUS

YES

ERASE

READY

B0h

YES

ERASE

SUSPEND

READY

READ

STATUS

(READ STATUS)

Program/Erase Controller Status bit in the Status Register

READ

STATUS

PROGRAM

COMMAND

ERROR

READ

STATUS

READ

SIGNATURE

CFI

QUERY

PROGRAM

BUFFER

LOAD

D0h

YES

70h

90h

98h

E8h

D0h

READ

ARRAY

YES

READ

STATUS

(ERASE RESUME)

AI03619

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Page 59

Figure 32. Command Interface and Program E rase Con trolle r Flowchart (c).

M58LW032C

WAIT FOR

COMMAND

WRITE

READ

STATUS

YES

PROGRAM

SUSPENDED

YES

READ

ARRAY

FFh

70h

YES

READ

STATUS

YES

PROGRAM

READY

B0h

YES

PROGRAM

SUSPEND

READY

READ

STATUS

(READ STATUS)

Program/Erase Controller Status bit in the Status Register

READ

STATUS

READ

SIGNATURE

CFI

QUERY

READ

ARRAY

YES

90h

98h

D0h

YES

READ

STATUS

(PROGRAM RESUME)

AI00618

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Page 60

M58LW032C

REVISION HIST ORY

Table 32. Document Revision History

Date Version Revision Details

11-Mar-2002 -01 First Issue (Data Brief) 10-Jul-2002 -02 Document expanded to full Product Preview

Revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot

06-Aug-2002 2.1

02-Sep-2002 2.2

16-Dec-2002 2.3

29-Apr-2003 3.0

(revision version 02 equals 2.0). Word Effective Programming Time modified. Program Write Buffer and Block Erase Time parameters modified in Table 9. Speed Class 90ns added. V V

signal descriptions modified.

SSQ

Figure 12, Asynchronous Latch Controlled Bus Read AC Waveforms REVISION HISTORY moved to after the appendices. Table 9, Program, Erase Times

and Program Erase Endurance Cycles table modified. All DU connections changed to NC in Table 4, TBGA64 Connections (Top view through package). V min modified in Table 14, DC Characteristics. Block Protect setup command address modified in Table 5, Commands. Data and Descriptions clarified in CFI Table 31, Extended Query information.

Document promoted to full datasheet. Summary Description clarified, Bus Operations clarified, Smart Protection added, Read Modes section added, Status Register and Configuration Register bit nomenclature modified, V Flowcharts. Lead-free packing options added to Ordering Information Scheme.

, V

, modified.

max and VIH

Invalid Error clarified in

PEN

, VSS and

DDQ

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Page 61

M58LW032C

Information furnishe d is bel i eved to be accurate and reliable. However, STMicroelectroni cs assumes no resp onsibility for t he consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implic ation or otherwise unde r any patent or patent ri ghts of STMicroelectronics. Speci fications me ntioned in th i s publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as crit i cal component s in l i fe support dev i ces or systems wi t hout express written approv al of STMicroelectronics.

The ST log o i s registered trademark of STM i croelect ronics All other nam es are the property of their respective owners

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Morocc o - Singapore - S pai n - Sweden - Swit zerland - United Kingdom - United States

STMicroelect ro n ics GRO UP OF COMPANI ES

www.st.com

61/61

Datasheet M58LW032C Datasheet (SGS Thomson Microelectronics)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES SUMMARY

Figure 1. Packages

TABLE OF CONTENTS

SUMMARY DESCRIPTION

Figure 2. Logi c D iag ram Table 1. Si gn a l Nam es

Figure 3. TSOP56 Connections

Figure 4. TBGA64 Connections (Top view through package)

Figure 5. Block Addresses

SIGNAL DESCRIPTIONS

Erase or Program operation. Data Inputs/Outputs (DQ0-DQ15). The Data In-

BUS OPERATIONS

Address Latch. Address latch operations input valid addresses.

ing edge of Address Latch. Bus Read. Bus Read operations are used to out-

Bus Write. Bus Write operations write Com­mands to the memory or latch addresses and input data to be programmed.

Output Disa bl e . The The Data Inputs/Outputs are high impedance when the Out put Enable i s at

Power-Down. The memory is in Power-Down mode when Reset/Power-Down, RP power consumption is reduced to the Power-Down level, I

Standby. Stan dby disables most of the inte rnal

Table 2. Bus Operations

READ MODES

Asynchronous Read Modes

Synchronous Read Mo de s

CONFIGURATION REGISTER

Burst Length Bit (CR2-CR0). The Burst Length bits set the maximum number of Words that can be output during a Synchronous Burst Read oper­ation.

Table 3. Configuration Register

Tabl e 4. Burst Type Definit ion

Figure 6. Burst Configuration X-1-1-1

Figure 7. Burst Configuration X-2-2-2

COMMAND INTERFACE

Write to Buffer and Program Command. The Write to Buffer and Program comm and is used to program the memory array.

Set Conf ig uration Regis te r Com m and. Th e Set Configuration Register command is used to write a new value to t he B urst Configurat ion Con­trol Register which defines the burst length, type, X and Y latencies, Synchronous/Asynchronous

Table 5. Commands

Table 6. Configuration Codes

Table 7. Read Electronic Signature

Table 8. Read Protection Register

Figure 8. Prot ect i on Register Mem o ry Map

Table 9. Program , Erase Times and Program Erase Endurance Cycles

STATUS REGISTER

Table 10. Status Register Bits

MAXIMUM RATING

Table 11. Absolute Maximum Ratings

DC AND AC PARAMETERS

Table 12. Operating and AC Measurement Conditions

Figure 9. AC Me asurement In put Ou t put Waveform

Figure 10. AC Measurement Lo a d Cir c ui t

Table 13. Capacitance

Table 14. DC Characteristics

Figure 11. Asynchronous Bus Read AC Waveforms

Table 15. Asynchronous Bus Read AC Characteristics .

Figure 12. Asynchronous Latch Controlled Bus Read AC Waveforms

Table 16. Asynchronous Latch Controlled Bus Read AC Characteris tics

Figure 13. Asynchronous Page Read AC Waveforms

Table 17. Asynchronous Page Read AC Characteristics

Figure 14. Asynchronous Write AC Waveform, Write Enable Controlled

Figure 15. Asynchronous Lat ch C on t rol le d W ri te AC Waveform, Write Ena bl e Cont ro ll ed

Table 18. Asynchronous Write and Latch Controlled Write AC Characteristics, Write Enable Controlled.

Figure 16. Asynchronous Write AC Waveforms, Chip Enable Controlled

Figure 17. Asynchronous Latch Controlled Write AC Waveforms, Chip Enable Controlled

Figure 18. Synchronous Burst Read AC Waveform

Figure 19. Synchronous Burst Read - Continuous - Valid Data Ready Output

Table 20. Synchronous Burst Read AC Characteristics

Figure 20. Reset, Power-Down and Power-up AC Waveform

Table 21. Reset, Power-Down and Power-u p AC Charac teris tics

PACKAGE MECHANICAL

Figure 21. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Outline

Table 22. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package M echa nical Data

Figure 22. TBGA64 10x13mm - 8x8 ball array, 1mm pitch, Pac kage Outline

Table 23. TBGA64 10x13mm - 8x8 ball array, 1mm pitch, Package Mec han ica l Data

PART NUMBERING

Table 24. Ordering Information Scheme

APPENDIX A. BLOCK ADDRESS TABLE

Table 25. Block Addresses

APPENDIX B. COMMON FLASH INTERFACE - CFI

Table 26. Query Structure Overview

Table 27. CFI - Query Address and Data Output

Table 28. CFI - Device Voltage and Timing Specification

Table 29. Device Geometry Definition

Bus Write. Bus Write operations write Commands to the memory or latch addresses and input data to be programmed.

Burst Length Bit (CR2-CR0). The Burst Length bits set the maximum number of Words that can be output during a Synchronous Burst Read operation.

Set Conf ig uration Regis te r Com m and. Th e Set Configuration Register command is used to write a new value to t he B urst Configurat ion Control Register which defines the burst length, type, X and Y latencies, Synchronous/Asynchronous