Datasheet M58LW032A Datasheet (SGS Thomson Microelectronics)

32 Mbit (2Mb x16, Uniform Block, Burst)

FEATURES SUMMARY

■ WIDE x16 DATA BUS for HIGH BANDWIDTH

■ SUPPLY VOLTAGE

= 2.7 to 3.6V core supply voltage for Pro-

–V

DD

gram, Erase and Read operations

–V

■ SYNCHRONOUS/ASYNCHRONOUS READ

– Synchronous Burst read
– Asynchronous Random Read
– Asynchronous Ad dress Latch C ontrolled

– Page Read

■ ACCESS TIME

– Synchronous Burst Read up to 56MHz
– Asynchronous Page Mode Read 90/25ns and

– Random Read 90ns, 110ns.

■ PROGRAMMING TIME

– 16 Word Write Buffer
–18µs Word effective programming time

■ 64 UNIFORM 32 KWord MEMORY BLOCKS

■ BLOCK PROTECTION/ UNPROTECTION

■ PROGRAM and ERASE SUSPEND

■ 128 bit PROTECTION REGISTER

■ COMMON FLASH INTERFACE

■ 100, 000 PROGRAM/ERASE CYCLES per

BLOCK

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 0020h
– Device Code M58LW 032A : 8816h

= 1.8V to VDD for I/O Buffers

DDQ

Read

110/25ns

M58LW032A

3V Supp l y Fl ash Memory

Figure 1. Packages

TSOP56 (N)

14 x 20 mm

TBGA

TBGA64 (ZA)

10 x 13 mm

1/61February 2003

M58LW032A

TABLE OF CONTENTS

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. TSOP56 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4. TBGA64 Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 5. Block Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Address Inputs (A1-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Data Inputs/Outputs (DQ0-DQ15 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Reset/Power-Down (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Latch Enable (L).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Clock (K).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Valid Data Ready (R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Ready/Busy (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Program/Erase Enable (V
V

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2

DD

V

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

DDQ

Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

V

SS

V

Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

SSQ

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

PP

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Asynchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Asynchronous Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Asynchronous Latch Controlled Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Asynchronous Page Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Asynchronous Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Asynchronous Latch Controlled Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Automatic Low Power.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Power-Down.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 2. Asynchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Synchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Synchronous Burst Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5

Table 3. Synchronous Burst Read Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Burst Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Read Select Bit (M15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

X-Latency Bits (M13-M11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Y-Latency Bit (M9). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

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M58LW032A

Valid Data Ready Bit (M8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Burst Type Bit (M7).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Valid Clock Edge Bit (M6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Burst Length Bit (M2-M0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 4. Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 5. Burst Type Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 6. Burst Configuration X-1-1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 7. Burst Configuration X-2-2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0

Read Memory Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Read Electronic Signature Comma nd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Read Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0

Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Write to Buffer and Program Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Program/Erase Suspend Comm and . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Set Burst Configuration Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Block Protect Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Blocks Unprotect Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2

Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 6. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 7. Read Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 8. Read Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 8. Protection Register Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 9. Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 25

STATUS REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6

Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Program Status (Bit 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

V

Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

PP

Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Block Protection Status (Bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 10. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 11. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 12. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

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Figure 9. AC Measurement Input Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 10. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 13. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 14. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 11. Asynchronous Bus Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 15. Asynchronous Bus Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 12. Asynchronous Latch Controlled Bus Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . 33

Table 16. Asynchronous Latch Controlled Bus Read AC Characteristics. . . . . . . . . . . . . . . . . . . 33

Figure 13. Asynchronous Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 17. Asynchronous Page Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 14. Asynchronous Write AC Waveform, Write Enable Controlled . . . . . . . . . . . . . . . . . . . 35

Figure 15. Asynchronous Latch Controlled Write AC Waveform, Write Enable Controlled . . . . . . 35

Table 18. Asynchronous Write and Latch Controlled Write AC Characteristics, Write Enable

Controlled.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 16. Asynchronous Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . 37

Figure 17. Asynchronous Latch Controlled Write AC Waveforms, Chip Enable Controlled . . . . . 37

Table 19. Asynchronous Write and Latch Controlled Write AC Characteristics, Chip Enable

Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 18. Synchronous Burst Read AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 19. Synchronous Burst Read - Continuous - Valid Data Ready Output. . . . . . . . . . . . . . . 40

Table 20. Synchronous Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 20. Reset, Power-Down and Power-up AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 21. Reset, Power-Down and Power-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 41

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2

Figure 21. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Outline . . . . . . . 42

Table 22. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Mechanical Data 42

Figure 22. TBGA64 10x13mm - 8x8 ball array 1mm pitch, Package Outline . . . . . . . . . . . . . . . . 43

Table 23. TBGA64 10x13mm - 8x8 ball array, 1mm pitch, Package Mechanical Data. . . . . . . . . 43

PART NUMBERING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 24. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4

APPENDIX A. BLOCK ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 25. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

APPENDIX B. COMMON FLASH INTERFACE - CFI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 26. Query Structure Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 27. CFI - Query Address and Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 28. CFI - Device Voltage and Timing Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 29. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 30. Block Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 31. Extended Query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

APPENDIX C. FLOW CHARTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 23. Write to Buffer and Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 50

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Figure 24. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . 51

Figure 25. Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 26. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . 53

Figure 27. Block Protect Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 28. Blocks Unprotect Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 29. Protection Register Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 56

Figure 30. Command Interface and Program Erase Controller Flowchart (a). . . . . . . . . . . . . . . . 57

Figure 31. Command Interface and Program Erase Controller Flowchart (b). . . . . . . . . . . . . . . . 58

Figure 32. Command Interface and Program Erase Controller Flowchart (c). . . . . . . . . . . . . . . . 59

REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 32. Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5/61

M58LW032A

SUMMARY DESCRIPTION

The M58LW032 is a 32 Mbit (2M b x16) non-vola­tile memory that can be read, erased and repro­grammed. These operations can be performed
using a single low voltage (2.7V to 3.6V) core sup­ply. On power-up the memory defaults to Read
mode with an asynchronous bus where it can be
read in the same way as a non-burst Flash mem­ory.

The memory is divided into 64 blocks of 512Kbit
that can be erased ind ependently so it is possible
to preserve valid data while old data is erased.
Program and Erase command s are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller simplifies the process of
programming or erasing the memory by taking
care of all of the special operations that are re­quired to update the memory contents. The end of
a Program or Erase operation can be detected and
any error conditions identified in the Status Regis­ter. The command set required to control the
memory is consistent with JEDEC standards.

The Write Buffer allows the microprocessor to pro­gram from 1 to 16 Words in parallel, both speeding
up the programming and freeing up the micropro­cessor to perform other work. A Word Program
command is available to program a single word.

Erase can be suspended in order to perform either
Read or Program in any other block and then re­sumed. Program ca n be s uspended to Read data
in any other block and then resum ed. Eac h block
can be programmed and erased over 100,000 cy­cles.

Individual block protection against Program or
Erase is provided for data security. All blocks are

protected during power-up. Th e protection of the
blocks is non-volatile; after power-up the protec­tion status of e ach block is restored to the state
when power was last removed. Software com­mands are provided to allow protection of some or
all of the blocks and to cancel all block protection
bits simultaneously. All Program or Erase opera­tions are blocked when the Program Erase Enable
input Vpp is low.

The Reset/Power-Down pin is used to apply a
Hardware Reset to the memory and to set the de­vice in power-down mode.

In asynchronous mode Chip Enable, Output En­able and Write Enable signals control the bus op­eration of the memory. An Address Latch input can
be used to latch addresses. Tog ether they allow
simple, yet powerful, connection to most micropro­cessors, often without additional logic.

In synchronous mode all Bus Read operations are
synchronous with the Clock. Chip Enable and Out­put Enable select the Bus Read operation and the
address is Latched using the Lat ch Enable input.
The signals are compatible with most micropro­cessor burst interfaces.

The device includes a 128 bit Protection Register.
The Protection Register is divided into two 64 bit
segments, the first one is written by the manufac­turer (contact STMicroelectronics to define the
code to be written here), while the second one is
programmable by the use r. The us er prog ra mma­ble segment can be locked.

The memory is available in TSOP56 (14 x 20 mm)
and TBGA64 (10 x 13mm, 1mm pitch) packages.

6/61

Figure 2. Logic Diagram

M58LW032A

A1-A21

V

PP

W
E

RP

V

V

DDQ

DD

21

16

DQ0-DQ15

M58LW032A

G

RB
R

L

K

V

V

SS

SSQ

AI04320

Table 1. Signal Names

A1-A21 Address inputs
DQ0-DQ15 Data Inputs/Outputs
E
G
K Clock
L
R Valid Data Ready
RB
RP
V

PP

W
V

DD

V

DDQ

V

SS

V

SSQ

NC Not Connected Internally
DU Do Not Use

Chip Enable
Output Enable

Latch Enable

Ready/Busy
Reset/Power-Down
Program/Erase Enable
Write Enable
Supply Voltage
Input/Output Supply Voltage
Ground
Input/Output Ground

7/61

M58LW032A

Figure 3. TSOP56 Connections

A21
A20
A19
A18
A17
A16

V

A15
A14
A13
A12

V

A11
A10

V

NC

DD

PP

RP

A9
A8

SS

A7
A6
A5
A4
A3
A2
A1

1

E

14

M58LW032A

15

28 29

56

43
42

NC
WR

G
RB
DQ15
DQ7
DQ14
DQ6
V

SS

DQ13
DQ5
DQ12
DQ4
V

DDQ

V

SSQ

DQ11
DQ3
DQ10
DQ2
V

DD

DQ9
DQ1
DQ8
DQ0

NC
K
NC

L

AI04321

8/61

Figure 4. TBGA64 Connections (Top view through package)

M58LW032A

87654321

A

B A19A2

C

D A16

E

F

G

A1

A4 A5

K

DU

A6 V

V

A7A3

DQ1

DQ0

DU

SS

A8

A10 A12

A11

DQ10

DQ2

PP

EA9

RP

DDQ

A13

A14

A15

DU

DQ4DQ3

DQ5V

V

DD

DU

DU

DU

DU

DU DU

DQ6

DQ15 RBDQ9DQ8

DQ14

A18

A20

DU

R

A21

A17

GDQ12DQ11

W

H

L

DU

V

DD

V

SSQ

DQ13

V

SS

DQ7

DU

AI04322

9/61

M58LW032A

Figure 5. Block Addresses

M58LW032A
Word (x16) Bus Width
Address lines A1-A21

1FFFFFh

1F8000h

1F7FFFh

1F0000h

00FFFFh

008000h

007FFFh

000000h

Note: Also see Appendix A, T able 25 for a full li st i ng of the Block Addresses

512 Kbit or

32 KWords

512 Kbit or

32 KWords

512 Kbit or

32 KWords

512 Kbit or

32 KWords

AI05500

10/61

SIGNAL DESCRIPTIONS

See Figure 2, Logic Diagram and Table 1, Signal
Names, for a brief overview of the signals connect­ed to this device.

Address Inputs (A1-A21). The Address Inputs are used to select the cells to access in the mem­ory array during Bus Read operations either to read or to program data to. During Bus Write oper­ations they control the commands sent to the Command Interface of the internal state m ac hine. Chip Enable and Latch Enable must be low when selecting the addresses.

The address inputs are latched on the rising edge
of Chip Enable, Write Enable or Latch Enable,
whichever occurs first in a Write operation. The
address latch is transparent when Latch Enable is
low, V

. The address is internally latched in an

IL

Erase or Program operation. Data Inputs/Outputs (DQ0-DQ15). The Data In-

puts/Outputs output the data stored at the selected
address during a Bus Read operation, or are used
to input the data during a program operation. Dur­ing Bus Write operations they repres ent the com­mands sent to the Command Interface of the
internal state machine. When used to input data or
Write commands they are latched on the rising
edge of Write Enable or Chip Enable, whichever
occurs first.

When Chip Enable and Output Enable are both
low, V

, the data bus outputs data from the mem-

IL

ory array, the Electronic Signature, the Block Pro­tection status, the CFI Information or the contents
of the Status Register. The data bus is high imped­ance when the chip is deselected, Output E nable
is high, V
low, V

or the Reset/Power-Down signal is

IH,

. When the Program/Erase Controller is

IL

active the Ready/Busy status is given on DQ7.

Chip Enable (E

). The Chip Enable, E, input acti-

vates the memory control logic, input buffers, de­coders and sense amplifiers. Chip Enable, E
V

deselects the memory and reduces the power

IH

consumption to the Standby level, I

Output Enable (G

). The Output Enable, G, gates

DD1

.

, at

the outputs through the data output buffers during
a read operation. When Output Enable, G

, is at V

IH

the outputs are high impedance. Output Enable,
G

, can be used to inhibit the data ou tput during a

burst read operation.

Write Enable (W

). The Write Enable input, W,

controls writing to the Command Interface, Input
Address and Data latches. Both addresses and
data can be latched on the rising edge of Write En­able (also see Latch Enable, L

Reset/Power-Down (RP

).

). The Reset/Power­Down pin can be used to apply a Hardware Reset
to the me mory.

M58LW032A

A Hardware Reset is achieved by holding Reset/
Power-Down Low, V
Reset/Power-Down is Low, V

, for at least t

IL

, the Status Regis-

IL

ter information is c leared and t he power consump­tion is reduced to power-down level. The device is
deselected and outputs are high impedance. If Re­set/Power-Down goes low, V

,during a Block

IL

Erase, a Write to Buffe r and Program or a Block
Protect/Unprotect the operation is aborted and the
data may be corrupted. In this case the Ready/
Busy pin stays low, V
t

PLPH

+ t

until the completion of the Reset/

PHRH,

, for a ma ximum timin g of

IL

Power-Down pulse.
After Reset/Power-Down goes High, V

memory will be ready for Bus Read and Bus Write
operations after t

. Note that Ready/Busy

PHQV

does not fall during a reset , s ee Rea dy /Busy Ou t­put section.

In an application, it is recommended to either as­sociate the Reset/Power-Down pin, RP
reset signal of the microprocessor, or to ensure
that the Reset/Power-Down pin is kept Low during
Power-on. Otherwise, if a reset operation occurs
while the memory is performing an Erase or Pr o­gram operation, the memory may output the Sta­tus Register information instead of being initialized
to the default Asynchronous Random Read.

Latch Enable (L

). The Bus Interface is config-

ured to latch the Address Inputs on the rising edge
of Latch Enable, L

. In synchronous bus operations
the address is latched on the active edge of the
Clock when Latch Enable is Low, V

IL

ing of Latch Enable, whichever occurs first. Once
latched, the addresses may change without affect­ing the address used by the memory. When Latch
Enable is Low, V

, the latch is transparent.

IL

Clo c k (K). The Clock, K, is used to synchronize the memory with the external bus during Synchro­nous Bus Read operations. The Clock can be con­figured to have an active rising or falling edge. Bus signals are latched on the active edge of the Clock during synchronous bus operations. In Synchro­nous Burst Read m ode the address is latched on the first active clock edge when Latch Enable is low, V

, or on the rising edge of Latch Enable,

IL

whichever occurs first.
During asynchronous bus operations the Clock is

not used. Valid Data Ready (R). The Valid Data Ready

output, R, is an open drain output that can be used
to identify if the memory is ready to output data or
not. The Valid Data Ready output is only active
during Synchronous Burst Read operat ions when
the Burst Length is set to Continuous. The Valid
Data Ready output can be configured to be active
on the clock edge of the invalid data read cycle or

. When

PLPH

, the

IH

, with the

or on the ris-

11/61

M58LW032A

one cycle before. Valid Data Ready Low, VOL, in­dicates that the data is not, or will not be valid. Val­id Data Ready in a high-impedance state indicates
that valid data is or will be available.

Unless Synchronous Burst Read has been select­ed, Valid Data Ready is high-impedance. It may be
tied to other components with the same Valid Data
Ready signal to create a unique System Ready
signal.

The Valid Data Ready, R, output has an internal
pull-up resistor of approximately 1 MΩ powered
from V

, designers should use an external pull-

DDQ

up resistor of the correct value to meet the external
timing requirements for Valid Data Ready rising.
Refer to Figure 19.

Ready/Busy (RB

). The Ready/Busy output, RB,

is an open-drain output that can be used to identify
if the Program/Erase Controller is currently active.
When Ready/Busy is high impedance, the mem o­ry is ready for any Read, Program or Erase opera­tion. Ready/Busy is Low, V

, during Program and

OL

Erase operations. When the device is busy it will
not accept any additional Program or Erase com­mands except Program/Erase Suspend. When the
Program/Erase Controller is idle, or suspended,
Ready Busy can float High through a pull-up resis­tor.

The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.

Ready/Busy is not Low during a reset unless the
reset was applied when the Program/Erase Con-

troller was active; Ready/Busy can rise before Re­set/Power-Down rises.

Program/Erase Enable (VPP). The Program/ Erase Enable input, V

is used to protect all

PP,

blocks, preventing Program and Erase operations
from affecting their data.

Program/Erase Enable must be kept High during
all Program/Erase Controller operations, other­wise the operations is not guaranteed to suc ceed
and data may become corrupt.

Supply Voltage. VDD provides the power

V

DD

supply to the internal core of the memory device.
It is the main power supply for all operations
(Read, Program and Erase).

Supply Voltage. V

V

DDQ

provides the power

DDQ

supply to the I/O pins and enables all Outputs to

. V

be powered independently from V
tied to V

or can use a separate supply.

DD

DD

DDQ

can be

It is recommended to power-up and power-down
V

DD

and V

together to avoid any condition that

DDQ

would result in data corruption.

Ground. Ground, V

V

SS

is the reference for

SS,

the core power supply. It must be connected to the
system ground.

V

Ground. V

SSQ

the input/output circuitry driven by V

ground is the reference for

SSQ

DDQ

. V

SSQ

must be connected to VSS.

Note: Each device in a system should have
V

DD

and V

decoupled with a 0.1µF cerami c

DDQ

capacitor close to the pin (high frequency, in­herently low inductance ca pacitors should b e
as close as possible to the package). See Fig­ure 10, AC Measurement Load Circuit.

12/61

BUS OPERATIONS

There are 12 bus operations that control the mem­ory. Each of these is described in this section, see
Tables 2 and 3, Bus Operat ions, for a summary.
The bus operation is selected through the Burst
Configuration Register; the bits in this register are
described at the end of this section.

On Power-up or after a Hardware Reset the mem­ory defaults to Asynchrono us Latch Enable Con­trolled Read and Asynchronous Bus Write, no
other bus operation can be performed until the
Burst Control Register has been configured.

The Electronic Signature, CFI or Status Register
will be read i n asynchr onous m ode or single sy n­chronous burst mode.

Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.

Asynchronous Bus Operation s

For asynchronous bus operations refer to Tabl e 3
together with the text below.

Asynchronous Bus Read. Asynchronous Bus
Read operations read from the memory cells, or
specific registers (Electronic Signature, Status
Register, CFI and Block Prot ection Status) in the
Command Interface. A valid bus operation in­volves setting the desired address on the Address
Inputs, applying a Low signal, V

, to Chip Enable,

IL

Output Enable and Latch Enable and keeping
Write Enable High, V

. The Data Inputs/Outputs

IH

will output the value, see Figure 11, Asynchronous
Bus Read AC Waveforms, and Table 15, Asyn­chronous Bus Read AC Characteristics, for details
of when the output becomes valid.

Asynchronous Latch Controlled Bus Read.

Asynchronous Latch Controlled Bus Read opera­tions read from the memory cells or specific regis­ters in the Command Interface. The address is
latched in the memory before the value is ou tput
on the data bu s, allowing the address to cha nge
during the cycle without affecting the address that
the memo r y uses.

A valid bus operation i nvolves set ting the des ired
address on the Address Inputs, setting Chip En­able and Latch Enable Low, V
Enable High, V

; the address is latched on the ris-

IH

and keeping Write

IL

ing edge of Address L atch. Once latched, the Ad­dress Inputs can change. Set Output Enable Low,
V

, to read the data on the Data Inputs/Outputs;

IL

see Figure 12, Asynchronous Latch Controlled
Bus Read AC Waveforms and Table 16, Asyn­chronous Latch Controlled B us Read AC Charac­teristics for details on when the output becomes
valid.

Note that, since the Latch Enable input is transpar­ent when set Low, V

, Asynchronous Bus Read

IL

M58LW032A

operations can be performed when the memory is
configured for Asynchronous Latch Enable bus
operations by holding Latch Enable Low, V
throughout the bus operation.

Asynchronous Page Read. Asynchronous Page
Read operations are used to read from several ad­dresses within the same memory page. Each
memory page is 4 Wo rds and has the same A3­A21, only A1 and A2 may change.

Valid bus operations are the same as Asynchro­nous Bus Read operations but with different tim­ings. The first read operation within the page has
identical timings, subsequent reads within the
same page have much sh orter access t i mes. If the
page changes then the normal, longer timings ap­ply again. See Figure 13, Asynchronous Page
Read AC Waveforms and Table 17, Asynchro­nous Page Read AC Characteristics for details on
when the outputs become valid.

Asynchronous Bus Write. Asynchronous Bus
Write operations write to the Command Interface
in order to send commands to the memory or to
latch addresses and in put data to program. Bus
Write operations are asynchronous, the clock, K,
is don’t care during Bus Write operations.

A valid Asynchronous Bus Write operation begins
by setting the desired address on the A ddress In­puts and setting Latch Enabl e Low, V
dress Inputs are latched by the Command
Interface on the rising edge of Chip Enable or
Write Enable, whichever occurs first. The Data In­puts/Outputs are la tched by the Comm and Inter­face on the rising edge of Chip Enable or Write
Enable, whichever occurs first. Output Enable
must remain High, V

, during the whole Asyn-

IH

chronous Bus Write operation. See Figures 14,
and 16, Asynchronous Write AC Wavef orms, and
Tables 18 and 19, Asynchronous Write and Latch
Controlled Write AC Characteristics, for details of
the timing requirements.

Asynchronous Latch Controlled Bus Write.

Asynchronous Latch Controlled Bus W rite opera­tions write to the Command Interface in order to
send commands to the memory or to latch ad­dresses and input data t o p rogram . Bus W r ite op­erations are asynchronous, the clock , K, is don’t
care during Bus Write operations.

A valid Asynchronous Latch Controlled Bus Write
operation begins by setting the desired address on
the Address Inputs and pulsing Latch Enable Low,

. The Address Inputs are latched b y the Com-

V

IL

mand Interface on the rising edge of Latch Enable,
Chip Enable or Write Enable, whichever occurs
first. The Data Inputs/Outputs are latched by the
Command Interface on the rising edge of Chip En­able or Write Enable, whichever occurs first. Ou t-

. The Ad-

IL

IL

13/61

M58LW032A

put Enable must remain High, VIH, during the
whole Asynchronous Bus Write operation. See
Figures 15 and 17 Asynchronous Latch Controlled
Write AC Waveforms, and Tables 18 and 19,
Asynchronous Write and Latch Controlled Write
AC Characteristics, for details of the timing re­quirements.

Output Disa bl e . The Data Inputs/Outputs are in the high impedance state when the Output Enable is High.

Standby. When Chip Enable is High, V

IH

, the
memory enters Standby mode and the Data In­puts/Outputs pins are placed in the high imped­ance state regardless of Output Enable or Write
Enable. The Supply Current is reduced to the
Standby Supply Current, I

DD1

.

During Program or Erase operations the memory
will continue to use the Program/Erase Supply

Current, I
til the operation completes.

Automatic Low Power. If there is no change in the state of the bus for a short period of time during Asynchronous Bus Re ad operations the memory enters Auto Low Pow er mode where the internal Supply Current is reduced to the Auto-Standby Supply Current, I still output data if a Bus Read operation is in progress.

Automatic Low Power is only available in Asyn­chronous Read modes.

Power-Down. The memory is in Power-Down mode when Reset/Power-Down, RP power consumption is reduced to the Power-Down level, I independent of Chip Enable, Output Enable or Write Enable.

Table 2. Asynchronous Bus Operations

Bus Operation Step E G W RP L A1-A21 DQ0-DQ15

V

Asynchronous Bus Read

Asynchronous Latch
Controlled Bus Read

Asynchronous Page Read
Asynchronous Bus Write
Asynchronous Latch

Controlled Bus Write
Output Disable
Standby
Power-Down X X X

Note: 1. X = Don’t Care VIL or VIH. High = VIH or VHH.

Address Latch
Read

Address Latch

V

IL

IL

V

V

IL

IL

V

V

IL

IL

V

V

IL

IL

V

V

IL

IH

V

V

IL

IH

V

V

IL

IH

V

X X High X X High Z

IH

, for Program or Erase operations un-

DD3

. The Data Inputs/Outputs will

DD5

, is Low. The

, and the out puts are high impedance,

DD2

V

High

IH

V

High

IH

V

High

IH

V

High

IH

V

High

IL

V

High

IL

V

High X X High Z

IH

V
V

V

V
V

V

V

IL

Address Data Output

IL

Address High Z

IL

IH

IL

IL

IL

X X High Z

X Data Output
Address Data Output
Address Data Input

Address Data Input

14/61

M58LW032A

Synchronous Bus Operations

For synchronous bus operat ions refer to Table 3
together with the text below.

Synchronous Burst Read. Synchronous Burst
Read operations are used to read from the memo­ry at specific times synchronized to an external ref­erence clock. The burst type, length and latency
can be configured. The different configurations for
Synchronous Burst Read operations are de­scribed in the Burst Configuration Register sec­tion.

A valid Synchronous Burst Read operation begins
when the address is set on the Address Inputs,
Write Enable is High, V
Latch Enable are Low, V

, and Chip Enable and

IH

, during the active edge

IL

of the Clock. The address is latched on the first ac­tive clock edge when Latch Enable i s low, or on
the rising edge of Latch Enable, whichever occurs

the X-latency specified in the Burst Control Regis­ter has expired. The output buffers are activated
by setting Output Enable Low, V
and 7 for exam ples of Synchronous Burst Read
operations.

In Continuous Burst mode one Burst Read opera­tion can access the entire m emo ry sequ entially. If
the starting address is not associated with a page
(4 Word) boundary the V alid Data Ready, R, ou t­put goes Low, V
be ready in time and additional wait-states are re­quired. The Valid Data Ready output timing (bit
M8) can be changed in the Burst Configuration
Register.

The Synchronous Burst Read timing diagrams
and AC Characteristics a re described in the AC
and DC Parameters section. See Figures 18, 19
and Table 20.

first. The data becomes available for output after

Table 3. Synchronous Burst Read Bus Operations

Bus Operation Step E G RP

Address Latch

Synchronous Burst Read

Note: 1. X = Don't Care, VIL or VIH.

2. M15 = 0, Bit M 15 i s in the Burst Configuration Register.

3. T = trans i tion, see M6 in the Bu rst Configurat i on Register for details on the ac tive edge of K.

Read
Read Abort

V
V

V

X

IL

V

IL

X

IH

. See Figures 6

IL

, to indicate that the data will not

IL

(3)

K

V

IH

V

IL

IH

V

IH

L

V

T
T X Data Output
X X High Z

IL

A1-A21

DQ0-DQ15

Address Input

15/61

M58LW032A

Burst Configuration Register

The Burst Configuration Register is used to config­ure the type of bus access that the memory will
perform. The Burst Configuration Register bits are
described in Table 4. They specify the selection of
the burst length, burst type, burst X and Y laten­cies and the Read operation. See figures 6 and 7
for examples of Synchronous Burst Read configu­rations.

The Burst Configuration Register is set through
the Command Interface and will retain its informa­tion until it is re-configured, the device is reset, or
the device goes into Reset/Power-Down mode.
The Burst Configuration Register is read using the
Read Electronic Signature Command at addres s
05h.

Read Select Bit (M15). The Read Select bit,
M15, is used to switch between asynchronous and
synchronous Bus Read operations. When the
Read Select bit is set to ’1’, Bus Read operations
are asynchronous; when the Read Select but is
set to ’0’, Bus Read operations are synchronous.

On reset or power-up the Read Select bit is set to
’1’ for asynchronous access.

X-Latency Bits (M13-M11). The X-Latency bits are used during Synchronous Bus Read opera­tions to set the number of clock cycles between the address being latched and the first data be­coming available. For correct operation the X-La­tency bits can only assume the values in Table 4, Burst Configuration Register.

Internal Clock Divider Bit (M10). The Internal
Clock Divider Bit is used to divide the internal clock
by two. When M10 is set to ‘1’ the internal clock is
divided by two, which effectively means that the X
and Y-Latency values are multiplied by two, that is
the number of clock cycles between the address
being latched and the first data becoming avail­able will be twice the value set in M13-M11, and
the number of clock cycles between consecutive
reads will be twice the value set in M9. For exam­ple 8-1-1-1 will become 16-2-2-2. When M10 is set
to ‘0’ the internal clock runs n ormally and the X
and Y-Latency values are those s et in M13-M11
and M9.

Y-Latency Bit (M9). The Y-Latency bit is used
during Synchronous Bus Read operations to set
the number of clock cycles between consecutive
reads. The Y-Latency value depends on both the
X-Latency value and the setting in M9.

When the Y-Latency is 1 the data changes each
clock cycle; when the Y-Latency is 2 the data
changes every seco nd clock cycle. See Tab le 4,
Burst Configuration Register for valid combina­tions of the Y-Latency, the X-Latency and the
Clock frequency.

Valid Data Ready Bit (M8). The Valid Data Ready bit controls the timing of the Valid Data Ready output pin, R. When the Valid Data Ready bit is ’0’ the Valid Data Ready output pin is driven Low for the active clock edge when invalid data is output on the bus. When the Valid Data Ready bit is ’1’ the Valid Data Ready output pin is driven Low one clock cycle prior to invalid data being output on the bus.

Burst Type Bit ( M7 ). The Burst Type bit is used to configure the sequence of addresses read as sequential or interleaved. When the Burst Type bit is ’0’ the memory outputs from interleaved ad­dresses; when the Burst Type bit is ’1’ the memory outputs from sequential addresses. See Tables 5, Burst Type Definition, for the sequence of ad­dresses output from a given starting address in each mode.

Valid Clock Edge Bit (M6). The Valid Clock E dge bit, M6, is used to configure the active edge of the Clock, K, during Synchronous Burst Read opera­tions. When the Valid Clock Edge bit is ’0’ the fall­ing edge of the Clock is the active edge; when the Valid Clock Edge bit is ’1 ’ the rising edge of the Clock is active.

Burst Length Bit (M2-M0). The Burst Length bits set the maximum number of Words that can be output during a Synchronous Burst Read opera­tion.

Table 4, Burst Configuration Register gives the
valid combinations of the Burst Length bits that the
memory accepts; Tables 5, Burst Type Definition,
give the sequence of addresses output from a giv­en starting address for each length.

M5 M4 and M3 are reserved for future use.

16/61

Table 4. Burst Configuration Register

Address

Bit

Mnemonic Bit Name

16 M15 Read Select 1

15 M14 Reserved

Reset
Value

Value Description

0 Synchronous Burst Read
1 Asynchronous Bus Read (default at power-up)

001 Reserved
010

X-Latency = 4, 4-1-1-1 (use only with Y-Latency = 1)

M58LW032A

(1)

14

to

12

M13-M11

X-Latency

(2)

XXX

011
100
101

X-Latency = 5, 5-1-1-1, 5-2-2-2
X-Latency = 6, 6-1-1-1, 6-2-2-2
X-Latency = 7, 7-1-1-1, 7-2-2-2

110 X-Latency = 8, 8-1-1-1, 8-2-2-2

11 M10

10 M9

9M8

Clock Divider

Y-Latency

Valid Data
Ready

Internal

(3)

X

X

X

0 X and Y-Latencies remains as set in M13-M11 and M9
1 Divides internal clock, X and Y-Latencies multiplied by 2
0 Y-Latency = 1
1 Y-Latency = 2
0 R valid Low during valid Clock edge
1 R valid Low one cycle before valid Clock edge
0 Interleaved

8 M7 Burst Type X

1 Sequential

7M6

Valid Clock
Edge

X

0 Falling Clock edge
1 Rising Clock edge

6 to 4 M5-M3 Reserved

3

to

M2-M0 Burst Length XXX

1

Note: 1. 4 - 2 - 2 - 2 (represents X-Y-Y -Y ) is not allowed.

2. X latencies can be calculated as: (t
is the clock period).

3. Y latencies can be calcul ated as: t

4. t

SYSTEM MARGIN

is the time m argin requir ed for the calculation.

AVQV

KHQV

– t

LLKH

+ t

SYSTEM MARGIN

001 4 Words
010 8 Words
111 Continuous

+ t

) + t

QVKH

SYSTEM MARGIN

+ t

QVKH

< Y t

K.

< (X - 1) t

is an integer number from 4 to 8 and t

K. (X

K

17/61

M58LW032A

Tabl e 5. Burst Type Defi nition

Starting

Addressx4Sequentialx4Interleaved

x8

Sequential

x8

Interleaved

Continuous

0 0-1-2-3 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10..

1 1-2-3-0 1-0-3-2 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 1-2-3-4-5-6-7-8-9-10-11..
2 2-3-0-1 2-3-0-1 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 2-3-4-5-6-7-8-9-10-11-12..

3 3-0-1-2 3-2-1-0 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 3-4-5-6-7-8-9-10-11-12-13..
4 – – 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-11-2-13-14..

5 – – 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 5-6-7-8-9-10-11-12-13-14..
6 – – 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 6-7-8-9-10-11-12-13-14-15..

7 – – 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 7-8-9-10-11-12-13-14-15-16..
8 – – – – 8-9-10-11-12-13-14-15-16-17..

Figure 6. Burst Configuration X-1-1-1

0123456789

K

ADD

L

DQ

DQ

DQ

DQ

DQ

4-1-1-1

5-1-1-1

6-1-1-1

7-1-1-1

8-1-1-1

VALID

VALID

VALID

VALID

VALIDVALIDVALIDVALID

VALIDVALIDVALID

VALID

VALIDVALIDVALIDVALID

VALID

VALID

VALID

VALIDVALID

AI05512

18/61

Figure 7. Burst Configuration X-2-2-2

0123456789

K

M58LW032A

ADD

L

DQ

DQ

DQ

DQ

5-2-2-2

6-2-2-2

7-2-2-2

8-2-2-2

VALID

NV

NV=NOT VALID

VALID

NV

NV

VALID

NV

VALID

NV

VALID

NV

VALID

NV

VALID

VALID

NV

VALID

NVNV

AI05513

19/61

M58LW032A

COMMAND INTERFACE

All Bus Write operations t o the me mory are in ter­preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper­ations. The Commands are summarized in Table
6, Commands. Refer to Table 6 in conjunction with
the text descriptions below.

After power-up or a Reset operation the memory
enters Read mode.

Synchronous Read operations and Latch Con­trolled Bus Read operations can only be used to
read the memory array. The Electr onic Sign ature,
CFI or Stat us Register will b e read in asynchro ­nous mode or single synchronous burst mode.
Once the memory returns to Read Memory Array
mode the bus will resume the s etting in the Burst
Configuration Register automatically.

Read Memory A rray Command. The Read Mem­ory Array command returns the memory to Read
mode. One Bus Write cycle is required to issue the
Read Memory Array command and return the
memory to Read mode. Once the command is is­sued the memory remains in Read mode until an­other command is issued. From Read mode Bus
Read commands will access the memory array.

While the Program/Erase Controller is executing a
Program, Erase, Block Protec t, Blocks Unprotect
or Protection Register Program operation the
memory will not accept the Read Mem ory Array
command until the operation completes.

Read Electronic S i g natur e Command . The Read
Electronic Signature command is used to read the
Manufacturer Code, the Device Code, t he Block
Protection Status, the Burst Configuration Regis­ter and the Protection Register. One Bus Write cy­cle is required to issue the Read Electronic
Signature command. Once the command is is­sued subsequent Bus Read ope rations read the
Manufacturer Code, the Device Code, t he Block
Protection Status, the Burst Configuration Regis­ter or the Protection Register until another com­mand is issued. Refer to Table 7, Read Electronic
Signature, Table 8, Read Protection Register and
Figure 8, Protection Register Memory Map for in­formation on the addresses.

Read Query Command. The Read Query Com­mand is used to read data from the Common Flash Interface (CFI) Memory Area. One Bus Write cycle is required to issue the Read Query Command. Once the command is issued subsequent Bus Read operations read from the Common Flash In­terface Memory Area. See Appendix B, Tables 26, 27, 28, 29, 30 and 31 for details on the information contained in the Common Flash Interface (CFI) memory area.

Read Statu s Register Co mm an d. The Read Sta­tus Register command is us ed to read the Status

Register. One Bus Write cycle is required to issue
the Read Status Register command. Once the
command is issued subsequent Bus Read opera­tions read the Status Register until another com­mand is issued.

The Status Register information is present on the
output data bus (DQ1-DQ 7) when both Chip En­able and Output Enable are low, V

.

IL

See the section on the Status Reg ister and Table
10 for details on the definitions of the Status Reg­ister bits

Clear Status Register Command. The Clear Sta­tus Register command can be used to reset bits 1,
3, 4 and 5 in the Status Register to ‘0’. One Bus
Write is required to issue the Clear Status Register
command.

The bits in the Status Register are stic ky and do
not automatically return to ‘0’ when a new Write to
Buffer and Program, Er ase, Block P rotec t, B lo cks
Unprotect or Protection Register Program com­mand is issued. If any error occurs then it is essen­tial to clear any error bits in the Status Register by
issuing the Clear Status Register command before
attempting a new Program, Erase or Resume
command.

Block Erase Command. The Block Erase com­mand can be used to e rase a block. I t sets all of
the bits in the block to ‘1’. All previous data in the
block is lost. If the block is protected then the
Erase operation will abort, the data in the block will
not be changed and the Status Register will output
the error.

Two Bus Write operations are required to issue the
command; the second Bus Write cycle latches the
block address in the internal state machine and
starts the Program/Erase Controller. Once the
command is issued subsequent Bus Read opera­tions read the Status Register. See the section on
the Status Register for details on the definitions of
the Status Register bits.

During the Erase operation the memory will only
accept the Read Status Register command and
the Program/Erase Su spend command. All ot her
commands will be ignored. Typical Erase times
are given in Table 9.

See Appendix C, Figure 25, Block Erase Flow­chart and Pseudo Code, for a suggested flowchart
on using the Block Erase command.

Word Program Command. T he Word Program
command is used to p rogram a single word in the
memory array. Two Bus Write operations are re­quired to issue the command; the first write cycle
sets up the Word Program command, the second
write cycle latches the address and data to be pro­grammed in the internal state machi ne and s tarts
the Program/Erase Controller.

20/61

M58LW032A

If the block being program m ed i s prote cted an er­ror will be set in the Status Register and the oper­ation will abort without affecting the data in the
memory array. The block must be unprotected us­ing the Blocks Unprotect command.

Write to Buffer and Program Command. The Write to Buffer and Program comm and is used to program the memory array.

Up to 16 Words can be loaded into the Write Buffer
and programmed into the memory. Each Write
Buffer has the same A5-A21 addresses.

Four successive steps are required to issue the
command.

1. One Bus Write operation is required to set up
the Write to Buffer and Program Comm and. Is­sue the set up command with the selected
memory Block Address where the program op­eration should occur (any address in the block
where the values will be programmed can be
used). Any Bus Read operations will start to out­put the Status Register after the 1st cycle.

2. Use one Bus Write operation to write the sam e
block address along with the value N on the
Data Inputs/Output, where N+1 is the number of
Words to be programmed.

3. Use N+1 Bus Write operations to load the ad­dress and data for each Word into the Write
Buffer. The addresses must have the same A5­A21.

4. Finally, use one Bus Write operation to issue the
final cycle to confirm the command and start the
Program operation.

Invalid address combinations or failing to follow
the correct sequence of Bus Write cycles will set
an error in the Status Register and abort the oper­ation without affecting the data in the memory ar­ray. The Status Register should be cleared before
re-issuing the command.

If the block being program m ed i s prote cted an er­ror will be set in the Status Register and the oper­ation will abort without affecting the data in the
memory array. The block must be unprotected us­ing the Blocks Unprotect command.

See Appendix C, Figure 23, Write to Buffer and
Program Flowchart and Pseudo Code, for a sug­gested flowchart on using the W rite to Buf fer and
Program command.

Program/Erase Suspend Command. The Pro­gram/Erase Suspend command is used to pause a
Write to Buffer and Program or Erase operation.
The command will only be acc ep t ed du ring a Pro­gram or an Erase operation. It can be issued at
any time during an Erase operation but will only be
accepted during a Write to Buffer and Program
command if the Program/Erase Controller is run­ning.

One Bus Write cycle is required to i ssue the P ro­gram/Erase Suspend command and pause the
Program/Erase Controller. Once the command is
issued it is necessary to poll the Program/Erase
Controller Status bit (bit 7) to find out when the
Program/Erase Controller has paused; no other
commands will be accepted until the Program/
Erase Controller has paused. After the Program/
Erase Controller has paused, the memory will con­tinue to output the Status Register until another
command is issued.

During the polling period between issuing the Pro­gram/Erase Suspend command and the Program/
Erase Controller pausing it is possible for the op­eration to complete. Once the Program/Erase
Controller Status bit (bit 7) i ndicates that the P ro­gram/Erase Controller is no longer active, the Pro­gram Suspend Status bit (bit 2) or the Erase
Suspend Status bit (bit 6) can be used to deter­mine if the operation has completed or is suspend­ed. For timing on the delay between issuing the
Program/Erase Suspend command and the Pro­gram/Erase Controller pausing see Table 9.

During Program/Erase Suspend the Read Memo­ry Array, Read Status Register, Read Elect ronic
Signature, Read Query and Program/Erase Re­sume commands will be accepted by the Com­mand Interface. Additionally, if the suspended
operation was Erase then the Word Program,
Write to Buffer and Program, and the Program
Suspend commands will also be ac cepted. W hen
a program operation is completed inside a Block
Erase Suspend the Read Memory Array command
must be issued to reset the device in Read mode,
then the Erase Resume command can be issued
to complete the whole seque nce. Only the blo cks
not being erased may be read or programmed cor­rectly.

See Appendix C, Figure 24 , Program Suspend &
Resume Flowchart and Pseudo Code, and Figure
26, Erase Suspend & Resume Flowchart and
Pseudo Code, for suggested flowcharts on using
the Program/Erase Suspend command .

Program / Erase Resum e Command. The Pro­gram/Erase Resume command can be used to re­start the Program/Erase Controller after a
Program/Erase Suspend operat ion h as paused it.
One Bus Write cycle is required to i ssue the P ro­gram/Erase Resume command. Once the com­mand is issued subsequ ent Bus Read operations
read the Status Register.

Set Burst Configuration Register Command.

The Set Burst Configuration Register command is
used to write a new value t o the Burst Conf igura­tion Control Register which defines the burst
length, type, X and Y latencies, Synchronous/
Asynchronous Read mode and the valid Clock
edge configuration.

21/61

M58LW032A

Two Bus Writ e cycles a re required to i ssue the Set
Burst Configuration Register command. Once the
command is issued the memory returns to Read
mode as if a Read Mem ory Array command had
been issued.

The value for the Burst Configuration Register is
presented on A1-A16. M0 is on A1, M1 on A2, etc.;
the other address bits are ignored.

Block Protect Command. The Block Protect command is used to protec t a block and prevent Program or Erase operations from changing the data in it. Two Bus Write cycles are required to is­sue the Block Protect command; the second Bus Write cycle latches the block address in the inter­nal state machine and sta rts the Program/Erase Controller. Once the command is issued subse­quent Bus Read operations read the Status Reg­ister. See the section on the Status Register for details on the definitions of the Status Register bits. Typical Block Protection times are given in Table 9.

The Block Protection bits are non-volatile, once
set they remain set through reset and power­down/power-up. They ar e cleared by a Blocks Un­protect command.

See Appendix C, Figure 27, Block Protect Flow­chart and Pseudo Code, for a suggested flowchart
on using the Block Protect command.

Blocks Unprotect Command. The Blocks Un­protect command is used to unprotect all of the blocks. Two Bus Write cycles are requir ed to issue the Blocks Unprotect command ; the second Bus Write cycle starts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Stat us Register for details on the definitions of the Status Register bits. Typical Block Protection times are given in Table 9.

See Appendix C, Figure 28, Blocks Unprotect
Flowchart and Pseudo Code, for a suggested flow­chart on using the Blocks Unprotect command.

Protectio n R egister Program Comman d. The
Protection Register Program c omm and is used to
Program the 64 bit user segment of the Protection
Register. The segment is programmed 16 bits at a
time. The memory must be reset by issuing the
Read Memory Array command before the Protec­tion Register Program com mand can be issued.
Two write cycles are required to issue the Protec­tion Register Program command.

■ The first bus cycle sets up the Protection

Register Program command.

■ The second latches the Address and the Data to

be written to the Protection Register and starts
the Program/Erase Controller.

Read operations output the Status Register con­tent after the programming has started.

The user-programmable segment can be locked
by programming bi t 1 of the Protection Register
Lock location to ‘0’ (see Table 8). Bit 0 of the Pro­tection Register Lock location locks the factory
programmed segment and is programmed to ‘0’ in
the factory. The locking of the Protec tion Regi ster
is not reversible, once the lock bits are pro­grammed no further changes c an be m ade to the
values stored in the Protection Register, see Fig­ure 8, Protection Register Memory Map. Attemp t­ing to program a previously protected Protection
Register will result in a Status Register error.

The Protection Register Program cannot be sus­pended. See Appendix C, Figure 29, Protection
Register Program Flowchart and Pseudo Code,
for the flowchart for using the P rotection Regi ster
Program command.

22/61

Table 6. Commands

M58LW032A

Bus Operations

Command

Cycles

1st Cycle 2nd Cycle Subsequent Final

Op. Addr. Data Op. Addr. Data Op. Addr. Data Op. Addr. Data

Read Memor y Array ≥ 2 Write X FFh Read RA RD

Read Electronic Signature ≥ 2 Write X 90h Read

ID A

(3)

IDD

(3)

Read Status Register 2 Write X 70h Read X SRD

Read Query ≥ 2 Write X 98h Read

QA

(4)

QD

(4)

Clear Status Register 1 Write X 50h

Block Erase 2 Write X 20h Write BA D0

Word Program 2 Write X

Write to Buffer and

Program

4 + N Write BA E8h Write BA N Write PA PD Write X D0h

40h

Write PA PD

10h

Program/Erase Suspend 1 Write X B0h

Program/Erase Resume 1 Write X D0h

Set Burst Configuration

Register

2 Write X 60h Write BCR 03h

Block Protect 2 Write X 60h Write BA 01h

Blocks Unprotect 2 Write X 60h Write X D0h

Protection Register

Program

Note: 1. X Don’t Care; RA Read Address, RD Read Data, IDA Identifier Address, IDD Identifier Data, SRD Status Register Data, PA Program

Address; PD Program Dat a, QA Query Address, QD Query Data, BA Any address in the Block , B CR Burst Configuratio n Register
value.

2. Base Ad dress, refer to Fi gure 8 and Table 8 for more infor m ation.

3. For Iden tifier addresses and data ref er to table 7, Rea d Electronic Signature.

4. For Query Address and Data refer to App endix B, CFI.

2 Write X C0h Write PRA PRD

Table 7. Read Electronic Signature

Code Address (A21-A1) Data (DQ15-DQ0)

Manufacturer Code 000000h 0020h
Device Code 000001h 8816h

Block Protection Status SBA+02h

Burst Configuration Register 000005h BCR
Protection Register

Note: 1. SBA is the Start Base Address of each block, BCR is B urst Configuration Regis ter data, PRD i s P rotection Register Data.

2. Base Ad dress, refer to Fi gure 8 and Tabl e 8 f or more inform ation.

000080h

(2)

0000h (Block Unprotected)

0001h (Block Protected)

PRD

23/61

M58LW032A

Table 8. Read Protection Register

Word Use A8A7A6A5A4A3A2A1

Lock Factory, User 10000000

0 Factory (Unique ID) 10000001
1 Factory (Unique ID) 10000010
2 Factory (Unique ID) 10000011
3 Factory (Unique ID) 10000100
4 User 10000101
5 User 10000110
6 User 10000111
7 User 10001000

Figure 8. Prot ect i on Register Mem o ry Map

WORD

ADDRESS

88h

User Programmable

85h
84h

81h
80h

Unique device number

Protection Register Lock 1 0

24/61

AI05501

M58LW032A

Table 9. Program, Erase Times and Progra m Erase Endurance Cycles

Parameters

Min Typ Max

Block (521Kb) Erase 1.1 s
Program Write Buffer 290 µs
Program Suspend Latency Time 20 µs
Erase Suspend Latency Time 25 µs
Block Protect Time 18 µs
Blocks Unprotect Time 0.75 s
Program/Erase Cycles (per block) 100,000 cycles

Note: TA = 0 to 70 °C; VDD = 2.7V to 3.6V ; V

DDQ

=1.8V

M58LW032A

Unit

25/61

M58LW032A

STATUS REGISTER

The Status Register provides information on the
current or previous Program, Erase, Block Protect
or Blocks Unprotect operation. The various bits in
the Status Register convey information and errors
on the operation. They are output on DQ7-DQ0.

To read the Status Register the Read Status Reg­ister command can be issued. The Status Register
is automatically read after Program, Erase, Block
Protect, Blocks Unprotect and Program/Erase Re­sume commands. The Status Register can be
read from any address.

The Status Register can only be read using Asyn­chronous Bus Read operations. Once the memory
returns to Read Memory Array mode the bus will
resume the setting in the Burst Configuration Reg­ister automatically.

The contents of the Status Register can be updat­ed during an Erase or Program operation by tog­gling the Output Enable pin or by dis-activating
(Chip Enable, V
able and Output Enable, V

Status Register bits 5, 4, 3 and 1 are associated
with various error conditions and can only be reset
with the Clear Status Register command. The Sta­tus Register bits are summarized in Table 10, Sta­tus Register Bits. Refer to Table 10 in conjunction
with the following text descriptions.

Program/Erase Controller Status (Bit 7). The Pro­gra m/Erase Controller Status bit indicates whether
the Program/Erase Controller is active or inactive.
When the Program/Erase Controller Status bit is
Low, V

, the Program/Erase Controller is active

OL

and all other Status Register bits are High Imped­ance; when the bit is High, V
Erase Controller is inactive.

The Program/Erase Controller Status is Low im­mediately after a Program/Erase Suspend com­mand is issued until the Program/Erase Controller
pauses. After the Program/Erase Controller paus­es the bit is High.

During Program, Erase, Block Protect and Blocks
Unprotect operations the Program/Erase Control­ler Status bit can be polled to find the end of the
operation. The other bits in the Status Register
should not be tested until the Program/Erase Con­troller completes the operation and the bit is High.

After the Program/Erase Cont roller completes its
operation the Erase S tatus, Program Status and
Block Protection Status bits should be tested for
errors.

Erase Suspend Status (Bit 6). The Erase Sus­pend Status bit indicates that an Erase o peration
has been suspended and is waiting to be re­sumed. The Erase Suspend Status should only be
considered valid when the Program/Erase Con­troller Status bit is High (Program/Erase Controller

) and then reactivating (Chip En-

IH

) the device.

IL

, the Program/

OH

inactive); after a Program/Erase Suspend com­mand is issued the memory may still complete the
operation rather than entering the Suspend mode.

When the Erase Suspend Statu s bit is Low, V

OL

the Program/Erase Controller is active or has com­pleted its operation; when the bit is High, V

OH

, a
Program/Erase Suspend com mand has been is­sued and the memory is waiting for a Program/
Erase Resume command.

When a Program/Erase Re sume command is is­sued the Erase Suspend Status bit returns Low.

Erase Status (Bit 5). The Erase Status bit can be
used to identify if the memory has failed to verify
that the block has erased correctly or that all
blocks have been unprotected successfully. The
Erase Status bit should be read once the Program/
Erase Controller Status bit is High (Program/Erase
Controller inactive).

When the Erase St atu s bit i s Low, V

, the mem-

OL

ory has successfully verified that the block has
erased correctly or all blocks have been unprotect­ed successfully. When the Erase Status bit is
High, V

, the erase operation has failed. De-

OH

pending on the cause of the failure othe r Status
Register bits may also be set to High, V

■ If only the Erase Status bit (bit 5) is set High,

V

then the Program/Erase Controller has

OH,

OH

.

applied the maximum number of pulses to the
block and still failed to verify that the block has
erased correctly or that all the blocks have been
unprotected successfully.

■ If the failure is due to an erase or blocks

unprotect with V
(bit 3) is also set High, V

■ If the failure is due to an erase on a protected

low, VOL, then VPP Status bit

PP

OH

.

block then Block Protection Status bit (bit 1) is
also set High, V

■ If the failure is due to a program or erase

OH

.

incorrect command sequence then Program
Status bit (bit 4) is also set High, V

OH

.

Once set High, the Erase Status bit can only be re­set Low by a Clear Status Register command or a
hardware reset. If set High it should be reset be­fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.

Program Status (Bit 4). The Program Status bit
is used to identify a Program or Block Pr otect fail­ure. The Program S tatus bit shoul d be read once
the Program/Erase Controller Status bit is High
(Program/Erase Controller inactive).

When the Program Status bit is Low, V

OL

, the
memory has successfully verified that the Write
Buffer has programmed correc tly or the block is
protected. When the Program Status bit is High,
V

, the program or block protect operation has

OH

,

26/61

M58LW032A

failed. Depending on the cause of the failure other
Status Register bits may also be set to High, V

■ If only the Program Status bit (bit 4) is set High,

V

then the Program/Erase Controller has

OH,

OH

applied the maximum number of pulses to the
byte and still failed to verify that the Write Buffer
has programmed correctly or that the Block is
protected.

■ If the failure is due to a program or block protect

with V
also set High, V

■ If the failure is due to a program on a protected

low, VOL, then VPP Status bit (bit 3) is

PP

OH

.

block then Block Protection Status bit (bit 1) is
also set High, V

■ If the failure is due to a program or erase

OH

.

incorrect command sequence then Erase
Status bit (bit 5) is also set High, V

OH

.

Once set High, the Program Status bit can only be
reset Low by a Clear Status Register command or
a hardware reset. If set High it should be reset be­fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.

Status (Bit 3). The VPP Status bit can be

V

PP

used to identify if a Word Pr ogram, Erase, Block
Protection or Blocks Unprotection operation has
been attempted when V

is Low, VIL. The V

PP

PP

Status bit cannot be used during a Write to Buffer
and Program operation.

When the V

Status bit is Low, VOL, no Word Pro-

PP

gram, Era se, Bl ock P rotecti on o r Bl ocks Unprot ec­tion operations have been attempted with V

PP

Low, VIL, since the last Clear S tatus Register com­mand, or hardware reset. When the V
is High, V

, a Word Program, Erase, Bloc k Pro-

OH

Status bit

PP

tection or Blocks Unprotection operation has been
attempted with V

Once set High, the V

Low, VIL.

PP

Status bit can only be reset

PP

by a Clear Status Register command or a hard­ware reset. If set High it should be reset befo re a
new Program, Erase, B lock Protection or Blocks

Unprotection command is issued, otherwise the
new command will appear to fail.

.

Program Suspend Status (Bit 2). The Program
Suspend Status bit indicates that a Program oper­ation has been suspended and is waiting to be re­sumed. The Program Suspend Status should only
be considered valid when the Program/Erase
Controller Status bit is High (Program/Erase Con­troller inactive); after a Program/Erase Suspend
command is issued the memory may still complete
the operation rather than entering the Suspend
mode.

When the Program Suspend Status bit is Low,
V

, the Program/Erase Controller is active or has

OL

completed its operation; when the bit is High, V
a Program/Erase Suspend command has been is­sued and the memory is waiting for a Program/
Erase Resume command.

When a Program/Erase Re sume command is is­sued the Program Suspend Status bit returns Low.

Block Protection Status (Bit 1). The Block Pro­tection Status bit can be used to identify if a Pro­gram or Erase operation has tried to modify the
contents of a protected block.

When the Block Protection Status bit is Low, V
no Program or Erase operations have been at­tempted to protected blocks since the last Clear
Status Register command or hardware reset;
when the Block Protection Status bit is High, V
a Program (Program Status bit 4 set High) or
Erase (Erase Status bit 5 set High) operation has
been attempted on a protected block.

Once set High, the Block Protection Status bit can
only be reset Low by a Clear Status Register com­mand or a hardware reset. If set High it should be
reset before a new Program or Erase command is
issued, otherwise the new command will appear to
fail.

Reserved (Bit 0). Bit 0 of the Status Register is
reserved. Its value should be masked.

OH

OL

OH

,

,

,

27/61

M58LW032A

Table 10. Status Register Bits

OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RB

Program/Erase Controller active 0
Write Buffer not ready 0

V
V

OL

OL

V
V

OL

OL

V
V

OL

OL

V
V

OL

OL

V
V

OL

OL

V

OL

V

OL

Write Buffer ready 1000000Hi-Z 80h
Write Buffer ready in Erase Suspend 1100000Hi-Z C0h
Program suspended 1000010Hi-Z 84h
Program suspended in Erase Suspend 1100010Hi-Z C4h
Program/Block Protect com plete d

successfully
Program completed successfully in Erase

Suspend
Program/Block protect failure due to

incorrect command sequence
Program failure due to incorrect command

sequence in Erase Suspend
Word Program/Block Protect failure due to

error

V

PP

Word Program failure due to V

error in

PP

Erase Suspend

1000000Hi-Z 80h

1100000Hi-Z C0h

1011000Hi-Z B0h

1111000Hi-Z F0h

1001100Hi-Z 98h

1101100Hi-Z D8h

Program failure due to Block Protection 1001001Hi-Z 92h

Result

(Hex)

V

OL

V

OL

N/A
N/A

Program failure due to Block Protection in
Erase Suspend

Program/Block Protect failure due to cell
failure

Program failure due to cell failure in Erase
Suspend

1101001Hi-Z D2h

1001000Hi-Z 90h

1101000Hi-Z D0h

Erase Suspended 1100000Hi-Z C0h
Erase/Blocks Unprotect completed

successfully
Erase/Blocks Unprotect failure due to

incorrect command sequence
Erase/Blocks Unprotect failure due to V

error

1000000Hi-Z 80h

1011000Hi-Z B0h

PP

1010100Hi-Z A8h

Erase failure due to Block Protection 1010001Hi-Z A2h
Erase/Blocks Unprotect failure due to

failed cells in Block

1010000Hi-Z A0h

28/61

MAXIMUM RATING

Stressing the device above the ratings listed in Ta­ble 11, Absolute Maximum Ratings, may cause
permanent damage to the device. These are
stress ratings only and operation of the dev ice at
these or any other conditions above those indicat­ed in the Operating sections of this specification is

Table 11. Absolute Maximum Ratings

Symbol Parameter

T

BIAS

T

STG

V

IO

, V

V

DD

DDQ

Temperature Under Bias –40 125 °C
Storage Temperature –55 150 °C
Input or Output Voltage –0.6
Supply Voltage –0.6 5.0 V

M58LW032A

not implied. Exposure to Absol ute Maxim um Ra t­ing conditions for extended periods may affect de­vice reliability. Refer also to the
STMicroelectronics SURE Program and other rel­evant quality documents.

Value

Min Max

V

DDQ

+0.6

Unit

V

29/61

M58LW032A

DC AND AC PARAMETERS

This section summarizes the operat ing and mea­surement conditions, and the DC and AC charac­teristics of the device. The parameters in t he DC
and AC characteristics Tables that follow, are de­rived from tests performed under the Measure-

Table 12. Operating and AC Measurement Conditions

Parameter

Supply Voltage (V
Input/Output Supply Voltage (V

Ambient Temperature (T

DD

)

)

DDQ

Grade 1 0 70 0 70 °C

)

A

Grade 6 –40 85 –40 85 °C

ment Conditions summarized in Table 12,
Operating and AC Measurem ent Conditions. De­signers should check that the operating conditions
in their circuit match the measurement conditions
when relying on the quoted parameters.

Min Max Min Max

2.7 3.6 2.7 3.6 V

1.8

M58LW032A

90 110

V

DD

1.8

V

DD

Units

V

Load Capacitance (C

)

L

30 30 pF
Clock Rise and Fall Times 3 3 ns
Input Rise and Fall Times 4 4 ns
Input Pulses Voltages
Input and Output Timing Ref. Voltages

Figure 9. AC Me asurement In put Ou t put Waveform

V

DDQ

0.5 V

0V

DDQ

AI00610

0 to V

DDQ

0.5 V

DDQ

Figure 10. AC Measurement Lo a d Cir c ui t

V

DDQ

V

DD

0.1µF

0.1µF

0 to V

DDQ

0.5 V

DDQ

1.3V

1N914

3.3kΩ

DEVICE
UNDER

TEST

CL

CL includes JIG capacitance

V
V

DQ

AI03459

S

Table 13. Capacitance

Symbol Parameter Test Condition Typ Max Unit

C

IN

C

OUT

Note: 1. TA = 25°C, f = 1 MHz

2. Sampled only, not 100% tested.

Input Capacitance
Output Capacitance

30/61

V

V

OUT

IN

= 0V

= 0V

68pF
812pF

M58LW032A

Table 14. DC Characteristics

Symbol Parameter Test Condition Min Max Unit

I

I

DDB

I
I
I

I

I

V

V

V

V

I

LI

I

LO

DD

DD1

DD5

DD2

DD3

DD4

V

IL

IH

OL

OH

LKO

0V≤ V

Input Leakage Curren t
Output Leakage Current
Supply Current (Random Read)
Supply Current (Burst Read)
Supply Current (Standby)
Supply Current (Auto Low-Power)
Supply Current (Reset/Power-Down)
Supply Current (Program or Erase,

Block Protect, Blocks Unprotect)
Supply Current

(Erase/Program Suspend)

0V

E

= VIL, G = VIH, f

E

= VIL, G = VIH, f

E
E

Program or Erase operation in

≤ V

IN

DDQ

≤ V

≤V

OUT

DDQ

add

clock

= VIH, RP = V

= VIL, RP = V

RP

= V

IL

progress

= V

E

IH

= 6MHz

= 50MHz

IH

IH

Input Low Voltage –0.5
Input High Voltage
Output Low Voltage
Output High Voltage

I

= 100µA

OL

I

= –100µA V

OH

0.7× V

DDQ

VDD Supply Voltage (Erase and
Program lockout)

0.3× V

DDQVDDQ

–0.2

±1 µA
±5 µA
20 mA
30 mA
40 µA
40 µ A
40 µA

30 mA

40 µA

DDQ

+ 0.5

V
V

0.2 V
V

2V

31/61

M58LW032A

Figure 11. Asynchronous Bus Read AC Waveforms

tAVAV

A1-A21

VALID

tELQV

tELQX

E

L

tGLQV

tGLQX

G

tAVQV

DQ0-DQ15

Note: Asyn chronous Read M 15 = 1

OUTPUT

Table 15. Asynchronous Bus Read AC Characteristics.

Symbol Parameter Test Condition

t

AVAV

t

AVQV

t

ELQX

t

ELQV

t

GLQX

t

GLQV

t

EHQX

t

GHQX

t

AXQX

t

EHQZ

t

GHQZ

Address Valid to Address Valid
Address Valid to Output Valid
Chip Enable Low to Output Transition
Chip Enable Low to Output Valid
Output Enable Low to Output Transition
Output Enable Low to Output Valid
Chip Enable High to Output Transition
Output Enable High to Output Transition
Address Transition to Output Transition
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z

E

= VIL, G = V

E

= VIL, G = V

G

= V

G

= V

E

= V

E

= V

G

= V

E

= V

E

= VIL, G = V

G

= V

E

= V

IL

IL

IL

IL

IL

IL

IL

IL

IL

IL

IL

tAXQX

tEHQZ

tEHQX

tGHQZ
tGHQX

AI05502

M58LW032A

Unit

90 110

Min 90 110 ns

Max 90 110 ns

Min 0 0 ns

Max 90 110 ns

Min 0 0 ns

Max 25 25 ns

Min 0 0 ns
Min 0 0 ns

Min 0 0 ns
Max 25 25 ns
Max 20 20 ns

32/61

Figure 12. Asynchronous Latch Controlled Bus Read AC Waveforms

M58LW032A

A1-A21

tAVLL

L

E

G

DQ0-DQ15

Note: Asynchronous Read M15 = 1

tAVLH

VALID

tELLL

tLHAX

tLLLH
tELLH

tGLQV
tGLQX

tLLQX
tLLQV

tEHLXtLHLL

tEHQZ
tEHQX

tGHQX

OUTPUT

Table 16. Asynchronous Latch Controlled Bus Read AC Characteris tics

Symbol Parameter Test Condition

t

AVLL

t

AVLH

t

LHLL

t

LLLH

t

ELLL

t

ELLH

t

LLQX

t

LLQV

t

LHAX

t

GLQX

t

GLQV

t

EHLX

Note: For ot her timings see Table 15, As ynchronous B us Read Chara ct eristics.

Address Valid to Latch Enable Low
Address Valid to Latch Enable High
Latch Enable High to Latch Enable Low Min 10 10 ns
Latch Enable Low to Latch Enable High
Chip Enable Low to Latch Enable Low Min 0 0 ns
Chip Enable Low to Latch Enable High Min 10 10 ns
Latch Enable Low to Output Transition
Latch Enable Low to Output Valid
Latch Enable High to Address Transition
Output Enable Low to Output Transition
Output Enable Low to Output Valid
Chip Enable High to Latch Enable Transition Min 0 0 ns

E

= V

E

= V

E

= V

E

= VIL, G = V

E

= VIL, G = V

E

= V

E

= V

E

= V

IL
IL

IL

IL
IL

IL

Min 0 0 ns

Min 10 10 ns

Min 10 10 ns

Min 0 0 ns

IL

Min 90 110 ns

IL

Min 6 6 ns

Min 0 0 ns
Max 25 25 ns

tGHQZ

AI05503

M58LW032A

Unit

90 110

33/61

M58LW032A

Figure 13. Asynchronous Page Read AC Waveforms

A1-A2

A3-A21

tAVQV

E

L

G

DQ0-DQ15

Note: Asyn chronous Read M 15 = 1

VALID VALID

VALID

tELQV
tELQX

tGLQV

tGLQX

OUTPUT OUTPUT

Table 17. Asynchronous Page Read AC Characteristics

Symbol Parameter Test Condition

t

AXQX1

t

AVQV1

Note: For ot her timings see Table 15, As ynchronous B us Read Chara ct eristics.

Address Transition to Output Transition
Address Valid to Output Valid

E

= VIL, G = V

E

= VIL, G = V

tAXQX

tAVQV1

tAXQX1

tEHQZ
tEHQX

tGHQZ

tGHQX

M58LW032A

90 110

Min 6 6 ns

IL

Max 25 25 ns

IL

AI05504

Unit

34/61

Figure 14. Asynchronous Write AC Waveform, Write Enable Controlled

M58LW032A

A1-A21

E

L

G

W

DQ0-DQ15

RB

V

PP

tELWL

tGHWL

tAVWH

tVPHWH

VALID

tWHEH

tWLWH

tDVWH

INPUT

tWHAX

tWHDX

tWHBL

tWHWL

tWHGL

Figure 15. Asynchronous Lat ch C on t rol le d W ri te AC Waveform, Write Ena bl e Cont ro ll ed

AI05505

A1-A21

L

E

G

W

DQ0-DQ15

RB

V

PP

tELLL

tELWL

tGHWL

tAVLH

VALID

tLLLH

tWLLH

tLHWH

tWLWH

tDVWH

tVPHWH

INPUT

tLHAX

tWHEH

tWHDX

tWHBL

tWHWL

tLHGL

tWHGL

AI05506

35/61

M58LW032A

Table 18. Asynchronous Write and Latch Controlled Write AC Characteristics, Write Enable Controlled.

Symbol Parameter Test Condition

t

AVLH

t

AVWH

t

DVWH

t

ELWL

t

ELLL

t

LHAX

t

LHGL

t

LHWH

t

LLLH

t

LLWH

t

VPHWH

t

WHAX

t

WHBL

t

WHDX

t

WHEH

t

GHWL

t

WHGL

t

WHWL

t

WLWH

t

WLLH

Address Valid to Latch Enable High Min 10 10 ns

E
E

= V
= V

Min 50 50 ns

IL

Min 50 50 ns

IL

Address Valid to Write Enable High
Data Input Valid to Write Enable High
Chip Enable Low to Write Enable Low Min 0 0 ns
Chip Enable Low to Latch Enable Low Min 0 0 ns
Latch Enable High to Address Transition Min 6 6 ns
Latch Enable High to Output Enable Low Min 95 95 ns
Latch Enable High to Write Enable High Min 0 0 ns
Latch Enable low to Latch Enable High Min 10 10 ns
Latch Enable Low to Write Enable High Min 50 50 ns
Program/Erase Enable High to Write Enable High Min 0 0 ns

E

Write Enable High to Address Transition

= V

Min 10 10 ns

IL

Write Enable High to Ready/Busy low Max 500 500 ns

E

Write Enable High to Input Transition

= V

Min 10 10 ns

IL

Write Enable High to Chip Enable High Min 0 0 ns
Output Enable High to Write Enable Low Min 20 20 ns
Write Enable High to Output Enable Low Min 35 35 ns
Write Enable High to Write Enable Low Min 30 30 ns

E
E

= V
= V

Min 70 70 ns

IL

Min 10 10 ns

IL

Write Enable Low to Write Enable High
Write Enable Low to Latch Enable High

M58LW032A

90 110

Unit

36/61

Figure 16. Asynchronous Write AC Waveforms, Chip Enable Controlled

M58LW032A

A1-A21

W

G

E

L

DQ0-DQ15

RB

V

PP

tWLEL

tGHEL

tAVEH

VALID

tELEH

tDVEH

tVPHEH

INPUT

tEHAX

tEHWH

tEHDX

tEHBL

tEHEL

tEHGL

Figure 17. Asynchronous Latch Controlled Write AC Waveforms, Chip Enable Controlled

AI05507

A1-A21

L

W

G

E

DQ0-DQ15

RB

V

PP

tWLLL

tWLEL

tAVLH

tAVEH

VALID

tLLLH

tELLH

tELEH

tDVEH

tVPHEH

INPUT

tLHAX

tEHAX

tLHEH

tEHWH

tEHDX

tEHBL

tEHEL

tLHGL

tEHGLtGHEL

AI05508

37/61

M58LW032A

Table 19. Asynchronous Write and Latch Controlled Write AC Characteristics, Chip Enable
Controlled

Symbol Parameter Test Condition

t

AVLH

t

AVEH

t

DVEH

t

WLEL

t

WLLL

t

LHAX

t

LHGL

t

LHEH

t

LLLH

t

LLEH

t

VPHEH

t

EHAX

t

EHBL

t

EHDX

t

EHWH

t

GHEL

t

EHGL

t

EHEL

t

ELEH

t

ELLH

Address Valid to Latch Enable High Min 10 10 ns

W
W

= V
= V

Min 5 0 50 ns

IL

Min 5 0 50 ns

IL

Address Valid to Chip Enable High
Data Input Valid to Chip Enable High
Write Enable Low to Chip Enable Low Min 0 0 ns
Write Enable Low to Latch Enable Low Min 0 0 ns
Latch Enable High to Address Transition Min 6 6 ns
Latch Enable High to Output Enable Low Min 35 35 ns
Latch Enable High to Chip Enable High Min 0 0 ns
Latch Enable low to Latch Enable High Min 10 10 ns
Latch Enable Low to Chip Enable High Min 50 50 ns
Program/Erase Enable High to Chip Enable High Min 0 0 ns

W

Chip Enable High to Address Transition

= V

Min 1 0 10 ns

IL

Chip Enable High to Ready/Busy low Max 500 500 ns

W

Chip Enable High to Input Transition

= V

Min 1 0 10 ns

IL

Chip Enable High to Write Enable High Min 0 0 ns
Output Enable High to Chip Enable Low Min 20 20 ns
Chip Enable High to Output Enable Low Min 35 35 ns
Chip Enable High to Chip Enable Low Min 30 30 ns

W
W

= V
= V

Min 7 0 70 ns

IL

Min 1 0 10 ns

IL

Chip Enable Low to Chip Enable High
Chip Enable Low to Latch Enable High

M58LW032A

90 110

Unit

38/61

Figure 18. Synchronous Burst Read AC Waveform

M58LW032A

AI05509

X+2Y+1 X+2Y+2

X+2YX+YX

X-1

2

tKHAX

tLHAX

tEHQX

tEHQZ

tGHQZ

tGHQX

tGLKH

Q2 Q3

tKHQX

Q1

tQVKH

tKHQV

1

0

tKHLL

K

Note: Valid Cl ock Edge = Rising (M6 = 1)

VALID

A1-A21

tLLKH

tLLLH

tELLH

tELKH

tAVLH

tAVKH

L

E

G

DQ0-DQ15

39/61

M58LW032A

Figure 19. Synchronous Burst Read - Continuous - Valid Data Ready Output

K

(2)

Output

R

Note: 1. Valid Data Ready = Va l i d Lo w during val i d clock edge (M8 = 0)

2. V= Valid output, NV= Not Valid output.

3. R is an ope n drain ou tput wi th an inte rnal pul l up resi stor of 1M Ω. Dep ending on the Vali d Data Re ady pin capa citan ce load an
external pul l up resistor must b e chosen accor di ng to the system clock period.

V

V V NV NV V V

tRLKH

(3)

Table 20. Synchronous Burst Read AC Characteristics

Symbol Parameter Test Condition

t

AVKH

t

AVLH

t

ELKH

t

ELLH

t

GLKH

t

KHAX

t

KHLL

t

KHLH

t

KHQX

t

LLKH

t

LLLH

t

KHQV

t

QVKH

t

RLKH

Note: For ot her timings see Table 15, As ynchronous B us Read Chara ct eristics.

Address Valid to Active Clock Edge
Address Valid to Latch Enable High
Chip Enable Low to Active Clock Edge
Chip Enable Low to Latch Enable High
Output Enable Low to Valid Clock Edge
Valid Clock Edge to Address Transition
Valid Clock Edge to Latch Enable Low
Valid Clock Edge to Latch Enable High
Valid Clock Edge to Output Transition
Latch Enable Low to Valid Clock Edge
Latch Enable Low to Latch Enable High
Valid Clock Edge to Output Valid
Output Valid to Active Clock Edge
Valid Data Ready Low to Valid Clock Edge

E

E
E
E

E

= V

IL

E

= V

IL

E

= V

IL

E

= V

IL

E

= VIL, L = V

E

= V

E

= V

E

= V

IH

IL

IL

IL

= VIL, G = VIL, L = V

E

= V

IL

E

= V

IL

= VIL, G = VIL, L = V
= VIL, G = VIL, L = V
= VIL, G = VIL, L = V

Min 7 7 ns
Min 10 10 ns
Min 10 10 ns
Min 10 10 ns
Min 20 20 ns
Min 5 5 ns
Min 0 0 ns
Min 0 0 ns
Min 3 3 ns

IH

Min 6 6 ns
Min 6 6 ns

Max 10 10 ns

IH

Min 5 5 ns

IH

Min 5 5 ns

IH

M58LW032A Unit
90 110

AI05510

40/61

Figure 20. Reset, Power-Down and Power-up AC Waveform

W

E, G

DQ0-DQ15

tPHQV

RB

RP

tVDHPH tPLPH

VDD, VDDQ

M58LW032A

tPLRH

Power-Up
and Reset

Table 21. Reset, Power-Down and Power-u p AC Charac teris tics

Symbol Parameter

t

PHQV

t

PLPH

t

PLRH

t

VDHPH

Reset/Power-Down High to Data Valid Max 150 150 ns
Reset/Power-Down Low to Reset/Power-Down High Min 100 100 ns
Reset/Power-Down Low to Ready High Max 30 30 µs
Supply Voltages High to Reset/Power-Down High Min 0 0 µs

Reset during
Program or Erase

AI05521

M58LW032A

Unit

90 110

41/61

M58LW032A

PACKAGE MECHANICAL

Figure 21. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Outline

A2

1

N

e

E

B

N/2

D1

D

DIE

A

CP

C

TSOP-a

Note: Drawing is not to scale.

LA1 α

Table 22. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package M echa nical Data

Symbol

Typ Min Ma x Typ Min Max

A 1.20 0.0472

mm inches

A1 0.05 0.15 0.0020 0.0059
A2 0.95 1.05 0.0374 0.0413

B 0.17 0.27 0.0067 0.0106
C 0.10 0.2 1 0.0039 0.0083
D 19.80 20.20 0.7795 0.7953

D1 18.30 18.50 0.7205 0.7283

E 13.90 14.10 0.5472 0 .5551
e 0.50 – – 0.0197 – –
L 0.50 0.7 0 0.0197 0.0276
α 0° 5° 0° 5°
N56 56

CP 0.10 0.0039

42/61

Figure 22. TBGA64 10x13mm - 8x8 ball array 1mm pitch, Packag e Outlin e

D

FD

FE

D1

SD

M58LW032A

SE

ddd

A2

A1

BGA-Z23

Note: Drawing is not to scale.

E1E

BALL "A1"

eb

A

Table 23. TBGA64 10x13mm - 8x8 ball array, 1mm pitch, Package Mechan ica l Data

Symbol

Typ Min Ma x Typ Min Max

A 1.200 0.0472
A1 0.300 0.200 0.350 0.0118 0.0079 0.0138
A2 0.850 0.0335

b 0.400 0.500 0.0 157 0.0197

D 1 0.000 9.900 10.100 0.3937 0.3898 0.3976
D1 7.000 – – 0.2756 – –

ddd 0.100 0.0039

millimeters inches

e 1.000 – – 0.0394 – –

E 13.000 1 2.900 13.100 0.5118 0.5079 0.5157
E1 7.000 – – 0.2756 – –
FD 1 .500 – – 0.0591 – –
FE 3.000 – – 0.1181 – –
SD 0.500 – – 0.0197 – –
SE 0 .500 – – 0.0197 – –

43/61

M58LW032A

PART NUMBERING

Table 24. Ordering Information Scheme

Example: M58LW032A 90 N 1 T

Device Type

M58

Architecture

L = Page Mode, Burst Mode

Operating Voltage

W = V

Device Function

032A = 32 Mbit (x16), Uniform Block

Speed

90 = 90ns
110 = 110ns

= 2.7V to 3.6V; V

DD

= 1.8V to V

DDQ

DD

Package

N = TSOP56: 14 x 20 mm
ZA = TBGA64: 10 x 13 mm, 1mm pitch

Temperature Range

1 = 0 to 70 °C
6 = –40 to 85 °C

Option

T = Tape & Reel Packing

Note: Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Pac kage, etc...) or for furthe r information on any aspect of this de-

vice, please contact the ST Sales Office nearest to you.

44/61

APPENDIX A. BLOCK ADDRESS TABLE

M58LW032A

Table 25. Block Addresses

Block Number

64 1F8000h-1FFFFFh
63 1F0000h-1F7FFFh
62 1E8000h-1EFFFFh
61 1E0000h-1E7FFFh
60 1D8000h-1DFFFFh
59 1D0000h-1D7FFFh
58 1C8000h-1CFFFFh
57 1C0000h-1C7FFFh
56 1B8000h-1BFFFFh
55 1B0000h-1B7FFFh
54 1A8000h-1AFFFFh
53 1A0000h-1A7FFFh
52 198000h-19FFFFh
51 190000h-197FFFh
50 188000h-18FFFFh
49 180000h-187FFFh
48 178000h-17FFFFh
47 170000h-177FFFh
46 168000h-16FFFFh
45 160000h-167FFFh
44 158000h-15FFFFh
43 150000h-157FFFh
42 148000h-14FFFFh
41 140000h-147FFFh
40 138000h-13FFFFh
39 130000h-137FFFh
38 128000h-12FFFFh
37 120000h-127FFFh
36 118000h-11FFFFh
35 110000h-117FFFh
34 108000h-10FFFFh
33 100000h-107FFFh

Address Range

(x16 Bus Width)

Block Number

32 0F8000h-0FFFFFh
31 0F0000h-0F7FFFh
30 0E8000h-0EFFFFh
29 0E0000h-0E7FFFh
28 0D8000h-0DFFFFh
27 0D0000h-0D7FFFh
26 0C8000h-0CFFFFh
25 0C0000h-0C7FFFh
24 0B8000h-0BFFFFh
23 0B0000h-0B7FFFh
22 0A8000h-0AFFFFh
21 0A0000h-0A7FFFh
20 098000h-09FFFFh
19 090000h-097FFFh
18 088000h-08FFFFh
17 080000h-087FFFh
16 078000h-07FFFFh
15 070000h-077FFFh
14 068000h-06FFFFh
13 060000h-067FFFh
12 058000h-05FFFFh
11 050000h-057FFFh
10 048000h-04FFFFh

9 040000h-047FFFh
8 038000h-03FFFFh
7 030000h-037FFFh
6 028000h-02FFFFh
5 020000h-027FFFh
4 018000h-01FFFFh
3 010000h-017FFFh
2 008000h-00FFFFh
1 000000h-007FFFh

Address Range

(x16 Bus Width)

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M58LW032A

APPENDIX B. COMMON FLASH INTERFACE - CFI

The Common Flash Interface is a JEDEC ap­proved, standardized data structure that can be
read from the Flash memory device. It allows a
system software to query the device to det ermine
various electrical and t iming parameters, density
information and functions supported by the mem­ory. The system can interface easily with the de-

Table 26. Query Structure Overview

Offset Sub-section Name Description

00h Manufacturer Code
01h Device Code
10h CFI Query Identification String Command set ID and algorithm data offset
1Bh System Interface Information Device timing and voltage information
27h Device Geometry Definition Flash memory layout

vice, enabling the software to upgrade itself when
necessary.

When the CFI Query C ommand (RCFI) is issued
the device enters CFI Query mode and the data
structure is read from the memory. Tables 26 , 27,
28, 29, 30 and 31 show the addresses used to re­trieve the data.

(1)

P(h)

A(h)

(SBA+02)h Block Status Register Block-related Information

Note: 1. Offset 15h defines P which points to the Primary Algorith m Extended Query Address Ta bl e.

2. Offset 19h defines A which points to th e Alt ernate Algori thm Extended Query Address Tabl e.

3. SBA is the S tart Base Addr ess for each block.

Primary Algorithm-specific Extended Query Table

(2)

Alternate Algorithm-specific Extended Query Table

Additional information specific to the Primary
Algorithm (optional)

Additional information specific to the Alternate
Algorithm (optional)

Table 27. CFI - Query Address and Data Output

Address

A21-A1

10h 51h "Q"
11h 52h "R"
12h 59h "Y"
13h 01h
14h 00h
15h 31h
16h 00h
17h 00h
18h 00h

Data Instruction

51h; "Q"
Query ASCII String 52h; "R"

59h; "Y"

Primary Vendor:
Command Set and Control Interface ID Code

Primary algorithm extended Query Address Table: P(h)

Alternate Vendor:
Command Set and Control Interface ID Code

19h 00h

(2)

1Ah

Note: 1. Query Dat a are always pr esented on DQ7-DQ0. DQ15 -DQ8 are set to '0'.

2. Offset 19h defines A which points to th e Alt ernate Algori thm Extended Query Address Table.

46/61

00h

Alternate Algorithm Extended Query address Table

Table 28. CFI - Device Voltage and Timing Specification

Address A21-A1

1Bh
1Ch
1Dh
1Eh
1Fh

20h 08h
21h 0Ah
22h

Data Description

(1)

27h
36h
00h
00h

04h

00h

(2)

VDD Min, 2.7V

(1)

VDD max, 3.6V
VPP min – Not Available

(2)

VPP max – Not Available
2n µs typical time-out for Word, DWord prog – Not Available

n

2

µs, typical time-out for max buffer write

n

2

ms, typical time-out for Erase Block

(3)

2n ms, typical time-out for chip erase – Not Available

M58LW032A

23h
24h 04h
25h 04h
26h

Note: 1. Bits are coded in Binary Code Decimal, bi t 7 to bit4 are scaled i n Volts and bit3 t o bi t0 in mV.

2. Bit7 to bit4 are coded in Hexadecimal and scaled in Volt s while bit3 to bit 0 are in Binary C ode Decimal and scaled in 100mV.

3. Not supported.

04h 2n x typical for Word Dword time-out max – Not Available

n

2

x typical for buffer write time-out max

n

2

x typical for individual block erase time-out maximum

(3)

00h

2n x typical for chip erase max time-out – Not Available

Table 29. Device Geometry Definition

Address

A21-A1

27h 16h
28h

29h
2Ah 05h
2Bh 00h
2Ch 01h Bit7-0 = number of Erase Block Regions in device
2Dh 3Fh
2Eh 00h
2Fh 00h
30h 01h

Data Description

n

is number of bytes memory Size

01h
00h

n where 2

Device Interface

Maximum number of bytes in Write Buffer, 2

Number (n-1) of Erase Blocks of identical size; n=64

Erase Block Region Information
x 256 bytes per Erase block (128K bytes)

n

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M58LW032A

Table 30. Block Status Register

Address A21-A1 Data Selected Block Information

bit0

(BA+2)h

(1)

bit1

bit7-2 0 Reserved for future features

Note: 1. BA specifies the block address loca tion, A21-A1 7.

2. Not Supported.

0 Block Unprotected
1 Block Protected

0
1

Last erase operation ended successfully
Last erase operation not ended successfully

(2)

(2)

48/61

Table 31. Extended Query information

Address

offset

(P)h 31h 50h "P"

(P+2)h 33h 49h "I"
(P+3)h 34h 31 h Major version number
(P+4)h 35h 31 h Minor version number
(P+5)h 36h CEh Optional Feature: (1=yes, 0=no)
(P+6)h 37h 01h
(P+7)h 38h 00h

(P+8)h 39h 00h

(P+9)h 3Ah 01h

Address

A21-A2

Data (Hex)

x16 Bus Width

Query ASCII string - Extended Table(P+1)h 32h 52h "R"

bit0, Chip Erase Supported (0=no)
bit1, Suspend Erase Supported (1=yes)
bit2, Suspend Program Supported (1=yes)
bit3, Protect/Unprotect Supported (1=yes)
bit4, Queue Erase Supported (0=no)
bit5, Instant Individual Block locking (0=no)
bit6, Protection bits supported (1=yes)
bit7, Page Read supported (1=yes)
bit8, Synchronous Read supported (1=yes)
Bits 9 to 31 reserved for future use

Function allowed after Suspend:
Program allowed after Erase Suspend (1=yes)
Bit 7-1 reserved for future use

M58LW032A

Description

(P+A)h 3Bh

01h

(P+B)h 3Ch 00h

(P+C)h 3Dh 33h
(P+D)h 3Eh 00h

Block Status Register
bit0, Block Protect Bit status active (1=yes)
bit1, Block Lock-Down Bit status, not supported
bits 2 to 15 reserved for future use

OPTIMUM Program/Erase voltage conditions

V

DD

V

OPTIMUM Program/Erase voltage conditions

PP

(P+E)h 3Fh 01h OTP protection: No. of protection register fields
(P+F)h 40h 80h Protection Register’s start address, least significant bits

(P+10)h 41h 00h Protection Register’s start address, most significant bits
(P+11)h 42h 03h
(P+12)h 43h 03h
(P+13)h 44h 04h

n where 2
n where 2
Page Read: 2

n

is number of factory reprogrammed bytes

n

is number user programmable bytes

n

Bytes (n = bits 0-7)
(P+14)h 45h 03h Synchronous mode configuration fields
(P+15)h 46h 01h

(P+16)h 47h 02h

n where 2
n where 2

n+1

is the number of Words for the burst Length = 4

n+1

is the number of Words for the burst Length = 8

(P+17)h 48h 07h Burst Continuous

Note: 1. Bit7 to bit4 are coded in Hexadecimal and scaled in Volt while bit3 to bit0 are in Binary Code Decimal and scaled in mV.

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M58LW032A

APPENDIX C. FLOW CHARTS

Figure 23. Write to Buffer and Program Flowchart and Pseudo Code

Start

Write to Buffer E8h

Command, Block Address

Read Status

Register

NO

Note 1: N+1 is number of Words

to be programmed

Note 2: Next Program Address must

have same A5-A21.

YES

(1)

NO

NO

,

YES

b7 = 1

Write N

Block Address

Write Buffer Data,

Start Address

X = 0

X = N

Write Next Buffer Data,
Next Program Address

X = X + 1

Write to Buffer

Timeout

(2)

YES

Try Again Later

Note 3: A full Status Register Check must be

done to check the program operation's

success.

50/61

Program Buffer to Flash

Confirm D0h

Read Status

Register

YES

NO

(3)

b7 = 1

Full Status

Register Check

End

AI05511

Figure 24. Program Suspend & Resume Flowchart and Pseudo Code

Start

Write B0h

M58LW032A

Write 70h

Read Status

Register

b7 = 1

YES

b2 = 1

YES

Write FFh

Read data from

another block

Write D0h

Program Continues

NO

NO

Program Complete

Write FFh

Read Data

Program/Erase Suspend Command:
– write B0h
– write 70h

do:
– read status register

while b7 = 1

If b2 = 0, Program completed

Read Memory Array instruction:
– write FFh
– one or more data reads
from other blocks

Program Erase Resume Command:
– write D0h
to resume erasure
– if the program operation completed
then this is not necessary. The device
returns to Read Array as normal
(as if the Program/Erase Suspend
command was not issued).

AI00612

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M58LW032A

Figure 25. Erase Flowchart and Pseudo Code

Start

Write 20h

Write D0h to

Block Address

Read Status

Register

b7 = 1

YES

b3 = 0

YES

b4, b5 = 0

YES

b5 = 0

NO

NO

NO

NO

NO

Suspend

VPP Invalid

Error (1)

Command

Sequence Error

Erase

Error (1)

YES

Suspend

Loop

Erase command:

– write 20h

– write D0h to Block Address

(A12-A17)

(memory enters read Status

Register after the Erase command)

do:

– read status register

– if Program/Erase Suspend command

given execute suspend erase loop

while b7 = 1

If b3 = 1, VPP invalid error:

– error handler

If b4, b5 = 1, Command Sequence error:

– error handler

If b5 = 1, Erase error:

– error handler

YES

b1 = 0

End

NO

YES

Erase to Protected

Block Error

If b1 = 1, Erase to Protected Block Error:

– error handler

AI00613B

Note: 1. If an err or is found, t he Status R egi ster must be cleared (Cl ear Statu s R egister Comm and) befo re further P rogram or Er ase oper-

ations.

52/61

Figure 26. Erase Suspend & Resume Flowchart and Pseudo Code

Start

Write B0h

M58LW032A

Write 70h

Read Status

Register

b7 = 1

YES

b6 = 1

YES

Write FFh

Read data from

another block

or Program

Write D0h

Erase Continues

NO

NO

Erase Complete

Write FFh

Read Data

Program/Erase Suspend Command:

– write B0h

– write 70h

do:

– read status register

while b7 = 1

If b6 = 0, Erase completed

Read Memory Array command:

– write FFh

– one or more data reads

from other blocks

Program/Erase Resume command:

– write D0h to resume the Erase

operation

– if the Program operation completed

then this is not necessary. The device

returns to Read mode as normal

(as if the Program/Erase suspend

was not issued).

AI00615

53/61

M58LW032A

Figure 27. Bl ock P rot ect Flowcha rt an d P se ud o C od e

Start

Write 60h

Block Address

Write 01h

Block Address

Block Protect Command
– write 60h, Block Adress
– write 01h, Block Adress

Read Status Register

(toggle G or E )

b7 = 1

YES

b3 = 1

b4, b5 = 1,1

b4 = 1

Block Protect

Sucessful

YES

NO

NO

NO

NO

YES

YES

VPP Invalid

Error

Invalid Command

Sequence Error

Block Protect

Error

do:
– read status register ( toggle G or E,
do not use the Read Status Register command)

while b7 = 1

If b3 = 1, V

If b4 = 1, b5 = 1 Invalid Command Sequence

If b4 = 1, Block Protect Error

Invalid Error

PP

Error

54/61

Write FFh

End

Read Memory Array Command:
– write FFh

AI06157b

Figure 28. Blocks Unprotect Flowchart and Pseudo Code

Start

M58LW032A

Write 60h

Write D0h

Read Status Register

(toggle G or E )

b7 = 1

YES

b3 = 1

NO

b4, b5 = 1,1

NO

NO

YES

YES

V

Invalid

PP

Error

Invalid Command

Sequence Error

Block Unprotect Command
– write 60h, Block Adress
– write D0h, Block Adress

do:
– read status register ( toggle G or E,
do not use the Read Status Register command)

while b7 = 1

If b3 = 1, V

If b4 = 1, b5 = 1 Invalid Command

Sequence Error

Invalid Error

PP

b5 = 1

NO

Blocks Unprotect

Sucessful

Write FFh

End

YES

Blocks Unprotect

Error

If b5 = 1, Blocks Unprotect Error

Read Memory Array Command:
– write FFh

AI06158b

55/61

M58LW032A

Figure 29. Protection Register Program Flowchart and Pseudo Code

Start

Write FFh

Write C0h

Write

PR Address, PR Data

Read Status Register

(toggle G or E )

b7 = 1

YES

b3 = 1

NO

b4 = 1

NO

YES

YES

V

Invalid Error

PP

Protection Register

Program Error

Read Memory Array Command
– write FFh

Protection Register Program Command
– write C0h
– write Protection Register Address,
Protection Register Data

do:
– read status register (toggle G or E,
do not use the Read Status Register command)

while b7 = 1

If b3 = 1 V

If b4 = 1 Protection Register

Program Error

Invalid Error

PP

b1 = 1

PR Program

Sucessful

Write FFh

End

Note: PR = Protection Register

56/61

NO

NO

YES

Protection Register

Protection Error

If b1 = 1 Program Error due to

Protection Register Protection

Read Memory Array Command:
– write FFh

AI06159b

Figure 30. Command Interface and Program E rase Con trolle r Flowchart (a)

WAIT FOR

COMMAND

WRITE

NO

90h

YES

M58LW032A

READ

SIGNATURE

98h

YES

CFI

QUERY

NO

70h

YES

READ

STATUS

NO

50h

CLEAR

STATUS

PROGRAM
COMMAND

ERROR

YES

NO

NO

PROGRAM

BUFFER

E8h

LOAD

D0h

C

YES

YES

NO

(1)

20h

YES

ERASE

SET-UP

D0h

YES

A

NO

NO

COMMAND

FFh

YES

ERASE

ERROR

READ

ARRAY

NO

B

Note 1. The Erase command (20h) can only be issued if the flash is not already in Erase Suspend.

AI03618

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M58LW032A

Figure 31. Command Interface and Program E rase Con trolle r Flowchart (b)

WAIT FOR

COMMAND

WRITE

B

READ

ARRAY

YES

FFh

NO

ERASE

SUSPENDED

YES

NO

READ

STATUS

YES

YES

A

ERASE

READY

?

NO

B0h

YES

ERASE

SUSPEND

READY

?

NO

READ

STATUS

(READ STATUS)

Program/Erase Controller
Status bit in the Status
Register

NO

READ

STATUS

PROGRAM

COMMAND

ERROR

READ

STATUS

READ

SIGNATURE

CFI

QUERY

PROGRAM

BUFFER

LOAD

NO

D0h

YES

c

YES

YES

YES

YES

70h

NO

90h

NO

98h

NO

E8h

NO

D0h

NO

READ

ARRAY

YES

READ

STATUS

(ERASE RESUME)

AI03619

58/61

Figure 32. Command Interface and Program E rase Con trolle r Flowchart (c).

B

C

M58LW032A

WAIT FOR

COMMAND

WRITE

READ

STATUS

YES

PROGRAM

SUSPENDED

YES

READ

ARRAY

FFh

NO

70h

YES

NO

NO

READ

STATUS

YES

YES

PROGRAM

READY

?

NO

B0h

YES

PROGRAM

SUSPEND

READY

?

NO

READ

STATUS

(READ STATUS)

Program/Erase Controller
Status bit in the Status
Register

NO

READ

STATUS

READ

SIGNATURE

CFI

QUERY

READ

ARRAY

YES

YES

NO

90h

98h

D0h

NO

NO

YES

READ

STATUS

(PROGRAM RESUME)

AI00618

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M58LW032A

REVISION HIST ORY

Table 32. Document Revision History

Date Version Revision Details

February 2001 -01 First Issue (Data Brief)
17-Sep-2001 -02 Expanded to full Product Preview.

Changes on Table 18, Asynchronous Write and Latch Controlled Write AC

27-Sep-2001 -03

1-Feb-2002 -04

12-Mar-2002 -05

07-May-2002 -06

Characteristics, Write Enable Controlled
Changes on Table 20, Synchronous Burst Read AC Characteristics

Status Register section and Table clarified, Burst Configuration Register Table
clarified, Block Protect, Blocks Unprotect and Protection Register Program
flowcharts added, Reset, Power-Down and Power-up AC Characteristics Table
modified.

Document Status changed to Preliminary Data. Table 18, tWHGL timing modified,
Table 19, tLHGL and tEHGL timings modified. I
table, T

removed from Absolute Maximum Ratings table. TFBGA64 Not

LEAD

Connected pins changed to Do Not Use.
Reference to Temporary Unprotect removed from Word Program Command section,

TFBGA package dimensions added to description. Block Protect and Blocks
Unprotect Flowcharts clarified, Protection Register Program description and
Flowchart clarified, Status Register V
Status changed to Datasheet.

modified in DC Characteristics

DD5

Status bit description clarified. Document

PP

04-Jul-2002 -07 110ns speed class added.

Revision numbering modified: a minor revision will be indicated by incrementing the
digit after the dot, and a major revision, by incrementing the digit before the dot.

06-Aug-2002 7.1

(revision version 07 equals 7.0).
Description of Reset/Power-Down pin, RP
descriptions modified. Table 24,Ordering Information Scheme modified.

Revision History moved to end of document. Block Protect setup command address

11-Feb-2003 7.2

modified in Table 6, Commands. CFI, Extended Query Information table descriptions
clarified. Protection Register Program Flowchart and Pseudo code clarified. Table 9,
Program, Erase Times and Program Erase Endurance Cycles modified.

, specified. VDD, V

, VSS and V

DDQ

SSQ

pin

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M58LW032A

Information furnishe d is bel i eved to be accurate and reliable. However, STMicroelectroni cs assumes no resp onsibility for t he consequence s
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or otherwise unde r any patent or patent ri ghts of STMicroelectronics. Speci fications me nt i oned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as crit i cal component s in l i fe support dev i ces or systems wi t hout express written approv al of STMicroelectronics.

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