Datasheet M56693GP, M56693FP Datasheet (Mitsubishi)

MITSUBISHI <CONTROL / DRIVER IC>

)

M56693FP/GP

Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER

DESCRIPTION

The M56693 is a semiconductor integrated circuit that has a built­in, 32-bit shift register and a latch of CMOS structure with serial
input and serial/parallel output, and a 32-bit totem-pole-type
parallel output driver of high pressure proof DMOS structure.
Employed are BI-CMOS and high pressure proof DMOS
processing technology.

FEATURES

● Serial input–serial/parallel output

● Cascade connections possible through serial output

● Latch circuit included for each stage

● Driver supply voltage: VH=120V

● Operating temperature: -20 – 75°C

APPLICATION

Vacuum Fluorescent Display ANODE DRIVER

FUNCTION

The M56693 comprises a 32-bit D type flip-flop with a 32 latches
connected to its output.
In accordance with truth table 1, inputting data to SIN and clock
pulse to CLK allows SIN signal to be put into the internal shift
register when the clock changes from “H” to “L”, and
simultaneously shift register data to be shifted sequentially.
Serial output SOUT is used by connecting to the next stage
M56693 SIN when more than one M56693 is used to expand bits
in the series.
In accordance with truth table 2, parallel output allows the latch to
pass data through if LAT input is turned to “H”, and data to be
retained if LAT is turned to “L”. Driver output HVOn allows data
from the latch to be output if BLK input is turned to “L”, and “L” to
be output if BLK input is turned to “H”, irrespective of data from the
latch.

PIN CONFIGURATION(TOP VIEW

HVO22

HVO21

HVO20

HVO19

HVO18

HVO17

HVO16

HVO15

HVO14

HVO23
HVO24
HVO25
HVO26
HVO27
HVO28
HVO29
HVO30
HVO31
HVO
PGND

N.C

N.C
HVO23
HVO24
HVO25
HVO26
HVO27
HVO28
HVO29
HVO30
HVO31
HVO32

3332313029282726252423
34
35
36
37
38
39
40
41
42

32

43
44

M56693FP

123456789

VH

VDD

N.C

LGND

SOUT

Outline 44P6N-A (FP)

HVO19

HVO18

HVO20

HVO21

HVO22

35

34

36

37
38
39
40
41
42
43
44
45
46
47
48

1

PGND

333231302928272625

M56693GP

2345678

H

V

VDD

LGND

SOUT

CLK

HVO17

CLK

LAT

HVO16

LAT

BLK

HVO15

BLK

SIN

HVO14

9

SIN

HVO13

10

VH

HVO13

10

H

V

HVO12

22
21
20
19
18
17
16
15
14
13
12

11

PGND

HVO12

N.C

11

12

1

HVO

PGND

HVO11
HVO10
HVO 9
HVO 8
HVO 7
HVO 6
HVO 5
HVO 4
HVO 3
HVO 2
HVO 1

24
23
22
21
20
19
18
17
16
15
14
13

N.C
HVO11
HVO10
HVO 9
HVO 8
HVO
N.C
HVO 6
HVO 5
HVO 4
HVO 3
HVO 2

7

Outline 48P6D-A (GP)

N.C: no connection

Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER

↓

BLOCK DIAGRAM (Note : Pin No. in paretheses are of M56693GP)

14

Q

VDD

BLK

(4)

(8)

12

(12) (13) (14)

Output
protect
circuit

3

8

Q

13

Q

MITSUBISHI <CONTROL / DRIVER IC>

M56693FP/GP

32HVO31HVO30HVO 3HVO 2HVO 1

HVO

42 4341

(46) (47)

Q

(48)

1

10

11

44

Q

Q

VH

(2)(10)

PGND

(1)(11)

LAT

SIN

CLK

(7)

(9)

(6)

L

7

9

D

T

6

L

D

Q

D

T

TRUTH TABLE
Truth table 1. Shift register section

CLK

H or L

Shift register operation

Truth table 2. Latch and driver sections

L

D

Q

D

Q

D

T

DATA is shifted.

No changes.

L

D

T

L

D

Q

D

T

L

D

Q

D

LGND

5

(5)

Q

D

2

SOUT

(3)

T

N.C

4

(18)(24)(25)
(37)(38)

HVOnDn LAT BLK

X
H
L

X

X
H
H

L

H
L
L

L

Output all “L”

H

L

Latch’s data output.

Dn=nth bit DFF retention data
HVOn=nth bit driver output
L=“L” level
H=“H” level
X=“L” level or “H” level

MITSUBISHI <CONTROL / DRIVER IC>

M56693FP/GP

Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER

PIN FUNCTION DESCRIPTION

FunctionPin name

VDD
LGND
V

H

PGND

CLK

SIN
SOUT

LAT

BLK
HVO1 – 32

ABSOLUTE MAXIMUM RATINGS (Ta=25°C, unless otherwise noted)

Symbol Ratings UnitParameter Conditions

DD

V

H

V
VI

V

O -0.3 – VDD+0.3

V

HVO

Pd
Tstg

Logic stage supply voltage
Logic stage ground
Output stage supply voltage
Output stage ground

Clock input for the internal shift resister. The data enter the internal shift resisters and the data in the shift registers will be
shifted in order by High to Low change of the clock.

Serial data input
Serial data output
Latch input. When the LATCH is set to “H”, the data in the shift resister will enter the each latch circuit.

When the LATCH input is set to “L”, the data will be held.
Enable input for output control. When the BLK input is set to “L”, data in the latch circuit will appear at outputs.

When the BLK input is set to “H”, all outputs will be set to “L”.
Output driver (push-pull)

Logic stage supply voltage
Output stage supply voltage
Logic inputs voltage
Logic outputs voltage

Outputs voltage
Power dissipation range
Storage temperature range

Data output
High supply voltage output pin

Ta ≤ 25°C

-0.3 – 7

-0.3 – 120

-0.3 – V

-0.3 – V
940

-55 – 150

DD+0.3

H

V
V
V
V
V

mW

°C

RECOMMENDED OPERATING CONDITIONS

Symbol Ratings UnitParameter Conditions

V

DD 4.5 – 5.5

VH

Topr

Supply voltage
Supply voltage

Operating temperature

10 – 110

-20 – 75

ELECTRICAL CHARACTERISTICS (VDD=5V, VH=110V and Ta=25°C, unless otherwise noted)

Symbol Test conditions

IDD

Supply current 1

IH Supply current 2
IIH
IIL
VHVOH

V

HVOL
OH

V
VOL
I

HVOH

IHVOL

TH

V
VTL

“H” input current
“L” input current

Driver output voltage

Logic output voltage
“H” output current

“L” output current
Output protect operating voltage

Parameter

No load
Output all “L”, no load
Output all “H”, no load
V

IH=5V Input pin
IL = 0V

V

SIN, LAT, CLK
BLK

IHVOH = -0.5mA

HVOL = 0.5mA

I
I

OH = -0.1mA
OL = 0.1mA

I
High supply voltage output pin

High supply voltage output pin

Limits

Min. Typ. Max.

1
0

2
02

0

-20

100

106

0.7

4.95

4.5

0.04

-1
1

3.4

3.1

2

50

4

-2

-100

2

0.4

-3
3

V
V

°C

Unit

mA

µA

mA

µA
µA
µA

V

V

mA
mA

V
V

MITSUBISHI <CONTROL / DRIVER IC>

M56693FP/GP

Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER

SWITCHING CHARACTERISTICS (VDD=5V, VH=110V and Ta=25°C, unless otherwise noted)

Symbol Test conditions UnitParameter

fCLK
tPLH(SO)
tPHL(SO)
tPLH(O UT)
tPHL(OUT)
trout
tfout

Clock frequency
Logic output propagation time

Driver output propagation time

Driver output rise and fall time

TEST CIRCUIT

PG

DUT

Duty = 45 – 55%
CL = 15pF

RO = 220KΩ
CO = 50pF

HVDDinput

V

(1) Pulse generator characteristics

tr≤20ns tf≤20ns

(2) Capacitance CL includes connection

SOUT

CL

floating capacitance and probe input
capacitance.
: RO=220KΩ
: CO=50pF

Limits

Min. Typ. Max.

8

120
100

0.16

0.35

300
300

1 µs

1.3

2
1

2.5
2

MHz

ns
ns

µs
µs
µs

50Ω

TIMING WAVEFORM

CLK

SIN

SOUT

BLK

HVOn

CO RO

1/fmax

50% 50%

50%

50%

tsu

tfso trso

90%

50%

10%

tPHL(SO)

50% 50%

th

10%

tPLH(SO)

50%

90%

50%

HVOn

tr

10%

tPLH(OUT)

OUT

90%

50%

90%

tPHL(OUT)

50%

tfOUT

10%

TYPICAL CHARACTERISTICS

MITSUBISHI <CONTROL / DRIVER IC>

M56693FP/GP

Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER

1.0

0.94

0.5

Power dissipation Pd (W)

0

10

9
8
7
6
5
4
3
2

Output current IOH (mA)

1

0

0

Thermal derating

0

Temperature Ta (°C)

Duty cycle vs Permissible
output current

20 10060 8040

Driver output VON–IOH

10

Ta=+75°C

8

Ta=+25°C

6

Ta=-20°C

4

2

“H” output current IOH(mA)

0

100755025

0246810

“H” output voltage V

ON (V)

Duty cycle vs Permissible
output current

1

13–

14
16

24

32

10

Output current IOH (mA)

9
8
7
6
5

4
3
2
1

0

20

0

40

80 100

60

Duty cycle (%)Duty cycle (%)

1 8–
9

16

24
32

Note •

Ta=25°C

•

Repeated frequency >100Hz

•

Figure in the circle represents the number of
concurrently operating output circuits.

•

Current value denotes a numerical value per circuit.

Note

1.

VDD=5V and VH=110V, unless otherwise noted

2.

Thermal derating characteristics represent those of an individual IC unit.

3.

Allowable duty cycle output current characteristics represent that when a standard
substrate is mounted. (Standard substrate: 70x70x1.6mm glass epoxy)

Note •

Ta=75°C

•

Repeated frequency >100Hz

•

Figure in the circle represents the number of
concurrently operating output circuits.

•

Current value denotes a numerical value per circuit.