Datasheet M56692FP Datasheet (Mitsubishi)

MITSUBISHI <CONTROL / DRIVER IC>

K

M56692FP

Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER

DESCRIPTION

The M56692FP is a semiconductor integrated circuit that has a
built-in, 32-bit shift register and a latch of CMOS structure with
serial input and serial/parallel output, and a 32-bit totem-pole-type
parallel output driver of high pressure proof DMOS structure.
Employed are Bi-CMOS and high pressure proof DMOS
processing technology.

FEATURES

● Serial input - serial/parallel output

● Bidirectional shift register (controlled at F/R terminal)

● Cascade connections possible through serial output.

● Latch circuit included for each stage.

● Driver supply voltage: VH=90V

● Operating temperature: -40 – 85°C

APPLICATION

Vacuum Fluorescent Display GRID DRIVER

PIN CONFIGURATION (TOP VIEW)

HVO22

HVO21

HVO20

HVO19

HVO18

HVO17

HVO16

HVO15

HVO14

HVO23
HVO24
HVO25
HVO26
HVO27
HVO28
HVO29
HVO30
HVO31
HVO
PGND

3332313029282726252423
34
35
36
37
38
39
40
41
42

32

43
44

M56692FP

123456789

VH

F/R

VDD

SOUT(SIN)

CLK

LGND

LAT

BLK

SIN(SOUT)

Outline 44P6N-A

HVO13

10

H

V

HVO12

22
21
20
19
18
17
16
15
14
13
12

11

PGND

HVO11
HVO10
HVO 9
HVO 8
HVO 7
HVO 6
HVO 5
HVO 4
HVO 3
HVO 2
HVO 1

BLOCK DIAGRAM

Output
protect
circuit

VDD

3

BL

8

LAT

SIN

5

7

9

6

LGND

(SOUT)

CLK

L D

HVO32HVO31HVO30HVO 3HVO 2HVO 1

42 4341141312

1

H

V

10

11

PGND

44

Q

QTD

L D

Q

QTD

L D

Q

QTD

L D

Q

QTD

L D

Q

Q

L D

QTD

QTD

2

4

SOUT
(SIN)

F/R

3-58

MITSUBISHI <CONTROL / DRIVER IC>

PIN FUNCTION DESCRIPTION

↓

↓

M56692FP

Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER

FUNCTION

The M56692FP comprises a 32 bit bidirectional shift register, a 32
bit latch, and a parallel output HVO 1 – HVO32 connected to its
output.
In accordance with truth table 1, the data transfer direction of shift
register depends upon F/R input, and F/R being at “H” or open
allows pin 9 to turn to SIN and pin 2 to turn to SOUT, and F/R
being at “L” allows pin 2 to turn to SIN and pin 9 to turn to SOUT,
permitting data transfer from SIN to SOUT, respectively.
Inputting data to SIN and clock pulse to CLK allows SIN signal to
be put into the internal shift register when the clock changes from
“H” to “L”, and shift register data to be shifted sequentially.

TRUTH TABLE
Truth table 1. Shift register section

Input Input/output

F/R

H
H
L
L

CLK

H or L

H or L

SIN(SOUT)

IN

IN
OUT
OUT

SOUT(SIN)

OUT
OUT

IN
IN

Truth table 2. Latch and driver sections

X
H
L

X
H
H

H
L
L

Serial-output SOUT is used by connecting to the next stage
M56692FP SIN when more than one M56692FP is used to expand
bits in the series.
In accordance with truth table 2, parallel output allows the latch to
pass data through if LAT input is turned to “H”, and data to be
retained if LAT input is turned to “L”. Driver output HVOn allows
data from the latch to be output if BLK input is turned to “L”, and “L”
to be output if BLK input is turned to “H” irrespective of data from
the latch.

Shift register

DATA is shifted.

No changes.

DATA is shifted.

No changes.

HVOnDn LAT BLK

Output all “L”

H

L

Dn=nth bit DFF retention data
HVOn=nth bit driver output
L = “L” level
H = “H” level
X = “L” level or “H” level

X

Pin name
VDD
LGND
V

H

PGND
CLK
SIN

SOUT
LAT

BLK
F/R

HVO1–32

Logic stage supply voltage
Logic stage ground

Output stage supply voltage
Output stage supply ground

Clock input for the internal shift resister. The data enter the internal shift resisters and the data in the shift registers will be
shifted in order by High to Low change of the clock.

Serial data input
Serial data output
Latch input. When the LATCH is set to “H”, the data in the shift resister will enter the each latch circuit.

When the LATCH input is set to “L”, the data will be held.
Enable input for output control. When the BLK input is set to “L”, data in the latch circuit will appear at outputs.

When the BLK input is set to “H”, all outputs will be set to “L”.
Direction Control for the internal shift resister

Output driver (push-pull)

L

L

Latch’s data output.

Function

ABSOLUTE MAXIMUM RATINGS (Ta=25°C, unless otherwise noted)

Symbol

VDD

H

V
VI

O

V
V

HVO

Pd
Tstg

Logic stage supply voltage
Output stage supply voltage
Logic inputs voltage
Logic output voltage
Output voltage
Power dissipation range
Storage temperature range

Data output
High supply voltage output pin
Ta ≤ 25°C

Conditions

Ratings UnitParameter

-0.3 – 7

-0.3 – 90

-0.3 – V

DD+0.3

-0.3 – VDD+0.3

H

-0.3 – V
850

-55 – 150

V
V
V
V
V

mW

°C

MITSUBISHI <CONTROL / DRIVER IC>

M56692FP

Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER

RECOMMENDED OPERATING CONDITIONS

Symbol Ratings

V

DD
H

V
Topr

Supply voltage
Supply voltage
Operating temperature

ELECTRICAL CHARACTERISTICS (VDD=5V, VH=80V and Ta=25°C, unless otherwise noted)

Symbol Test conditions

IDD
IH Supply current 2

IIH
IIL

HVOH

V

HVOL

V
V

OH

VOL
IHVOH
IHVOL

TH

V
VTL

* Maximum numbers of Outputs High State are two at the same time.

Supply current 1

“H” input current
“L” input current

Driver output voltage

Logic output voltage
“H” output current

“L” output current
Output protect operating voltage

Parameter Conditions

Parameter

No load
Output all “L”, no load

1 bit “H”, no load
VIH=5V input pin

V

IL = 0V

I

HVOH = -50mA

I

HVOL = 10mA

I

OH = -0.1mA

I

OL = 0.1mA

SIN, LAT, CLK
BLK, F/R

Duty cycle ≤ 2.5%*

4 – 6

40 – 90

-40 – 85

Limits

Min.

70

4.5

Typ.

0.4

0.4

Max.

2

0

1

1
01
0

-1

-250

-500

75.5

0.5

2.5

4.9

0.1

-50
10

0.4

-100
20

3.3

3.0

Unit

V

V

°C

Unit

mA
mA

mA

µA
µA
µA

V

V

mA

mA

V
V

SWITCHING CHARACTERISTICS (VDD=5V, VH=80V and Ta=25°C, unless otherwise noted)

Symbol Test conditions

fCLK
t PLH(SO)
t PHL(SO)
tPLH(OUT)
tPHL(OUT)
trout
tfout

Clock frequency
Logic output propagation time

Driver output propagation time

Driver output rise and fall time

Parameter

Min. Typ. Max.

Duty = 45 – 55%
CL = 15pF

RO = 220KΩ
CO = 50pF

TEST CIRCUIT

VHVDDINPUT

(1) Characteristics of pulse generator (PG)

tr≤20ns tf≤20ns

(2) Capacitance CL includes connection

floating capacitance and probe input
capacitance.
: RO=220KΩ
: CO=50pF

PG

50Ω

DUT

SOUT

CL

HVOn

Limits

8

180

90

180

60
95 ns
70
35
65

Unit

MHz

ns
ns

ns
ns
ns

CO

RO

TIMING WAVEFORM

MITSUBISHI <CONTROL / DRIVER IC>

M56692FP

Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER

1/fmax

CLK

SIN

SOUT

BLK

HVOn

50%

90%

50%

tPHL(SO)

tfso

10%

50%

50%

10%

tPLH(OUT)

tr

OUT

50%

50%

tsu

90%

50%

th

10%

tPLH(SO)

trso

50%

50%

tPHL(OUT)

90%

50%

90%

50%

tfOUT

10%

TYPICAL CHARACTERISTICS

MITSUBISHI <CONTROL / DRIVER IC>

M56692FP

Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER

Thermal derating

1.0

0.8

0.6

0.4

0.2

Power dissipation Pd(W)

0.0
0 25 50 75 100 125 150

Temperature Ta (°C)

Duty cycle vs Permissible
output current

100

90
80
70
60
50
40
30
20

Output current IOH(mA)

10

0

0 20 40 60 80 100

Duty cycle (%)

Driver output VON–IOH

-100
Ta=-40°C

-80

-60

-40

-20

“H” output current IOH(mA)

0

0246810

“H” output ON voltage V

Ta=25°C

Ta=85°C

12

ON (V)

Duty cycle vs Permissible
output current

1

2

4

8

16
24
32

100

90
80
70
60
50
40
30

Output current IOH(mA)

20
10

0

32

0 20406080100

Duty cycle (%)

1

2

4

8

16

24

• Ta=25°C

Note

• Repeated frequency>100Hz

• Figure in the circle represents the number of
concurrently operating output circuits.

• Current value denotes a numerical value per circuit.

(Note)

1. VDD=5V and VH=80V unless otherwise noted.

2. Thermal derating curve represents that of an individual IC unit.

3. Allowable duty cycle output curve represents that when a standard
substrate is mounted. (Standard substrate: 70x70x1.6mm glass epoxy)

• Ta=85°C

Note

• Repeated frequency>100Hz

• Figure in the circle represents the number of
concurrently operating circuits.

• Current value denotes a numerical value per circuit.