The M5482 is a monolithic MOS integrated circuit
produced with an N-channel silicon gate technology. It utilizes the M5451 die pack aged in a 20-pin
plastic package copper frame, making it ideal for a
2-digit display . A single pin controls the LED display
brightness by setting a reference current thro ugh a
variable resistor connected either to V
separate supply of 13.2V maximum.
PIN CONN E CTI O NS
OUTPUT BIT 8
OUTPUT BIT 7
OUTPUT BIT 6
OUTPUT BIT 5
OUTPUT BIT 4
OUTPUT BIT 3
OUTPUT BIT 2
OUTPUT BIT 1
BRIGHTNESS CONTROL
or to a
DD
V
DD
ORDER CODE : M5482B7
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OUTPUT BIT 9
OUTPUT BIT 10
OUTPUT BIT 11
OUTPUT BIT 12
OUTPUT BIT 13
V
SS
OUTPUT BIT 14
OUTPUT BIT 15
DATA IN
CLOCK
May 1993
5482-01.EPS
1/6
Page 2
M5482
BLOCK DIAGRAM
BRITGHTN ESS
CONT ROL
V
DD
OUTPUT
BIT 15
108
13
OUTPUT
BIT 1
35 OUTPUT BUFERS
35 LATCHES
35 BIT SHIFT REGISTER
LOAD
RESET
1nF
SERIAL
DATA
CLOCK
9
12
11
1
ABSOL UTE MAX IM UM R ATINGS
SymbolParameterValueUnit
V
DD
V
V
O (off)
I
O
P
tot
T
T
oper
T
stg
Stresses in excess of those listed under "Absolute Maximum Rat ings" may cause permanent damage to the device. This is a stress rat ing only
and functional operation of the device at these or any other conditions in excess of those indicate d in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage– 0.3 to 15V
Input Voltage– 0.3 to 15V
I
Off State Output Voltage15V
Output Sink Current40mA
Total Package Power Dissipation at 25 °C
at 85 °C
Junction Temperature150°C
j
1.5
800
Operating Temperature Range– 25, + 85°C
Storage Temperature Range– 65, + 150°C
W
mW
5482-02.EPS
5482-01.TBL
2/6
Page 3
M5482
STATIC ELECTRICAL CHARACTERISTICS
(T
within operating range, VDD = 4.75V to 13.2V, VSS = 0V,unless otherwise specified)
amb
SymbolParameterTest ConditionsMin.Typ.Max.Unit
V
I
V
V
O(off)
f
clock
Notes : 1. Output matching is calculated as the percent variation from I
Supply Voltage4.7513.2V
DD
Supply CurrentVDD = 13.2 V7mA
DD
Input Voltages
V
I
Logical "0" Level
Logical "1" Level
I
Brightness Input Current (note 2)00.75mA
B
Brightness Input Voltage (pin 9)Input Current = 750 µA
B
± 10 µA Input Bias
4.75 ≤ V
VDD > 5.25
T
amb
DD
= 25oC
≤ 5.25
– 0.3
2.2
VDD – 2
34.3V
Off State Output Voltage13.2V
I
Output Sink Current (note 3)
O
Segment OFF
Segment ON
VO = 3 V
= 1 V (note 4)
V
O
Brightness In. = 0 µA
Brightness In. = 100 µA
Brightness In. = 750 µA
12
0
2
2.7
15
Input Clock Frequency00.5MHz
I
Output Matching (note 1)± 20%
O
+ I
/2.
MAX
2. With a fixed resistor on the brightness input some variation in brightness will occur from one device to another.
3. Absolute maximum for each output should be limited to 40 mA.
4. The V
voltage should be regulated by the user.
O
MIN
0.8
V
V
DD
DD
10
10
4
25
V
V
V
µA
µA
mA
mA
5482-02.TBL
FUNCTIONAL DESCRIPTION
The M5482 uses the M5451 die which is packaged
to operate 2-digit alphanumeric displays with m in imal interface w ith the dis p lay and the dat a s ourc e.
Serial data transfer from the data source to the
display driver is accomplished with 2 s ignals, serial
data and clock. Using a format of a leading "1"
followed by the 35 data bits allows data transfer
without an additional load signal.
The 35 data bits are latched after the 36th bit is
complete, thus providing non-multiplexed, direct
drive to the display. Outputs change only if the
serial data bits differ from the previous time. Display
brightness is determined by control of the output
Figure 2 : Input Dat a Form at
1
CLOCK
DATA
LOAD
(INTERNAL)
START
BIT 1
current for LE D displays. A 1nF capacitor should be
connected to brightness control, Pin 9, to prevent
possible oscillations.
A block diagram is shown in Figure 1. The output
current is typically 20 tim es greater than the current
into Pin 9, which is set by an external variable
resistor.
There is an internal limiting resistor of 400Ω nominal value.
Figure 2 shows the input data format. A start bit of
logical "1" precedes the 35 bits of data. At the 36th
clock a LOAD signal is generated synchronously
with the high state of the cloc k, which loads the 3 5
bits of the shift registers into the latches.
36
BIT 34 BIT 35
RESET
(INTERNAL)
5482-03.EPS
3/6
Page 4
M5482
At the low state of the clock a RESET signal is
generated which clears all the shift regist ers for the
next set of data. The shift regist ers are static master
slave configurations. There is no clear for the master portion of the first shift register, thus allowing
continuous operation.
There must be a complete set of 36 clocks or the
shift registers will not clear.
When power is first applied to the chip an internal
power ON reset signal is generated which resets
all registers and all latches . The ST AR T bit and the
first clock return the chip to its normal operation.
Figure 3 shows the timing relationships between
per output or operate the part at higher than 1V
V
.
OUT
The following equation can be used for calculations.
T
≡ [(V
j
(80 °C/W) + T
OUT
)(I
)(no.of segments) + VDD . 7 mA]
LED
amb
where :
T
= junction temperature (150 °C max)
j
V
= the voltage at the LED driver outputs
OUT
I
= the LED current
LED
80 °C/W = thermal coefficient of the package
T
= ambient temperature
amb
Figure 3
Data and Clock.
A maximum clock frequency of 0.5 MHz is as-
sumed.
CLOCK
Figure 4 shows the Output Data Format for the
M5482. Because it uses only 15 of the possible 35
outputs, 20 of the bits are "Don’t Cares".
For applications where a lesser number of output s
are used it is possible to either increase the current
DATA
300ns (min.)
Figure 4 : Serial Data Bus / Outputs Correspondance
The power dissipation of the IC can be limited using
different configurations.
a)
V
V
OUT
+V
C
R
I
D
D
In this application R must be chosen taking into
account the worst operating conditions.
R is determined by the maximum number of segments activated.
R =
VC − V
DMAX
N
MAX
−V
⋅ I
O MIN
D
The worst case condition for the device is when
roughly half of the maximum number of segments
are activated.
It must be checked that the total power diss ipation
does not exceed the absolute maximum ratings of
the device.
In critical cases more resistors can be used in
conjunction with groups of segments. In this case
the current variation in the single resistor is reduced
and P
limited.
tot
+V
b)
C
In this configuration the drop on the serial connected diodes is quite stable if the diodes are
properly chosen.
The total power dissipation of the IC is, in first
approximation, depending only on the number of
5482-06.EPS
segments activated.
+V
c)
In this configuration V
C
V
OUT+VD
+ VD is constant. The total
OUT
power dissipation of the IC depends only on the
number of segments activated.
5482-07.EPS
5482-08.EPS
5/6
Page 6
M5482
PACKA G E MECHANICAL DATA
20 PINS - PLASTIC DIP
I
a1
L
Z
e3
b
B
e
E
Z
D
2011
F
110
Dimensions
Min.Typ.Max.Min.Typ.Max.
a10.2540.010
B1.391.650.0550.065
b0.450.018
b10.250.010
D25.41.000
E8.50.335
e2.540.100
e322.860.900
F7.10.280
i3.930.155
L3.30.130
Z1.340.053
MillimetersInches
b1
PM-DIP20.EPS
DIP20.TBL
Information furnished i s believed to be accurate and rel iabl e. However, S GS-THOMSON Microel ectroni cs assumes no responsibil ity
for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result
from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics.
Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all
information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life
support devices or systems without express written approval of SGS-THOMSON Microelectronics.