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M52790FP
Datasheet (Mitsubishi)
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Datasheet M52790SP, M52790FP Datasheet (Mitsubishi)

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Page 1
M I T S U B I S H I
- 9
MITSUBISHI ICs (AV COMMON)
M52790SP/FP
PRELIMINARY
Some parametric limits are subject to change.
DESCRIPTION
FEATURES
APPLICATION
Video equipment
RECOMMENDED OPERATING CONDITION
1234567151413121110
9
1
TUNER IN
Rch T IN
SDA
Lch 1 OUT
C IN
8
16
VIDEO 2 IN
CHIP SELECT
Lch 2 IN
Y 3 IN
C 3 IN
Lch 3 IN
Rch 4 IN
VIDEO 4 IN
GND
PIN CONFIGURATION ( TOP VIEW )
(Lead pitch :0.8mm)
17183635343332313022232425262728292120
19
C 1 OUT
V 2 OUT
C 2 OUT
Y 2 OUT
1234567151413121110
9
TUNER IN
Rch T IN
SDA
Lch 1 OUT
C IN
8
16
VIDEO 2 IN
CHIP SELECT
Lch 2 IN
Y 3 IN
C 3 IN
Lch 3 IN
Rch 4 IN
VIDEO 4 IN
GND
17183635343332313022232425262728292120
19
C 1 OUT
V 2 OUT
C 2 OUT
Y 2 OUT
of
output 0dB or 6dB .
Notice. This is not a final specification.
The M52790 is AV switch semiconductor integrated circuit with I2C bus control . This IC contains 2-channels of 4-input audio switches and 2­channels of 4-input video switches. Each channel can be controled independently . The video switches contain amplifiers can be controled a gain
•Video and stereo sound switches in one package
•Wide frequency range ( video switch )...........DC~20MHz
•High separation ( video switch )
.................Crosstalk -60dB ( typ. ) at 1MHz
•Two types of packages are provided : SDIP with a lead pitch of
1.778mm ( M52790SP ) ; and SSOP with a lead pitch of 0.8mm
( M52790FP ) .
PIN CONFIGURATION ( TOP VIEW )
VCC
Lch T IN
C 2 IN
Rch 2 IN
Y 2 IN
VIDEO 3 IN
Rch 3 IN
Lch 4 IN
C 4 IN
Y 4 IN
SCL
Outline 36P4E
(Lead pitch :1.778mm)
Y IN V 1 OUT
Rch 1 OUT Y 1 OUT
Lch 2 OUT
Rch 2 OUT
BIAS
Supply voltage 4.7V ~ 9.3V Rated supply voltage 5V,9V
Maximum output current 63mA(at 9V)
VCC
C 2 IN
Rch 2 IN
Y 2 IN
VIDEO 3 IN
Rch 3 IN
Lch 4 IN
C 4 IN
Y 4 IN
SCL
Outline 36P2R-D
Lch T IN
Y IN V 1 OUT
Rch 1 OUT Y 1 OUT
Lch 2 OUT
Rch 2 OUT
BIAS
AUG.'98
Page 2
M I T S U B I S H I
- 9
MITSUBISHI ICs (AV COMMON)
M52790SP/FP
PRELIMINARY
Some parametric limits are subject to change.
BLOCK DIAGRAM
VIDEO 2 IN
Y 1 OUT
Y 2 IN
Y 3 IN
Y 4 IN
C 2 IN
C 3 IN
C 4 IN
TUNER IN
VIDEO 3 IN
VIDEO 4 IN
Y 2 OUT
C 1 OUT
C 2 OUT
V 1 OUT
V 2 OUT
SDA
SCL
GND
CHIP SELECT
VCC
C IN
Y IN
Rch 1 OUT
Lch 1 OUT
Rch 2 OUT
Lch 2 OUT
Rch T IN
Lch 3 IN
Rch 2 IN
Rch 3 IN
Rch 4 IN
Lch 4 IN
Lch 2 IN
Lch T IN
BIAS
2
I C Control
NNS
0/6dB
0dB
0/6dB
0/6dB
0/6dB
0/6dB
0/6dB
0dB
0dB
0dBLRMLRMLRMLRM
23456789101112131415161718192021222324252627282930313233343536
V-SW1
V-SW2
Y-SW1
Y-SW2
C-SW1
C-SW2
R-SW1
R-SW2
L-SW1
L-SW2
R-MODE1
R-MODE2
L-MODE1
L-MODE2
Sepa.
Notice. This is not a final specification.
1
Y/C
S
BIAS
2
2
AUG.'98
Page 3
M I T S U B I S H I
- 9
MITSUBISHI ICs (AV COMMON)
M52790SP/FP
PRELIMINARY
Some parametric limits are subject to change.
3
Vcc2VIDEO 2 IN
34Lch 2 IN
C 2 IN
5
Rch 2 IN
3.6V
4.7V
4.7V7VIDEO 3 IN
12
VIDEO 4 IN
36
TUNER IN
8
Lch 3 IN
6
Y 2 IN
11
Y 3 IN
16
Y 4 IN
32
Y IN13Lch 4 IN
10
Rch 3 IN
9
C 3 IN
1415Rch 4 IN
C 4 IN
17
SCL
Rch T IN
34
C IN35Lch T IN
18
SDA
30K
20K
Name
Peripheral circuit pins
Remarks
Notice. This is not a final specification.
DESCRIPTION OF PIN
Pin No.
1
33
DC voltage(V)
9V
5~9V
Clamp in
VIL max.=1.5V VIH min.=3.0V
VIL max.=1.5V VIH min.=3.0V VOL max.=0.4V
(at Iin=3mA)
AUG.'98
Page 4
M I T S U B I S H I
- 9
MITSUBISHI ICs (AV COMMON)
M52790SP/FP
PRELIMINARY
Some parametric limits are subject to change.
Pin No.
Name
Peripheral circuit pins
GND
20
SELECT
21
BIAS
22
Y 2 OUT
26
V 2 OUT
27
Y 1 OUT
31
V 1 OUT
23
Rch 2 OUT
25
Lch 2 OUT
28
Rch 1 OUT
30
Lch 1 OUT
4.2V
DC=2.9V
C 2 OUT
29
C 1 OUT
4.0V
70K
30K
30K
1.5K
1.5K
15K5K5K5K5K
Remarks
4
Notice. This is not a final specification.
DESCRIPTION OF PIN (cont.)
19
DC voltage(V)
CHIP
SLAVE
ADDRESS
0~1.5V-------90H
2.5~Vcc------92H OPEN--------90H
SYNC CHIP
24
4.0V
AUG.'98
Page 5
M I T S U B I S H I
- 9
MITSUBISHI ICs (AV COMMON)
M52790SP/FP
PRELIMINARY
Some parametric limits are subject to change.
5
A ; Acknownledge
DATA1 ,SW2 is controled by DATA2 .
the
wired-AND function .
2
23456789129
A
SDA
MSB
LSB
S
A
DATA2
A
P : Stop
SLAVE ADDRESS
100100X
receiver )
2
Notice. This is not a final specification.
I C BUS
I C BUS(Inter IC BUS)is multi master bus system developed by PHILIPS . Two wires ( SDA - serial data, SCL - serial clock ) realize functions of start , stop , transferring data , synchronization and arbitration. The output stages of device connected to the bus must have an open drain or open collector in order to perform
A
LSB
SCL
S
1
S ; Start condition, a high to low transition of the SDA line while SCL is high P ; Stop condition, a low to high transition of the SDA line while SCL is high
Every byte put on the SDA line must be 8-bits long . Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB ) first . The data on the SDA line must be stable during the HIGH period of the clock . The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW .
MSB
P
CONTROL
This IC controls 2-channel switchs with 2-byte data ( DATA1 and DATA2 ) . SW1 is controled by
SLAVE ADDRESS
S : Start A : Acknowledge
DATA1
0
P
A
R/W bit Usually ` 0 ` ( W : Master transmitter transmits to slave
Possible to select 20PIN Hi:1,Lo:0
AUG.'98
Page 6
M I T S U B I S H I
- 9
MITSUBISHI ICs (AV COMMON)
M52790SP/FP
PRELIMINARY
Some parametric limits are subject to change.
6
Data byte format
M52790 FUNCTION TABLE
S
SLAVE ADDRESS
A
DATA(D7~D0)
A
DATA(DF~D8)
APSLAVE ADDRESS
SLAVE ADDRESS
A6A5A4A3A2A1A0
R/W100100
0 / 10DATA1(D7~D0) CONT
DATA
D7D6D5D4D3D2D1D0CONT
AUDIO MODE1
Y/C AMP1
V AMP1
S/N
SW1 CONT
VIDEO SW1 CONT
AMP1 GAIN CONT.
DATA
OUT
DATA
AMP
DATA
AMP
S/N(S:1)
V-SW1
V OUT1
Y OUT1
C OUT1
D4
YC AMP1
D3
V AMP1
D2D1D000dB00dB000T IN
Y IN
C IN16dB16dB001V 2 IN
Y IN
C IN010V 3 IN
Y IN
C IN
AUDIO MODE1 CONT
011
V 4 IN
Y IN
C IN
DATA
MODE
100
Y/C MIX T
Y IN
C IND7D6101Y/C MIX 2
Y 2 IN
C 2 IN
00MUTE
110
Y/C MIX 3
Y 3 IN
C 3 IN
01R/R111Y/C MIX 4
Y 4 IN
C 4 IN
10L/L11
NORMAL
AUDIO SW1 CONT
MODE
MUTE
R/R
L/L
NORMAL
DATA
OUT
OUT
OUT
OUTD1D0
Lch OUT 1
Rch OUT 1
Lch OUT 1
Rch OUT 1
Lch OUT 1
Rch OUT 1
Lch OUT 1
Rch OUT 1
00MUTE
MUTE
Rch T IN
Rch T IN
Lch T IN
Lch T IN
Lch T IN
Rch T IN
01MUTE
MUTE
Rch 2 IN
Rch 2 IN
Lch 2 IN
Lch 2 IN
Lch 2 IN
Rch 2 IN
10MUTE
MUTE
Rch 3 IN
Rch 3 IN
Lch 3 IN
Lch 3 IN
Lch 3 IN
Rch 3 IN
11MUTE
MUTE
Rch 4 IN
Rch 4 IN
Lch 4 IN
Lch 4 IN
Lch 4 IN
Rch 4 IN
DATA2(DF~D8) CONT
DATA
DFDEDDDCDBDAD9D8CONT
AUDIO MODE2
Y/C AMP2
V AMP2
SW2 CONT
VIDEO SW2 CONT
AMP2 GAIN CONT.
DATA
OUT
DATA
AMP
DATA
AMP
S/N(S:1)
V-SW2
V OUT2
Y OUT2
C OUT2
DC
YC AMP2
DB
V AMP2
DAD9D800dB00dB000T IN
Y IN
C IN16dB16dB001V 2 IN
Y 2 IN
C 2 IN
010
V 3 IN
Y 3 IN
C 3 IN
AUDIO MODE2 CONT
011
V 4 IN
Y 4 IN
C 4 IN
DATA
MODE
100
Y/C MIX T
Y IN
C INDFDE101Y/C MIX 2
Y 2 IN
C 2 IN
00MUTE
110
Y/C MIX 3
Y 3 IN
C 3 IN
01R/R111Y/C MIX 4
Y 4 IN
C 4 IN
10L/L11
NORMAL
AUDIO SW2 CONT
MODE
MUTE
R/R
L/L
NORMAL
DATA
OUT
OUT
OUT
OUTD9D8
Lch OUT 2
Rch OUT 2
Lch OUT 2
Rch OUT 2
Lch OUT 2
Rch OUT 2
Lch OUT 2
Rch OUT 2
00MUTE
MUTE
Rch T IN
Rch T IN
Lch T IN
Lch T IN
Lch T IN
Rch T IN
01MUTE
MUTE
Rch 2 IN
Rch 2 IN
Lch 2 IN
Lch 2 IN
Lch 2 IN
Rch 2 IN
10MUTE
MUTE
Rch 3 IN
Rch 3 IN
Lch 3 IN
Lch 3 IN
Lch 3 IN
Rch 3 IN
11MUTE
MUTE
Rch 4 IN
Rch 4 IN
Lch 4 IN
Lch 4 IN
Lch 4 IN
Rch 4 IN
S/N
Notice. This is not a final specification.
AUG.'98
Page 7
M I T S U B I S H I
- 9
MITSUBISHI ICs (AV COMMON)
M52790SP/FP
PRELIMINARY
Some parametric limits are subject to change.
7
Parameter
Test condition
Max.
Unit
Supply voltage
V
VIDEO
IccmAVcc=9V,Vin=0Vp-p,Rl=∞Ω
4.7
63835471(Ta=25°C,Vcc=9V,unless otherwise noted)
---
ELECTRICAL CHARACTERISTICS
Voltage gain
Dynamic Range
Crosstalk
Frequency characteristics
Total harmonic distortion
Dynamic Range
Input impedance
F
D
CTGF
D
CT
dBdBVp-p
dBdBdB%dBkΩmV
<1.0%
-0.500.5
6
2.0
42142026
-54
0
-0.500.5
010.01
5.5
020223038--------0.500.5
6
42-----------90--84
6.002.0
2.0
2.0
Notice. This is not a final specification.
Circuit current
Frequency
characteristics
Symbol
Vcc
G
Vcc=5V,Vin=0Vp-p,Rl=∞Ω
f=100kHz,1Vp-p (0dB)(T V1OUT) f=100kHz,1Vp-p (6dB)(T V1OUT)
f=100kHz,1Vp-p (0dB)(Y V1OUT) f=100kHz,1Vp-p (6dB)(Y V1OUT)
f=10MHz/100kHz,1Vp-p (0dB)(T V1OUT) f=10MHz/100kHz,1Vp-p (6dB)(T V1OUT) f=10MHz/100kHz,1Vp-p (0dB)(Y V1OUT)
f=10MHz/100kHz,1Vp-p (6dB)(Y V1OUT) Vcc=9V(0dB)(T V1OUT)
Vcc=5V(0dB)(T V1OUT) Vcc=9V(0dB)(Y V1OUT)
f=100kHz Maximum
with distortion
Min.
5.5
5.5
-2.0 0
-2.0
-2.0 0
-2.0 0
Typ.
9.3
6.5
6.5
Input impedance
AUDIO
Voltage gain
Output DC offset voltage
Crosstalk
ZIC
ZIV ZIY
THD
VOFF
Z1
Vcc=5V(0dB)(Y V1OUT)
(C,C2,C3,C4) Clamp in(T,V2,V3,V4)
Clamp in(Y,Y2,Y3,Y4)
f=1MHz,1Vp-p T V1OUT (at V2 mode)
f=1kHz ,1Vp-p (Vcc9V)(RT R1OUT) f=1kHz ,1Vp-p (Vcc5V)(RT R1OUT)
f=100kHz/1kHz , 1Vp-p(RT R1OUT) f=1kHz,2Vp-p,at 400HzHPF+30kHzLPF
(RT R1OUT) f=1kHz ,Maximum with distortion<0.5%
(RT R1OUT)
(MODE:RT,R2,R3,R4 R1OUT ) (RT,R2,R3,R4,LT,L2,L3,L4 )
1kHz,1Vp-p RT R1OUT(at R2 mode)
-0.5
-2.0
-20
kΩ
-60
0.5
0.05
Vp-p
AUG.'98
Page 8
M I T S U B I S H I
- 9
MITSUBISHI ICs (AV COMMON)
M52790SP/FP
PRELIMINARY
Some parametric limits are subject to change.
tBUF
P
tHD;STA
tLOWtRtHD;DAT
tHIGHtFtSU;DAT
tSU;STA
Sr
tHD;STA
tSU;STO
P
SDA
I C BUS CONTROL SIGNAL
2
I2C BUS CONTROL SIGNAL
(Ta=25°C,Vcc=9V,unless otherwise noted)
ELECTRICAL CHARACTERISTICS
Max. input high voltage
4.0
4.0
5.0
4.0--
1000
kHz
-------
Low level input current
Time of bus must be free before
Hold time at start condition
The high period of the clock
Hold time DATA
Rise time of both SDA and SCL line
Setup time for stop condition
V
SDA , SCL = 4.5 V
3.0
0.0
-10
1.5
1010----------------0.0
Symbol
Min.
Typ.
a new transmission can start
Notice. This is not a final specification.
Parameter
Min. input low voltage Low level output voltage(SDA)
High level input current
SCL clock frequency
The low period of the clock
Setup time for start condition
Setup time DATA
VIH VIL VOL
IIH IIL
fSCL
tBUF
tHD;STA
tLOW
tHIGH tSU;STA tHD;DAT
tSU;DAT
tR
Test condition
SDA = 3mA
SDA , SCL = 0.4 V
0.0
-10
4.7
4.7
4.7
250
Max.
5.0
0.4
100
Unit
µA
µS
nS
Fall time of both SDA and SCL line
SCL
S
tF
tSU;STO
300
-
µS
8
AUG.'98
Page 9
M I T S U B I S H I
- 9
MITSUBISHI ICs (AV COMMON)
M52790SP/FP
PRELIMINARY
Some parametric limits are subject to change.
Application Circuit Example
3534333231302223242526272829212019234567151413121110981617181
TUNER IN
SCL
Rch T IN
Lch T IN
SDA
Y 2 IN
Lch 1 OUT
Rch 1 OUT
C IN
Y IN
VIDEO 2 IN
C 2 IN
CHIP SELECT
Rch 2 IN
Lch 2 IN
VCC
Y 3 IN
VIDEO 3 IN
C 3 IN
Rch 3 IN
Lch 3 IN
Lch 4 IN
Rch 4 IN
C 4 IN
VIDEO 4 IN
Y 4 IN
GND
V 1 OUT
C 1 OUT
Y 1 OUT
V 2 OUT
Lch 2 OUT
C 2 OUT
Rch 2 OUT
Y 2 OUT
BIAS
100µ
10µ750.47µ750.01µ750.47µ
10µ750.47µ
10µ750.01µ750.47µ
10µ750.47µ
10µ750.01µ750.47µ
10µ
10K
220
10K
220
10µ
10µ
0.47µ
0.01µ
10µ
0.47µ
75
5V
Sepa.
0.01µ75757575757575757575
Notice. This is not a final specification.
VCC
36
Y/C
5V
Note how to use this IC
Input signal with sufficient low impedance to input terminal. The capacitance of output terminal as small as possible. Set the capacitance between Vcc and GND near the pins if possible. Assign an area as large as possible for grounding.
Power-on Reset
The M52790 has an intermal power-on reset function that sets each control register to "0" during IC power ON. The power-on reset VTH has 2.5V.
slave address Change(VCC/GND)
9
AUG.'98
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