intercareer system.
AFT coil is necessary.
AFT mute is not used.
The M52766FP optimum for VTR and color TV,with video
output-pin,because this IC has a built in EQ amplifier.
VCC correspond to 5V,be main strem of tuner in future.
Flat package is 24-pin SSOP of mini flat (0.8mm pich ),
suitable for space saving.
The M52766FP is a semiconducttor IC with PLL system of
VIF/ SIF.
The circuit includes video UF amplifier,PLL video
detector,IFAGC,RFAGC,VCO,AFT,LOCK
DET,EQ,REG,QIFamplifier,QIF detector,QIF AGC,LIM,FM
detector function.
The circuit realize no abjustment SIF,nothing coil AFT.
FEATURES
Dynamic AGC realizes high speed AGC with double filtre.
The M52766FP can correspond to 2tipe sound career,from
change on standard board,with sound LIM input have
2pins (12,13pin).
Sound FM detection can correspond to wide SIF
MITSUBISHI ICs(TV)
M52766FP
PLL SPLIT VIF / SIF
PIN CONFIGURATION (TOP VIEW)
EQ OUT
VIDEOINV.OUT
APC FILTER
EQ IN
VCO COIL
VCO COIL
IF AGC FILTER
VIDEO OUT
QIF OUT
LIMITER IN (NTSC)
APPLICATION
VCC
GND
10
11
12
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
15
14
13
EQF/B
IF AGC FILTER
RF AGC DELAY
VIF IN
VIF IN
GND
AFT OUT
RF AGC OUT
QIF DET IN
NFB
AUDIO OUT
LIMITER IN(PAL)
BLOCK DIAGRAM
IF AGC
EQ
AMP
RF AGC
Delay
Vcc
AFT
IF IN
VIF AMP
APC
AFT
OUT
VIDEO
DET
Vcc
VCO
TV sets, VTR tuners.
RECOMMEND OPERATING CONDITION
Supply voltage range • • • • 5.0 ± 0.25V
Recommended supply voltage • • • 5.0V
RF AGC
OUT
RF AGC
AF OUT
131415161718192021222324
AF AMP
FM DET
QIF AMP
LIM AMP
QIF DET
EQ OUT
1
2
3
456789101112
+
4.5MHz Trap
Vcc
VIDEO OUT
4.5MHz Filter
( / 15 )
1
Page 2
MITSUBISHI ICs(TV)
*
PLL SPLIT VIF / SIF
Absolute maximum ratings( Ta = 25°C, unless otherwise noted )
M52766FP
Parameter
Symbol
RatingsUnit
Supply
Voltage 1
Power
Vcc
Pd
6.0
1524mW
Consumption
Operating
Temperature
Storage
Temperature
Surge voltage
Topr
Tstg
Surge
-20 to +75
-40 to +150
±200
resistance
There is not all pins problem about surge, but the case of use
pay attention about latch up because the ninth pin is weak a few.
Temperature Characteristics( maximum ratings )
Mounting in standard circuit board
1750
V
°C
°C
V
Note
surge protection
capacitance 200pF
resistance 0Ω
1500
1250
1190
1000
750
500
250
0
-20
0255075100125
Ambient temperature Ta (°C )
Recommended Operating Condition
( Ta = 25°C, unless otherwise noted )
Supply Voltage Range (Vcc) • • • • • 4.75 to 5.25 V
Input SG2 into VIF IN and measure the video out(Pin 1) noise in r.m.s at TP1B
through a 5MHz (-3dB) L.P.F.
M52766FP
S/N=20 log
2. Video Band Width: BW
1. Measure the 1MHz component level of Video output TP1A with a spectrum
analyzer when SG3(f2=57.75MHz) is input into VIF IN. At that time, measure
the voltage at TP23 with SW23, set to position 2, and then fix V23 at that
voltage.
2. Reduce f2 and measure the value of (f2-f0) when the (f2-f0) component level
reaches -3dB from the 1MHz component level as shown below.
TP1A
-3dB
0.7 x Vo det
NOISE
[dB]
( f2 - f0 )
1 MHzBW
3. Input Sensitivity: VIN MIN
Input SG4 (Vi=90dBµ) into VIF IN , and then gradually reduce Vi and
measure the input level when the 20KHz component of Video output TP1A
reaches -3dB from Vo det level.
4. Maximum Allowable Input: VIN MAX
1. Input SG5 (Vi=90dBµ) into VIF IN , and measure the level of the 20KHz
component of Video output.
2. Gradually increase the Vi of SG and measure the input level when the
output reaches -3dB.
( / 15 )
9
Page 10
5. AGC Control Range: GR
GR = VIN MAX - VIN MIN [dB]
6. RF AGC Operating Voltage: V17
Input SG8 into VIF IN and gradually reduce Vi and then measure the input
level when RF AGC output TP17 reaches 1/2 VCC, as shown below.
TP17
Voltage
V17H
MITSUBISHI ICs(TV)
M52766FP
PLL SPLIT VIF / SIF
1/2VCC
V17L
Vi
Vi(dBµ)
7. Capture range: CL - U
1. Increase the frequency of SG9 until the VCO is out of locked-oscillation.
2. Decrease the frequency of SG9 and measure the frequency fU when the
VCO locks.
CL - U = fU - 58.75 [MHz]
8. Capture range: CL - L
1. Decrease the frequency of SG9 until the VCO is out of locked-oscillation.
2. Increase the frequency of SG9 and measure the frequency fL when the
VCO locks.
CL - L = 58.75 - fL [MHz]
9. Capture range: CL - T
CL - T = CL - U + CL - L [MHz]
( / 15 )
10
Page 11
MITSUBISHI ICs(TV)
M52766FP
PLL SPLIT VIF / SIF
10. AFT sensitivity µ, Maximum AFT voltage V18H , Minimum AFT voltage V18L
1. Input SG10 into VIF IN , and set the frequency of SG10 so that the voltage
of AFT output TP18 is 3[V] . This frequency is named f(3).
2. Set the frequency of SG10 so that the AFT output voltage is 2[V].
This frequency is named f(2)
3. IN the graph, maximum and minimum DC voltage are V18H and V18L,
respectively.
TP2
Voltage
3V
µ =
1000 [mV]
f(2) - f(3) [kHz]
[mV/kHz]
2V
V18H
f(3)f(2)
11. Inter modulation: IM
1. Input SG11 into VIF IN, and measure video output TP9 with an oscilloscope.
2. Adjust AGC filter voltage V23 so that the minimum DC level of the output
waveform is 1.0V.
3. At this time, measure TP9 with a spectrum analyzer .
The inter modulation is defined as a difference between 0.92MHz and
3.58 MHz frequency components.
V18L
f(MHz)
( / 15 )
11
Page 12
MITSUBISHI ICs(TV)
PLL SPLIT VIF / SIF
12. Limiting Sensitivity: LIM
1. Input SG17 (SG22) into SIF input, and measure the 400Hz component level
of AF output TP14.
2. Input SG20 (SG25) into SIF input, and measure the 400Hz component level
of AF output TP14 .
3. The input limiting sensitivity is defined as the input level when a difference
between each 400Hz components of audio output (TP14) is 30dB, as shown
below.
Audio Output
M52766FP
(mVrms)
30dB
Audio output while SG17 (SG22) is input.
Audio output while SG20 (SG25) is input.
(dBµ)
SIF Input
13. AM Rejection: AMR
1. Input SG18 (SG23) into SIF IN ,and measure the output level of Audio output
(TP12). This level is named VAM.
2. AMR is;
AMR = 20log
VoAF (mVr.m.s)
VAM (mVr.m.s)
[dB]
14. AF S/N: AF S/N
1. Input SG19 (SG24) into SIF input ,and measure the output noise level of Audio
output (TP14). This level is named VN.
2. S/N is;
VoAF (mVr.m.s)
S/N = 20log
VN (mVr.m.s)
[dB]
15. QIF Control : CQIF
Lower the voltage of V16 ,and measure the voltage of V16 when DC voltage of
TP10 begins to change.
( / 15 )
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3 4
8
Structure of package (Cross section)
MITSUBISHI ICs(TV)
M52766FP
PLL SPLIT VIF / SIF
Structure
Matrrial
Inner Lead Plating
Die Bond
Lead Flame
Lead Flame
Mold resin : Epoxy resin
Internal lead : Au wire ( 25µm)
External lead plating : Solder plating
Lead frame : Copper alloy
Passivation : Nitride coat
Outer Passivation
Pellet
Plastic Molding
Wire
Back Metalize
Lead Flame
Manufacturing place (Wafer process,assembly,final inspection)
Mitsubishi Electric Corporation Fukuoka Semiconductor Factory