Datasheet M48Z58Y-70PC1, M48Z58Y, M48Z58-70PC1, M48Z58 Datasheet (SGS Thomson Microelectronics)
Page 1
64 Kbit (8Kb x 8) ZEROPOWER® SRAM
INTEGRATED ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY
READ CYCLE TIME EQUALS WRITE CYCLE
TIME
AUTOMATIC P OWER-F AIL CHIP DES ELECT and
WRITE PROTECTION
WRITE PROTECT VOLT AGES
= Power-fail Deselect Voltage):
(V
PFD
– M48Z58: 4.50V ≤ V
– M48Z58Y: 4.20V ≤ V
SELF-CONTAINED BATTERY in the CAPHAT
DIP PACKAGE
PACKAGING INCLUDES a 28-LEAD SOIC
and SNAPHAT
®
TOP
(to be Ordered Separately)
SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY and CRYSTAL
PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 8K x 8 SRAMs
PFD
PFD
4.75V
≤
≤
4.50V
SNAPHAT (SH)
Battery
28
28
1
SOH28 (MH)
Figure 1. Logic Diagram
M48Z58
M48Z58Y
1
PCDIP28 (PC)
Battery CAPHAT
DESCRIPTION
The M48Z58/58Y ZEROPOW ER
®
RAM is an 8K x
V
CC
8 non-volatile static RAM that integrates power-fail
deselect circuitry and battery control logic on a
single die. The monolithic chip is available in two
special packages to provide a highly integrated
A0-A12
13
8
DQ0-DQ7
battery backed-up memory solution.
T ab le 1. Signal Names
W
A0-A12 Address Inputs
DQ0-DQ7 Data Inputs / Outputs
E Chip Enable
G Output Enable
W Write Enable
V
CC
V
SS
March 1999 1/17
Supply Voltage
Ground
E
G
M48Z58
M48Z58Y
V
SS
AI01176B
Page 2
M48Z58, M48Z58Y
Figure 2A. DIP Pin Connections
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AI01177B
CC
W
NC
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V
Warning:
NC V
1
A12
2
3
A7
4
A6
5
A5
6
A4
7
A3
A2
A1
A0
DQ0
8
9
10
11
M48Z58
M48Z58Y
12
13
DQ2
14
SS
NC = Not Connected.
T ab le 2. Absolute Maximum Ratings
(1)
Figure 2B. SOIC Pin Connections
Warning:
NC V
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
1
2
3
4
5
6
7
M48Z58Y
8
9
10
11
12
DQ2
SS
13
14
NC = Not Connected.
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AI01178B
Symbol Parameter Value Unit
T
A
T
STG
(2)
T
SLD
V
IO
V
CC
I
O
P
D
Notes:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indi cat ed in the operati onal
section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may
affect reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negat i ve undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
Ambient Operating Temperature Grade 1
Grade 6
Storage T emper ature (VCC Off) –40 to 85 °C
Lead Solder Temperature for 10 seconds 260 °C
Input or Output Voltages –0.3 to 7 V
Supply Voltage –0.3 to 7 V
Output Current 20 mA
Power Dissipation 1 W
0 to 70
–40 to 85
CC
W
NC
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V
°C
T ab le 3. Operating Modes
Mode V
CC
(1)
Deselect
Write V
Read V
4.75V to 5.5V
or
4.5V to 5.5V
Read V
Deselect V
SO
to V
Deselect ≤ V
Notes
: 1. X = V
2. See Table 7 for details.
or VIL; VSO = Battery Back-up Switchover Voltage.
IH
PFD
(min)
SO
(2)
2/17
E G W DQ0-DQ7 Power
V
IH
IL
IL
IL
X X High Z Standby
XVILD
V
IL
V
IH
V
IH
V
IH
IN
D
OUT
High Z Active
Active
Active
X X X High Z CMOS Standby
X X X High Z Battery Back-up Mode
Page 3
Figure 3. Block Diagram
M48Z58, M48Z58 Y
A0-A12
LITHIUM
CELL
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
V
CC
DESCRIPTION
(cont’d)
The M48Z58/58Y is a non-volatile pin and function
equivalent to any JEDEC standard 8K x 8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special write
timing or limitations on the number of writes t hat
can be performed.
The 28 pin 600mil DIP CAPHAT houses the
M48Z58/58Y silicon with a long life lithium button
cell in a single package.
The 28 pin 330mil SOIC provides s ockets with gold
plated contacts at both ends for direct connection
to a separate SNAPHAT housing containing the
battery. The unique design allows the SNAPHAT
battery package to be mounted on top of the SOIC
package after the completion of the surface mount
process. Insertion of the SNAPHAT housing after
reflow prevents potential battery damage due to the
high temperatures required for device surfacemounting. The SNAPHAT housing is keyed to prevent reverse insertion.
The SOIC and battery packages are shipped separately in plastic anti-static tubes or in Tape & Reel
form.
POWER
V
PFD
8K x 8
SRAM ARRAY
V
SS
Table 4. AC Measurement Conditions
Input Rise and Fall Times ≤ 5ns
Input Pulse Voltages 0 to 3V
Input and Output Timing Ref. Voltages 1.5V
Note that Output Hi-Z is defined as the point where data is no
longer driven.
Figure 4. AC Testing Load Circuit
5V
1.9kΩ
DEVICE
UNDER
TEST
1kΩ
CL includes JIG capacitance
CL = 100pF or 5pF
DQ0-DQ7
E
W
G
AI01394
OUT
AI01030
3/17
Page 4
M48Z58, M48Z58Y
(1, 2)
T ab le 5. Capacitance
= 25 °C)
(T
A
Symbol Parameter T est Condition Min Max Unit
C
IN
(3)
C
IO
Notes:
1. Effective capacitance measured with power supply at 5V .
2. Sampled only, not 100% tested.
3. Outputs deselected.
Input Capacitance VIN = 0V 10 pF
Input / Output Capacitance V
= 0V 10 pF
OUT
T ab le 6. DC Characteristics
= 0 to 70°C or –40 to 85°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
(T
A
Symbol Parameter Test Condition Min Max Unit
I
LI
I
LO
Supply Current Outputs open 50 mA
I
CC
I
CC1
I
CC2
V
IL
V
IH
V
OL
V
OH
T able 7. Power Down/Up Trip Points DC Characteristics
= 0 to 70°C or –40 to 85°C)
(T
A
Input Leakage Current 0V ≤ VIN ≤ V
Output Leakage Current 0V ≤ V
Supply Current (Standby) TTL E = V
Supply Current (Standby) CMOS E = VCC – 0.2V 3 mA
OUT
≤ V
IH
CC
CC
±1 µA
±5 µA
3mA
Input Low Voltage –0.3 0.8 V
Input High Voltage 2.2 VCC + 0.3 V
Output Low Voltage IOL = 2.1mA 0.4 V
Output High Voltage IOH = –1mA 2.4 V
(1)
Symbol Parameter Min Typ Max Unit
V
PFD
V
PFD
Power-fail Deselect Voltage (M48Z58/58Y) 4.5 4.6 4.75 V
Power-fail Deselect Voltage (M48Z58/58YY) 4.2 4.35 4.5 V
V
SO
t
DR
Notes:
1. All voltages referenced to V
2. At 25 °C
DESCRIPTION
Battery Back-up Switchover Voltage 3.0 V
(2)
Expected Data Retention Time 10 YEARS
.
SS
(cont’d)
For the 28 lead SOIC, the battery package (i.e.
SNAPHAT) part number is "M4Z28-BR00SH1".
The M48Z58/58Y also has its own Power-fail Detect circuit. The control circuitry constantly monitors
the single 5V supply for an out of tolerance condi-
4/17
tion. When V
is out of tolerance, the circuit write
CC
protects the SRAM, providing a high degree of data
security in the midst of unpredictable system operation brought on by low V
. As VCC falls below
CC
approximately 3V , the control circuitry connects the
battery which maintains data until valid power returns.
Page 5
M48Z58, M48Z58 Y
T able 8. Power Down/Up Mode AC Characteristics
= 0 to 70°C or –40 to 85°C)
(T
A
Symbol Parameter Min Max Unit
E or W at VIH before Power Down 0 µs
V
(max) to V
PFD
V
(min) to VSS VCC Fall Time 10 µs
PFD
V
(min) to V
PFD
VSS to V
V
(max) to V
PFD
passes V
CC
(min) to VSS fall time of less than tFB may cause corruption of RAM data.
PFD
(min) = 20ms for industrial temperature grade 6 device.
REC
PFD
(max) to Inputs Recognized 40 200 ms
PFD
(min) fall time of less than tF may result in deselection/writ e protection not occ urri ng until 200 µs after
PFD
(min).
PFD
(min) VCC Fall Time 300 µs
PFD
(max) VCC Rise Time 10 µs
PFD
(min) VCC Rise Time 1 µs
Notes
t
t
F
t
FB
t
t
REC
:1.V
2. V
3. t
PD
(1)
(2)
t
R
RB
(3)
V
Figure 5. Power Down/Up Mode AC Waveforms
V
CC
V
(max)
PFD
V
(min)
PFD
VSO
INPUTS
OUTPUTS
tF
tPD
tFB
tDR
tRB
DON'T CARE
VALID VALID
(PER CONTROL INPUT)
HIGH-Z
tR
tREC
RECOGNIZEDRECOGNIZED
(PER CONTROL INPUT)
AI01168C
5/17
Page 6
M48Z58, M48Z58Y
T ab le 9. Read Mode AC Characteristics
= 0 to 70°C or –40 to 85°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
(T
A
Symbol Parameter
Notes:
t
AVAV
(1)
t
AVQV
(1)
t
ELQV
(1)
t
GLQV
(2)
t
ELQX
(2)
t
GLQX
(2)
t
EHQZ
(2)
t
GHQZ
(1)
t
AXQX
1. C
= 100pF (see Figure 4).
L
= 5pF (see Figure 4).
2. C
L
Read Cycle Time 70 ns
Address Valid to Output Valid 70 ns
Chip Enable Low to Output Valid 70 ns
Output Enable Low to Output Valid 35 ns
Chip Enable Low to Output Transition 5 ns
Output Enable Low to Output Transition 5 ns
Chip Enable High to Output Hi-Z 25 ns
Output Enable High to Output Hi-Z 25 ns
Address Transition to Output Transitio n 10 ns
M48Z58 / M48Z58Y
-70
Min Max
Unit
Figure 6. Read Mode AC Waveforms
A0-A12
E
G
DQ0-DQ7
Note:
Write Enable (
W) = High.
tAVAV
VALID
tAVQV tAXQX
tELQV
tELQX
tGLQX
tGLQV
tGHQZ
VALID
tEHQZ
AI01385
6/17
Page 7
M48Z58, M48Z58 Y
T ab le 10. Write Mode AC Characteristics
= 0 to 70°C or –40 to 85°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
(T
A
Symbol Parameter
t
WLQZ
t
AVAV
t
AVWL
t
AVEL
t
WLWH
t
ELEH
t
WHAX
t
EHAX
t
DVWH
t
DVEH
t
WHDX
t
EHDX
(1, 2)
Write Cycle Time 70 ns
Address Valid to Write Enable Low 0 ns
Address Valid to Chip Enable Low 0 ns
Write Enable Pulse Width 50 ns
Chip Enable Low to Chip Enable High 55 ns
Write Enable High to Address Transition 0 ns
Chip Enable High to Address Transition 0 ns
Input Valid to Write Enable High 30 ns
Input Valid to Chip Enable High 30 ns
Write Enable High to Input Transition 5 ns
Chip Enable High to Input Transition 5 ns
Write Enable Low to Output Hi-Z 25 ns
M48Z58 / M48Z58Y
-70
Min Max
Unit
Notes:
t
AVWH
t
AVEH
(1, 2)
t
WHQX
1. C
= 5pF (see Figure 4).
L
E goes low simultaneously with W going low, the outputs remain in the high impedance state.
2. If
Address Valid to Write Enable High 60 ns
Address Valid to Chip Enable High 60 ns
Write Enable High to Output Transition 5 ns
READ MODE
The M48Z58/58Y is in the Read Mode whenever
W (Write Enable) is high, E (Chip Enable) is low.
Thus, the unique address specified by the 13 Address Inputs defines which one of the 8,192 bytes
of data is to be accessed. Valid data will be available at the Dat a I/O pins within Address Access
time (t
stable, providing that the
also satisfied. If the
) after the last address input signal is
AV Q V
E and G acce ss times a re
E and G access times are not
met, valid data will be available after the latter of
the Chip Enable Access time (t
Enable Access time (t
GLQV
).
) or Output
ELQV
The state of the eight three-state Data I/O signals
is controlled by
before t
AVQ V
indeterminate state until t
puts are changed while
E and G. If the outputs are activated
, the data lines will be driven to an
. If the Address In-
AVQV
E and G remain active,
output data will remain valid for Output Data Hold
time (t
) but will go indeterminate until the next
AXQX
Address Access.
WRITE MODE
The M48Z58/58Y is in the W rite Mode whenever
E are low. The start of a write is referenced
and
from the latter occurring falling edge of
W or E. A
write is terminated by the earlier rising edge of
or
E. The addresses must be held valid throughout
the cycle.
of t
E or W must return high for a minimum
from Chip Enable or t
EHAX
WHAX
from Write
W
W
Enable prior to the initiation of another read or write
cycle. Data-in must be valid t
of write and remain valid for t
prior to the end
DVWH
afterward. G
WHDX
should be kept high during write cycles to avoid bus
contention; although, if the output bus has been
activated by a low on
disable the outputs t
E and G, a low on W will
after W falls.
WLQZ
7/17
Page 8
M48Z58, M48Z58Y
Figure 7. Write Enable Controlled, Write AC Waveforms
tAVAV
A0-A12
tAVEL
E
tAVWL
W
tWLQZ
DQ0-DQ7
VALID
tAVWH
tWLWH
Figure 8. Chip Enable Controlled, Write AC Waveforms
tDVWH
tWHAX
tWHQX
tWHDX
DATA INPUT
AI01386
8/17
A0-A12
E
W
DQ0-DQ7
tAVEL
tAVWL
tAVAV
VALID
tAVEH
tELEH
tDVEH
tEHAX
tEHDX
DATA INPUT
AI01387B
Page 9
M48Z58, M48Z58 Y
DA TA RETE NT ION MODE
With valid V
applied, the M48Z58/58Y operates
CC
as a conventional BYTEWIDE static RAM.
Should the supply voltage decay, the RAM will
automatically power-fail deselect, write protecting
itself when V
(min) window. All outputs become high imped-
V
PFD
falls within the V
CC
PFD
(max),
ance, and all inputs are treated as "don’t care."
Note:
A power failure during a write cycle may
corrupt data at the c urrently addressed location,
but does not jeopardize the rest of the RAM’s
content. At voltages below V
(min), the user can
PFD
be assured the memory will be in a write protected
state, provided the V
fall time is not less than tF.
CC
The M48Z58/58Y may respond to transient noise
spikes on V
during the time the device is s ampling V
that reach into the deselect window
CC
. There-
CC
fore, decoupling of the power supply lines is recommended.
When V
drops below VSO, the control circuit
CC
switches power to the internal batter y which preserves data. The internal button c ell will maintain
data in the M48Z58/58Y for an accumulated period
of at least 10 years when V
As system power returns and V
is less than VSO.
CC
rises above VSO,
CC
the battery is disconnected, and the power supply
is switched to external V
tinues until V
reaches V
CC
Normal RAM operation can resume t
exceeds V
PFD
(max).
. Write protection con-
CC
(min) plus t
PFD
REC
REC
after V
(min).
CC
For more information on Battery Storage Life refer
to the Application Note AN1012.
POWER SUPPLY DECOUPLING and UNDERSHOOT PROTECTION
transients, including those produced by output
I
CC
switching, can produce voltage fluctuations, resulting in spikes on the V
bus. These transients can
CC
be reduced if capacitors are used to store energy,
which stabilizes the V
bus. The energy stored in
CC
the bypass capacitors will be released as low going
spikes are generated or energy will be absorbed
when overshoots occur . A ceramic bypass capacitor value of 0.1µF (as shown in Figure 9) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal
SRAM operation, power cycling can generate
negative voltage spikes on V
values below V
by as much as one Volt. These
SS
that drive it to
CC
negative spikes can cause data corruption in the
SRAM while in battery backup mode. To protect
from these voltage spikes, it is recommeded to
connect a schottky diode from V
connected to V
, anode to VSS). Schottky diode
CC
to VSS (cathode
CC
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount.
Figure 9. Supply Voltage Protection
V
CC
V
CC
0.1µF DEVICE
V
SS
AI02169
9/17
Page 10
M48Z58, M48Z58Y
ORDERING INFORMATION SCHEME
Example: M48Z58Y -70 MH 1 TR
Supply Voltage and Write
Protect Voltage
(1)
58
VCC = 4.75V to 5.5V
V
= 4.5V to 4.75V
PFD
58Y V
Notes:
Caution:
= 4.5V to 5.5V
CC
V
= 4.2V to 4.5V
PFD
1. The M48Z58 part is offered with the PCDIP28 (i.e. CAPHAT) package only.
2. The SOIC package (SOH28) requires the battery package (SNAPHAT) which is ordered separately under the part number
"M4Z28-BR00SH1" in plasti c tube or "M4Z28 -BR 00SH 1T R" in Tape & Reel form.
3. Delivery may include either the 2-pin version of the SOIC/SNAPHAT or the 4-pin version of the SOIC/SNAPHAT. Both are
functionally equivalent (see package drawing section for details).
4. Industrial temperature grade available in SOIC package (SOH28) only.
Do not place the SNAPHAT battery package "M4Z28-BR00SH1" in conductive foam since this will drain the lithium button-cel l
battery.
Speed
-70 70ns
Package
PC PCDIP28
(2,3)
MH
SOH28
Temp. Range
1 0 to 70 °C
(4)
6
–40 to 85°C
Shipping Method
for SOIC
blank Tubes
TR Tape & Reel
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device,
please contact the STMicroelectronics Sales Office nearest to you.
10/17
Page 11
PCDIP2 8 - 28 pin Plastic D I P, batter y CAPHAT
M48Z58, M48Z58 Y
Symb
Typ Min Max Typ Min Max
A 8.89 9.65 0.350 0.380
A1 0.38 0.76 0.015 0.030
A2 8.38 8.89 0.330 0.350
B 0.38 0.53 0.015 0.021
B1 1.14 1.78 0.045 0.070
C 0.20 0.31 0.008 0.012
D 39.37 39.88 1.550 1.570
E 17.83 18.34 0.702 0.722
e1 2.29 2.79 0.090 0.110
e3 29.72 36.32 1.170 1.430
eA 15.24 16.00 0.600 0.630
L 3.05 3.81 0.120 0.150
N28 28
mm inches
Drawing is not to scale.
B1 B e1
e3
D
N
1
A2
A1AL
E
C
eA
PCDIP
11/17
Page 12
M48Z58, M48Z58Y
SOH28 - 28 le ad Plastic Smal l O utl ine, 4-soc ket battery SNAP HAT
Symb
Typ Min Max Typ Min Max
A 3.05 0.120
A1 0.05 0.36 0.002 0.014
A2 2.34 2.69 0.092 0.106
B 0.36 0.51 0.014 0.020
C 0.15 0.32 0.006 0.012
D 17.71 18.49 0.697 0.728
E 8.23 8.89 0.324 0.350
e1.27– –0.050– –
eB 3.20 3.61 0.126 0.142
H 11.51 12.70 0.453 0.500
L 0.41 1.27 0.016 0.050
α 0° 8° 0° 8°
N28 28
CP 0.10 0.004
mm inches
Be
Drawing is not to scale.
12/17
N
1
SOH-A
A2
A
C
eB
CP
D
E
H
LA1 α
Page 13
M48Z58, M48Z58 Y
SOH28 - 28 le ad Plastic Smal l O utl ine, 2-soc ket battery SNAP HAT
Symb
Typ Min Max Typ Min Max
A 3.05 0.120
A1 0.05 0.36 0.002 0.014
A2 2.34 2.69 0.092 0.106
B 0.36 0.51 0.014 0.020
C 0.15 0.32 0.006 0.012
D 17.71 18.49 0.697 0.728
E 8.23 8.89 0.324 0.350
e1.27– –0.050– –
eB 3.20 3.61 0.126 0.142
H 11.51 12.70 0.453 0.500
L 0.41 1.27 0.016 0.050
α 0° 8° 0° 8°
N28 28
CP 0.10 0.004
mm inches
Be
Drawing is not to scale.
N
1
SOH-B
A2
A
C
eB
CP
D
E
H
LA1 α
13/17
Page 14
M48Z58, M48Z58Y
SH - 4-pin SNAPHAT Housing for 49 mAh Batte r y
Symb
Typ Min Max Typ Min Max
A 9.78 0.385
A1 6.73 7.24 0.265 0.285
A2 6.48 6.99 0.255 0.275
A3 0.38 0.015
B 0.46 0.56 0.018 0.022
D 21.21 21.84 0.835 0.860
E 14.22 14.99 0.560 0.590
eA 15.55 15.95 0.612 0.628
eB 3.20 3.61 0.126 0.142
L 2.03 2.29 0.080 0.090
mm inches
Drawing is not to scale.
14/17
eA
D
A1
E
A2
A
B
A3
L
eB
SH
Page 15
M48Z58, M48Z58 Y
SH - 2-pin SNAPHAT Housing for 49 mAh Batte r y
Symb
Typ Min Max Typ Min Max
A 9.78 0.385
A1 6.73 7.24 0.265 0.285
A2 6.48 6.99 0.255 0.275
A3 0.38 0.015
B 0.46 0.56 0.018 0.022
D 21.21 21.84 0.835 0.860
E 14.22 14.99 0.560 0.590
eB 3.20 3.61 0.126 0.142
L 2.03 2.29 0.080 0.090
mm inches
Drawing is not to scale.
A1
A
B
D
eB
A2
A3
L
E
SHZP-A
15/17
Page 16
M48Z58, M48Z58Y
SH - 2-pin SNAPHAT Housing for 130 mAh Battery
Symb
Typ Min Max Typ Min Max
A 10.54 0.415
A1 8.00 8.51 0.315 0.335
A2 7.24 8.00 0.285 0.315
A3 0.38 0.015
B 0.46 0.56 0.018 0.022
D 21.21 21.84 0.835 0.860
E 17.27 18.03 0.680 0.710
eB 3.20 3.61 0.126 0.142
L 2.03 2.29 0.080 0.090
mm inches
Drawing is not to scale.
16/17
A1
A
B
D
eB
A2
A3
L
E
SHZP-B
Page 17
M48Z58, M48Z58 Y
Information furnished is believed to be accurate and reliable. However, STMicroelectronics as sumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and repl aces all information previously supplied. STMicroelectron ics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelect roni cs
© 1999 STMicroelectronics - All Rights Reserved
® ZEROP OWER and SNAPHAT are registered trademarks of STMicroelectronics
CAPHAT and BYTEWIDE are trademarks of STMicroelectronics
Australia - Brazil - China - France - Germany - Italy - Japan - Korea - Malaysi a - Malta - Mexico - Moro cc o - The Netherl ands -
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
STMicroelectronics GROUP OF COMPANIES
http://www.st.com
17/17
Loading...