Page 1
查询M48T201V-85MH1供应商
FEAT URES SUM MARY
■ CONVERTS LOW POWER SRAM INTO
NVRAMs
■ YEAR 2000 COMPLIANT
■ BATTERY LOW FLAG
■ INTEGRATED RE AL T IME C LOCK, POWER-
FAIL CONTROL CIRCUIT, BATTERY AND
CRYSTAL
■ WATCHDOG TIMER
■ CHOICE OF WRITE PROTECT VOLTA GES
= Power-fail Deselect Voltage):
(V
PFD
– M48T201Y: V
4.1V ≤ V
PFD
– M48T201V: V
2.7V ≤ V
■ MICROPROCESSOR POWER-ON RESET
PFD
(Valid even during battery back-up mode.)
■ PROGRAMMABLE ALAR M OUTPUT
ACTIVE IN THE BATTERY BACKED-UP
MODE
■ PACKAGING INCLUDES A 44-LEAD SOIC
AND SNAPHAT
separately)
■ SOIC PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT
WHICH CONTAINS THE BATTERY AND
CRYSTAL
= 4.5 to 5.5V
CC
≤ 4.5V
= 3.0 to 3.6V
CC
≤ 3.0V
®
TOP (to be ordered
®
TOP
M48T201Y
M48T201V
5.0 or 3.3V TIMEKEEPER® Supervisor
Figure 1. Package
SNAPHAT (SH)
Crystal/Battery
44
1
SOH44 (MH)
44-pin SOIC
1/33September 2004
Page 2
M48T201Y, M48T201V
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. SOIC Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Address Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. G
Figure 6. READ Cycle Timing: RTC and External RAM Control Signals . . . . . . . . . . . . . . . . . . . . .9
Table 3. RE A D Mode AC Charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7. WRITE Cycle Timing: RTC & External RAM Control Signals . . . . . . . . . . . . . . . . . . . . .11
Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Timing When Switching Between RTC and External SRAM. . . . . . . . . . . . . . . . . . 8
CON
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
TIMEKEEPER® Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Reading the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Setting the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Stopping and Starting the Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. TIMEKEEPER® Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Setting the Alarm Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. Alarm Interrupt Reset Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. A larm Repeat Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 9. Back-up Mode Alarm Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Square Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 7. S quare Wav e Output Frequen cy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Reset Inputs (RSTIN1
Figure 10.RSTIN1
Table 8. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12.Calibration Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Battery Low Warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
& RSTIN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
and RSTIN2 Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/33
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M48T201Y, M48T201V
Table 9. Default Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
V
Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
CC
Figure 13.Supply Voltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 10.Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 11. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 14.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 12.Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 13.DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 15.Power Down/Up Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 14.Power Down/Up Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 16.SOH44 – 44-lead Plastic Small Outline, SNAPHAT, Package Outlin e . . . . . . . . . . . . . . 28
Table 15. SOH44 – 44-lead Plastic Small Outline, SNAPHAT, Package Mechanical Data . . . . . . 28
Figure 17.SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline . . . . . . . 29
Table 16. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mech. Data. . . . 29
Figure 18.SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline . . . . . . 30
Table 17. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data. . . 30
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 18.Ordering Information Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 19.SNAPHAT® Battery Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 20.Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3/33
Page 4
M48T201Y, M48T201V
DESCRIPTION
The M48T201Y/V are self-co ntained devices that
include a real time clock (RTC), programmable
alarms, a watchdog timer, and a square wave output which provides control of up to 512K x 8 of external low-power static RAM. Access to all RTC
functions and the external RAM is the same as
conventional bytewide SRAM. The 16 TIMEKEEPER
®
registers offer year, month, date, day,
hour, minute, second, calibration, alarm, century,
watchdog, and square wave output data. Externally attached static RAMs are controlled by the
M48T201Y/V via the G
CON
and E
CON
signals.
The 44-pin, 330mil SOIC provides sockets with
gold plated contacts at bot h ends for direct connection to a separate SNAPHAT
®
housing containing the battery and crystal. The unique design
allows the SNAPHAT battery package to be
Figure 2. Logic Diagram Table 1. Signal Names
mounted on top of the SOIC package after the
completion of the surface mount process.
Insertion of the SNAPHAT housing after reflow
prevents potential battery damage due to the high
temperatures required for device surface-moun ting. The SNAPHAT hous ing is keyed to prevent
reverse insertion. The SOIC and battery packages
are shipped separately in plastic anti-static tubes
or in Tape & Reel form. For the 44-lead SOIC, the
battery/crystal package (e.g., SNAPHAT) part
number is “M4Txx-BR12SH” (see Table
19., page 31).
Caution: Do not place the SNAPHAT battery/crystal top in conductive foam as this will drain the lithium button-cell battery.
A0-A18 Address Inputs
A0-A18
WDI
W
RSTIN1
RSTIN2
DQ0-DQ7 Data Inputs / Outputs
V
CC
19
M48T201Y
E
G
M48T201V
V
SS
8
DQ0-DQ7
IRQ/FT
RST
G
CON
E
CON
SQW
V
OUT
AI02240
RSTIN1
RSTIN2
RST
WDI Watchdog Input
E
G
W
E
CON
G
CON
/FT
IRQ
SQW Square Wave Output
V
OUT
V
CC
Reset 1 Input
Reset 2 Input
Reset Output (Open Drain)
Chip Enable Input
Output Enable Input
WRITE Enable Input
RAM Chip Enable Output
RAM Enable Output
Interrupt / Frequency Test Output
(Open Drain)
Supply Voltage Output
Supply Voltage
4/33
V
SS
NC Not Connected Internally
Ground
Page 5
Figure 3. SOIC Connections
M48T201Y, M48T201V
RSTIN1
RSTIN2
RST
NC
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
WDI
G
CON
DQ0
DQ1
DQ2 21
V
SS
1
2
3
4
5
6
7
8
9
10
11
M48T201Y
12
M48T201V
13
14
15
16
17
18
19
20
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
2322
AI02241
V
CC
V
OUT
SQW
IRQ/FT
A17
A15
A13
A8
A9
A11
G
W
NC
A10
E
E
CON
DQ7
DQ6
DQ5
DQ4
DQ3
NC
5/33
Page 6
M48T201Y, M48T201V
Figure 4. Hardware Hookup
0.1µF
5V
32,768 Hz
CRYSTAL
LITHIUM
CELL
M48T201Y/V
V
CC
E
W
G
WDI
RSTIN1
RSTIN2
V
SS
A0-A18
IRQ/FT
DQ0-DQ7
V
OUT
ECON
GCON
RST
SQW
0.1µF
V
E2
E
W
G
V
A0-Axx
CC
(1)
CMOS
SRAM
SS
DQ0-DQ7
AI00604
Note: 1. If the se cond chip enabl e pin (E2) is unused, it sh ould be tied to V
OUT
.
6/33
Page 7
OPERATION
Automatic backup and write protection for an ex-
, E
ternal SRAM is provided through V
G
pins. (Users are urged to insure that voltage
CON
OUT
specifications, for both the SUPERVISOR chip
and external SRAM chosen, are similar.) The
SNAPHAT
®
containing the lithium energy source
is used to retain the RTC and RAM data in the absence of V
chip enable output to RAM (E
enable output to RAM (G
power through the V
CC
CON
OUT
) and the output
CON
) are controlled during power transients to prevent data corruption.
The date is automatically adjusted for months with
less than 31 days and corrects for leap years (valid
until 2100). The internal watchdog timer prov ides
programmable alarm windows.
The nine clock bytes (7FFFFh-7FFF9h and
7FFF1h) are not the actual clock counters, they
are memory locations consisting of BiPORT™
READ/WRITE memory cells within the static RAM
array. Clock circuitry updates the clock bytes with
current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory
array. Byte 7FFF8h is the clock control register.
This byte controls user access to the clock information and also stores the clock calibration setting.
Byte 7FFF7h contains the watchdog timer setting.
The watchdog timer can generate either a reset or
an interrupt, depending on the state of the Watchdog Steering Bit (WDS). Bytes 7FFF6h-7FFF2h
include bits that, when programmed, provide for
clock alarm functionality. Alarms are activated
when the register content matches the month,
, and
CON
pin. The
M48T201Y, M48T201V
date, hours, minutes, and seconds of the clock
registers. Byte 7FFF1h contains ce ntury information. Byte 7FFF0h contains additional flag information pertaining to the watchdog timer, the alarm
condition, the battery status and square wave output operation. 4 bits are included within this register (RS0-RS3) that are used to program the
Square Wave Output Frequency (see Table
7., page 18). The M48T201Y/V also has its own
Power-Fail Detect circuit. This control circuitry
constantly monitors the supply voltage for an out
of tolerance condition. When V
ance, th e cir cuit wri te pro tect s the TIMEK EEPER
register data and external SRAM, providing dat a
security in the midst of unpredictable system operation. As V
Switchover Voltage (V
falls below the Battery Back-up
CC
), the control circuitry au-
SO
tomatically switches to the battery, maintaining
data and clock operation until valid power is restored.
Address Decoding
The M48T201Y/V accommodates 19 address
lines (A0-A18) which allow direct connection of up
to 512K bytes of static RAM. Regardless of SRAM
density used, timekeeping, watchdog, alarm, century, flag, and control regi sters are located in the
upper RAM locations. All TIMEKEEPER registers
reside in the upper R AM l oc ations without conflict
by inhibiting the G
(output enable RAM) signal
CON
during clock access . The RAM's physica l location s
are transparent to the user and the memory m ap
looks continuous from the first clock address to the
upper most attached RAM addresses.
is out of toler-
CC
®
Table 2. Operating Modes
Mode
Deselect
WRITE
READ
READ
Deselect
Deselect
Note: X = VIH or VIL; VSO = Battery B ack-up Switc hover Volta ge
1. See Table 14., page 27 for details.
VSO to V
V
CC
4.5V to 5.5V
or
3.0V to 3.6V
(min)
PFD
(1)
≤ V
SO
(1)
E G W DQ7-DQ0 Power
V
IH
V
IL
V
IL
V
IL
X X X High-Z CMOS Standby
X X X High-Z Battery Back-Up
X X High-Z Standby
X
V
IL
V
IH
V
IL
V
IH
V
IH
D
IN
D
OUT
High-Z Active
Active
Active
7/33
Page 8
M48T201Y, M48T201V
READ Mode
The M48T201Y/V executes a RE AD Cycle whenever W
able) is low. The unique address specified by the
address inputs (A0-A18) def ines wh ich one of the
on-chip TIMEKEEPER
SRAM locations is to be acc essed. Whe n the address presented to the M48T201Y/V is in the
range of 7FFFFh-7FFF0h, one of the on-board
TIMEKEEPER registers is accessed and valid
data will be available to the eight data output drivers within t
stable, providing that the E
are also satisfied. If they are not, then data access
(WRITE Enable) is high and E (Chip En-
®
registers or external
after the address input signal is
AVQV
and G access times
must be measured from the latter occurring signal
or G) and the limiting parameter is either t
(E
for E or t
for G rather than the address access
GLQV
ELQV
time. When one of the on-chip TIMEKEEPER registers is select ed for RE AD, the G
signal wi ll
CON
remain inactive throughout the READ Cycle.
When the address value presented to the
M48T201Y/V is outside the range of TIMEKEEPER registers, an external SRAM location will be
selected. In this case the G
or t
pin, with the specified dela y times of
CON
.
OERL
to the G
t
AOEL
signal will be passed
Figure 5. G
ADDRESS
G
G
CON
E
Timing When Switching Between RTC and External SRAM
CON
00000h - 7FFEFh 7FFF0h - 7FFFFh 00000h - 7FFEFh7FFF0h - 7FFFFh
RTC
External SRAM
tAOEL
RTC
tAOEH
tOERL
External SRAM
tRO
AI02333
8/33
Page 9
Figure 6. READ Cycle Timing: RTC and External RAM Control Signals
READ READ WRITE
tAVAV
ADDRESS
tAVAV tAVAV
M48T201Y, M48T201V
E
G
G
CON
E
CON
W
DQ0-DQ7
tEPD
tELQV
tELQX
tGLQV
tAVQV tWHAXtAVWL
tAXQXtGLQX
DATA OUT
VALID
tRO
tWLWH
DATA OUT
VALID
tGHQZ
DATA IN
VALID
AI02334
9/33
Page 10
M48T201Y, M48T201V
Table 3. READ Mode AC Characteristics
M48T201Y M48T201V
Symbol
t
AVAV
t
AVQV
t
ELQV
t
GLQV
t
ELQX
t
GLQX
t
EHQZ
t
GHQZ
t
AXQX
t
AOEL
t
AOEH
t
EPD
t
OERL
t
RO
Note: 1. Vali d fo r Ambient Op erating Temperature : TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3. 0 to 3.6V (exc ept where not ed).
2. C
READ Cycle Time 70 85 ns
Address Valid to Output Valid 70 85 ns
Chip Enable Low to Output Valid 70 85 ns
Output Enable Low to Output Valid 25 35 ns
(2)
Chip Enable Low to Output Transition 5 5 ns
(2)
Output Enable Low to Output Transition 0 0 ns
(2)
Chip Enable High to Output Hi-Z 20 25 ns
(2)
Output Enable High to Output Hi-Z 20 25 ns
Address Transition to Output Transition 5 5 ns
External SRAM Address to G
SUPERVISOR SRAM Address to G
E to E
CON
G Low to G
G High to G
= 5pF.
L
Parameter
Low or High
Low
CON
High
CON
(1)
CON
Low
CON
High
Min Max Min Max
20 30 ns
20 30 ns
10 15 ns
15 20 ns
10 15 ns
Unit–70 –85
10/33
Page 11
WRITE Mode
The M48T201Y/V is in the WRITE Mode whenever
(WRITE Enable) and E (Chip Ena ble) are low
W
state after the address inputs are stable. The start
of a WRITE is referenced from the latter occurring
falling edge of W
the earlier rising edge of W
must be held valid th roughout the cycle. E
must return high for a minimum of t
Enable or t
or E. A WRITE is terminated by
or E. The addresses
from WRITE Enable prior to the
WHAX
EHAX
or W
from Chip
initiation of another READ or WRITE Cycle. Datain must be valid t
and remain valid for t
prior to the end of WRITE
DVWH
afterw ard. G should be
WHDX
tention; although, if the output bu s has be en activated by a low on E
the outputs t
WLQZ
When the address value presented to the
M48T201Y/V during the WRITE is in the range of
7FFFFh-7FFF0h, one of the on-board TIMEKEEPER
®
registers will be selected and data will
be written into the device. When the address value
presented to M48T201Y/V is outside the range of
TIMEKEEPER registers, an external SRAM location is selected .
kept high during WRI TE Cyc les to avoid bus con-
Figure 7. WRITE Cycle Timing: RTC & External RAM Control Signals
WRITE WRITE READ
tAVAV
ADDRESS
tAVAV
M48T201Y, M48T201V
and G a low on W will disable
after W falls.
tAVAV
E
E
CON
G
G
CON
W
DQ0-DQ7
tAVEL
tAVWL
DATA OUT
VALID
tEPD
tRO
tAVEH
tELEH tEHAX
tEPD
tWLWH
tEHQZ
DATA IN
tEHDX
tDVEH
VALID
tAVWH
tDVWH
tWHAX
DATA IN
VALID
tWHQX
tWHDX
tAVQV
tGLQV
DATA OUT
tWLQZ
VALID
AI02336
11/33
Page 12
M48T201Y, M48T201V
Table 4. WRITE Mode AC Characteristics
M48T201Y M48T201V
Symbol
t
AVAV
t
AVWL
t
AVEL
t
WLWH
t
ELEH
t
WHAX
t
EHAX
t
DVWH
t
DVEH
t
WHDX
t
EHDX
t
WLQZ
t
AVWH
t
AVEH
t
WHQX
Note: 1. Vali d fo r Ambient Op erating Temperature : TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3. 0 to 3.6V (exc ept where not ed).
2. C
3. If E
WRITE Cycle Time 70 85 ns
Address Valid to WRITE Enable Low 0 0 ns
Address Valid to Chip Enable Low 0 0 ns
WRITE Enable Pulse Width 45 55 ns
Chip Enable Low to Chip Enable High 50 60 ns
WRITE Enable High to Address Transition 0 0 ns
Chip Enable High to Address Transition 0 0 ns
Input Valid to WRITE Enable High 25 30 ns
Input Valid to Chip Enable High 25 30 ns
WRITE Enable High to Input Transition 0 0 ns
Chip Enable High to Input Transition 0 0 ns
(2,3)
WRITE Enable Low to Output High-Z 20 25 ns
Address Valid to WRITE Enable High 55 65 ns
Address Valid to Chip Enable High 55 65 ns
(2,3)
WRITE Enable High to Output Transition 5 5 ns
= 5pF
L
goes low simultaneously with W going low, the output s rem ai n in the high im pedance stat e.
Parameter
(1)
Min Max Min Max
Unit–70 –85
12/33
Page 13
Data Retention Mode
With valid V
applied, the M48T201Y/V can be
CC
accessed as described above with READ or
WRITE cycles. Should the supply voltage deca y,
the M48T201Y/V will automatically deselect, write
protecting itself (and any external SRAM) when
falls between V
V
CC
(max) and V
PFD
PFD
(min).
This is accomplished by internally inhibiting access to the clock registers via the E
time, the Reset pin (RST
remain active until V
) is driven active an d wi ll
returns to nominal levels.
CC
signal. At this
External RAM access is inhibited in a similar manner by forcing E
within 0.2V of the V
level as long as V
ance condition. When V
the battery (V
the V
pin to the SNAPHAT® battery and the
CC
to a high lev el. This level is
CON
BAT
. E
BAT
remains at an out-of-toler-
CC
will remain at this
CON
falls below the level of
CC
), power input is switched from
clock registers are maintained from the att ached
battery supply. External RAM is also powered by
the SNAPHAT battery. All out puts except G
, RST, IRQ/ FT and V
E
CON
pedance. The V
pin is capable of supplying
OUT
, become high im-
OUT
CON
M48T201Y, M48T201V
100µA of current to the attached memory with less
than 0.3V drop under this condition. On power up,
when V
tion continues for 200ms (max) by inhibiting E
The RST
time (see Figure 15., page 27).
Note: Most low power SRAMs on the market today can be used with the M48T201Y/V TIMEKEEPER
some criteria which should be used in making the
final choice of an SRAM to use.
The SRAM must be designed in a way where the
chip enable input disables a ll other inputs to the
SRAM. This allows inputs to the M48T201Y/V and
SRAMs to be “Don't care” once V
V
PFD
data retention dow n to V
able access time must be sufficient to meet the
system needs with the chip enable (and output en-
,
able) output propagation delays included.
returns to a nominal value, write protec-
CC
signal also remains active during this
®
SUPERVISOR. There are, however
CC
(min). The SRAM should also guarantee
= 2.0V. T he chip en-
CC
CON
falls below
.
13/33
Page 14
M48T201Y, M48T201V
CLOCK OPERATIO N
TIMEKEEPER® Registers
The M48T201Y/V offers 16 internal registers
which contain TIMEKEEPER
Flag, and Control data (see Table 5., page 15).
These registers are memory locations which contain external (user accessible) and internal copies
of the data (usually referred to as BiPORT™
TIMEKEEPER cells). The external copies are independent of internal functions except that they
are updated periodically by the simultaneous
transfer of the incremented interna l copy. TIMEKEEPER and Alarm Registers store data in BCD.
Control, Watchdog and Flags (Bits D0 to D3) Registers store data in Binary Format.
Reading the Clock
Updates to the TIMEKEEPER registers should be
halted before clock data is read to prevent reading
data in transition. The BiPORT TIMEKEEPER
cells in the RAM array are only data registers and
not the actual clock counters, so updating the registers can be halted without disturbing the clock itself.
Updating is halted when a '1' is written to the
READ Bit, D6 in the Control Register (7FFF8h). As
long as a '1' remains in that position , updating is
halted. After a h alt is issu ed, the registers reflect
the count; that is, the day, date, and time that were
current at the moment the halt command was issued.
All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in
progress. Updating occurs approximately 1 second after the READ Bit is reset to a '0.'
®
, Alarm, Watchdog,
Setting the Clock
Bit D7 of the Control Register (7FFF8h) is the
WRITE Bit. Setting the WRITE Bit to a '1,' like the
READ Bit, halts updates to the TIMEKEEPER registers. The user can then load t hem with the correct day, date, and time data in 24-hour BCD
format (see Table 5., p age 15).
Resetting t he WRITE Bit to a '0' th en transfers the
values of all time registers (7FFFFh-7FFF9h,
7FFF1h) to the actua l TIMEKE EPER counters and
allows normal operation to resume. After the
WRITE Bit is reset, the next clock update will occur
approximately one second later.
Note: Upon power-up following a power failure,
both the WRITE Bit and the READ Bit will be reset
to '0.'
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
Bit is located at Bit D7 within the Seconds Register
(7FFF9h). Setting it to a '1' stops the oscillator.
When reset to a '0,' the M48T201Y/V oscillator
starts within one second.
Note: It is not necessary to set the WRITE Bit
when setting or resetting the FREQUENCY TEST
Bit (FT) or the STO P Bi t (ST).
14/33
Page 15
M48T201Y, M48T201V
Table 5. TIMEKEEPER® Register Map
Address
Data
D7 D6 D5 D4 D3 D2 D1 D0
7FFFFh 10 Years Year Year 00-99
7FFFEh 0 0 0 10 M Month Month 01-12
7FFFDh 0 0 10 Date Date: Day of Month Date 01-31
7FFFCh 0 FT 0 0 0 Day Day 01-07
7FFFBh 0 0 10 Hours Hours (24 Hour Format) Hours 00-23
7FFFAh 0 10 Minutes Minutes Minutes 00-59
7FFF9h ST 10 Seconds Seconds Seconds 00-59
7FFF8h W R S Calibration Control
7FFF7h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog
7FFF6h AFE SQWE ABE Al.10M Alarm Month Al. Month 01-12
7FFF5h RPT4 RPT5 Al. 10 Date Alarm Date Al. Date 01-31
7FFF4h RPT3 0 Al. 10 Hours Alarm Hours Al. Hours 00-23
7FFF3h RPT2 Alarm 10 Minutes Alarm Minutes Al. Minutes 00-59
7FFF2h RPT1 Ala r m 10 Seconds Alarm Seconds Al. Seconds 00 -59
Function/Range
BCD Format
7FFF1h 1000 Years 100 Years Century 00-99
7FFF0h WDF AF 0 BL RS3 RS2 RS1 RS0 Flags
Keys : S = Sign Bi t
FT = Frequency Test Bit
R = READ Bit
W = WRITE B i t
ST = Stop Bit
0 = Must be set to '0'
WDS = Watchdog Steeri ng Bit
AF = Alarm Flag
BL = Battery Low Flag
SQWE = Square Wave Enable Bit
BMB0-BMB4 = Watchdog Multiplier Bits
RB0-RB 1 = Watchdog Resolution Bit s
AFE = Alarm Flag Enable Flag
ABE = Alarm in Battery Back-Up Mode Enable Bit
RPT1-RP T 5 = Alarm Repe at M ode Bits
WDF = Watchdog Flag
RS0-RS 3 = S QW F requency
15/33
Page 16
M48T201Y, M48T201V
Setting the Alarm Clock
Registers 7FFF6h-7FFF2 h contain t he alarm settings. The alarm can be configured to go off at a
prescribed time on a specific month, day of month,
hour, minute, or second or repeat every month,
day of month, hour, minute, or second.
It can also be programmed to go off while the
M48T201Y/V is in the battery back-up to serve as
a system wake-up call.
Bits RPT5-RPT1 put the alarm in the repeat mode
of operation. Table 6 shows the poss ible configurations. Codes not listed in the table default to the
once per second mode t o qu ickly alert the us er of
an incorrect alarm setting.
Note: User must transition address (or toggle chip
enable) to see Flag Bit change.
When the clock information matches the alarm
clock settings based on the m atch criteria d efined
by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE
(Alarm Flag Enable) is also set, the alarm condi-
Figure 8. Alarm Interrupt Reset Waveforms
tion activa tes the IRQ
/FT pin. To disable alarm,
write ’0’ to the Alarm-Date register and RPT1-5.
The IRQ
/FT output is cleare d by a READ to the
Flags Register as shown in Figure 8. A subsequent READ of the Flags Register is necessary to
see that the value of the Alarm Flag has been reset to '0 . '
The IRQ
tery back-up mode. The IRQ
/FT pin can also be activated in the bat-
/FT will go low if an
alarm occurs and both ABE (Alarm in Battery
Back-up Mode Enable) and AFE are set. The ABE
and AFE Bits are reset during power-up, therefore
an alarm generated during power-up will only set
AF. The user can read the Flag Register at system
boot-up to determine if an alarm was generated
while the M48T201Y/V was in the deselect mode
during power-up. Figure 9., page 17 illustrates the
back-up mode alarm timing.
A0-A18
ACTIVE FLAG BIT
IRQ/FT
ADDRESS 7FFF0h
15ns Min
HIGH-Z
AI02331
Table 6. Alarm Repeat Modes
RPT5 RPT4 RPT3 RPT2 RPT1 Alarm Setting
11111 Once per Second
11110 Once per Minute
11100 Once per Hour
11000 Once per Day
10000 Once per Month
00000 Once per Year
16/33
Page 17
Figure 9. Back-up Mode Alarm Waveforms
V
CC
V
(max)
PFD
V
(min)
PFD
V
SO
AFE bit/ABE bit
AF bit in Flags Register
IRQ/FT
M48T201Y, M48T201V
tREC
HIGH-Z
Watchdog Timer
The watchdog timer can be used to detect an outof-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the Watchdog Register, address
7FFF7h. Bits BMB4-BMB0 store a binary multiplier
and the two lower order bits RB1-RB0 select the
resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. The
amount of time-out is then determined to be the
multiplication of the five-bit multiplier value with the
resolution. (For example: writing 00001110 in the
Watchdog Register = 3*1 or 3 seconds).
Note: Accuracy of timer is within ± the selected
resolution.
If the processor does not reset the timer within the
specified period, the M48T201Y/V sets the WDF
(Watchdog Flag) and generates a watchdog interrupt or a microprocessor reset. WDF is reset by
reading the Flag Register (Address 7FFF0h).
The most significant bit of the Watchdog Register
is the Watchdog Steering Bit (WDS). When set to
a '0', the watchdog will activate the IRQ
/FT pin
when timed-out. When WDS is set to a '1,' the
watchdog will output a negative pulse on th e RST
pin for t
. The Watchdog register and the AFE,
REC
SQWE, ABE, and FT Bits will reset to a '0' at the
end of a Watchdog time-out when the W DS Bit is
set to a ' 1 . '
HIGH-Z
AI03520
The watchdog timer can be reset by two methods:
1. a transition (high-to-low or low-to-high) can be
applied to the Watchdog Input pin (WDI) or
2. the microprocessor can pe rform a WRITE of
the Watchdog Register.
The time-out period then starts over. The WDI pin
should be tied to V
if not used. The watchdog
SS
will be reset on each transition (edge) seen by the
WDI pin.
In order to perform a software reset of the watchdog timer, the original time-out period can be written into the Watchdog Register, effectively
restarting the count -d o wn cycle.
Should the watchdog timer time-out, and the WDS
Bit is programmed to output an interrupt, a value of
00h needs to be written to the Watchdog Register
in order to clear the IRQ
/FT pin. This will also disable the watchdog function until it is again programmed correctly. A READ of the Flags Register
will reset the Watchdog Flag (Bit D7; Register
7FFF0h).
The watchdog function is automatically disabled
upon power-down and the Watchd og Register is
cleared. If the watchdog function is set to output to
the IR Q
/FT pin and the frequency tes t function is
activated, the watchdog or alarm function prevails
and the frequency test function is denied.
Note: The user must transition the address (or
toggle chip enable) to see the Flag Bit change.
17/33
Page 18
M48T201Y, M48T201V
Square Wave Output
The M48T201Y/V offers the user a programmable
square wave function which is output on the SQW
pin. RS3-RS0 Bits located in 7FFF0h establish the
square wave output frequency. These frequencies
are listed in Table 7. Once the selection of the
Table 7. Square Wave Output Frequency
Square Wave Bits Square Wave
RS3 RS2 RS1 RS0 Frequency Units
0000Hi-Z0 0 0 1 32.768 kHz
00108.192kHz
00114.096kHz
01002.048kHz
01011.024kHz
0110512Hz
0111256Hz
SQW frequency has been completed, the SQW
pin can be turned on and o ff under s oftware control with the Square Wave Enabl e Bit (SQWE ) located in Register 7FFF6h.
1000128Hz
100164Hz
101032Hz
101116Hz
11008Hz
11014Hz
11102Hz
11111Hz
18/33
Page 19
M48T201Y, M48T201V
Power-on Reset
The M48T201Y/V continuously monitors V
When V
the RST
power-up for t
The RST
priate pull-up resistor to V
falls to the power fail detect trip point,
CC
pulls low (open drain) and remains low on
after VCC passes V
REC
PFD
(max).
pin is an open drain output and an appro-
should b e chosen to
CC
control rise time.
Figure 10. RSTIN1
and RSTIN2 Timing Waveforms
RSTIN1
RSTIN2
RST
tR1 tR1HRZ
CC
Reset Inputs (RSTIN1
.
The M48T201Y/V provides two independent in-
& RSTIN2)
puts which can generate an output reset. The duration and function of these resets is identical to a
reset generated by a pow er cycle. Figure 10 and
Table 8 illustrate the AC reset characteristics of
this functio n. Pu lses shorte r than t
R1
not generate a reset condition. RSTIN1
RSTIN2
are each internally pulled up to V
through a 100KΩ resistor.
tR2
Hi-Z
Hi-Z
tR2HRZ
AI01679
and tR2 will
and
CC
Table 8. Reset AC Characteristics
Symbol
t
R1
t
R2
t
R1HRZ
t
R2HRZ
Note: 1. Vali d fo r Ambient Op erating Temperature : TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3. 0 to 3.6V (exc ept where not ed).
= 5pF (see Figure 14., page 25).
2. C
L
RSTIN1 Low to RST Low 50 200 ns
RSTIN2 Low to RST Low 20 100 ms
(2)
RSTIN1 High to RST Hi-Z 40 200 ms
(2)
RSTIN2 High to RST Hi-Z 40 200 ms
Parameter
(1)
Min Max Unit
19/33
Page 20
M48T201Y, M48T201V
Calibrating the C lock
The M48T201Y/V is driven by a quartz controlled
oscillator with a nominal frequency of 32,768Hz.
The devices are factory calibrated at 25°C and
tested for accuracy. Clock accuracy will not exceed ±35 ppm (parts per million) oscillator frequency error at 25°C, which equates to about
±1.53 minutes per month. When the Calibration
circuit is properly employed, accuracy improves to
better than +1/–2 ppm at 25°C.
The oscillation rate of crystals changes with temperature (see Figure 11., page 21). The
M48T201Y/V design employs periodic counter
correction. The calibration circuit adds or subtracts
counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure
12., page 21.
The number of times pulses which are blanked
(subtracted, negative calibration) or split (added,
positive calibration) depends upon the value loaded into the five Calibration bits found in the Control
Register. Adding counts speeds the clock up, subtracting counts slows the clock down.
The Calibration bits occupy the five lower order
bits (D4-D0) in the Control Register 7FFF8h.
These bits can be se t to represent any value between 0 and 31 in binary form. Bit D5 is a Sign Bit ;
'1' indicates positive calibration, '0' indicates negative calibration (see Figure 12., page 21). Calibration occurs within a 64 minute cycle. The first 62
minutes in the cycle may, once per minute, have
one second either shortened by 128 or lengthened
by 256 oscillator cycles. If a binary '1' is loaded into
the register, only the first 2 minutes in the 64
minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on.
Therefore, each calibration step has t he effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 ppm of adjustment per calibration step in the calibrat ion registe r. Assum ing that
the oscillator is running at exactly 32,768Hz, each
of the 31 increments in the Calibration byte wou ld
represent +10.7 or –5.35 seconds per month
which corresponds to a total range of +5.5 or –2.75
minutes per month.
Two methods are available for ascertaining how
much calibration a given M48T201Y/V may require. The first involves setting the clock, letting it
run for a month and comparing it to a known accurate reference and recording deviation over a fixed
period of time. Calibration values, including the
number of seconds los t or gained in a given period, can be found in the STMicroelectronics Application Note AN934, “TIMEKEEPER
CALIBRATION.” This allows the designer to give
the end user the ability to calibrate the clock as the
environment requires, even if the final product is
packaged in a non-user serviceable enclosure.
The designer could provide a simple utility that accesses the Calibration byte.
The second approach is better suited t o a manufacturing environment, and involves the use of the
/FT pin. The pin will toggle at 512Hz, when the
IRQ
Stop Bit (ST, D7 of 7FFF9 h) is '0,' the F requency
Test Bit (FT, D6 of 7FFFCh) is '1,' the Alarm Flag
Enable Bit (AFE, D7 of 7FFF6h) is '0,' and the
Watchdog Steering Bit (WDS, D7 of 7FFF7h) is '1'
or the Watchdog Register (7FFF7h=0) is reset.
Note: A 4-second settling time must be allowed
before reading the 512Hz output.
Any deviation from 512Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. For example, a reading of
512.010124Hz would indicate a +20 ppm oscillator
frequency error, requiring a –10 (WR001010) to be
loaded into the Calibration Byte for correction.
Note that setting or changing the Calibration Byte
does not affect the Frequency Test output frequency.
The IRQ
quires a pull-up resistor to V
/FT pin is an open drain output which re-
for proper opera-
CC
tion. A 500-10kΩ resistor is recommended in order
to control the rise time. The FT Bit is cleared on
power-down.
®
20/33
Page 21
Figure 11. Crystal Accuracy Across Temp eratur e
Frequency (ppm)
20
0
–20
–40
–60
–80
–100
–120
–140
–160
0 10203040506070
∆F
F
Temperature °C
= -0.038 (T - T
ppm
2
C
T0 = 25 °C
)2 ± 10%
0
M48T201Y, M48T201V
80–10–20–30–40
AI00999
Figure 12. Cal ib ra ti on W aveform
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
21/33
Page 22
M48T201Y, M48T201V
Battery Low Warning
The M48T201Y/V automatically performs battery
voltage monitoring upon power-up and at factoryprogrammed time intervals of approximately 24
hours. The Battery Low (BL) Bit, Bit D4 of Flags
Register 7FFF0h, will be asserted if the battery
voltage is found to be less than approximately
2.5V. The BL Bit will remain asserted until completion of battery replacement and subsequent battery low monitoring tests, either during the next
power-up sequence or the next scheduled 24-hour
interval.
If a battery low is generated during a power-up sequence, this indicates that the battery is below approximately 2.5V and may not be able to maintain
data integrity in the SRAM. Data should be considered suspect and verified as correct. A fresh battery should be installed.
If a battery low indication is generated during the
24-hour interval check, this indicates that the battery is near end o f life. However, data is not compromised due to the fact that a nominal V
supplied. In order to insure data integrity during
CC
is
subsequent periods of bat tery back-up m ode, the
battery should be replaced. The S NAPHAT
may be replaced while V
is applied to the de-
CC
®
top
vice.
Note: This will cause the clock to lose time during
the interval the battery/crystal is removed.
The M48T201Y/V only monitors the battery when
a nominal V
is applied to the device. Thus appli-
CC
cations which require extensive durations in the
battery back-up mode should be powered-up periodically (at least once every few months) in order
for this technique to be beneficial. Additionally, if a
battery low is indicated, data integrity should be
verified upon power-up via a checksum or ot her
technique.
Initi a l Powe r - on Defaults
Upon application of power to the de vice, the following register bits are set to a '0' state: WDS;
BMB0-BMB4; RB0-RB1; AFE; ABE; SQWE; W; R;
FT (see Table 9).
Table 9. Default Values
Condition W R FT AFE ABE SQWE
Initial Power-up
(Battery Attach for SNAPHAT)
RESET
Power-down
Note: 1. WD S, BMB0-BMB4, RB0, RB 1.
(3)
(4)
2. Stat e of other control bits undefined.
3. Stat e of other control bits rem ains unchanged.
4. Assuming these bits set to '1' prior to power-down.
(2)
WATCHDOG
Register
000000 0
000000 0
000111 0
(1)
22/33
Page 23
M48T201Y, M48T201V
VCC Noise And Negative Going Transients
transients, including those produced by output
I
CC
switching, can produce voltage fluctuations, resulting in spikes on the V
bus. These transients
CC
can be reduced if capacitors are used to store energy which stabilizes the V
bus. The energy
CC
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1µF (as shown in Figure
13) is recommended in order to provide the need-
ed filtering.
In addition to transients that are caused by normal
SRAM operation, power cycling can generate negative voltage spikes on V
below V
by as much as one volt. These negative
SS
that drive it to values
CC
spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, STMicroelectronics recommends connecting a schottky diode from V
(cathode connected to VCC, anode to VSS).
V
SS
CC
to
Schottky diode 1N5817 is recommended for
through hole and MBRS120T3 is recommended
for surface mount.
Figure 13. Supply Voltage Protection
V
CC
V
CC
0.1µF DEVICE
V
SS
AI00605
23/33
Page 24
M48T201Y, M48T201V
MAXIMUM RA T ING
Stressing the device above the rating l isted in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this specification is
Table 10. Absolute Maximum Ratings
Symbol Parameter Value Unit
not implied. Exposure to Absol ute Max imum Ra ting conditions for extended periods may affect device reliability. Refer also to the
STMicroelectronics SURE Program and other relevant quality documents.
T
T
A
STG
Ambient Operating Temperature 0 to 70 °C
Storage Temperature
SNAPHAT
®
–40 to 85 °C
SOIC –55 to 125 °C
T
SLD
V
(1)
IO
Lead Solder Temperature for 10 seconds 260 °C
Input or Output Voltage
–0.3 to V
CC
+ 0.3
V
M48T201Y –0.3 to 7.0 V
V
CC
(2)
I
O
P
D
Note: 1. Reflow at peak temperature of 215°C to 225°C for < 60 seconds (total thermal budget not to exceed 180°C for between 90 to 12 0
seconds).
CAUTION: Negative und ershoots be l ow –0.3V are not al l owed on any pi n while in the B attery Back-up mode.
CAUTION: Do NOT wave sol der SOIC to avoid damaging SNAP HAT sock ets.
Supply Voltage
M48T201V –0.3 to 4.6 V
Output Current 20 mA
Power Dissipation 1 W
24/33
Page 25
M48T201Y, M48T201V
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Meas ure-
Table 11. DC and AC Measurement Conditions
Parameter M48T201Y M48T201V Unit
V
Supply Voltage
CC
Ambient Operating Temperature 0 to 70 0 to 70 °C
Load Capacitance (C
)
L
Input Rise and Fall Times ≤ 5 ≤ 5ns
Input Pulse Voltages 0 to 3 0 to 3 V
Input and Output Timing Ref. Voltages 1.5 1.5 V
Note: O utput High Z is def i ned as the point where dat a i s no longer driven.
Figure 14. AC Testing Load Ci rcuit
ment Conditions listed in t he relevant tables. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
4.5 to 5.5 3.0 to 3.6 V
100 50 pF
DEVICE
UNDER
TEST
CL includes JIG capacitance
Notes:Exc l uding open- drain output pin; 50pF for M 48T 201V.
645Ω
CL = 100pF
1.75V
AI04764
Table 12. Capacitance
Symbol
C
C
OUT
Note: 1. Effective capa citance measured with power supply at 5V; samp l ed only, not 100% tested.
Input Capacitance 10 pF
IN
(3)
Input/Output Capacitance 10 pF
2. At 25°C; f = 1MHz.
3. Outputs desele ct ed.
Parameter
(1,2)
Min Max Unit
25/33
Page 26
M48T201Y, M48T201V
Table 13. DC Characteristics
Sym Parameter
(2)
I
I
LO
I
I
I
Input Leakage Current
LI
(3)
Output Leakage Current
I
Supply Current Outputs open 8 15 4 10 mA
CC
Supply Current (Standby)
CC1
TTL
Supply Current (Standby)
CC2
CMOS
Battery Current OSC ON
BA T
Battery Current OSC
OFF
V
Input Low Voltage –0.3 0.8 –0.3 0.8 V
IL
V
Input High Voltage 2.2
IH
Test Condition
0V ≤ V
0V ≤ V
E
E
= V
IN
OUT
= V
CC
≤ V
≤ V
IH
–0.2
VCC = 0V
CC
M48T201Y M48T201V
(1)
Min Typ Max Min Typ Max
±1 ±1 µA
CC
±1 ±1 µA
53mA
32mA
575 800 575 800 nA
100 100 nA
+
V
CC
0.3
2.0
VCC +
0.3
Unit–70 –85
V
I
Output Low Voltage
V
OL
Output Low Voltage
(open drain)
V
V
OHB
I
OUT1
I
OUT2
V
V
V
Note: 1. Vali d fo r Ambient Op erating Temperature : TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3. 0 to 3.6V (exc ept where not ed).
Output High Voltage
OH
(5)
VOH Battery Back-up I
(6)
V
OUT
V
OUT
Back-up)
Power-fail Deselect
PFD
Voltage
Battery Back-up
SO
Switchover Voltage
Battery Voltage 3.0 3.0 V
BA T
2. RSTIN1
3. Outputs desele ct ed.
4. For IRQ
5. Conditioned outputs (E
6. External SRAM must match TIMEKEEPER SUPERVISOR chip V
and RSTI N2 internally pulled-up to VCC through 100KΩ resistor. WDI internally pulled-down to VSS through 100KΩ resistor.
/FT & RST pins (Open Drain).
will reduce battery life.
(4)
Current (Active) V
Current (Battery
- G
CON
CON
OL
IOL = 10mA
I
= –1.0mA
OH
OUT2
OUT1
V
OUT2
= 2.1mA
= –1.0µA
> VCC –0.3
> V
–0.3
BA T
2.4 2.4 V
2.0 3.6 2.0 3.6 V
0.4 0.4 V
0.4 0.4 V
100 70 mA
100 100 µA
4.1 4.35 4.5 2.7 2.9 3.0 V
–
V
3.0
) can only sustain CMOS leakage currents in the battery back-up mode. Higher leakage currents
specification.
CC
PFD
100mV
V
26/33
Page 27
Figure 15. Power Down/Up Mode AC Waveforms
V
CC
V
(max)
PFD
V
(min)
PFD
VSO
M48T201Y, M48T201V
INPUTS
OUTPUTS
RST
tF
tFB
VALID VALID
VALID VALID
DON'T CARE
HIGH-Z
tR
tRECtRB
Table 14. Power Down/Up Mode AC Characteristics
Symbol
(2)
t
F
(3)
t
FB
t
R
t
REC
t
RB
Note: 1. Vali d fo r Ambient Op erating Temperature : TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3. 0 to 3.6V (exc ept where not ed).
2. V
3. V
V
(max) to V
PFD
V
(min) to VSS VCC Fall Time
PFD
V
(min) to V
PFD
V
(max) to RST High
PFD
VSS to V
(max) to V
PFD
es V
PFD
(min) to VSS fall time of less than tFB may cause corruption of RAM data.
PFD
(min).
PFD
PFD
PFD
(min) VCC Rise Time
PFD
(min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC pass-
Parameter
(min) VCC Fall Time
(max) VCC Rise Time
(1)
Min Max Unit
300 µs
M48T201Y 10 µs
M48T201V 150 µs
10 µs
40 200 ms
5µs
AI03519
27/33
Page 28
M48T201Y, M48T201V
PACKAGE ME CHANICAL INFORMATIO N
Figure 16. SOH44 – 44-lead Plastic Small Outline, SNAPHAT, Package Outline
A2
A
C
Be
eB
CP
D
N
E
H
LA1 α
1
SOH-A
Note: D rawing is not to scale.
Table 15. SOH44 – 44-lead Plastic Small Outline, SNAPHAT, Package Mechanica l Data
Symb
Typ Min Max Typ Min Max
mm inches
A 3.05 0.120
A1 0.05 0.36 0.002 0.014
A2 2.34 2.69 0.092 0.106
B 0.36 0.46 0.014 0.018
C 0.15 0.32 0.006 0.012
D 17.71 18.49 0.697 0.728
E 8.23 8.89 0.324 0.350
e0.81– –0.032– –
eB 3.20 3.61 0.126 0.142
H 11.51 12.70 0.453 0.500
L 0.41 1.27 0.016 0.050
α 0° 8° 0° 8°
N44 44
CP 0.10 0.004
28/33
Page 29
M48T201Y, M48T201V
Figure 17. SH – 4-pin SNAPHAT Housing for 4 8m Ah Battery & Crystal, Package Outline
eA
D
A1
A
B
eB
A3
L
E
SHTK-A
Note: D rawing is not to scale.
Table 16. SH – 4-pin SNAPHAT Housing for 48mAh Bat tery & Crystal , Package Mech. D ata
Symb
Typ Min Max Typ Min Max
A 9.78 0.385
mm inches
A2
A1 6.73 7.24 0.265 0.285
A2 6.48 6.99 0.255 0.275
A3 0.38 0.015
B 0.46 0.56 0.018 0.022
D 21.21 21.84 0.835 0.860
E 14.22 14.99 0.560 0.590
eA 15.55 15.95 0.612 0.628
eB 3.20 3.61 0.126 0.142
L 2.03 2.29 0.080 0.090
29/33
Page 30
M48T201Y, M48T201V
Figure 18. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline
eA
D
A1
A
B
eB
A3
L
E
SHTK-A
Note: D rawing is not to scale.
Table 17. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data
Symb
Typ Min Max Typ Min Max
A 10.54 0.415
mm inches
A2
A1 8.00 8.51 0.315 .0335
A2 7.24 8.00 0.285 0.315
A3 0.38 0.015
B 0.46 0.56 0.018 0.022
D 21.21 21.84 0.835 0.860
E 17.27 18.03 0.680 .0710
eA 15.55 15.95 0.612 0.628
eB 3.20 3.61 0.126 0.142
L 2.03 2.29 0.080 0.090
30/33
Page 31
M48T201Y, M48T201V
PART NUMBERING
Table 18. Ordering Information Example
Example: M48T 201Y –70 MH 1 TR
Device Type
M48T
Supply and Write Protect Voltage
201Y = V
201V = V
Speed
–70 = 70ns (for M48T201Y)
–85 = 85ns (for M48T201V)
= 4.5 to 5.5V; V
CC
= 3.0 to 3.6V; V
CC
= 4.1V to 4.5V
PFD
= 2.7V to 3.0V
PFD
Package
(1)
MH
= SOH44
Temperature Range
1 = 0 to 70°C
Shipping Method for SOIC
blank = Tubes
TR = Tape & Reel
Note: 1. The SOI C package (SOH4 4) requires the bat tery pack age (SNAPHAT®) which is o rdered separately under the part numbe r
Note: 1. Caution: Do not place the SNAPHAT b attery p ackage “M4 Txx-BR12SH” in con ductive f oa m as it will drain the lithium button-cell
“M4Txx-B R12SH” in pl astic tube or “M 4Txx-BR12SHTR” in T ape & Reel form .
battery.
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
®
Table 19. SNAPHAT
Part Number Description Package
M4T28-BR12SH Lithium Battery (48mAh) SNAPHAT SH
Battery Ta bl e
M4T32-BR12SH Lithium Battery (120mAh) SNAPHAT SH
31/33
Page 32
M48T201Y, M48T201V
REVISION HISTORY
Table 20. Document Revision History
Date Rev. # Revision Details
November 1999 1.0 First Issue
10-May-01 2.0 Reformatted; added Industrial temperature (Table 10, 13, 3, 4, 14)
14-May-01 2.1 Corrected table footnote (Table 14)
30-May-01 2.2 Change “Controller” references to “SUPERVISOR”
01-Aug-01 2.3
Formatting changes from recent document review findings; E2 added to Hookup (Figure
4)
08-Aug-01 2.4 Improve text in “Setting the Alarm Clock” section
18-Dec-01 2.5
Added I
values for Industrial Temperature device (Table 13)
BA T
13-May-02 2.6 Modify reflow time and temperature footnote (Table 10)
16-Jul-02 2.7 Update DC Characteristics, footnotes (Table 13)
27-Mar-03 3.0 v2.2 template applied; update test condition (Table 13)
24-Sep-04 4.0
M48T201, M48T201Y, M48T201V, 48T201, 48T201Y, 48T201V, T201, T201Y, T20 1V, SUPERVISOR, SUPERVI SOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER,
TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM,
NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM,
NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM , NVRAM , NVRAM, NVRAM, NVRAM , NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, RTC, RTC, RTC, RTC, RTC, RTC, RTC,
RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RT C, RTC, RTC, RTC, RT C, RTC, RTC, RTC, RTC,
RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, M icroprocesso r, Microprocessor, Mi croprocessor, Microproce ssor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microproce ssor, Microprocessor, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Lo w, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Lo w, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Lo w, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Lo w, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Lo w, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Lo w, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Lo w, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Lo w, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Lo w, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Lo w, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Lo w, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Lo w, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Lo w, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Lo w, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Lo w, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Lo w, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Lo w, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Lo w, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Lo w, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Lo w, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Lo w, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Lo w, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Lo w, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Lo w, Low, Low, Low, Low, Low,
Low, Low , Low, Low, Low, Lo w , Low, Low, Low, Low, Low, Low, Low, Low , Low, Low, Lo w , Low, Low, Alarm , Al arm, Alar m , Al ar m , Al a r m, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm,
Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, A larm,
Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, A larm,
Alarm, Alarm, Alarm, Ala rm , Alarm, Alarm, Alarm, Alar m, Alarm, Alarm, Alarm, Alarm, Alarm, Al arm, Alarm, Alarm, Alarm, Alarm, Al arm, Alarm, Alarm, Alarm, Alarm, Al arm, A larm, Alarm, Ala rm, Watchdog, Watchdog, Wa t chdog, Watchdog, W at chdog, Wa t chdog, Wat chdog, Wa t chdog, Watchdog, W at chdog, Wa t chdog, Watchdog, Watchd og, Watch do g, Watchd og , Watchdo g, Watch dog , Watchd og, Watch dog, Watc hdog,
Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog,
Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI,
PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, P FO , PFO, PFO, PF O, PFO, PFO, P F O, PFO , PFO,
PFO, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset,
Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset,
Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset,
Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Batt ery, Batt ery, Battery, Batt ery,
Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Batt ery, Batt ery, Battery, Batt ery,
Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover,
Power-fail , Power-fai l, Power- fail, Po wer-fail , Power-f ail, Power-fai l, Power-f ail, Po wer-fail, Power-f ail, Power- fai l, Comparator, C om parator , Comparat or, Co mp ar ator, Compara t or , Compar ator, C om parator , Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator,
Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT,
SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT,
SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC,
SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V,
5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V
Reformatted, remove Industrial T emperature (Ambient Operating) references (T ab le 3, 4,
8, 10, 13, 14, 18)
32/33
Page 33
M48T201Y, M48T201V
Information furnished is believed to be accurate and reliable. However, STMicroelectronics a ssumes no responsibility fo r the c onsequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authori zed for use as crit i cal compon ents in life support devic es or systems without ex press written approval of STMicroel ectronics.
The ST logo is a registered trademark of STM i croelectr onics.
All other nam es are the pro perty of their respectiv e owners
© 2004 STMi croelectronics - All rights reser ved
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Page 34
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