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M38504E6SP
Datasheet (Mitsubishi)
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Datasheet M38504M6-XXXSP, M38504M6-XXXFP, M38504E6SS, M38504E6SP, M38504E6FP Datasheet (Mitsubishi)

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Page 1
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

DESCRIPTION

The 3850 group is the 8-bit microcomputer based on the 740 fam­ily core technology. The 3850 group is designed for the household products and office automation equipment and includes serial I/O functions, 8-bit timer, and A-D converter.

FEATURES

●Minimum instruction execution time .................................. 0.5 µs
(at 8 MHz oscillation frequency)
●Memory size
ROM ................................................................... 8K to 24K bytes
RAM.....................................................................512 to 640 byte
●Programmable input/output ports ............................................ 34
●Interrupts ................................................. 14 sources, 14 vectors
●Timers ............................................................................. 8-bit ✕ 4
●Serial I/O ....................... 8-bit ✕ 1(UART or Clock-synchronized)
●PWM ............................................................................... 8-bit ✕ 1
●A-D converter ............................................... 10-bit ✕ 5 channels
●Watchdog timer ............................................................ 16-bit ✕ 1
●Clock generating circuit..................................... Built-in 2 circuits
(connect to external ceramic resonator or quartz-crystal oscillator)
●Power source voltage
In high-speed mode .................................................. 4.0 to 5.5 V
(at 8 MHz oscillation frequency)
In high-speed mode .................................................. 2.7 to 5.5 V
(at 4 MHz oscillation frequency)
In middle-speed mode............................................... 2.7 to 5.5 V
(at 8 MHz oscillation frequency)
In low-speed mode.................................................... 2.7 to 5.5 V
(at 32 kHz oscillation frequency)
●Power dissipation
In high-speed mode .......................................................... 34 mW
(at 8 MHz oscillation frequency, at 5 V power source voltage)
In low-speed mode............................................................ 60 µW
(at 32 kHz oscillation frequency, at 3 V power source voltage)
●Operating temperature range.................................... –20 to 85°C

APPLICATION

Office automation equipment, FA equipment, Household products, Consumer electronics, etc.

PIN CONFIGURATION (TOP VIEW)

V
CC
REF
V
SS
AV
P44/INT3/PWM
P43/INT
2
P42/INT
1
P41/INT
0
P40/CNTR
7
/CNTR0/S
P2
P26/S
P20/X
Package type : FP ........................... 42P2R-A (42-pin plastic-molded SSOP)
Package type : SP ........................... 42P4B (42-pin shrink plastic-molded DIP)
RDY
CLK
P25/TxD
4
/RxD
P2
P2 P2
CNV
P21/X
CIN
COUT
RESET
X
X
OUT
V
1
3 2
SS
IN
SS
P30/AN
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21
M38503M4-XXXSP
M38503M4-XXXFP
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
0
P31/AN
1
P32/AN
2
P33/AN
3
P34/AN
4
P0
0
P0
1
P0
2
P0
3
P0
4
P0
5
P0
6
P0
7
P1
0
P1
1
P1
2
P13/(LED0)
4
/(LED1)
P1
5
/(LED2)
P1 P16/(LED3) P1
7
/(LED4)
Fig. 1 M38503M4-XXXFP/SP pin configuration
Page 2

FUNCTIONAL BLOCK

INT
0
–
CNTR
0
CNTR
1
V
REF
AV
SS
R A M
R O M
C P U
A
X
Y
S
PC
H
PCLPS
V
SS
21
RESET
18
V
CC
1 15
CNV
SS
23
X
IN
19
20
SI/O(8)
Reset input
Clock generating circuit
Main-clock
input
Main-clock
output
A-D
converter
(10)
Timer Y( 8 )
Timer X( 8 )
Prescaler 12(8)
Prescaler X(8)
Prescaler Y(8)
Timer 1( 8 )
Timer 2( 8 )
Sub-clock
input
X
OUT
X
CIN
X
COUT
Sub-clock
output
Watchdog
timer
Reset
P2(8)
P3(5)
I/O port P2
I/O port P3
P4(5)
I/O port P4
INT
3
4
68 5
7
39
4138 40
42
9
11
13
17
10
12
14
16
P1(8)
I/O port P1
22 24 26 2823 25 27 29
P0(8)
I/O port P0
30 3132 3334 35 36
37
PWM
(8)
X
CIN
X
COUT
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL BLOCK DIAGRAM
Fig. 2 Functional block diagram
2
Page 3

PIN DESCRIPTION

Table 1 Pin description
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
VCC, VSS
RESET
IN
X
XOUT
P00–P07
P10–P17
P20/XCOUT P21/XCIN P22 P23 P24/RxD P25/TxD P26/SCLK
P27/CNTR0/ SRDY
P30/AN0– P34/AN4
P4
0/CNTR1
P41/INT0– P43/INT2
P44/INT3/PWM
NamePin
Power source
SS inputCNVSS
CNV Reset input Clock input
Clock output
I/O port P0
I/O port P1
I/O port P2
I/O port P3
I/O port P4
Functions
•Apply voltage of 2.7 V – 5.5 V to Vcc, and 0 V to Vss.
•This pin controls the operation mode of the chip.
•Normally connected to V
•Reset input pin for active “L.”
•Input and output pins for the clock generating circuit.
•Connect a ceramic resonator or quartz-crystal oscillator between the X the oscillation frequency.
•When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
•8-bit CMOS I/O port.
•I/O direction register allows each pin to be individually programmed as either input or output.
•CMOS compatible input level.
•CMOS 3-state output structure.
•P1
3 to P17 (5 bits) are enabled to output large current for LED drive.
•8-bit CMOS I/O port.
•I/O direction register allows each pin to be individually programmed as either input or output.
•CMOS compatible input level.
•P20, P21, P24 to P27 : CMOS3-state output structure.
•P22, P23: N-channel open-drain structure.
•8-bit CMOS I/O port with the same function as port P0.
•CMOS compatible input level.
•CMOS 3-state output structure.
•8-bit CMOS I/O port with the same function as port P0.
•CMOS compatible input level.
•CMOS 3-state output structure.
SS.
Function except a port function
IN and XOUT pins to set
• Sub-clock generating circuit I/O pins (connect a resonator)
• Serial I/O function pin
• Serial I/O function pin/ Timer X function pin
• A-D converter input pin
• Timer Y function pin
• Interrupt input pins
• Interrupt input pin
• PWM output pin
3
Page 4

PART NUMBERING

MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Product
M3850 3 M 4 XXX FP
Package type
: 42P2R-A package
FP SP
: 42P4B package
SS
: 42S1B-A package
ROM number
Omitted in some types.
ROM/PROM size
: 4096 bytes
1
: 8192 bytes
2
: 12288 bytes
3
: 16384 bytes
4
: 20480 bytes
5
: 24576 bytes
6
: 28672 bytes
7
: 32768 bytes
8
: 36864 bytes
9 A
: 40960 bytes
B
: 45056 bytes
C
: 49152 bytes
D
: 53248 bytes
E
: 57344 bytes : 61440 bytes
F
Fig. 3 Part numbering
The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used.
Memory type
ME : Mask ROM version
: EPROM or One Time PROM version
RAM size
: 192 bytes
0
: 256 bytes
1
: 384 bytes
2
: 512 bytes
3
: 640 bytes
4
: 768 bytes
5
: 896 bytes
6
: 1024 bytes
7
: 1536 bytes
8
: 2048 bytes
9
4
Page 5
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

GROUP EXPANSION

Mitsubishi plans to expand the 3850 group as follows:

Memory T ype

Support for mask ROM, One Time PROM, and EPROM versions.

Memory Size

ROM/PROM size................................................... 8K to 24K bytes
RAM size .............................................................. 512 to 640 bytes

Memory Expansion Plan

ROM size (bytes)
48K
32K
28K
24K
20K
16K
12K
8K
Mass production
M38503M4/E4
Mass production
M38503M2

Packages

42P4B..........................................42-pin shrink plastic molded DIP
42P2R-A ............................................ 42-pin plastic molded SSOP
42S1B-A ................... 42-pin shrink ceramic DIP(EPROM version)
Under development
M38504M6/E6
128 192 256
Products under development or planning : the development schedule and specification may be revised without notice. Planning products may be stopped the development.
Fig. 4 Memory expansion plan
Currently planning products are listed below.
Table 2 Support products
Product name
M38503M2-XXXSP M38503M2-XXXFP
(P) ROM size (bytes) ROM size for User in ( )
8192
(8062)
M38503M4-XXXSP M38503E4-XXXSP M38503E4SP M38503E4SS
16384
(16254)
M38503M4-XXXFP M38503E4-XXXFP M38503E4FP M38504M6-XXXSP M38504E6-XXXSP M38504E6SP M38504E6SS
32768
(32638)
M38504M6-XXXFP M38504E6-XXXFP M38504E6FP
384 512 640 768 896 1024
RAM size (bytes)
RAM size (bytes)
512
Package
42P4B
42P2R-A
Remarks
Mask ROM version Mask ROM version
Mask ROM version
42P4B
One Time PROM version One Time PROM version (blank)
512
42S1B-A
EPROM version (stock only replaced by M38504E6SS) Mask ROM version
42P2R-A
One Time PROM version One Time PROM version (blank) Mask ROM version
42P4B
One Time PROM version One Time PROM version (blank)
640
42S1B-A
EPROM version Mask ROM version
42P2R-A
One Time PROM version One Time PROM version (blank)
As of August 1998
5
Page 6
FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU)
The 3850 group uses the standard 740 Family instruction set. Re­fer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used. The STP, WIT, MUL, and DIV instructions can be used.
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit, etc. The CPU mode register is allocated at address 003B
16.
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
CPU mode register
(
CPUM : address
003B16)
Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : 1 0 : Not available 1 1 :
Stack page selection bit 0 : 0 page 1 : 1 page
Not used (return “1” when read)
(Do not write “0” to this bit.)
C
switch bit
Port X
0 : I/O port function (stop oscillating)
CIN–XCOUT
1 : X
Main clock (X
0 : Oscillating 1 : Stopped
Main clock division ratio selection bits b7 b6 0 0 : φ = f(X 0 1 : φ = f(X 1 0 : φ = f(X 1 1 : Not available
IN–XOUT
oscillating function
) stop bit
IN
)/2 (high-speed mode)
IN
)/8 (middle-speed mode)
CIN
)/2 (low-speed mode)
Fig. 5 Structure of CPU mode register
6
Page 7
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MEMORY Special Function Register (SFR) Area
The Special Function Register area in the zero page contains con­trol registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine calls and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reser ved for device testing and the rest is user area for storing programs.

Interrupt Vector Area

The interrupt vector area contains reset and interrupt vectors.
RAM area
RAM size
(bytes)
192 256 384 512 640 768
896 1024 1536 2048 3072 4032
Address XXXX
00FF 013F 01BF 023F 02BF 033F 03BF 043F 063F 083F 0C3F 0FFF
16
16
16
16
16
16
16
16 16 16 16
16
16

Zero Page

Access to this area with only 2 bytes is possible in the zero page addressing mode.

Special Page

Access to this area with only 2 bytes is possible in the special page addressing mode.
0000
RAM
0040
0100
XXXX
0440
16
16
16
16
16
SFR area
Zero page
Reserved area
Not used
ROM area
ROM size
(bytes)
4096
8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440
Fig. 6 Memory map diagram
Address
YYYY
F000 E000 D000 C000 B000 A000 9000 8000 7000 6000 5000 4000 3000 2000 1000
YYYY
16
Reserved ROM area
Address
16
16
16 16 16 16
16 16 16 16 16 16 16 16 16 16
ZZZZ
F080 E080 D080 C080 B080 A080 9080 8080 7080 6080 5080 4080 3080 2080 1080
16 16
16 16 16 16
16 16 16 16 16 16 16 16 16 16
ROM
ZZZZ
FF00
FFDC
FFFE FFFF
16
16
16
16 16
(128 bytes)
Interrupt vector area
Reserved ROM area
Special page
7
Page 8
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F 0010 0011 0012 0013 0014 0015 0016 0017 0018 0019 001A 001B 001C 001D 001E 001F
Port P0 (P0)
16
Port P0 direction register (P0D)
16
Port P1 (P1)
16
Port P1 direction register (P1D)
16
Port P2 (P2)
16
Port P2 direction register (P2D)
16
Port P3 (P3)
16
Port P3 direction register (P3D)
16
Port P4 (P4)
16
Port P4 direction register (P4D)
16 16 16
16
16 16 16 16 16 16 16 16 16
Reserved ✽
16
Reserved ✽
16
Reserved ✽
Transmit/Receive buffer register (TB/RB)
16
Serial I/O status register (SIOSTS)
16
Serial I/O control register (SIOCON)
16
UART control register (UARTCON)
16
Baud rate generator (BRG)
16
PWM control register (PWMCON)
16
PWM prescaler (PREPWM)
16
PWM register (PWM)
16
✽ Reserved : Do not write “1” to this address.
0020 0021 0022 0023 0024 0025 0026 0027 0028 0029 002A 002B 002C 002D 002E 002F 0030 0031 0032 0033 0034 0035 0036 0037 0038 0039 003A 003B 003C 003D 003E 003F
Prescaler 12 (PRE12)
16
Timer 1 (T1)
16
Timer 2 (T2)
16
Timer XY mode register (TM)
16
Prescaler X (PREX)
16
Timer X (TX)
16
Prescaler Y (PREY)
16
Timer Y (TY)
16
Timer count source selection register (TCSS)
16 16
16 16
Reserved ✽ Reserved ✽
16 16
Reserved ✽
16
Reserved ✽
16
Reserved ✽
16
Reserved ✽
16 16 16
A-D control register (ADCON)
16
A-D conversion low-order register (ADL)
16
A-D conversion high-order register (ADH)
16 16
MISRG
16
Watchdog timer control register (WDTCON)
16
Interrupt edge selection register (INTEDGE)
16
CPU mode register (CPUM)
16
Interrupt request register 1 (IREQ1)
16
Interrupt request register 2 (IREQ2)
16
Interrupt control register 1 (ICON1)
16
Interrupt control register 2 (ICON2)
16
Fig. 7 Memory map of special function register (SFR)
8
Page 9

I/O PORTS

The I/O ports have direction registers which determine the input/ output direction of each individual pin. Each bit in a direction reg­ister corresponds to one pin, and each pin can be set to be input port or output port. When “0” is written to the bit corresponding to a pin, that pin be­comes an input pin. When “1” is written to that bit, that pin becomes an output pin. If data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating.
Table 3 I/O port function
Pin
P00–P07 P10–P17 P20/XCOUT
P21/XCIN
P22 P23
Name
Port P0 Port P1
Input/Output
I/O Structure Non-Port Function
CMOS compatible input level CMOS 3-state output Sub-clock generating
CMOS compatible input level N-channel open-drain output
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Related SFRs
circuit
CPU mode register
Ref.No .
(1)
(2) (3)
(4)
P24/RxD P25/TxD
6/SCLK
P2
P27/CNTR0/SRDY
P30/AN0– P34/AN4
P40/CNTR1 P41/INT0–
P43/INT2
P44/INT3/PWM
Port P2
Port P3
Port P4
Input/output, individual bits
CMOS compatible input level CMOS 3-state output
Serial I/O function I/O
Serial I/O function I/O
Serial I/O function I/O Timer X function I/O
A-D conversion input
Timer Y function I/O
External interrupt input
External interrupt input PWM output
Serial I/O control register
Serial I/O control register
Serial I/O control register Timer XY mode register
A-D control register
Timer XY mode register Interrupt edge selection
register Interrupt edge selection
register PWM control register
(5) (6)
(7)
(8)
(9)
(10) (11)
(12)
9
Page 10
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Port P0, P1
Data bus
(3) Port P2
Data bus
1
Port XC switch bit
(5) Port P2
Serial I/O enable bit
Receive enable bit
Data bus
Direction register
Port latch
Direction register
Port latch
Sub-clock generating circuit input
4
Direction register
Port latch
(2) Port P2
Data bus
(4) Port P2
Data bus
(6) Port P2
0
Port XC switch bit
Direction register
Port latch
2, P23
Port latch
5
P-channel output disable bit
Serial I/O enable bit
Transmit enable bit
Direction register
Direction register
Port P2
Port X
Oscillator
1
C
switch bit
(7) Port P2
Serial I/O clock
Serial I/O enable bit Serial I/O mode selection bit
Data bus
6
selection bit
Serial I/O enable bit
Direction register
Port latch
Serial clock output
Fig. 8 Port block diagram (1)
Serial I/O input
External clock input
Data bus
(8) Port P2
Serial I/O mode selection bit
7
Serial I/O enable bit
RDY
output enable bit
S
Data bus
Serial ready output
Port latch
Serial I/O output
Pulse output mode
Pulse output mode
Direction register
Port latch
Timer output
CNTR
0
interrupt
input
10
Page 11
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(9) Port P30–P3
Data bus
(11) Port P41–P4
Data bus
4
Direction register
Port latch
A-D converter input
3 Direction
register
Port latch
Fig. 9 Port block diagram (2)
Analog input pin selection bit
Interrupt input
(10) Port P4
(12) Port P4
Data bus Port latch
0
Data bus
4
PWM output enable bit
Direction register
PWM output
Direction register
Port latch
Pulse output mode
Timer output
CNTR1 interrupt input
11
Page 12
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

INTERRUPTS

Interrupts occur by 14 sources among 14 sources: six external, seven internal, and one software.

Interrupt Control

Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software in­terrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are “1” and the in­terrupt disable flag is “0”. Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction cannot be disabled with any flag or bit. The I (interrupt disable) flag disables all interrupts except the BRK in­struction interrupt. When several interrupts occur at the same time, the interrupts are received according to priority.

Interrupt Operation

By acceptance of an interrupt, the following operations are auto­matically performed:
1. The contents of the program counter and the processor status register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt request bit is cleared.
3. The interrupt jump destination address is read from the vector table into the program counter.

■Notes

When the active edge of an external interrupt (INT0–INT3, CNTR0, CNTR
1) is set, the corresponding interrupt request bit may also be
set. Therefore, take the following sequence:
1. Disable the interrupt
2. Change the interrupt edge selection register (the timer XY mode register for CNTR
3. Clear the interrupt request bit to “0”
4. Accept the interrupt.
0 and CNTR1)
12
Page 13
Table 4 Interrupt vector addresses and priority
Interrupt Source Reset (Note 2)
INT0
Reserved
INT1
INT2
INT3
Reserved Timer X Timer Y Timer 1 Timer 2
Serial I/O reception
Serial I/O Transmission
CNTR
0
CNTR1
A-D converter BRK instruction
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
Priority
1 2
3 4
5
6 7
8 9
10 11
12
13
14
15 16
17 Non-maskable software interrupt
Vector Addresses (Note 1)
High
FFFD16
FFFB16 FFF916 FFF716
FFF516
FFF316 FFF116
FFEF16
FFED16
FFEB16 FFE916
FFE716
FFE516
FFE316
FFE116 FFDF16
FFDD16
Low
FFFC FFFA
FFF816 FFF616
FFF416
FFF216 FFF016
FFEE16 FFEC16 FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016 FFDE16
FFDC16
16
16
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupt Request
Generating Conditions
At reset
At detection of either rising or falling edge of INT
Reserved At detection of either rising or
falling edge of INT
At detection of either rising or falling edge of INT2 input
At detection of either rising or falling edge of INT
Reserved
At timer X underflow At timer Y underflow At timer 1 underflow At timer 2 underflow At completion of serial I/O data
reception At completion of serial I/O trans-
fer shift or when transmission buffer is empty
At detection of either rising or falling edge of CNTR
At detection of either rising or falling edge of CNTR1 input
At completion of A-D conversion At BRK instruction execution
0 input
1 input
3 input
0 input
3850 Group
Remarks
Non-maskable External interrupt
(active edge selectable)
External interrupt (active edge selectable)
External interrupt (active edge selectable)
External interrupt (active edge selectable)
STP release timer underflow
Valid when serial I/O is selected
Valid when serial I/O is selected
External interrupt (active edge selectable)
External interrupt (active edge selectable)
13
Page 14
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 10 Interrupt control
b7 b0
b7 b0
Interrupt edge selection register (INTEDGE : address 003A
16
)
INT0 active edge selection bit INT
1
active edge selection bit
INT
2
active edge selection bit
INT
3
active edge selection bit Reserved(Do not write “1” to this bit) Not used (returns “0” when read)
Interrupt request register 1 (IREQ1 : address 003C
16
)
INT0 interrupt request bit Reserved INT
1
interrupt request bit
INT
2
interrupt request bit
3
interrupt request bit
INT Reserved Timer X interrupt request bit Timer Y interrupt request bit
0 : No interrupt request issued 1 : Interrupt request issued
BRK instruction
Reset
0 : Falling edge active 1 : Rising edge active
b7 b0
Interrupt request
Interrupt request register 2 (IREQ2 : address 003D
Timer 1 interrupt request bit Timer 2 interrupt request bit Serial I/O reception interrupt request bit Serial I/O transmit interrupt request bit CNTR
0
interrupt request bit
CNTR
1
interrupt request bit AD converter interrupt request bit Not used (returns “0” when read)
0 : No interrupt request issued 1 : Interrupt request issued
16
)
b7 b0
Interrupt control register 1
(ICON1 : address 003E
INT0 interrupt enable bit Reserved(Do not write "1" to this bit)
1
interrupt enable bit
INT INT
2
interrupt enable bit
INT
3
interrupt enable bit Reserved(Do not write "1" to this bit) Timer X interrupt enable bit Timer Y interrupt enable bit
0 : Interrupts disabled 1 : Interrupts enabled
Fig. 11 Structure of interrupt-related registers (1)
14
b7 b0
16
)
Interrupt control register 2 (ICON2 : address 003F
16
)
Timer 1 interrupt enable bit Timer 2 interrupt enable bit Serial I/O reception interrupt enable bit Serial I/O transmit interrupt enable bit CNTR
0
interrupt enable bit
CNTR
1
interrupt enable bit AD converter interrupt enable bit Not used (returns “0” when read) (Do not write “1” to this bit)
0 : Interrupts disabled 1 : Interrupts enabled
Page 15
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

TIMERS

The 3850 group has four timers: timer X, timer Y, timer 1, and timer 2. The division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. All timers are count down. When the timer reaches “00 derflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to “1”.
b7
b0
Timer XY mode register (TM : address 0023
Timer X operating mode bit
b1b0
0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode
CNTR0 active edge selection bit
0: Interrupt at falling edge
Count at rising edge in event counter mode
1: Interrupt at rising edge
Count at falling edge in event counter mode
Timer X count stop bit
0: Count start 1: Count stop
Timer Y operating mode bit
b5b4
0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode
1 active edge selection bit
CNTR
0: Interrupt at falling edge
Count at rising edge in event counter mode
1: Interrupt at rising edge
Count at falling edge in event counter mode
Timer Y count stop bit
0: Count start 1: Count stop
Fig. 12 Structure of timer XY mode register
16”, an un-
16)

Timer 1 and Timer 2

The count source of prescaler 12 is the oscillation frequency which is selected by timer 12 count source selection bit. The out­put of prescaler 12 is counted by timer 1 and timer 2, and a timer underflow sets the interrupt request bit.

Timer X and Timer Y

Timer X and Timer Y can each select in one of four operating modes by setting the timer XY mode register.

(1) Timer Mode

The timer counts the count source selected by Timer count source selection bit.

(2) Pulse Output Mode

The timer counts the count source selected by Timer count source selection bit. Whenever the contents of the timer reach “00 signal output from the CNTR CNTR
0 (or CNTR1) active edge selection bit is “0”, output begins
0 (or CNTR1) pin is inverted. If the
16”, the
at “ H”. If it is “1”, output starts at “L”. When using a timer in this mode, set the corresponding port P2
7 ( or port P40) direction register to out-
put mode.

(3) Event Counter Mode

Operation in event counter mode is the same as in timer mode, ex­cept that the timer counts signals input through the CNTR CNTR
1 pin.
When the CNTR rising edge of the CNTR When the CNTR falling edge of the CNTR
0 (or CNTR1) active edge selection bit is “0”, the
0 (or CNTR1) pin is counted.
0 (or CNTR1) active edge selection bit is “1”, the
0 (or CNTR1) pin is counted.
0 or

(4) Pulse Width Measurement Mode

If the CNTR0 (or CNTR1) active edge selection bit is “0”, the timer counts the selected signals by the count source selection bit while the CNTR tive edge selection bit is “1”, the timer counts it while the CNTR (or CNTR1) pin is at “L”.
0 (or CNTR1) pin is at “H”. If the CNTR0 (or CNTR1) ac-
0
b7
b0
Timer count source selection register (TCSS : address 0028
Timer X count source selection bit
IN
)/16 (f(X
CIN
)/16 (f(X
)/16 (f(X
)
CIN
CIN
CIN
CIN
)/16 at low-speed mode)
)/2 at low-speed mode)
)/16 at low-speed mode)
)/2 at low-speed mode)
)/16 at low-speed mode)
0 : f(X 1 : f(XIN)/2 (f(X
Timer Y count source selection bit 0 : f(X
IN
1 : f(XIN)/2 (f(X Timer 12 count source selection bit
0 : f(X
IN
1 : f(X
CIN
Not used (returns “0” when read)
16
)
Fig. 13 Structure of timer count source selection register
The count can be stopped by setting “1” to the timer X (or timer Y) count stop bit in any mode. The corresponding interrupt request bit is set each time a timer underflows.

■Note

When switching the count source by the timer 12, X and Y count source bit, the value of timer count is altered in unconsiderable amount owing to generating of a thin pulses in the count input signals. Therefore, select the timer count source before set the value to the prescaler and the timer.
15
Page 16
Data bus
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
f(XIN)/16
f(XIN)/2
Timer X count source selection bit
7/CNTR0
P2
7
Port P2
direction register
f(XIN)/16
f(XIN)/2
Timer Y count source selection bit
P40/CNTR1
Port P4
direction register
CNTR edge selection
“0”
“1”
Port P2 latch
Pulse output mode
CNTR edge selection
“0”
“1”
Port P4
0
Pulse output mode
latch
0 active
bit
7
1 active
bit
0
Pulse width measurement mode
Event counter mode
CNTR edge selection bit
Pulse width measure­ment mode
Event counter mode
CNTR1 active edge selection bit
Timer mode Pulse output mode
Timer X count stop bit
0 active
“1”
“0”
Timer mode Pulse output mode
Timer Y count stop bit
“1”
“0”
Data bus
Prescaler X latch (8)
Prescaler X (8)
Q
Toggle flip-flop
Q
R
Data bus
Prescaler Y latch (8)
Prescaler Y (8)
Q
Toggle flip-flop
Q
R
Timer X latch (8)
Timer X (8)
T
Timer X latch write pulse Pulse output mode
Timer Y latch (8)
Timer Y (8)
T
Timer Y latch write pulse Pulse output mode
To timer X interrupt request bit
To CNTR
0 interrupt
request bit
To timer Y interrupt request bit
To CNTR
1 interrupt
request bit
Prescaler 12 latch (8)
f(XIN)/16
f(XCIN)
Timer 12 count source selection bit
Prescaler 12 (8)
Fig. 14 Block diagram of timer X, timer Y, timer 1, and timer 2
16
Timer 1 latch (8)
Timer 1 (8)
Timer 2 latch (8)
Timer 2 (8)
To timer 2 interrupt request bit
To timer 1 interrupt request bit
Page 17
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

SERIAL I/O

Serial I/O can be used as either clock synchronous or asynchro­nous (UART) serial I/O. A dedicated timer is also provided for baud rate generation.
Data bus
Address 0018
Transmit shift register
Transmit buffer register
Data bus
P24/RXD
P26/SCLK
P2
7/SRDY
P2
5/TXD
XIN
Receive buffer register
Receive shift register
BRG count source selection bit
1/4
F/F
Falling-edge detector

(1) Clock Synchronous Serial I/O Mode

Clock synchronous serial I/O mode can be selected by setting the serial I/O mode selection bit of the serial I/O control register (bit 6 of address 001A For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB.
16
Shift clock
Serial I/O synchronous clock selection bit Frequency division ratio 1/(n+1)
Baud rate generator
Address 001C
Shift clock
Address 0018
Clock control circuit
16
Clock control circuit
16
16) to “1”.
Serial I/O control register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
1/4
Transmit interrupt source selection bit
Serial I/O status register
Address 001A16
Transmit shift completion flag (TSC)
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Address 0019
16
Fig. 15 Block diagram of clock synchronous serial I/O
Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock)
Serial output TxD
Serial input RxD
Receive enable signal S
RDY
D
0
D
0
Write pulse to receive/transmit buffer register (address 0018
16
)
TBE = 0
TBE = 1 TSC = 0
1: As the transmit interrupt (TI), either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has
Notes
ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data
is output continuously from the TxD pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 16 Operation of clock synchronous serial I/O function
D
D
1
D
2
D
1
D
2
D
3
D
3
D
4
D
4
D
5
D
5
D
6
D
6
7
D
7
RBF = 1 TSC = 1
Overrun error (OE) detection
17
Page 18
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(2) Asynchronous Serial I/O (UART) Mode

Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O mode selection bit (b6) of the serial I/O con­trol register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the
Data bus
Address 001816
Receive buffer register
Receive shift register
PE FE
SP detector
Frequency division ratio 1/(n+1)
Baud rate generator
Address 001C
ST/SP/PA generator
Transmit shift register
Transmit buffer register
Data bus
P2
P2
P2
4/RXD
6/SCLK1
XIN
5/TXD
OE
Character length selection bit
ST detector
BRG count source selection bit
1/4
7 bits 8 bits
Serial I/O synchronous clock selection bit
Character length selection bit
two buffers have the same address in memory. Since the shift reg­ister cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received.
Serial I/O control register
Receive buffer full flag (RBF) Receive interrupt request (RI)
Clock control circuit
16
1/16
Transmit interrupt source selection bit
Address
001816
Serial I/O status register
Address 001A
1/16
16
UART control register
Address 001B
Transmit shift completion flag (TSC)
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Address
16
001916
Fig.17 Block diagram of UART serial I/O
18
Page 19
Transmit or receive clock
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Transmit buffer write
Receive buffer read
signal
TBE=0 TBE=0
TSC=0 TBE=1
Serial output TXD
signal
Serial input R
Notes
X
D
1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1.” 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
ST
0
D
1
1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s)
ST
0
D
1
Fig. 18 Operation of UART serial I/O function
[Transmit Buffer Register/Receive Buffer Register (TB/RB)] 0018
16
[Serial I/O Status Register (SIOSTS)] 001916
The read-only serial I/O status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg­ister, and the receive buffer full flag is set. A write to the ser ial I/O status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O enable bit SIOE (bit 7 of the serial I/O control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O status register are initialized to “0” at re­set, but if the transmit enable bit (bit 4) of the serial I/O control register has been set to “1”, the transmit shift completion flag (bit
2) and the transmit buffer empty flag (bit 0) become “1”.
TBE=1
STD
SP
RBF=1
STD
SP D
D
0
D
1
Generated at 2nd bit in 2-stop-bit mode
RBF=0
0
D
1
TSC=1
SP
RBF=1
SP
Serial I/O Control Register (SIOCON)] 001A16
The serial I/O control register consists of eight control bits for the serial I/O function.
[UART Control Register (UARTCON)] 001B16
The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer and one bit (bit 4) which is al­ways valid and sets the output structure of the P2
5/TXD pin.
[Baud Rate Generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial trans­fer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate genera­tor.
19
Page 20
MITSUBISHI MICROCOMPUTERS
b7
b7
Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty
Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full
Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed
Overrun error flag (OE) 0: No error 1: Overrun error
Parity error flag (PE) 0: No error 1: Parity error
Framing error flag (FE) 0: No error 1: Framing error
Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1
Not used (returns “1” when read)
Serial I/O status register
Serial I/O control register
b0
b0
BRG count source selection bit (CSS) 0: f(X
IN
)
1: f(X
IN
)/4
Serial I/O synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected, external clock input divided by 16 when UART is selected.
S
RDY
output enable bit (SRDY)
0: P2
7
pin operates as ordinary I/O pin
1: P2
7
pin operates as S
RDY
output pin
Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed
Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled
Receive enable bit (RE) 0: Receive disabled 1: Receive enabled
Serial I/O mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O
Serial I/O enable bit (SIOE) 0: Serial I/O disabled (pins P2
4
to P27 operate as ordinary I/O pins) 1: Serial I/O enabled (pins P2
4
to P27 operate as serial I/O pins)
b7
UART control register
Character length selection bit (CHAS) 0: 8 bits 1: 7 bits
Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled
Parity selection bit (PARS) 0: Even parity 1: Odd parity
Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits
P2
5/TX
D P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode)
Not used (return “1” when read)
b0
(SIOSTS : address 001916)
(SIOCON : address 001A
16
)
(UARTCON : address 001B
16
)
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 19 Structure of serial I/O control registers
20
Page 21
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

PULSE WIDTH MODULATION (PWM)

The 3850 group has a PWM function with an 8-bit resolution, based on a signal that is the clock input X vided by 2.
IN or that clock input di-

Data Setting

The PWM output pin also functions as port P44. Set the PWM pe­riod by the PWM prescaler, and set the “H” term of output pulse by the PWM register. If the value in the PWM prescaler is n and the value in the PWM register is m (where n = 0 to 255 and m = 0 to 255) : PWM period = 255 ✕ (n+1) / f(X
= 31.875 ✕ (n+1) µs (when f(X
Output pulse “H” term = PWM period ✕ m / 255
= 0.125 ✕ (n+1) ✕ m µs
(when f(X
IN) = 8 MHz)
IN)
IN) = 8 MHz)

PWM Operation

When bit 0 (PWM enable bit) of the PWM control register is set to “1”, operation starts by initializing the PWM output circuit, and pulses are output starting at an “H”. If the PWM register or PWM prescaler is updated during PWM output, the pulses will change in the cycle after the one in which the change was made.
31.875 ✕ m ✕ (n+1) 255
PWM output
T = [31.875 ✕ (n+1)] µs
m: Contents of PWM register n : Contents of PWM prescaler T : PWM period (when f(X
Fig. 20 Timing of PWM period
µs
IN) = 8 MHz)
Data bus
prescaler pre-latch
prescaler latch
Count source selection bit
1/2
“0”
PWM prescaler
“1”
XIN
Fig. 21 Block diagram of PWM function
PWM
Transfer control circuit
PWM
PWM
register pre-latch
PWM
register latch
PWM register
Port P44 latch
PWM enable bit
Port P4
4
21
Page 22
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
Fig. 22 Structure of PWM control register
b0
PWM control register (PWMCON : address 001D
PWM function enable bit
0: PWM disabled 1: PWM enabled
Count source selection bit
IN)
0: f(X
IN)/2
1: f(X
Not used (return “0” when read)
ABC
PWM output
PWM register write signal
16)
T
T
(Changes “H” term from “A” to “B”.)
T2
C
B
=
T2
T
PWM prescaler write signal
(Changes PWM period from “T” to “T2”.)
When the contents of the PWM register or PWM prescaler have changed, the PWM output will change from the next period after the change.
Fig. 23 PWM output timing when PWM register or PWM prescaler is changed

■Note

The PWM starts after the PWM enable bit is set to enable and "L" level is output from the PWM pin. The length of this "L" level output is as follows:
n+1
2 • f(X
n+1
f(X
sec (Count source selection bit = 0, where n is the value set in the prescaler)
IN)
sec (Count source selection bit = 1, where n is the value set in the prescaler)
IN)
22
Page 23
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D CONVERTER [A-D Conversion Registers (ADL, ADH)] 0035
16, 003616
The A-D conversion registers are read-only registers that store the result of an A-D conversion. Do not read these registers during an A-D conversion
[AD Control Register (ADCON)] 003416
The AD control register controls the A-D conversion process. Bits 0 to 2 select a specific analog input pin. Bit 4 indicates the completion of an A-D conversion. The value of this bit remains at “0” during an A-D conversion and changes to “1” when an A-D conversion ends. Writing “0” to this bit starts the A-D conversion.

Comparison V oltage Generator

The comparison voltage generator divides the voltage between AV
SS and VREF into 1024 and outputs the divided voltages.

Channel Selector

The channel selector selects one of ports P30/AN0 to P34/AN4 and inputs the voltage to the comparator.

Comparator and Control Circuit

The comparator and control circuit compare an analog input volt­age with the comparison voltage, and the result is stored in the A-D conversion registers. When an A-D conversion is completed, the control circuit sets the A-D conversion completion bit and the A-D interrupt request bit to “1”. Note that because the comparator consists of a capacitor cou­pling, set f(X
IN) to 500 kHz or more during an A-D conversion.
b7
Fig. 24 Structure of AD control register
b0
AD control register (ADCON : address 0034
Analog input pin selection bits
b2 b1 b0
0 0 0: P3 0 0 1: P31/AN1 0 1 0: P32/AN2 0 1 1: P33/AN3
1 0 0: P34/AN4 Not used (returns “0” when read) A-D conversion completion bit
0: Conversion in progress
1: Conversion completed
Not used (returns “0” when read)
0/AN0
10-bit reading
16
(Read address 0036
before 003516)
b7 b0
16
(Address 0036
)
b7
16
(Address 0035
Note : The high-order 6 bits of address 003616 become “0”
at reading.
)
b7 b6 b5 b4 b3 b2 b1 b0
8-bit reading (Read only address 0035
b7
16
(Address 0035
)
b9 b8 b7 b6 b5 b4 b3 b2
b9
16
16)
b8 b0
)
b0
AD control register
(Address 0034
P30/AN P31/AN P32/AN P33/AN P34/AN
Fig. 26 Block diagram of A-D converter
16
0 1 2 3 4
b7 b0
)
3
Comparator
Channel selector
Fig. 25 Structure of A-D conversion registers
Data bus
A-D control circuit
A-D conversion high-order register
A-D conversion low-order register
10
Resistor ladder
REF
AV
V
SS
A-D interrupt request
(Address 0036 (Address 0035
16
)
16
)
23
Page 24
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

WA TCHDOG TIMER

The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, be­cause of a software run-away). The watchdog timer consists of an 8-bit watchdog timer L and an 8-bit watchdog timer H.

Standard Operation of Watchdog Timer

When any data is not written into the watchdog timer control reg­ister (address 0039 stop state. The watchdog timer starts to count down by writing an optional value into the watchdog timer control register (address 0039
16) and an internal reset occurs at an underflow of the watch-
dog timer H. Accordingly, programming is usually performed so that writing to the watchdog timer control register (address 0039 started before an underflow. When the watchdog timer control reg­ister (address 0039 of the watchdog timer H, STP instruction disable bit, and watch­dog timer H count source selection bit are read.
●Initial value of watchdog timer
At reset or writing to the watchdog timer control register (address 0039
16), each watchdog timer H and L is set to “FF16.”
16) after resetting, the watchdog timer is in the
16) may be
16) is read, the values of the high-order 6 bits
●Watchdog timer H count source selection bit operation
Bit 7 of the watchdog timer control register (address 0039
16) per-
mits selecting a watchdog timer H count source. When this bit is set to “0”, the count source becomes the underflow signal of watchdog timer L. The detection time is set to 131.072 ms at f(X = 8 MHz frequency and 32.768 s at f(X
CIN) = 32 kHz frequency.
IN)
When this bit is set to “1”, the count source becomes the signal divided by 16 for f(X is set to 512 µs at f(X
IN) (or f(XCIN)). The detection time in this case
IN) = 8 MHz frequency and 128 ms at f(XCIN)
= 32 kHz frequency. This bit is cleared to “0” after resetting.
●Operation of STP instruction disable bit
Bit 6 of the watchdog timer control register (address 0039
16) per-
mits disabling the STP instruction when the watchdog timer is in operation. When this bit is “0”, the STP instruction is enabled. When this bit is “1”, the STP instruction is disabled, once the STP instruction is executed, an internal reset occurs. When this bit is set to “1”, it cannot be rewritten to “0” by program. This bit is cleared to “0” after resetting.
“FF
16” is set when
XCIN
Main clock division ratio selection bits (Note)
XIN
STP instruction disable bit
RESET
Note: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
watchdog timer control register is written to.
“10”
1/16
“00” “01”
STP instruction
Fig. 27 Block diagram of Watchdog timer
b7
Watchdog timer L (8)
“0”
“1”
Watchdog timer H count source selection bit
b0
Watchdog timer control register (WDTCON : address 0039
Watchdog timer H (for read-out of high-order 6 bit) STP instruction disable bit
0: STP instruction enabled 1: STP instruction disabled
Watchdog timer H (8)
Reset circuit
Data bus
“FF16” is set when watchdog timer control register is written to.
Internal reset
16)
Fig. 28 Structure of Watchdog timer control register
24
Watchdog timer H count source selection bit 0: Watchdog timer L underflow
IN)/16 or f(XCIN)/16
1: f(X
Page 25

RESET CIRCUIT

To reset the microcomputer, RESET pin must be held at an "L" level for 2 µs or more. Then the RESET pin is returned to an "H" level (the power source voltage must be between 2.7 V and 5.5 V, and the oscillation must be stable), reset is released. After the re­set is completed, the program starts from the address contained in address FFFD byte). Make sure that the reset input voltage is less than 0.54 V for V
CC of 2.7 V.
16 (high-order byte) and address FFFC16 (low-order
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Poweron
(Note)
0.2V
CC
RESET
V
CC
Power source voltage
0V
Reset input voltage
0V
Note : Reset release voltage ; Vcc=2.7 V
X
IN
φ
RESET
RESETOUT
RESET
V
CC
Fig. 29 Reset circuit example
Power source voltage detection circuit
Address
Data
SYNC
XIN: 8 to 13 clock cycles
Fig. 30 Reset sequence
AD
?
?
?
Notes
??
??
1: The frequency relation of f(XIN) and f(φ) is f(XIN) = 2 • f(φ). 2: The question marks (?) indicate an undefined state that depends on the previous state. 3: All signals except X
?
?
FFFC FFFD
?
IN and RESET are internals.
AD
L
H,L
Reset address from the vector table.
ADH
25
Page 26
(1)
Port P0 direction register (P0D)
(2)
Port P1 direction register (P1D)
(3)
Port P2 direction register (P2D)
(4)
Port P3 direction register (P3D)
(5)
Port P4 direction register (P4D)
(6)
Serial I/O status register (SIOSTS)
(7)
Serial I/O control register (SIOCON)
(8)
UART control register (UARTCON)
(9)
PWM control register (PWMCON)
(10)
Prescaler 12 (PRE12)
(11)
Timer 1 (T1)
(12)
Timer 2 (T2)
(13)
Timer XY mode register (TM)
(14)
Prescaler X (PREX)
(15)
Timer X (TX)
(16)
Prescaler Y (PREY)
(17)
Timer Y (TY)
(18)
Timer count source select register
(19)
Reserved
(20)
Reserved
(21)
Reserved
(22)
Reserved
(23)
Reserved
(24)
AD control register (ADCON)
(25)
MISRG
(26)
Watchdog timer control register (WDTCON)
(27)
Interrupt edge selection register (INTEDGE)
(28)
CPU mode register (CPUM)
(29)
Interrupt request register 1 (IREQ1)
(30)
Interrupt request register 2 (IREQ2)
(31)
Interrupt control register 1 (ICON1)
(32)
Interrupt control register 2 (ICON2)
(33)
Processor status register
(34)
Program counter
Note : X indicates Not fixed .
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Address Register contents
0001 000316 000516 000716 000916
001916 001A16 001B16 001D16
002016
002116
002216
002316
002416
002516
002616
002716
002816 002C16 002D16 002E16
002F16
003016
003416
003816
003916 003A16 003B16 003C16 003D16 003E16
003F16
(PS)
(PC
(PC
16
H) L)
0016 0016 0016 0016 0016
10000000
0016
11100000
0016 FF16 0116 0016 0016 FF16 FF16 FF16 FF16
0016 Not fixed Not fixed Not fixed Not fixed Not fixed
00010000
00
16
00111111
0016
010010 0
0
00
16
0016
0016
0016
1
XXXXXXX
FFFD16 contents
FFFC16 contents
Fig. 31 Internal status at reset
26
Page 27
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

CLOCK GENERATING CIRCUIT

The 3850 group has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between X X
OUT (XCIN and XCOUT). Use the circuit constants in accordance
with the resonator manufacturer’s recommended values. No exter­nal resistor is needed between X resistor exists on-chip. However, an external feed-back resistor is needed between X Immediately after power on, only the X oscillating, and X
CIN and XCOUT.
CIN and XCOUT pins function as I/O ports.
IN and XOUT since a feed-back
IN oscillation circuit starts
IN and
Frequency Control (1) Middle-speed mode
The internal clock φ is the frequency of XIN divided by 8. After re­set, this mode is selected.

(2) High-speed mode

The internal clock φ is half the frequency of XIN.

(3) Low-speed mode

The internal clock φ is half the frequency of XCIN.

■Note

If you switch the mode between middle/high-speed and low­speed, stabilize both X is required for the sub-clock to stabilize, especially immediately af­ter power on and at returning from the stop mode. When switching the mode between middle/high-speed and low-speed, set the fre­quency on condition that f(X
IN and XCIN oscillations. The sufficient time
IN) > 3•f(XCIN).

(4) Low power dissipation mode

The low power consumption operation can be realized by stopping the main clock X bit 5 of the CPU mode register to “1.” When the main clock X restarted (by setting the main clock stop bit to “0”), set sufficient time for oscillation to stabilize. The sub-clock X clocks that are generated externally. Accordingly, make sure to cause an external resonator to oscillate.
IN in low-speed mode. To stop the main clock, set
IN is
CIN-XCOUT oscillating circuit can not directly input
be generated.

(2) Wait mode

If the WIT instruction is executed, the internal clock φ stops at an “H” level, but the oscillator does not stop. The internal clock φ re­starts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted.
To ensure that the interrupts will be received to release the STP or WIT state, their interrupt enable bits must be set to “1” before ex­ecuting of the STP or WIT instruction. When releasing the STP state, the prescaler 12 and timer 1 will start counting the clock XIN divided by 16. Accordingly, set the timer 1 interrupt enable bit to “0” before executing the STP instruc­tion.

■Note

When using the oscillation stabilizing time set after STP instruction released bit set to “1”, evaluate time to stabilize oscillation of the used oscillator and set the value to the timer 1 and prescaler 12.
XCIN XCOUT XIN XOUT
Rf
Rd
COUT
CCOUT
CCIN
Fig. 32 Ceramic resonator circuit
CIN
Oscillation Control (1) Stop mode
If the STP instruction is executed, the internal clock φ stops at an “H” level, and X stabilizing time set after STP instruction released bit is “0,” the prescaler 12 is set to “FF oscillation stabilizing time set after STP instruction released bit is “1,” set the sufficient time for oscillation of used oscillator to stabi­lize since nothing is set to the prescaler 12 and timer 1. Either X count source. Oscillator restarts when an external interrupt is re­ceived, but the internal clock φ is not supplied to the CPU (remains at “H”) until timer 1 underflows. The internal clock φ is supplied for the first time, when timer 1 underflows. This ensures time for the clock oscillation using the ceramic resonators to be stabilized. When the oscillator is restarted by reset, apply “L” level to the RESET pin until the oscillation is stable since a wait time will not
IN and XCIN oscillation stops. When the oscillation
16” and timer 1 is set to “0116.” When the
IN or XCIN divided by 16 is input to the prescaler 12 as
XCIN XCOUT XIN XOUT
Rf
Rd
External oscillation circuit
CCOUT
CCIN
Fig. 33 External clock input circuit
Vcc Vss
Open
27
Page 28
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
MISRG (MISRG : address 0038
Oscillation stabilizing time set after STP instruction released bit

Middle-speed mode automatic switch set bit

Middle-speed mode automatic switch wait time set bit
Middle-speed mode automatic switch start bit (Depending on program)
Not used (return “0” when read)
Fig. 34 Structure of MISRG
X
CIN
16
)
0: Automatically set “0116” to Timer 1,
“FF
16
” to Prescaler 12
1: Automatically set nothing
0: Not set automatically 1: Automatic switching enable
0: 4.5 to 5.5 machine cycles 1: 6.5 to 7.5 machine cycles
0: Invalid 1: Automatic switch start
X
COUT
“0”
“1”
Port X
C
switch bit
Middle-speed mode automatic switch set bit
By setting the middle-speed mode automatic switch set bit to “1” while operating in the low-speed mode, X cally starts and the mode is automatically switched to the middle-speed mode when defecting a rising/falling edge of the S
CL or SDA pin. The middle-speed automatic switch wait time set
bit can select the switch timing from the low-speed to the middle­speed mode; either 4.5 to 5.5 machine cycles or 6.5 to 7.5 machine cycles in the low-speed mode. Select it according to os­cillation start characteristics of used X The middle-speed mode automatic switch start bit is used to auto­matically make to X
IN oscillation start and switch to the
middle-speed mode by setting this bit to “1” while operating in the low-speed mode.
IN oscillation automati-
IN oscillator.
X
IN
SRQ
Interrupt disable flag l
Interrupt request
X
Reset
OUT
Main clock division ratio selection bits (Note)
Low-speed mode
High-speed or middle-speed mode
Main clock stop bit
STP instruction
1/2 1/4
low-speed mode
WIT instruction
1/2
Main clock division ratio selection bits (Note)
Middle-speed mode
High-speed or
SRQ
Prescaler 12 Timer 1
FF
16
Timing φ (internal clock)
SRQ
STP instruction
01
16
Reset or STP instruction
Note: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
When low-speed mode is selected, set port Xc switch bit (b1) to “1”.
Fig. 35 System clock generating circuit block diagram (Single-chip mode)
28
Page 29
Reset
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Middle-speed mode
(f(φ)=1 MHz)
CM7=0
6=1
CM
5=0(8 MHz oscillating)
CM CM
4=0(32 kHz stopped)
CM4
“1”←→“0”
Middle-speed mode
(f(φ)=1 MHz)
CM
7=0 6=1
CM CM
5=0(8 MHz oscillating) 4=1(32 kHz oscillating)
CM
4
CM
“1”←→“0”
CM
6
“1”←→“0”
CM6 “1”←→“0”
CM6 “1”←→“0”
“0”←→“1”
CM
“1”←→“0”
CM
“1”←→“0”
CM
7
6
CM
“0”←→“1”
4
6
High-speed mode
(f(φ)=4 MHz)
7=0
CM
6=0
CM
5=0(8 MHz oscillating)
CM CM
4=0(32 kHz stopped)
CM4
“1”←→“0”
High-speed mode
(f(φ)=4 MHz)
7=0
CM CM
6=0 5=0(8 MHz oscillating)
CM
4=1(32 kHz oscillating)
CM
CM7
“1”←→“0”
Low-speed mode
(f(φ)=16 kHz)
CM
7=1
CM
6=0 5=0(8 MHz oscillating)
CM
4=1(32 kHz oscillating)
CM
b7 b4
CPU mode register (CPUM : address 003B16)
Notes
1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.) 2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is
ended.
3 : Timer operates in the wait mode. 4 : When the stop mode is ended, a delay of approximately 1 ms occurs by connecting prescaler 12 in middle/high-speed mode. 5 : When the stop mode is ended, a delay of approximately 16 ms occurs by Timer 1 and Timer 2 in low-speed mode. 6 : Wait until oscillation stabilizes after oscillating the main clock X
mode.
7 : The example assumes that 8 MHz is being applied to the X
Fig. 36 State transitions of system clock
CM5
“1”←→“0”
Low-speed mode
(f(φ)=16 kHz)
CM
7=1 6=0
CM
5=1(8 MHz stopped)
CM CM
4=1(32 kHz oscillating)
IN pin and 32 kHz to the XCIN pin. φ indicates the internal clock.
CM4 : Port Xc switch bit 0 : I/O port function (stop oscillating) 1 : X CM 0 : Operating 1 : Stopped CM b7 b6 0 0 : φ = f(X 0 1 : φ = f(X 1 0 : φ = f(X 1 1 : Not available
IN before the switching from the low-speed mode to middle/high-speed
CIN-XCOUT oscillating function
5 : Main clock (XIN- XOUT) stop bit
7, CM6: Main clock division ratio selection bit
IN)/2 ( High-speed mode) IN)/8 (Middle-speed mode) CIN)/2 (Low-speed mode)
29
Page 30
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
NOTES ON PROGRAMMING Processor Status Register
The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1.” After a reset, initialize flags which affect program execution. In particu­lar, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations.

Interrupts

The contents of the interrupt request bits do not change immedi­ately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction.

Decimal Calculations

• To calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction be­fore executing a SEC, CLC, or CLD instruction.
• In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid.

Timers

If a value n (between 0 and 255) is written to a timer latch, the fre­quency division ratio is 1/(n+1).

A-D Converter

The comparator uses capacitive coupling amplifier whose charge will be lost if the clock frequency is too low. Therefore, make sure that f(X A-D conversion. Do not execute the STP or WIT instruction during an A-D conver­sion.
IN) is at least on 500 kHz during an

Instruction Execution Time

The instruction execution time is obtained by multiplying the fre­quency of the internal clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock φ is half of the X high-speed mode.
IN frequency in

Multiplication and Division Instructions

• The index X mode (T) and the decimal mode (D) flags do not af­fect the MUL and DIV instruction.
• The execution of these instructions does not change the con­tents of the processor status register.

Ports

The contents of the port direction registers cannot be read. The following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction regis­ter as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register.
Use instructions such as LDM and STA, etc., to set the port direc­tion registers.

Serial I/O

In clock synchronous serial I/O, if the receive side is using an ex­ternal clock and it is to output the S enable bit, the receive enable bit, and the S to “1.” Serial I/O continues to output the final bit from the T transmission is completed. When an external clock is used as synchronous clock in serial I/O, write transmission data to the transmit buffer register while the transfer clock is “H.”
RDY signal, set the transmit
RDY output enable bit
XD pin after
30
Page 31
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

DATA REQUIRED FOR MASK ORDERS

The following are necessary when ordering a mask ROM produc­tion:
1.Mask ROM Order Confirmation Form
2.Mark Specification Form
3.Data to be written to ROM, in EPROM form (three identical cop­ies)

DATA REQUIRED FOR ROM WRITING ORDERS

The following are necessary when ordering a ROM writing:
1.ROM Writing Confirmation Form
2.Mark Specification Form
3.Data to be written to ROM, in EPROM form (three identical cop­ies)

ROM PROGRAMMING METHOD

The built-in PROM of the blank One Time PROM version and built­in EPROM version can be read or programmed with a general-purpose PROM programmer using a special programming adapter. Set the address of PROM programmer in the user ROM area.
Table 5 Programming adapter
Package
42P2R-A
42P4B
The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To en­sure proper operation after programming, the procedure shown in Figure 49 is recommended to verify programming.
Name of Programming Adapter
PCA4738F-42A
PCA4738S-42A
Programming with PROM
programmer
Screening (Caution)
(150 °C for 40 hours)
Verification with
PROM programmer
Functional check in
target device
Caution :
Fig. 37 Programming and testing of One Time PROM version
The screening temperature is far higher than the storage temperature. Never expose to 150 °C exceeding 100 hours.
31
Page 32
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS
Table 6 Absolute maximum ratings
Symbol Parameter Conditions Ratings
VCC
VI
VI VI VI
VO
VO Pd Topr Tstg
Power source voltage Input voltage P00–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44,
VREF Input voltage P22, P23 Input voltage RESET, XIN Input voltage CNVSS Output voltage P00–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44,
XOUT Output voltage P22, P23 Power dissipation Operating temperature Storage temperature
All voltages are based on VSS. Output transistors are cut off.
Ta = 25 °C
–0.3 to 7.0
–0.3 to VCC +0.3
–0.3 to 5.8
–0.3 to VCC +0.3
–0.3 to 13
–0.3 to VCC +0.3
–0.3 to 5.8
–20 to 85
–40 to 125
3850 Group
Unit
V
V
V V V
V
V
300
mW
°C °C
Table 7 Recommended operating conditions (1) (V
CC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
SS
0 0 0
Limits
Typ. Max.
5.0
5.0 0
0
5.5
5.5
VCC
VCC VCC VCC
0.2VCC
0.2VCC
0.16VCC –80
–80 80 80 80 –40 –40 40 40 40
Unit
V V
V V V V V V V V
mA mA mA mA mA mA mA mA mA mA
Symbol Parameter
VCC VSS
VREF AVSS VIA VIH VIH VIL VIL VIL
ΣIOH(peak) ΣIOH(peak) ΣIOL(peak) ΣIOL(peak) ΣIOL(peak) ΣIOH(avg) ΣIOH(avg) ΣIOL(avg) ΣIOL(avg) ΣIOL(avg)
Note : The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured
over 100 ms. The total peak current is the peak value of all the currents.
Power source voltage (At 8 MHz) Power source voltage (At 4 MHz) Power source voltage A-D convert reference voltage Analog power source voltage Analog input voltage AN “H” input voltage P00–P07, P10–P17, P20–P27, P30–P34, P40–P44 “H” input voltage RESET, XIN, CNVSS
“L” input voltage P00–P07, P10–P17, P20–P27, P30–P34, P40–P44 “L” input voltage RESET, CNVSS “L” input voltage XIN
“H” total peak output current P00–P07, P10–P17, P30–P34 (Note) “H” total peak output current P20, P21, P24–P27, P40–P44 (Note) “L” total peak output current P00–P07, P10–P12, P30–P34 (Note) “L” total peak output current P13–P17 (Note) “L” total peak output current P20–P27,P40–P44 “H” total average output current P00–P07, P10–P17, P30–P34 (Note) “H” total average output current P20, P21, P24–P27, P40–P44 (Note) “L” total average output current P00–P07 , P10–P12, P30–P34 (Note) “L” total average output current P13–P17 (Note) “L” total average output current P20–P27 ,P40 –P44
0–AN4
(Note)
(Note)
Min.
4.0
2.7
2.0
AV
0.8VCC
0.8VCC
32
Page 33
Table 8 Recommended operating conditions (2) (V
CC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol Parameter
IOH(peak)
IOL(peak) IOL(peak) IOH(avg)
IOL(avg) IOL(avg)
f(XIN) f(XIN)
Notes 1: The peak output current is the peak current flowing in each port.
2: The average output current I 3: When the oscillation frequency has a duty cycle of 50%.
“H” peak output current P00–P07, P10–P17, P20, P21, P2 4–P27, P30–P34,
P40–P44 (Note 1)
“L” peak output current P00–P07, P10–P12, P20–P27, P30–P34, P40–P44
“L” peak output current P13–P17 (Note 1) “H” average output current P00–P07, P10–P17, P20, P21, P24–P27, P30–P34,
P40–P44 (Note 2)
“L” average output current P00–P07, P10–P12, P20–P27, P30–P34, P40–P44
“L” peak output current P13–P17 (Note 2) Internal clock oscillation frequency (VCC = 4.0 to 5.5V) (Note 3) Internal clock oscillation frequency (VCC = 2.7 to 5.5V) (Note 3)
OL(avg), IOH(avg) are average value measured over 100 ms.
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(Note 1)
(Note 2)
Min.
Limits
Typ. Max.
–10
10 20 –5
15
Unit
mA
mA mA mA
5
mA mA
8
MHz
4
kHz
33
Page 34
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 9 Electrical characteristics (V
CC = 2.7 to 5.5 V, VSS = 0 V , T a = –20 to 85 °C, unless otherwise noted)
Symbol Unit
“H” output voltage
VOH
VOL
VOL
VT+–VT– VT+–VT–
VT+–VT–
IIH
IIH IIH
IIL
IIL IIL VRAM 2.0
Note: P25 is measured when the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
P0 P24–P27, P30–P34, P40–P44
(Note)
“L” output voltage
P00–P07, P10–P12, P20–P27 P30–P34, P40–P44
“L” output voltage
P13–P17
Hysteresis
CNTR0, CNTR1, INT0–INT3
Hysteresis Hysteresis RESET
“H” input current
P0 P24–P27, P30–P34, P40–P44
“H” input current RESET, CNVSS “H” input current X IN “L” input current
P00–P07, P10–P17, P20–P27
P30–P34, P40–P44 “L” input current RESET,CNVSS “L” input current XIN RAM hold voltage
Parameter
0–P07, P10–P17, P20, P21,
RxD, S
CLK
0–P07, P10–P17, P20, P21,
Test conditions
IOH = –10 mA VCC = 4.0–5.5 V IOH = –1.0 mA VCC = 2.7–5.5 V
I
OL = 10 mA
VCC = 4.0–5.5 V IOL = 1.0 mA VCC = 2.7–5.5 V
IOL = 20 mA VCC = 4.0–5.5 V
IOL = 10 mA VCC = 2.7–5.5 V
VI = VCC
VI = VCC VI = VCC
VI = VSS
VI = VSS VI = VSS When clock stopped
Min. Typ. Max.
VCC–2.0 VCC–1.0
Limits
2.0
1.0
2.0
1.0
0.4
0.5
0.5
5.0
5.0
4
–5.0
–5.0
–4
5.5
V V V V V V
V V
V
µA µA
µA
µA
µA µA
V
34
Page 35
Table 10 Electrical characteristics (V
CC = 2.7 to 5.5 V, VSS = 0 V , T a = –20 to 85 °C, unless otherwise noted)
ICC
Symbol
Parameter
Power source current
High-speed mode f(XIN) = 8 MHz f(XCIN) = 32.768 kHz Output transistors “off”
High-speed mode f(XIN) = 8 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors “off”
Low-speed mode f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off”
Low-speed mode f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off”
Low-speed mode (VCC = 3 V) f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off”
Low-speed mode (VCC = 3 V) f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off”
Middle-speed mode f(XIN) = 8 MHz f(XCIN) = stopped Output transistors “off”
Middle-speed mode f(XIN) = 8 MHz (in WIT state) f(XCIN) = stopped Output transistors “off”
Increment when A-D conversion is executed f(XIN) = 8 MHz
All oscillation stopped (in STP state) Output transistors “off”
Test conditions
Ta = 25 °C Ta = 85 °C
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Min.
Limits
Typ. Max.
6.8 mA
1.6
60
20
20
5.0
4.0
1.5
800
0.1
13
200
40
55
10.0
7.0
1.0 10
Unit
mA
µA
µA
µA
µA
mA
mA
µA
µA µA
35
Page 36
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 11 A-D converter characteristics (V
CC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 8 MHz, unless otherwise noted)
Test conditionsSymbol
V
REF = 5.0 V
– –
CONV
t RLADDER IVREF II(AD)
Parameter
Resolution Absolute accuracy (excluding quantization error) Conversion time Ladder resistor Reference power source input current A-D port input current
MITSUBISHI MICROCOMPUTERS
3850 Group
Min.
50
Limits
Typ.
35
150
0.5
Max.
10 ±4 61
200
5.0
Unit
bit LSB tc(φ)
kΩ
µA µA
36
Page 37
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS
Table 12 Timing requirements (1) (V
CC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol Unit
tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tC(SCLK) tWH(SCLK) tWL(SCLK) tsu(RxD-SCLK) th(SCLK-RxD)
Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when f(X
Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR
0, CNTR1 input cycle time
CNTR0, CNTR1, INT0–INT3 input “H” pulse width CNTR0, CNTR1, INT0–INT3 input “L” pulse width Serial I/O clock input cycle time (Note) Serial I/O clock input “H” pulse width (Note) Serial I/O clock input “L” pulse width (Note) Serial I/O input setup time Serial I/O input hold time
IN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
Parameter
Min.
2
125
50 50
200
80
80 800 370 370 220 100
Limits
Typ. Max.
µs ns ns ns ns ns ns ns ns ns ns ns
Table 13 Timing requirements (2) (V
CC = 2.7 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tC(SCLK) tWH(SCLK) tWL(SCLK) tsu(RxD-SCLK) th(SCLK-RxD)
Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when f(X
Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1, INT0–INT3 input “H” pulse width CNTR0, CNTR1, INT0–INT3 input “L” pulse width Serial I/O clock input cycle time (Note) Serial I/O clock input “H” pulse width (Note) Serial I/O clock input “L” pulse width (Note) Serial I/O input setup time Serial I/O input hold time
IN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
Parameter
Min.
2 250 100 100 500 230 230
2000
950 950 400 200
Limits
Typ.
Max.
Unit
µs ns ns ns ns ns ns ns ns ns ns ns
37
Page 38
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 14 Switching characteristics 1 (V
CC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol Unit
tWH (SCLK) tWL (SCLK) td (SCLK-TXD) tv (SCLK-TXD) tr (SCLK) tf (SCLK) tr (CMOS) tf (CMOS)
Notes 1: For tWH(SCLK), tWL(SCLK), when the P51/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: The X
Serial I/O clock output “H” pulse width Serial I/O clock output “L” pulse width Serial I/O output delay time (Note 1) Serial I/O output valid time (Note 1) Serial I/O clock output rising time Serial I/O clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2)
OUT pin is excluded.
Parameter
t
C(SCLK)/2–30
tC(SCLK)/2–30
Table 15 Switching characteristics 2 (V
CC = 2.7 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol Unit
tWH (SCLK) tWL (SCLK) td (SCLK-TXD) tv (SCLK-TXD) tr (SCLK) tf (SCLK) tr (CMOS) tf (CMOS)
Notes 1: For tWH(SCLK), tWL(SCLK), when the P51/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: The X
Serial I/O clock output “H” pulse width Serial I/O clock output “L” pulse width Serial I/O output delay time (Note 1) Serial I/O output valid time (Note 1) Serial I/O clock output rising time Serial I/O clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2)
OUT pin is excluded.
Parameter
tC(SCLK)/2–50 tC(SCLK)/2–50
Min.
–30
Min.
–30
Limits
Limits
Typ.
10 10
Typ.
20 20
Max.
140
30 30 30 30
Max.
350
50 50 50 50
ns ns ns ns ns ns ns ns
ns ns ns ns ns ns ns ns
38
Page 39
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Measurement output pin
100pF
CMOS output
Fig. 38 Circuit for measuring output switching characteris-
tics (1)
1kΩ
Measurement output pin
100pF
N-channel open-drain output
Fig. 39 Circuit for measuring output switching characteris-
tics (2)
39
Page 40
CNTR0, CNTR1
0.8VCC
tWH(CNTR)
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
tC(CNTR)
tWL(CNTR)
0.2VCC
INT0 to INT3
RESET
XIN
SCLK
R
XD
tf
0.8VCC
0.2VCC
0.8VCC
0.2VCC
tWH(INT)
0.2VCC
tW(RESET)
tC(XIN)
tWH(XIN)
0.2VCC
tC(SCLK)
tWL(SCLK) tWH(SCLK)
tsu(RxD-SCLK)
0.8VCC
0.2VCC
tr
0.8VCC
th(SCLK-RxD)
tWL(INT)
tWL(XIN)
0.8VCC
TXD
Fig. 40 Timing diagram
40
td(SCLK-TXD)
tv(SCLK-TXD)
Page 41

MASK ROM CONFIRMATION FORM

GZZ-SH53-11B<86A0>
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38503M2-XXXSP/FP
Date:
Section head
signature
Supervisor
signature
MITSUBISHI ELECTRIC
Receipt
Note : Please fill in all items marked ❈.
Company name
Customer❈
Date
issued
Date:
TEL ()
Submitted by
Issuance
signature
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name: M38503M2-XXXSP M38503M2-XXXFP
Supervisor
Checksum code for entire EPROM (hexadecimal notation)
EPROM type (indicate the type used)
27256
EPROM address
0000
16
Product name
ASCII code :
000F16
001016
607F16
608016
7FFD16 7FFE16
7FFF16
‘M38503M2-’
ROM (8K-130) bytes
data
27512
EPROM address
0000
16
Product name
ASCII code :
000F16 001016
E07F16
E08016
FFFD16 FFFE16
FFFF16
‘M38503M2-’
ROM (8K-130) bytes
data
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF
16”.
(2) The ASCII codes of the product name “M38503M2–”
must be entered in addresses 0000 set the data “FF
16” in addresses 000916 to 000F16.
16 to 000816. And
The ASCII codes and addresses are listed to the right in hexadecimal notation.
In the address space of the microcomputer, the internal ROM area is from address 6080 vector is stored in addresses FFFC
Address
16
0000 000116 000216 000316 000416 000516 000616 000716
‘M’ = 4D16 ‘3’ = 3316 ‘8’ = 3816 ‘5’ = 3516 ‘0’ = 3016 ‘3’ = 3316 ‘M’ = 4D16 ‘2’ = 3216
16 to FFFD16. The reset
16 and FFFD16.
Address 0008
16
‘–’ = 2D16 000916 000A16 000B16 000C16 000D16 000E16 000F16
FF16 FF16 FF16 FF16 FF16 FF16 FF16
(1/2)
41
Page 42
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GZZ-SH53-11B<86A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38503M2-XXXSP/FP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program be­cause ASCII codes of the product name are written to addresses 0000
EPROM type
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM
will not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (42P4B for M38503M2-XXXSP, 42P2R-A for M38503M2-XXXFP) and attach it to the mask ROM confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the X
Ceramic resonator External clock input
IN-XOUT oscillator?
.BYTE ‘M38503M2–’
Quartz crystal Other ( )
27256
*= $8000
16 to 000816 of EPROM.
27512
*= $0000
.BYTE ‘M38503M2–’
At what frequency? f(XIN) =
(2) Which function will you use the pins P21 /XCIN and P20/XCOUT as P21 and P20, or XCIN and XCOUT ?
❈ 4. Comments
Ports P2
1 and P20 function
CIN and XCOUT function (external resonator)
X
(2/2)
MHz
42
Page 43
MASK ROM CONFIRMATION FORM
GZZ-SH11-40A<6YA0>
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38503M4-XXXSP/FP
Date:
Section head
signature
Supervisor
signature
MITSUBISHI ELECTRIC
Receipt
Note : Please fill in all items marked ❈.
Company name
Customer❈
Date
issued
Date:
TEL
()
Submitted by
Issuance
signature
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name: M38503M4-XXXSP M38503M4-XXXFP
Supervisor
Checksum code for entire EPROM (hexadecimal notation)
EPROM type (indicate the type used)
27256
EPROM address
0000
16
Product name
ASCII code :
000F16
001016
407F16
408016
7FFD16
7FFE16 7FFF16
‘M38503M4-’
ROM (16K-130) bytes
data
27512
EPROM address
000016
000F16
001016
C07F16
C08016
FFFD16
FFFE16 FFFF16
Product name
ASCII code : ‘M38503M4-’
ROM (16K-130) bytes
data
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF
16”.
(2) The ASCII codes of the product name “M38503M4–”
must be entered in addresses 0000 set the data “FF
16” in addresses 000916 to 000F16.
16 to 000816. And
The ASCII codes and addresses are listed to the right in hexadecimal notation.
In the address space of the microcomputer, the internal ROM area is from address C080 vector is stored in addresses FFFC
Address
16
0000 000116 000216 000316 000416 000516 000616 000716
‘M’ = 4D16 ‘3’ = 3316 ‘8’ = 3816 ‘5’ = 3516 ‘0’ = 3016 ‘3’ = 3316 ‘M’ = 4D16 ‘4’ = 3416
16 to FFFD16. The reset
16 and FFFD16.
Address 0008
16
‘–’ = 2D16 000916 000A16 000B16 000C16 000D16 000E16 000F16
FF16 FF16 FF16 FF16 FF16 FF16 FF16
(1/2)
43
Page 44
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GZZ-SH11-40A<6YA0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38503M4-XXXSP/FP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program be­cause ASCII codes of the product name are written to addresses 0000
EPROM type
The pseudo-command
Note : If the name of the product wr itten to the EPROMs does not match the name of the mask confirmation form, the ROM
will not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (42P4B for M38503M4-XXXSP, 42P2R-A for M38503M4-XXXFP) and attach it to the mask ROM confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the X
Ceramic resonator External clock input
IN-XOUT oscillator?
.BYTE ‘M38503M4–’
Quartz crystal Other ( )
27256
*= $8000
16 to 000816 of EPROM.
27512
*= $0000
.BYTE ‘M38503M4–’
At what frequency? f(XIN) =
(2) Which function will you use the pins P21/XCIN and P20/XCOUT as P21 and P20, or XCIN and XCOUT ?
Ports P2
❈ 4. Comments
1 and P20 function
XCIN and XCOUT function (external resonator)
(2/2)
MHz
44
Page 45

ROM PROGRAMMING CONFIRMATION FORM

GZZ-SH11-41A<6YA0>
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38503E4-XXXSP/FP
Date:
Section head
signature
Supervisor
signature
MITSUBISHI ELECTRIC
Receipt
Note : Please fill in all items marked ❈.
Company name
Customer❈
Date
issued
Date:
TEL ()
Submitted by
Issuance
signature
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on this data. We shall assume the responsibility for errors only if the programming data on the products we produce dif­fers from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name: M38503E4-XXXSP M38503E4-XXXFP
Supervisor
Checksum code for entire EPROM (hexadecimal notation)
EPROM type (indicate the type used)
27256
EPROM address
000016 000F16
001016
407F16 408016
7FFD16
7FFE16 7FFF16
Product name
ASCII code : ‘M38503E4-’
ROM (16K-130) bytes
data
27512
EPROM address
0000
16
Product name
ASCII code :
000F16
001016
C07F16
C08016
FFFD16
FFFE16 FFFF16
‘M38503E4-’
ROM (16K-130) bytes
data
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF
16”.
(2) The ASCII codes of the product name “M38503E4–”
must be entered in addresses 0000 set the data “FF
16” in addresses 000916 to 000F16.
16 to 000816. And
The ASCII codes and addresses are listed to the right in hexadecimal notation.
In the address space of the microcomputer, the internal ROM area is from address C080 vector is stored in addresses FFFC
Address
16
0000 000116 000216 000316 000416 000516 000616 000716
‘M’ = 4D16 ‘3’ = 3316 ‘8’ = 3816 ‘5’ = 3516 ‘0’ = 3016 ‘3’ = 3316 ‘E’ = 4516 ‘4’ = 3416
16 to FFFD16. The reset
16 and FFFD16.
Address 0008
16
‘–’ = 2D16
000916 000A16 000B16 000C16 000D16 000E16 000F16
FF16 FF16 FF16 FF16 FF16 FF16 FF16
(1/2)
45
Page 46
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GZZ-SH11-41A<6YA0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38503E4-XXXSP/FP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program be­cause ASCII codes of the product name are written to addresses 0000
EPROM type
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation
form, the ROM will not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropr iate
mark specification form; 42P2R-A for the M38503E4-XXXFP, the shrink DIP package Mark Specification Form (only for built-in One Time PROM microcomputer) for the M38503E4-XXXSP; and attach it to the ROM programming confirma­tion form.
.BYTE ‘M38503E4–’
27256
*= $8000
16 to 000816 of EPROM.
27512
*= $0000
.BYTE ‘M38503E4–’
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the X
Ceramic resonator External clock input
At what frequency? f(XIN) =
(2) Which function will you use the pins P21 /XCIN and P20/XCOUT as P21 and P20, or XCIN and XCOUT ?
Ports P2
❈ 4. Comments
IN-XOUT oscillator?
1 and P20 function
Quartz crystal Other ( )
MHz
CIN and XCOUT function (external resonator)
X
46
(2/2)
Page 47

MARK SPECIFICATION FORM

MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
47
Page 48
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
48
Page 49
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SHRINK DIP MARK SPECIFICATION FORM
for One Time PROM version microcomputers
Enter the catalog number of the microcomputer for which this mark specification is intended. (If you do not know the R OM code number, enter XXX in its place.)
The catalog number of the microcomputer
A. Standard Mitsubishi Mark Customer specified part number will be printed together with the ROM code number on the top line. Enter the desired part number left aligned in the box below. (up to 10 characters)
Note2 :
M
RXXX
Mitsubishi catalog name (blank model number before writing)
Mitsubishi lot number
(6-digit or 7-digit)
Note1 : The following characters can be used in the part number :
Uppercase alphabet, numbers, ampersand, hyphen, period, comma, +, /, (, ), ( will be printed at 1.5
2 : XXX is the ROM code number.
B. Special Mark Required If you desire anything other than the standard Mitsubishi mark, it will be treated as a special mark. Special marks will take longer to produce and should be avoided if possible. If a special mark is to be printed, indicate the desired layout of the mark in the figure below. The layout will be duplicated as closely as possible.
x
character width)
Note1 : If the customer’s trademark logo must be used in the Special Mark, please submit a clean original logo.
Note that special marks require extra cost and time to produce.
49
Page 50

PACKAGE OUTLINE

SSOP42-P-450-0.80
Weight(g)
–
JEDEC Code
0.63
EIAJ Package Code
Lead Material
Alloy 42/Cu Alloy
42P2R-A
Plastic 42pin 450mil SSOP
Symbol
Min Nom Max
A
A
2
b c
D
E
L
L
1
y
Dimension in Millimeters
H
E
A
1
I
2
– –
.350
.050
.130 .317 .28
–
.6311
.30 – –
–
.271
–
–
.02 .40 .150 .517 .48 .80 .9311 .50 .7651
–
.4311
–
–
.42
–
.50 .20 .717 .68
–
.2312 .70
–
.150
–
b
2
–.50–
–
0°–10°
e
e
1
42
22
21
1
H
E
E
D
b
e
y
F
A
A
2
A
1
L
1
L
c
e
b
2
e
1
I
2
Recommended Mount Pad
Detail F
SDIP42-P-600-1.78
Weight(g)
–
JEDEC Code
4.1
EIAJ Package Code
Lead Material
Alloy 42/Cu Alloy
42P4B
Plastic 42pin 600mil SDIP
Symbol
Min Nom Max
A
A
2
b
b
1
b
2
c
E
D
L
Dimension in Millimeters
A
1
0.51 – – –3.8–
0.35 0.45 0.55
0.9 1.0 1.3
0.63 0.73 1.03
0.22 0.27 0.34
36.5 36.7 36.9
12.85 13.0 13.15 – 1.778 – – 15.24 –
3.0 – – 0° –15°
– – 5.5
e
e
1
42
22
21
1
E
c
e
1
A
2
A
1
b
b
1
b
2
e
LA
SEATING PLANE
D
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
50
Page 51
MITSUBISHI MICROCOMPUTERS
WDIP42-C-600-1.78
Weight(g)
JEDEC Code
EIAJ Package Code
42S1B-A
Metal seal 42pin 600mil DIP
–– –– ––
0.46
0.25 ––
3.44
15.8 –
– – –
– –
3.05
––
––
–
Symbol
Min Nom Max
A
A
2
b
b
1
c D E
L
Z
Dimension in Millimeters
A
1
3.05
15.24
1.778
41.1
0.33 0.17
0.9 0.8 0.7
0.540.38
1.0
5.0
e
e
1
e
E
D
1
42
22
21
bZ
SEATING PLANE
AL
A
2
A
1
b
1
e
1
c
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
© 1998 MITSUBISHI ELECTRIC CORP. New publication, effective Aug. 1998. Specifications subject to change without notice.
Keep safety first in your circuit designs!
● Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
● These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
● Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials.
● All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein.
● Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
● The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
● If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the
approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
● Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
Page 52

REVISION DESCRIPTION LIST 3850 GROUP DATA SHEET

Rev. Rev.
No. date
1.0 First Edition 980817
Revision Description
(1/1)
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