Datasheet M38027E8SS, M38027E8SP, M38027E8FS, M38027M8-XXXSP, M38027M8-XXXFP Datasheet (Mitsubishi)

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Programmable input/output ports ............................................. 56

DESCRIPTION

The 3802 group is the 8-bit microcomputer based on the 740 fam­ily core technology.
The 3802 group is designed for controlling systems that require
analog signal processing and include two serial I/O functions, A-D
converters, and D-A converters.
The various microcomputers in the 3802 group include variations
of internal memory size and packaging. For details, refer to the
section on part numbering.
For details on availability of microcomputers in the 3802 group, re­fer to the section on group expansion.

FEATURES

Basic machine-language instructions....................................... 71

•

The minimum instruction execution time ............................ 0.5 µs

•

(at 8 MHz oscillation frequency)
Memory size

•

ROM .................................................................. 8 K to 32 K bytes

RAM ................................................................. 384 to 1024 bytes

•

Interrupts .................................................. 16 sources, 16 vectors

•

Timers ............................................................................. 8 bit ✕ 4

•

Serial I/O1 .................... 8-bit ✕ 1 (UART or Clock-synchronized)

•

Serial I/O2 ....................................8-bit ✕ 1 (Clock-synchronized)

•

PWM................................................................................ 8-bit ✕ 1

•

A-D converter .................................................. 8-bit ✕ 8 channels

•

D-A converter.................................................. 8-bit ✕ 2 channels

•

Clock generating circuit ....................... Internal feedback resistor

•

(connect to external ceramic resonator or quartz-crystal oscillator)

Power source voltage..................................................3.0 to 5.5 V

•

(Extended operating temperature version : 4.0 to 5.5 V)

Power dissipation............................................................... 32 mW

•

Memory expansion possible

•

Operating temperature range .................................... –20 to 85°C

•

(Extended operating temperature version : –40 to 85°C)

APPLICATIONS

Office automation, VCRs, tuners, musical instruments, cameras,
air conditioners, etc.

PIN CONFIGURATION (TOP VIEW)

P37/RD

P36/WR

P35/SYNC

P34/φ

P33/RESETOUT

P32/ONW

P31/DA2
P30/DA1

VCC

VREF

SS

AV

7

/AN

7

P6

6

/AN

6

P6

P65/AN5
P64/AN4

P63 /AN3

2

/AD3

P01/AD1

P03

P00/AD0

P02/AD

45

46

48

47
49
50
51
52
53
54
55
56

M38022M4-XXXFP

57
58
59
60
61
62
63
64

123

4

/AN1

/INT3

P60/AN0

P62/AN2

P61

P57

7

P04/AD4

P06/AD6

P05/AD5

P07/AD

41

44

43

42

56789

0

/PWM

/SRDY2

/CNTR1

5

P56

P53

P54/CNTR

P5

/AD8
P10

40

P52/SCLK2

P11/AD9

39

10

P51/SOUT2

/AD13

P12/AD10

P14/AD12

P16/AD14

P13/AD11

P15

38

37

35

36

34

11

12

131415

D

/SIN2
P50

/SRDY1
P47

P46/SCLK1

4/RXD

P45/TX

P4

Package type : 64P6N-A

64-pin plastic-molded QFP

P17/AD15

33

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

16

/INT2

3

P4

P20/DB0
P21/DB1
P22/DB2
P23/DB3
P24/DB4
P25/DB5
P26/DB6
P27/DB7
VSS
XOUT
XIN
P40/INT4
P41/INT0
RESET
CNVSS
P42/INT1

PIN CONFIGURATION (TOP VIEW)

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

V

V

AV
P67/AN
P66/AN
P65/AN
P64/AN
P63/AN

2

/AN

P6

1

/AN

P6
P60/AN

P57/INT

P56/PWM

P5

5

/CNTR

P54/CNTR

/S

RDY2

P5

3

2/SCLK2

P5
P51/S

OUT2

P50/S

P47/S

RDY1

P46/S

CLK1

5/TX

P4

P44/R

3

/INT

P4
P42/INT

CNV

RESET
P41/INT
P40/INT

X

OUT

V

REF

IN2

X

X

CC

1
2

SS

7
6
5
4
3
2
1
0
3

3
4
5
6
7
8

9
10
11
12

M38022M4-XXXSP

13
14

1

15

0

16
17
18
19
20
21

D
D

SS

22
23
24

2

25

1

26
27
28

0

29

4

IN

30
31

SS

32

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

P3

0

/DA

1

P31/DA

2

P32/ONW
P33/RESET
P34/φ
P3

5

/SYNC

/WR

6

P3

/RD

7

P3

P00/AD

0

P01/AD

1

P02/AD

2
3

P03/AD
P04/AD

4

P05/AD

5

P06/AD

6
7

P07/AD

0

/AD

8

P1
P11/AD

9

P12/AD

10

P13/AD

11

P14/AD

12

P15/AD

13
14

P16/AD

15

P17/AD
P20/DB

0

P21/DB

1

P22/DB

2

P23/DB

3

P24/DB

4

P25/DB

5

P26/DB

6

P27/DB

7

OUT

Package type : 64P4B

64-pin shrink plastic-molded DIP

2

MITSUBISHI MICROCOMPUTERS

CNTR1

CNTR

0

VREF AVSS

RAM

ROM

CPU

A

X

Y

S

PC

H

PCL

PS

VSS

32

RESET

27

VCC

1

26

CNVSS

P0(8)

49 50 51

52 53

54

55

56

P1(8)

41

43 45

47

42 44

46

48

P2(8)

33 35 37 39

36

38 40

P3(8)

57 59

61 63

58 60

62 64

P4(8)

20 22

24 28

21 23

25

29

P5(8)

12 14

16 18

13

15

17

19

P6(8)

46

10

59

11

3

34

2

XIN

30

XOUT

31

D-A

(8)

D-A

(8)

A-D

(8)

Reset input

Clock generating circuit

Clock input Clock output

Prescaler 12 (8)

Timer 1 (8)

Timer 2 (8)

I/O port P4 I/O port P0I/O port P1I/O port P2I/O port P3

I/O port P5

I/O port P6

7 8

SI/O1 (8)

INT

0

INT2

INT4

Prescaler X (8)

Timer X (8)

Prescaler Y (8)

Timer Y (8)

converter 2

converter 1

~

SI/O2 (8)

PWM (8)

INT3

converter

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

FUNCTIONAL BLOCK DIAGRAM (Package : 64P4B)

3

PIN DESCRIPTION

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Pin

VCC, VSS

CNVSS

VREF

AVSS

RESET
XIN
XOUT

P00–P07
P10–P17
P20–P27
P30/DA1,

P31/DA2

Name

Power source

CNVSS

Analog reference
voltage

Analog power
source

Reset input
Clock input
Clock output

I/O port P0
I/O port P1
I/O port P2
I/O port P3

Function

Function except a port function

• Apply voltage of 3.0 V–5.5 V to VCC, and 0 V to VSS.
(Extended operating temperature version : 4.0 V to 5.5 V)

• This pin controls the operation mode of the chip.

• Normally connected to VSS.

• If this pin is connected to VCC, the internal ROM is inhibited and external memory is accessed.

• Reference voltage input pin for A-D and D-A converters

• GND input pin for A-D and D-A converters

• Connect to VSS.

• Reset input pin for active “L”

• Input and output signals for the clock generating circuit.

• Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the
oscillation frequency.

• If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.

• The clock is used as the oscillating source of system clock.

• 8 bit CMOS I/O port

• I/O direction register allows each pin to be individually programmed as either input or output.

• At reset this port is set to input mode.

• In modes other than single-chip, these pins are used as address, data, and control bus I/O pins.

• CMOS compatible input level

• CMOS 3-state output structure

• D–A conversion output pins

P32–P37
P40/INT4,

P41/INT0,
P42/INT1,
P43/INT2

P44/RXD,
P45/TXD,
P46/SCLK1,
P47/SRDY1

P50/SIN2,
P51/SOUT2,
P52/SCLK2,
P53/SRDY2

P54/CNTR0,
P55/CNTR1

P56/PWM
P57/INT3
P60/AN0–

P67/AN7

I/O port P4

I/O port P5

I/O port P6

• 8-bit CMOS I/O port with the same function as port P0

• CMOS compatible input level

• CMOS 3-state output structure

• 8-bit CMOS I/O port with the same function as port P0

• CMOS compatible input level

• CMOS 3-state output structure

• 8-bit CMOS I/O port with the same function as port P0

• CMOS compatible input level

• CMOS 3-state output structure

• External interrupt input pin

• Serial I/O1 I/O pins

• Serial I/O2 I/O pins

• Timer X and Timer Y I/O pins

• PWM output pin

• External interrupt input pin

• A-D conversion input pins

4

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

GROUP EXPANSION

Mitsubishi plans to expand the 3802 group as follows:
(1) Support for mask ROM, One Time PROM, and EPROM

versions

ROM/PROM capacity................................... 8 K to 32 K bytes

RAM capacity .............................................. 384 to 1024 bytes

Memory Expansion Plan

ROM size (bytes)

32K

28K

Mass product

24K

20K

Mass product

16K

12K

Mass product

8K

M38022M4

M38022M2

(2) Packages

64P4B ............................................ Shrink plastic molded DIP

64P6N-A................................................... Plastic molded QFP

64S1B-E.................................................... Shrink ceramic DIP

64D0................................................................... Ceramic LCC

Mass product

M38027M8/E8

M38024M6

4K

192

256 384 512 640 768 896 1024

Currently supported products are listed below

Product

M38022M2-XXXSP
M38022M2-XXXFP
M38022M4-XXXSP
M38022M4-XXXFP
M38024M6-XXXSP
M38024M6-XXXFP

(P) ROM size (bytes)
ROM size for User in ( )

8192

(8062)
16384

(16254)

24576

(24446)

M38027M8-XXXSP
M38027E8-XXXSP
M38027E8SP
M38027M8-XXXFP
M38027E8-XXXFP

32768

(32638)

M38027E8FP
M38027E8SS
M38027E8FS

RAM size (bytes)

RAM size (bytes)

384

384

640

1024

Package

64P4B

64P6N-A

64P4B

64P6N-A

64P4B

64P6N-A

64P4B

64P6N-A

64S1B-E

64D0

As of May 1996

Remarks

Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
One Time PROM version
One Time PROM version (blank)
Mask ROM version
One Time PROM version
One Time PROM version (blank)
EPROM version
EPROM version

5

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

GROUP EXPANSION (Extended operating temperature version)

Mitsubishi plans to expand the 3802 group (extended operating
temperature version) as follows:
(1) Support for mask ROM One Time PROM, and EPROM ver-

sions

ROM/PROM capacity................................... 8 K to 32 K bytes

RAM capacity .............................................. 384 to 1024 bytes

(2) Packages

64P4B ............................................ Shrink plastic molded DIP

64P6N-A................................................... Plastic molded QFP

Memory Expansion Plan (Extended operating temperature version)

ROM size (bytes)

32K

28K

24K

20K

Mass product

16K

12K

Mass product

8K

M38022M4D

M38022M2D

Mass product

M38027M8D/E8D

4K

192

256 384 512 640 768 896 1024

RAM size (bytes)

Currently supported products are listed below. As of May 1996

Product
M38022M2DXXXSP
M38022M2DXXXFP
M38022M4DXXXSP
M38022M4DXXXFP
M38027M8DXXXSP
M38027E8DXXXSP
M38027E8DSP
M38027M8DXXXFP
M38027E8DXXXFP
M38027E8DFP

(P) ROM size (bytes)

8192
(8062)
16384

(16254)

32768

(32638)

RAM size (bytes)

384

384

1024

Package

64P4B

64P6N-A

64P4B

64P6N-A

64P4B

64P6N-A

Remarks
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
One Time PROM version
One Time PROM version (blank)
Mask ROM version
One Time PROM version
One Time PROM version (blank)

6

PART NUMBERING

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Product

M3802 2 M 4 - XXX SP

Package type

SP : 64P4B package
FP : 64P6N-A package
SS : 64S1B-E package
FS : 64D0 package

ROM number

Omitted in some types.

Normally, using hyphen.
When electrical characteristic, or division of quality
identification code using alphanumeric character

– : standard

D : Extended operating temperature version
ROM/PROM size

: 4096 bytes

1

: 8192 bytes

2

: 12288 bytes

3

: 16384 bytes

4

: 20480 bytes

5

: 24576 bytes

6

: 28672 bytes

7

: 32768 bytes

8

The first 128 bytes and the last 2 bytes of ROM
are reserved areas ; they cannot be used.

Memory type

M

: Mask ROM version

E

: EPROM or One Time PROM version

RAM size

: 192 bytes

0

: 256 bytes

1

: 384 bytes

2

: 512 bytes

3

: 640 bytes

4

: 768 bytes

5

: 896 bytes

6

: 1024 bytes

7

7

FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)

The 3802 group uses the standard 740 family instruction set. Re­fer to the table of 740 family addressing modes and machine in­structions or the SERIES 740 <Software> User’s Manual for de­tails on the instruction set.
Machine-resident 740 family instructions are as follows:

The FST and SLW instruction cannot be used.
The STP, WIT, MUL, and DIV instruction can be used.

CPU mode register

The CPU mode register is allocated at address 003B16.
The CPU mode register contains the stack page selection bit.

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

b7

b0

CPU mode register

(

Fig. 1 Structure of CPU mode register

CPUM : address

Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Microprocessor mode
1 1 : Not available

Stack page selection bit
0 : 0 page
1 : 1 page

Not used (return “0” when read)

003B16)

8

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Memory
Special function register (SFR) area

The Special Function Register area in the zero page contains con­trol registers such as I/O ports and timers.

RAM

RAM is used for data storage and for stack area of subroutine
calls and interrupts.

ROM

The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.

Interrupt vector area

The interrupt vector area contains reset and interrupt vectors.

RAM area

RAM capacity

(bytes)

192
256
384
512
640
768
896

1024

Address
XXXX

00FF
013F
01BF
023F
02BF
033F
03BF
043F

16

16
16
16
16
16
16
16
16

Zero page

The 256 bytes from addresses 000016 to 00FF16 are called the
zero page area. The internal RAM and the special function regis­ters (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.

Special page

The 256 bytes from addresses FF0016 to FFFF16 are called the
special page area. The special page addressing mode can be
used to specify memory addresses in the special page area. Ac­cess to this area with only 2 bytes is possible in the special page
addressing mode.

0000

RAM

0040

0100

XXXX

16

16

16

16

SFR area

Zero page

Reserved area

ROM area

ROM capacity

(bytes)

4096

8192
12288
16384
20480
24576
28672
32768

Fig. 2 Memory map diagram

Address
YYYY

F000
E000
D000
C000
B000
A000
9000
8000

0440

16

Not used

16
16

16
16
16
16

16
16
16

Address
ZZZZ

F080
E080
D080
C080
B080
A080
9080
8080

16
16

16
16
16
16

16
16
16

ROM

YYYY

ZZZZ

FF00

FFDC

FFFE
FFFF

16

Reserved ROM area

(128 bytes)

16

16

16

Interrupt vector area

16

Reserved ROM area

16

Special page

9

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Port P0 (P0)

000016

Port P0 direction register (P0D)

000116

Port P1 (P1)

000216

Port P1 direction register (P1D)

000316

Port P2 (P2)

000416

Port P2 direction register (P2D)

000516

Port P3 (P3)

000616

Port P3 direction register (P3D)

000716

Port P4 (P4)

000816

Port P4 direction register (P4D)

000916

Port P5 (P5)

000A16

Port P5 direction register (P5D)

000B16

Port P6 (P6)

000C16

Port P6 direction register (P6D)

000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716

Transmit/Receive buffer register (TB/RB)

001816

Serial I/O1 status register (SIO1STS)

001916

Serial I/O1 control register (SIO1CON)

001A16

UART control register (UARTCON)

001B16

Baud rate generator (BRG)

001C16

Serial I/O2 control register (SIO2CON)

001D16
001E16

Serial I/O2 register (SIO2)

001F16

Prescaler 12 (PRE12)

002016

Timer 1 (T1)

002116

Timer 2 (T2)

002216

Timer XY mode register (TM)

002316

Prescaler X (PREX)

002416

Timer X (TX)

002516

Prescaler Y (PREY)

002616

Timer Y (TY)

002716
002816
002916
002A16

PWM control register (PWMCON)

002B16

PMW prescaler (PREPWM)

002C16
002D16

PWM register (PWM)
002E16
002F16
003016
003116
003216
003316

AD/DA control register (ADCON)

003416

A-D conversion register (AD)

003516

D-A1 conversion register (DA1)

003616

D-A2 conversion register (DA2)

003716
003816
003916

Interrupt edge selection register (INTEDGE)

003A16

CPU mode register (CPUM)

003B16

Interrupt request register 1(IREQ1)

003C16

Interrupt request register 2(IREQ2)

003D16

Interrupt control register 1(ICON1)

003E16

Interrupt control register 2(ICON2)

003F16

Fig. 3 Memory map of special function register (SFR)

10

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

I/O Ports
Direction registers

The 3802 group has 56 programmable I/O pins arranged in seven
I/O ports (ports P0 to P6). The I/O ports have direction registers
which determine the input/output direction of each individual pin.
Each bit in a direction register corresponds to one pin, each pin
can be set to be input port or output port.
When “0” is written to the bit corresponding to a pin, that pin be­comes an input pin. When “1” is written to that bit, that pin be­comes an output pin.

Pin

P00–P07

P10–P17

P20–P27

P30/DA1
P31/DA2
P32–P37
P40/INT4,
P41/INT0,
P43/INT2
P44/RXD,
P45/TXD,
P46/SCLK1,
P47/SRDY1
P50/SIN2,
P51/SOUT2,
P52/SCLK2,
P53/SRDY2
P54/CNTR0,
P55/CNTR1
P56/PWM
P57/INT3

P60/AN0–
P67/AN7

Note 1: For details of the functions of ports P0 to P3 in modes other than single-chip mode, and how to use double-function ports as func-

tion I/O ports, refer to the applicable sections.

2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.

When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.

Name

Port P0

Port P1

Port P2

Port P3

Port P4

Port P5

Port P6

Input/Output

Input/output,
individual bits

Input/output,
individual bits

Input/output,
individual bits

Input/output,
individual bits

Input/output,
individual bits

Input/output,
individual bits

Input/output,
individual bits

I/O Format
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level

CMOS 3-state output
CMOS compatible
input level

CMOS 3-state output
CMOS compatible
input level

CMOS 3-state output
CMOS compatible
input level

If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.

Non-Port Function

Address low-order byte
output

Address high-order
byte output

Data bus I/O

D-A conversion output

Control signal I/O

External interrupt input

Serial I/O1 function I/O

Serial I/O2 function I/O

Timer X and Timer Y
function I/O
PWM output
External interrupt input

A-D conversion input

Related SFRs

CPU mode register

CPU mode register

CPU mode register

AD/DA control register
CPU mode register
CPU mode register

Interrupt edge selection
register

Serial I/O1 control
register
UART control register

Serial I/O2 control
register

Timer XY mode register
PWM control register

Interrupt edge selection register

Ref.No.

(1)

(2)
(1)

(3)

(4)
(5)
(6)
(7)
(8)

(9)
(10)
(11)

(12)
(13)

(3)

(14)

11

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(1) Ports P0, P1, P2, P32–P37

Direction register

Data bus

Port latch

(3) Ports P40–P43, P57

Direction register

Data bus

Port latch

Interrupt input

(2) Ports P30, P31

Direction register

Data bus

Port latch

(4) Port P44

Serial I/O1 enable bit

Receive enable bit

Direction register

Data bus

Port latch

D–A conversion output

DA1 output enable bit (P30)
DA

2 output enable bit (P31)

Serial I/O1 input

(5) Port P45 (6) Port P46

P45/TXD P-channel output disable bit

Serial I/O1 enable bit

Transmit enable bit

Direction register

Data bus

Port latch

Serial I/O1 output

Serial I/O1 synchronous
clock selection bit

Serial I/O1 enable bit

Serial I/O1 mode selection bit

Data bus

(7) Port P47 (8) Port P50

Serial I/O1 mode selection bit

Serial I/O1 enable bit

S

RDY1 output enable bit

Data bus

Direction register

Port latch

Data bus

Serial I/O1 enable bit

Direction register

Port latch

Serial I/O1 clock output

Direction register

Port latch

Serial I/O2 input

Serial I/O1
external
clock input

Serial I/O1 ready output

Fig. 4 Port block diagram (single-chip mode) (1)

12

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(9) Port P5

Data bus

(11) Port P5

1

P5

1/SOUT2

Serial I/O2 transmit end signal

Serial I/O2 port selection bit

Direction register

Port latch

Serial I/O2 output

3

Data bus

Serial I/O2 ready output

P-channel output disable bit

S

RDY2

output enable bit

Direction register

Port latch

(10) Port P5

Data bus

2

Serial I/O2
synchronous clock selection bit

Serial I/O2 port selection bit

Serial I/O2 clock output

(12) Ports P54, 5

Data bus

Direction register

Port latch

5

Direction register

Port latch

Pulse output mode

Timer output

Serial I/O2 external clock input

CNTR

0

, CNTR

Interrupt input

1

6

PWM output enable bit

Direction register

Data bus

Port latch

PWM output

Fig. 5 Port block diagram (single-chip mode) (2)

(14) Port P6(13) Port P5

Data bus

Direction register

Port latch

A-D conversion input

Analog input pin selection bit

13

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

INTERRUPTS

Interrupts occur by sixteen sources: seven external, eight internal,
and one software.

Interrupt control

Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in­terrupt set by the BRK instruction. An interrupt occurs if the corre­sponding interrupt request and enable bits are “1” and the inter­rupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
(interrupt disable) flag disables all interrupts except the BRK in­struction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.

Table 1. Interrupt vector addresses and priority

Interrupt Source
Reset (Note 2)
INT

0

INT1
Serial I/O1

reception
Serial I/O1

transmission
Timer X

Timer Y
Timer 1
Timer 2

CNTR0

CNTR1

Serial I/O2

INT2

INT3

INT4
A-D converter

Priority

1
2

3

4

5

6
7
8
9

10

11

12

13

14

15
16

Vector Addresses (Note 1)

High

FFFD16
FFFB16

FFF916

FFF716

FFF516

FFF316
FFF116
FFEF16
FFED16

FFEB16

FFE916

FFE716

FFE516

FFE316

FFE116
FFDF16

Low

FFFC16
FFFA16

FFF816

FFF616

FFF416

FFF216
FFF016
FFEE16
FFEC16

FFEA16

FFE816

FFE616

FFE416

FFE216

FFE016
FFDE16

Interrupt operation

When an interrupt is received, the contents of the program counter
and processor status register are automatically stored into the
stack. The interrupt disable flag is set to inhibit other interrupts
from interfering.The corresponding interrupt request bit is cleared
and the interrupt jump destination address is read from the vector
table into the program counter.

Notes on use

When the active edge of an external interrupt (INT0 to INT4,
CNTR

0, or CNTR1) is changed, the corresponding interrupt re-

quest bit may also be set. Therefore, please take following se­quence;
(1) Disable the external interrupt which is selected.
(2) Change the active edge selection.
(3) Clear the interrupt request bit which is selected to “0”.
(4) Enable the external interrupt which is selected.

Interrupt Request

Generating Conditions
At reset
At detection of either rising or
falling edge of INT0 input
At detection of either rising or
falling edge of INT1 input
At completion of serial I/O1
data reception
At completion of serial I/O1
transfer shift or when
transmission buffer is empty
At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 2 underflow
At detection of either rising or
falling edge of CNTR0 input
At detection of either rising or
falling edge of CNTR1 input
At completion of serial I/O2
data transfer
At detection of either rising or
falling edge of INT2 input
At detection of either rising or
falling edge of INT3 input
At detection of either rising or
falling edge of INT4 input
At completion of A-D conversion

Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)

Valid when serial I/O1 is selected

Valid when serial I/O1 is selected

STP release timer underflow

External interrupt
(active edge selectable)
External interrupt
(active edge selectable)

Valid when serial I/O2 is selected
External interrupt

(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)

Remarks

BRK instruction

Note 1: Vector addresses contain interrupt jump destination addresses.

2: Reset function in the same way as an interrupt with the highest priority.

14

17

FFDD16

FFDC16

At BRK instruction execution

Non-maskable software interrupt

Interrupt request bit

Interrupt enable bit

Interrupt disable flag (I)

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Fig. 6 Interrupt control

b7 b0

b7 b0

BRK instruction

Interrupt edge selection register

16

(INTEDGE : address 003A

)

INT0 active edge selection bit
INT

1

active edge selection bit
Not used (returns “0” when read)
INT

2

active edge selection bit
INT

3

active edge selection bit
INT

4

active edge selection bit
Not used (returns “0” when read)

Interrupt request register 1
(IREQ1 : address 003C

16

)

INT0 interrupt request bit
INT

1

interrupt request bit

Serial I/O1 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit

Reset

0 : Falling edge active
1 : Rising edge active

b7 b0

Interrupt request

Interrupt request register 2
(IREQ2 : address 003D

CNTR0 interrupt request bit
CNTR

1

interrupt request bit
Serial I/O2 interrupt request bit
INT2 interrupt request bit
INT

3

interrupt request bit

INT

4

interrupt request bit
AD converter interrupt request bit
Not used (returns “0” when read)

0 : No interrupt request issued
1 : Interrupt request issued

16

)

b7 b0

Interrupt control register 1
(ICON1 : address 003E

INT0 interrupt enable bit
INT

1

interrupt enable bit
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit

Fig. 7 Structure of interrupt-related registers

b7 b0

16

)

Interrupt control register 2
(ICON2 : address 003F16)

CNTR0 interrupt enable bit
CNTR

1

interrupt enable bit
Serial I/O2 interrupt enable bit
INT

2

interrupt enable bit

INT

3

interrupt enable bit

INT

4

interrupt enable bit
AD converter interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)

0 : Interrupts disabled
1 : Interrupts enabled

15

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Timers

The 3802 group has four timers: timer X, timer Y, timer 1, and timer

2.
All timers are count down. When the timer reaches “00
derflow occurs at the next count pulse and the corresponding
timer latch is reloaded into the timer and the count is continued.
When a timer underflows, the interrupt request bit corresponding
to that timer is set to “1”.
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.

b7

b0

Timer XY mode register
(TM : address 002316)

Timer X operating mode bit

b1b0

0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode

CNTR0 active edge switch bit

0: Interrupt at falling edge

Count at rising edge in event

counter mode

1: Interrupt at rising edge

Count at falling edge in event

counter mode

Timer X count stop bit

0: Count start
1: Count stop

Timer Y operating mode bit

b4b5

0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode

CNTR1 active edge switch bit

0: Interrupt at falling edge

Count at rising edge in event
counter mode

1: Interrupt at rising edge

Count at falling edge in event
counter mode

Timer Y count stop bit

0: Count start
1: Count stop

16”, an un-

Timer 1 and Timer 2

The count source of prescaler 12 is the oscillation frequency di­vided by 16. The output of prescaler 12 is counted by timer 1 and
timer 2, and a timer underflow sets the interrupt request bit.

Timer X and Timer Y

Timer X and Timer Y can each be selected in one of four operating
modes by setting the timer XY mode register.

Timer Mode

The timer counts f(X

Pulse Output Mode

Timer X (or timer Y) counts f(X
the timer reach “00
CNTR

1) pin is inverted. If the CNTR0 (or CNTR1) active edge

switch bit is “0”, output begins at “ H”.
If it is “1”, output starts at “L”. When using a timer in this mode, set
the corresponding port P5
put mode.

Event Counter Mode

Operation in event counter mode is the same as in timer mode,
except the timer counts signals input through the CNTR
CNTR

1 pin.

Pulse Width Measurement Mode

If the CNTR
counts at the oscillation frequency divided by 16 while the CNTR
(or CNTR1) pin is at “H”. If the CNTR0 (or CNTR1) active edge
switch bit is “1”, the count continues during the time that the
CNTR

0 (or CNTR1) pin is at “L”.

In all of these modes, the count can be stopped by setting the
timer X (timer Y) count stop bit to “1”. Every time a timer
underflows, the corresponding interrupt request bit is set.

IN)/16 in timer mode.

IN)/16. Whenever the contents of

16”, the signal output from the CNTR0 (or

4 ( or port P55) direction register to out-

0 or

0 (or CNTR1) active edge selection bit is “0”, the timer

0

Fig. 8 Structure of timer XY register

16

Oscillator Divider

f(X

P54/CNTR0 pin

Port P5

direction register

IN

) 1/16

CNTR
edge switch bit

“0”
“1”

4

Pulse output
mode

0

active

Port P5
latch

Pulse width
measurement
mode

Event
counter
mode

0

CNTR
edge switch
bit

4

active

Timer mode
Pulse output
mode

Timer X count stop bit

Q

“1”

“0”

Toggle flip- flop T

Q

Data bus

Prescaler X latch (8)

Prescaler X (8)

R

Data bus

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Timer X latch (8)

Timer X (8)

Timer X latch write pulse
Pulse output mode

To timer X interrupt
request bit

0

To CNTR

interrupt

request bit

P55/CNTR1 pin

Port P5

direction register

CNTR1 active
edge switch bit

“0”
“1”

5

Pulse output
mode

Port P5
latch

Pulse width
measurement
mode

Event
counter
mode

1

CNTR
edge switch
bit

5

active

Timer mode
Pulse output
mode

Timer Y count stop bit

Q

“1”

“0”

Prescaler

12 latch (8)

Toggle flip- flop T

Q

Prescaler Y latch (8)

Prescaler Y (8)

R

Data bus

Timer Y latch (8)

Timer Y (8)

Timer Y latch write pulse
Pulse output mode

Timer 2 latch (8) Timer 1 latch (8)

To timer Y interrupt
request bit

To CNTR

1

request bit

interrupt

Prescaler 12 (8)

Fig. 9 Block diagram of timer X, timer Y, timer 1, and timer 2

Timer 2 (8)Timer 1 (8)

To timer 2 interrupt
request bit

To timer 1 interrupt
request bit

17

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Serial I/O1

Serial I/O1 can be used as either clock synchronous or asynchro­nous (UART) serial I/O. A dedicated timer is also provided for
baud rate generation.

Data bus

Address 0018

Shift clock

Serial I/O1 synchronous
clock selection bit
Frequency division ratio 1/(n+1)

Transmit shift register

Transmit buffer

Data bus

P44/RXD

P46/SCLK1

f(XIN)

XIN

7/SRDY1

P4

5/TXD

P4

Receive shift register

BRG count source selection bit

1/4

F/F

Falling-edge detector

Receive buffer

Clock synchronous serial I/O mode

Clock synchronous serial I/O1 mode can be selected by setting
the mode selection bit of the serial I/O1 control register to “1”.
For clock synchronous serial I/O1, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB (address 0018

16

Clock control circuit

Baud rate generator

Address 001C

16

Clock control circuit

Shift clock

Address 0018

16

Serial I/O1 control register

Receive buffer full flag (RBF)

Receive interrupt request (RI)

1/4

Transmit interrupt source selection bit

Transmit buffer empty flag (TBE)

Serial I/O1 status register

Address 001A

Transmit shift completion flag (TSC)

Transmit interrupt request (TI)

Address 0019

16).

16

16

Fig. 10 Block diagram of clock synchronous serial I/O1

Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)

Serial output TxD

Serial input RxD

Receive enable signal S

Write pulse to receive/transmit
buffer (address 0018

Notes

1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer has emptied (TBE=1) or after the

transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1

control register.

2 : If data is written to the transmit buffer when TSC=0, the transmit clock is generated continuously and serial data is
3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .

RDY1

16

)

output continuously from the TxD pin.

TBE = 0

TBE = 1
TSC = 0

D

0

D

D

0

D

Fig. 11 Operation of clock synchronous serial I/O1 function

D

1

D

2

1

D

2

D

3

D

4

D

5

D

6

D

3

D

4

D

5

D

6

7

D

7

RBF = 1
TSC = 1

Overrun error (OE)
detection

18

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Asynchronous serial I/O (UART) mode

Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O mode selection bit of the serial I/O control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the

Data bus

P4

P4

4/RXD

6/SCLK1

P4

f(XIN)

5/TXD

Address 0018

OE

Character length selection bit

STdetector

BRG count source selection bit

1/4

7 bits
8 bits

Serial I/O1 synchronous clock selection bit

Character length selection bit

16

Receive buffer

Receive shift register

PE FE

SP detector

Frequency division ratio 1/(n+1)

Baud rate generator

Address 001C16

ST/SP/PA generator

Transmit shift register

Transmit buffer

Data bus

two buffers have the same address in memory. Since the shift reg­ister cannot be written to or read from directly, transmit data is
written to the transmit buffer, and receive data is read from the re­ceive buffer.
The transmit buffer can also hold the next data to be transmitted,
and the receive buffer can hold a character while the next charac­ter is being received.

Serial I/O1 control register

Receive buffer full flag (RBF)
Receive interrupt request (RI)

Clock control circuit

1/16

Transmit interrupt source selection bit

Address

001816

Serial I/O1 status register

Address 001A

1/16

16

UART control register

Address 001B

Transmit shift completion flag (TSC)

Transmit interrupt request (TI)

Transmit buffer empty flag (TBE)

Address

16

001916

Fig. 12 Block diagram of UART serial I/O

19

Transmit or receive clock

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Transmit buffer write

Receive buffer read

signal

TBE=0 TBE=0

TSC=0
TBE=1

Serial output TXD

signal

X

Serial input R

Notes

D

1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception).
2: The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes "1", depending on the setting of the transmit interrupt

source selection bit (TIC) of the serial I/O control register.

3: The receive interrupt (RI) is set when the RBF flag becomes "1".
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.

ST SP

D

0

D

1

1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)

ST

D

0

D

1

Fig. 13 Operation of UART serial I/O function

Serial I/O1 control register (SIO1CON) 001A16

The serial I/O control register consists of eight control bits for the
serial I/O function.

UART control register (UARTCON) 001B16

The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer. One bit in this register (bit 4) is
always valid and sets the output structure of the P4

5/TXD pin.

Serial I/O1 status register (SIO1STS) 001916

The read-only serial I/O1 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer, and
the receive buffer full flag is set. A write to the serial I/O status reg­ister clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, re-

TBE=1

ST

SP

RBF=1

ST

SP D

D

0

D

1

✽

Generated at 2nd bit in 2-stop-bit mode

RBF=0

D

1

0

TSC=1

RBF=1

SP

✽

spectively). Writing “0” to the serial I/O enable bit SIOE (bit 7 of
the Serial I/O Control Register) also clears all the status flags, in­cluding the error flags.
All bits of the serial I/O1 status register are initialized to “0” at re­set, but if the transmit enable bit (bit 4) of the serial I/O control reg­ister has been set to “1”, the transmit shift completion flag (bit 2)
and the transmit buffer empty flag (bit 0) become “1”.

Transmit buffer/Receive buffer register (TB/
RB) 0018

The transmit buffer and the receive buffer are located at the same

address. The transmit buffer is write-only and the receive buffer is
read-only. If a character bit length is 7 bits, the MSB of data stored
in the receive buffer is “0”.

16

Baud rate generator (BRG) 001C16

The baud rate generator determines the baud rate for serial trans­fer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate genera­tor.

20

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

b7

b0

Serial I/O1 status register
(SIO1STS : address 0019

16

)

b7

Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty

Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full

Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed

Overrun error flag (OE)
0: No error
1: Overrun error

Parity error flag (PE)
0: No error
1: Parity error

Framing error flag (FE)
0: No error
1: Framing error

Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1

Not used (returns "1" when read)

b0

Serial I/O1 control register
(SIO1CON : address 001A16)

BRG count source selection bit (CSS)
0: f(X

IN

)

1: f(X

IN

)/4

Serial I/O1 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O is selected, BRG output divided by 16
when UART is selected.
1: External clock input when clock synchronous serial
I/O is selected, external clock input divided by 16
when UART is selected.

S

RDY1

output enable bit (SRDY)

0: P4

7

pin operates as ordinaly I/O pin

1: P4

7

pin operates as S

RDY1

output pin

Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed

Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled

Receive enable bit (RE)
0: Receive disabled
1: Receive enabled

Serial I/O1 mode selection bit (SIOM)
0: Asynchronous serial I/O (UART)
1: Clock synchronous serial I/O

b7

b0

UART control register
(UARTCON : address 001B

Character length selection bit (CHAS)
0: 8 bits
1: 7 bits

16

)

Serial I/O enable bit (SIOE)
0: Serial I/O disabled
(pins P4

4

to P47 operate as ordinary I/O pins)

1: Serial I/O enabled
(pins P4

4

to P47 operate as serial I/O pins)

Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled

Parity selection bit (PARS)
0: Even parity
1: Odd parity

Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits

P4

5/TX

D P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)

Not used (return "1" when read)

Fig. 14 Structure of serial I/O control registers

21

Serial I/O2

Serial I/O2 control register
(SIO2CON : address 001D

16

)

b7

Internal synchronous clock selection bits
0 0 0: f(XIN)/8

0 0 1: f(X

IN

)/16

0 1 0: f(X

IN

)/32

0 1 1: f(X

IN

)/64

1 1 0: f(X

IN

)/128

1 1 1: f(X

IN

)/256

Serial I/O2 port selection bit (SM2

3

)
0: I/O port
1: S

OUT2,SCLK2

output pin

S

RDY2

output enable bit (SM24)
0: I/O port
1: S

RDY2

output pin

Transfer direction selection bit (SM2

5

)
0: LSB first
1: MSB first

Serial I/O2 synchronous clock selection bit (SM2

6

)
0: External clock
1: Internal clock

P5

1/SOUT2

P-channel output disable bit
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode)

b0

b2 b1 b0

The serial I/O2 function can be used only for clock synchronous
serial I/O.
For clock synchronous serial I/O the transmitter and the receiver
must use the same clock. If the internal clock is used, transfer is
started by a write signal to the serial I/O2 register.

Serial I/O2 control register (SIO2CON) 001D16

The serial I/O2 control register contains seven bits which control
various serial I/O functions.

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Fig. 15 Structure of serial I/O2 control register

1/8
1/16

X

IN

P53 latch

S

RDY2

P52 latch

P5

"0"

"1"

"0"

"0"

"1"

output enable bit

1

latch

"1"

P53/S

RDY2

P52/S

CLK2

Serial I/O2 port selection bit

Fig. 16 Block diagram of serial I/O2 function

P51/S

P50/S

OUT2

Serial I/O2 port selection bit

IN2

Serial I/O2 synchronous

S

RDY2

clock selection bit

Synchronization circuit

CLK2

S

External clock

1/32
1/64

Divider

1/128
1/256

"1"

"0"

Serial I/O counter 2 (3)

Serial I/O shift register 2 (8)

Internal synchronous
clock selection bits

Data bus

Serial I/O2
interrupt request

22

Transfer clock (Note 1)

Serial I/O2 register

write signal

Serial I/O2 output S

Serial I/O2 input SIN2

Receive enable signal SRDY2

Notes

OUT2

1: When the internal clock is selected as the transfer clock, the divide ratio can be selected by setting bits 0 to 2 of the serial

I/O2 control register.

2: When the internal clock is selected as the transfer clock, the S

D2

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(Note 2)

D3 D4 D5 D6

Serial I/O2 interrupt request bit set

OUT2 pin goes to high impedance after transfer completion.

D7D0 D1

Fig. 17 Timing of serial I/O2 function

23

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

PULSE WIDTH MODULATION (PWM)

The 3802 group has a PWM function with an 8-bit resolution,
based on a signal that is the clock input X
vided by 2.

IN or that clock input di-

Data Setting

The PWM output pin also functions as port P56. Set the PWM pe­riod by the PWM prescaler, and set the period during which the
output pulse is an “H” by the PWM register.
If the value in the PWM prescaler is n and the value in the PWM
register is m (where n = 0 to 255 and m = 0 to 255) :
PWM period = 255 ✕ (n+1)/f(X

= 51 ✕ (n+1) µs (when X

Output pulse “H” period = PWM period ✕ m/255

IN)

IN = 5 MHz)

= 0.2 ✕ (n+1) ✕ m µs

(when X

IN = 5 MHz)

PWM Operation

When bit 0 (PWM enable bit) of the PWM control register is set to
“1”, operation starts by initializing the PWM output circuit, and
pulses are output starting at an “H”.
If the PWM register or PWM prescaler is updated during PWM
output, the pulses will change in the cycle after the one in which
the change was made.

51 ✕ m ✕ (n+1)

255

PWM output

T = [51 ✕ (n+1)] µs

m: Contents of PWM register
n : Contents of PWM prescaler
T : PWM cycle (when X

Fig. 18 Timing of PWM cycle

IN

= 5 MHz)

µs

Data bus

prescaler pre-latch

Count source
selection bit

1/2

“0”

“1”

XIN

Fig. 19 Block diagram of PWM function

PWM

Transfer control circuit

PWM

prescaler latch

PWM prescaler

PWM

register pre-latch

PWM

register latch

PWM register

Port P56 latch

PWM enable bit

Port P5

6

24

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

b7

b0

PWM control register
(PWMCON : address 002B

PWM function enable bit

0: PWM disabled
1: PWM enabled

Count source selection bit

IN

)

0: f(X
1: f(X

IN

)/2

Not used (return “0” when read)

Fig. 20 Structure of PWM control register

PWM output

PWM register
write signal

16

)

C

B

=

T2

ABC

T

(Changes from “A” to “B” during “H” period)

T

T

T2

PWM prescaler
write signal

When the contents of the PWM register or PWM prescaler have changed, the PWM
output will change from the next period after the change.

(Changes from “T” to “T2” during PWM period)

Fig. 21 PWM output timing when PWM register or PWM prescaler is changed

25

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

A-D Converter

The functional blocks of the A-D converter are described below.

[A-D conversion register]

The A-D conversion register is a read-only register that stores the
result of an A-D conversion. When reading this register during an
A-D conversion, the previous conversion result is read.

[AD/DA control register]

The AD/DA control register controls the A-D conversion process.
Bits 0 to 2 select a specific analog input pin. Bit 3 signals the
completion of an A-D conversion. The value of this bit remains at
“0” during an A-D conversion, and changes to “1” when an A-D
conversion ends. Writing “0” to this bit starts the A-D conversion.
Bits 6 and 7 are used to control the output of the D-A converter.

[Comparison voltage generator]

The comparison voltage generator divides the voltage between
AV

SS and VREF into 256, and outputs the divided voltages.

[Channel selector]

The channel selector selects one of the ports P60/AN0 to P67/AN7,
and inputs the voltage to the comparator.

[Comparator and Control circuit]

The comparator and control circuit compares an analog input volt­age with the comparison voltage, then stores the result in the A-D
conversion register. When an A-D conversion is complete, the
control circuit sets the AD conversion completion bit and the AD
interrupt request bit to “1”.
Note that the comparator is constructed linked to a capacitor, so
set f(X

IN) to 500 kHz or more during an A-D conversion.

b7

b0

AD/DA control register
(ADCON : address 0034

Analog input pin selection bits

b2 b1 b0

0 0 0: P6
0 0 1: P61/AN1
0 1 0: P62/AN2
0 1 1: P63/AN3
1 0 0: P64/AN4
1 0 1: P65/AN5
1 1 0: P66/AN6
1 1 1: P67/AN7

AD conversion completion bit
0: Conversion in progress
1: Conversion completed

Not used (return "0" When read)
DA

0: DA
1: DA

DA
0: DA
1: DA

0/AN0

1 output enable bit

1 output disabled
1 output enabled

2 output enable bit

2 output disabled
2 output enabled

16)

AD/DA control register

(Address 0034

P60/AN
P61/AN
P62/AN
P63/AN
P64/AN
P65/AN
P66/AN
P67/AN

16

0
1
2
3
4
5
6
7

Fig. 23 Block diagram of A-D converter

b7 b0

)

3

Comparator

Channel selector

Fig.22 Structure of AD/DA control register

Data bus

A-D control circuit

A-D conversion register

Resistor ladder

REF

V

8

AV

SS

A-D interrupt request

(Address 0035

16

)

26

D-A Converter

The 3802 group has two internal D-A converters (DA1 and DA2)
with 8-bit resolutions.
The D-A converter is performed by setting the value in the D-A
conversion register. The result of D-A converter is output from the
DA

1 or DA2 pin by setting the DA output enable bit to “1”.

When using the D-A converter, the corresponding port direction
register bit (P3
tus).
The output analog voltage V is determined by the value n (base

10) in the D-A conversion register as follows:

V = V

REF ✕ n/256 (n = 0 to 255)

Where V

At reset, the D-A conversion registers are cleared to “0016”, the DA
output enable bits are cleared to “0”, and the P3
DA

2 pins are set to input (high impedance).

The D-A output is not buffered, so connect an external buffer when
driving a low-impedance load.
Set V

CC to 3.0 V or more when using the D-A converter.

0/DA1 or P31/DA2) should be set to “0” (input sta-

REF is the reference voltage.

0/DA1 and P31/

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

D-A1 conversion register (8)

DA

1

output enable bit

R-2R resistor ladder

Data bus

D-A2 conversion register (8)

DA

R-2R resistor ladder

2

P30/DA

1

output enable bit

P3

1

/DA

2

1

output enable bit

DA

"0"

P30/DA1

D-A1 conversion
register

AV

SS

V

REF

Fig. 25 Equivalent connection circuit of D-A converter

"1"

MSB

"0"

2R

"1"

R

2R

Fig. 24 Block diagram of D-A converter

R

2R

R

2R

R

R

2R

R

2R

R

2R 2R

LSB

2R

27

Reset Circuit

To reset the microcomputer, the RESET pin should be held at an
“L” level for 2 µs or more. Then the RESET pin is returned to an “H”
level (the power source voltage should be between 4.0 V and 5.5
V), reset is released. Internal operation begin until after 8 to 13 X
clock cycles are completed. After the reset is completed, the pro­gram starts from the address contained in address FFFD
order byte) and address FFFC

16 (low-order byte).

Make sure that the reset input voltage is less than 0.6 V for V

3.0 V (Extended operating temperature version : the reset input
voltage is less than 0.8 V for V

CC of 4.0 V).

4.0V

Power source

voltage

Reset input

voltage

0V

0V

1

M51953AL

3

5

4

0.1 µ F

0.8V

V

CC

RESET

SS

V

3802 group

Fig. 26 Example of reset circuit

16 (high-

CC of

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Address

(1)

Port P0 direction register

(2)

IN

Port P1 direction register

(3)

Port P2 direction register

(4)

Port P3 direction register

(5)

Port P4 direction register

(6)

Port P5 direction register

(7)

Port P6 direction register
Serial I/O1 status register

(8)
(9)

Serial I/O1 control register

(10)

UART control register

(11)

Serial I/O2 control register

(12)

Prescaler 12

(13)

Timer 1
Timer 2

(14)
(15)

Timer XY mode register

(16)

Prescaler X

(17)

Timer X

(18)

Prescaler Y

(19)

Timer Y

(20)

PWM control register

(21)

AD/DA control register

(22)

D-A1 conversion register
D-A2 conversion register

(23)
(24)

Interrupt edge selection register

(25)

CPU mode register
Interrupt request register 1

(26)

Interrupt request register 2

(27)

Interrupt control register 1

(28)
(29)

Interrupt control register 2

(30)

Processor status register
Program counter

(31)

(000116) · · ·
(0003

(0005
(0007
(0009
(000B

(000D
(0019

(001A
(001B

(001D
(0020
(0021
(0022

(0023
(0024

(0025
(0026

(0027
(002B
(0034
(0036

(0037
(003A

(003B
(003C
(003D
(003E
(003F16) · · ·

Register contents

16) · · ·

16) · · ·

16) · · ·

16) · · ·

16) · · ·

16) · · ·

16) · · ·

100000 00

16) · · ·

16) · · ·

111000 00

16) · · ·

16) · · ·

16) · · ·

16) · · ·

16) · · ·

16) · · ·

16) · · ·

16) · · ·

16) · · ·

16) · · ·

16) · · ·

000010 00

16) · · ·

16) · · ·

16) · · ·

000000 0

16) · · ·

16) · · ·

16) · · ·

16) · · ·

✕✕✕✕✕1✕✕

(PS)

Contents of address FFFD16

H)

(PC

Contents of address FFFC16

(PC

L)

0016
0016
0016
0016
0016
00
0016

0016

0016
FF16

0116
FF16
0016
FF16
FF16
FF16
FF16
0016

0016
0016
0016

0016
0016
0016
0016

16

✽

28

Note. ✕ : Undefined
✽ : The initial values of CM

CNV

SS pin.

The contents of all other registers and RAM are undefined
after a reset, so they must be initialized by software.

1 are determined by the level at the

Fig. 27 Internal status of microcomputer after reset

X

RESET

RESET

OUT

(internal reset)

SYNC

Address

Data

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

IN

φ

ADH, AD

?

XIN: 8 to 13 clock cycles

?

?

?

?

Notes

??

??

1: f(XIN) and f(φ) are in the relationship: f(XIN)=2 • f(φ).
2: A question mark (?) indicates an undefined status that depends on the previous status.

?

FFFC FFFD

?

?

AD

AD

L

L

Reset address from the vector table

H

Fig. 28 Timing of reset

29

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Clock Generating Circuit

An oscillation circuit can be formed by connecting a resonator be­tween X

IN and XOUT. To supply a clock signal externally, input it to

the X

IN pin and make the XOUT pin open.

Oscillation control

Stop Mode

If the STP instruction is executed, the internal clock φ stops at an
“H”. Timer 1 is set to “01
Oscillator restarts when an external interrupt is received, but the
internal clock φ remains at an “H” until timer 1 underflow.
This allows time for the clock circuit oscillation to stabilize.
If oscillator is restarted by a reset, no wait time is generated, so
keep the RESET pin at an “L” level until oscillation has stabilized.

Wait Mode

If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator itself does not stop. The internal clock
restarts if a reset occurs or when an interrupt is received.
Since the oscillator does not stop, normal operation can be started
immediately after the clock is restarted.
To ensure that interrupts will be received to release the STP or
WIT state, interrupt enable bits must be set to “1” before the STP
or WIT instruction is executed.

16” and prescaler 12 is set to “FF16”.

When the STP status is released, prescaler 12 and timer 1 will
start counting and reset will not be released until timer 1
underflows, so set the timer 1 interrupt enable bit to “0” before the
STP instruction is executed.

XIN XOUT

CIN

COUT

Fig. 29 Ceramic resonator circuit

Interrupt request

Interrupt disable
flag (I)

Reset

Single-chip mode

X

IN

STP instruction

ONW pin

Rf

X

OUT

SQ

R

1/2

Rd

XIN XOUT

External oscillation
circuit

Fig. 30 External clock input circuit

S

Q

WIT
instruction

ONW
control

1/8

R

Prescaler 12

FF

16

01

Q

Timer 1

16

Vcc
Vss

S

STP instruction

R

Internal clock φ

Open

Reset

φ output

Reset or STP instruction

Fig. 31 Block diagram of clock generating circuit

30

Processor Modes

Single-chip mode, memory expansion mode, and microprocessor
mode can be selected by changing the contents of the processor
mode bits CM
memory expansion mode and microprocessor mode, memory can
be expanded externally through ports P0 to P3. In these modes,
ports P0 to P3 lose their I/O port functions and become bus pins.

Table 2. Functions of ports in memory expansion mode and

Port Name
Port P0
Port P1

Port P2

Port P3

Note: If CNVSS is connected to VSS, the microcomputer goes to

Single-Chip Mode

Select this mode by resetting the microcomputer with CNV
nected to V

Memory Expansion Mode

Select this mode by setting the processor mode bits to “01” in soft­ware with CNV
memory expansion while maintaining the validity of the internal
ROM. Internal ROM will take precedence over external memory if
addresses conflict.

0 and CM1 (bits 0 and 1 of address 003B16). In

microprocessor mode

Function
Outputs low-order byte of address.
Outputs high-order byte of address.
Operates as I/O pins for data D7 to D0
(including instruction codes).
P30 and P31 function only as output pins
(except that the port latch cannot be read).
P32 is the ONW input pin.
P33 is the RESETOUT output pin. (Note)
P34 is the φ output pin.
P35 is the SYNC output pin.
P36 is the WR output pin, and P37 is the
RD output pin.

single-chip mode after a reset, so this pin cannot be used
as the RESETOUT output pin.

SS con-

SS.

SS connected to VSS. This mode enables external

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

000016
0008

16

SFR area

16

0040

Internal RAM
reserved area

0440

16

✽

16

YYYY
FFFF

Fig. 32 Memory maps in various processor modes

Fig. 33 Structure of CPU mode register

Internal ROM

16

Memory expansion mode

The shaded areas are external memory areas.

✽

:

YYYY16 is the start address of internal ROM.

b7

b0

CPU mode register
(CPUM : address 003B

000016

16

0008
0040

0440

FFFF

Processor mode bits

b1 b0

0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Microprocessor mode
1 1 : Not available

Stack page selection bit
0 : 0 page
1 : 1 page

Not used (return “0” when read)

SFR area

16

Internal RAM
reserved area

16

16

Microprocessor mode

16

)

Microprocessor Mode

Select this mode by resetting the microcomputer with CNV
nected to V
software with CNV
the internal ROM is no longer valid and external memory must be
used.

CC, or by setting the processor mode bits to “10” in

SS connected to VSS. In microprocessor mode,

SS con-

31

Bus control with memory expansion

The 3802 group has a built-in ONW function to facilitate access to
external memory and I/O devices in memory expansion mode or
microprocessor mode.
If an “L” level signal is input to the ONW pin when the CPU is in a
read or write state, the corresponding read or write cycle is ex­tended by one cycle of φ. During this extended period, the RD or
WR signal remains at “L”. This extension period is valid only for
writing to and reading from addresses 0000
0440

16 to FFFF16 in microprocessor mode, 044016 to YYYY16 in

memory expansion mode, and only read and write cycles are ex­tended.

16 to 000716 and

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

φ

AD15 to AD

0

RD

WR

ONW

✽ :

Period during which ONW input signal is received
During this period, the ONW signal must be fixed at either “H” or “L”. At all other times, the input level of the ONW
signal has no affect on operations.
The bus cycles is not extended for an address in the area 000816 to 043F
is received.

Fig. 34 ONW function timing

Read cycle Write cycle

Dummy cycle

Write cycle

Read cycle Dummy cycle

✽✽✽

16,

regardless of whether the ONW signal

32

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

NOTES ON PROGRAMMING
Processor Status Register

The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”. Af­ter a reset, initialize flags which affect program execution.
In particular, it is essential to initialize the index X mode (T) and
the decimal mode (D) flags because of their effect on calculations.

Interrupts

The contents of the interrupt request bits do not change immedi­ately after they have been written. After writing to an interrupt re­quest register, execute at least one instruction before executing a
BBC or BBS instruction.

Decimal Calculations

To calculate in decimal notation, set the decimal mode flag (D) to
“1”, then execute an ADC or SBC instruction. Only the ADC and
SBC instructions yield proper decimal results. After executing an
ADC or SBC instruction, execute at least one instruction before
executing a SEC, CLC, or CLD instruction.

In decimal mode, the values of the negative (N), overflow (V), and
zero (Z) flags are invalid.
The carry flag can be used to indicate whether a carry or borrow
has occurred. Initialize the carry flag before each calculation.
Clear the carry flag before an ADC and set the flag before an
SBC.

Timers

If a value n (between 0 and 255) is written to a timer latch, the fre­quency division ratio is 1/(n + 1).

Multiplication and Division Instructions

The index X mode (T) and the decimal mode (D) flags do not af­fect the MUL and DIV instruction.
The execution of these instructions does not change the contents
of the processor status register.

Ports

The contents of the port direction registers cannot be read.
The following cannot be used:

• The data transfer instruction (LDA, etc.)

• The operation instruction when the index X mode flag (T) is “1”

• The addressing mode which uses the value of a direction regis­ter as an index

• The bit-test instruction (BBC or BBS, etc.) to a direction register

• The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a
direction register

Use instructions such as LDM and STA, etc., to set the port direc­tion registers.

Serial I/O

In clock synchronous serial I/O, if the receive side is using an ex­ternal clock and it is to output the S
enable bit, the receive enable bit, and the S
to “1”.
Serial I/O1 continues to output the final bit from the T
transmission is completed. The S
high impedance after transmission is completed.

RDY1 signal, set the transmit

RDY1 output enable bit

XD pin after

OUT2 pin from serial I/O2 goes to

A-D Converter

The comparator uses internal capacitors whose charge will be lost
if the clock frequency is too low.
Make sure that f(X
sion. (If the ONW pin has been set to “L”, the A-D conversion will
take twice as long to match the longer bus cycle, and so f(X
must be at least 1 MHz.)
Do not execute the STP or WIT instruction during an A-D conver­sion.

IN) is at least 500 kHz during an A-D conver-

IN)

D-A Converter

The accuracy of the D-A converter becomes poor rapidly under
the V

CC = 3.0 V or less condition.

Instruction Execution Time

The instruction execution time is obtained by multiplying the fre­quency of the internal clock φ by the number of cycles needed to
execute an instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
The frequency of the internal clock φ is half of the X
When the ONW function is used in modes other than single-chip
mode, the frequency of the internal clock φ may be one fourth the
X

IN frequency.

IN frequency.

Memory Expansion Mode

The memory expansion mode is not available in the following mi­crocomputers.

• M38024M6-XXXSP

• M38024M6-XXXFP

Memory Expansion Mode and Microproces­sor Mode

Execute the LDM or STA instruction for writing to port P3 (address
0006

16) in memory expansion mode and microprocessor mode.

Set areas which can be read out and write to port P3 (address
0006

16) in a memory, using the read-modify-write instruction

(SEB, CLB).

33

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

DATA REQUIRED FOR MASK ORDERS

The following are necessary when ordering a mask ROM produc­tion:

1. Mask ROM Order Confirmation Form

2. Mark Specification Form

3. Data to be written to ROM, in EPROM form (three identical
copies)

ROM PROGRAMMING METHOD

The built-in PROM of the blank One Time PROM version and built­in EPROM version can be read or programmed with a general­purpose PROM programmer using a special programming
adapter. Set the address of PROM programmer in the user ROM
area.

Package

64P4B, 64S1B

64P6N

64D0

The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To en­sure proper operation after programming, the procedure shown in
Figure 35 is recommended to verify programming.

Name of Programming Adapter

PCA4738S-64A
PCA4738F-64A
PCA4738L-64A

Programming with PROM

programmer

Screening (Caution)
(150°C for 40 hours)

Verification with

PROM programmer

Functional check in

target device

Caution :

Fig. 35 Programming and testing of One Time PROM version

The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.

34

ABSOLUTE MAXIMUM RATINGS

Symbol

VCC

VI

VI
VI

VO

Pd
Topr
Tstg

Note: 300 mW in case of the flat package.

Power source voltage
Input voltage P00–P07, P10–P17, P20–P27,

Input voltage RESET, XIN
Input voltage CNVSS
Output voltage P00–P07, P10–P17, P20–P27,

Power dissipation
Operating temperature
Storage temperature

Parameter

P30–P37, P40–P47, P50–P57,
P60–P67,
VREF

P30–P37, P40–P47, P50–P57,
P60–P67,
XOUT

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Conditions Ratings

All voltages are based on VSS.
Output transistors are cut off.

Ta = 25 °C

MITSUBISHI MICROCOMPUTERS

3802 Group

Unit

–0.3 to 7.0

–0.3 to V

–0.3 to V

–0.3 to 13

–0.3 to V

1000 (Note)

–20 to 85

–40 to 125

CC +0.3

CC +0.3

CC +0.3

V

V

V
V

V

mW

°C
°C

RECOMMENDED OPERATING CONDITIONS (Vcc = 3.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)

3.0

4.0

2.0

3.0

0
0

0

Limits

Typ. Max.

5.0

5.0
0

V
VCC

0

VCC
VCC
VCC

0.2 VCC

0.2 VCC

0.16 V
–80
–80

–40
–40

–10

6 VCC–16

Symbol Parameter

VCC
VSS
VREF
AVSS

VIA
VIH
VIH
VIL
VIL

VIL

ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)

IOH(peak)

IOL(peak)

IOH(avg)

IOL(avg)

f(XIN)

Note 1: The minimum power source voltage is [V] (f(XIN) = XMHz) on the condition of 2 MHz < f(XIN) < 8 MHz.

2: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an aver-

3: The peak output current is the peak current flowing in each port.
4: The average output current I

Power source voltage (f(XIN) < 2 MHz) (Note 1)
Power source voltage (f(XIN) = 8 MHz) (Note 1)
Power source voltage
Analog reference voltage (when A-D converter is used)
Analog reference voltage (when D-A converter is used)
Analog power source voltage
Analog input voltage AN0–AN7
“H” input voltage P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,

“H” input voltage RESET, XIN, CNVSS
“L” input voltage P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,

“L” input voltage RESET, CNVSS
“L” input voltage XIN
“H” total peak output current
“H” total peak output current P40–P47,P50–P57, P60–P67 (Note 2)
“L” total peak output current
“L” total peak output current P40–P47,P50–P57, P60–P67 (Note 2)
“H” total average output current
“H” total average output current P40–P47,P50–P57, P60–P67 (Note 2)
“L” total average output current
“L” total average output current P40–P47,P50–P57, P60–P67 (Note 2)
“H” peak output current P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,

“L” peak output current P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,

“H” average output current P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,

“L” average output current P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,

Internal clock oscillation frequency (VCC = 4.0 to 5.5 V)
Internal clock oscillation frequency (VCC = 3.0 to 4.0 V)

age value measured over 100 ms. The total peak current is the peak value of all the currents.

OL(avg), IOH(avg) in an average value measured over 100 ms.

P50–P57, P60–P67

P50–P57, P60–P67

P00–P07, P10–P17, P20–P27, P30–P37 (Note 2)

P00–P07, P10–P17, P20–P27, P30–P37 (Note 2)

P00–P07, P10–P17, P20–P27, P30–P37 (Note 2)

P00–P07, P10–P17, P20–P27, P30–P37 (Note 2)

P50–P57, P60–P67 (Note 3)

P50–P57, P60–P67 (Note 3)

P50–P57, P60–P67 (Note 4)

P50–P57, P60–P67 (Note 4)

X+16

6

Min.

AVSS

0.8 VCC

0.8 VCC

5.5

5.5

CC

80
80

40
40

10

–5

Unit

V
V
V
V

V
V

V
V
V

CC

V
mA
mA
mA
mA
mA
mA
mA
mA

mA

mA

mA

5

mA

8

MHz

35

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

ELECTRICAL CHARACTERISTICS (VCC = 3.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Symbol Parameter

“H” output voltage P00–P07, P10–P17, P20–P27,

VOH

P30–P37, P40–P47, P50–P57,
P60–P67 (Note 1)

“L” output voltage P00–P07, P10–P17, P20–P27,

VOL

P30–P37, P40–P47,P50–P57,
P60–P6

IOH = –10 mA
VCC = 4.0 to 5.5 V

IOH = –1.0 mA
VCC = 3.0 to 5.5 V

IOL = 10 mA
VCC = 4.0 to 5.5 V

7

IOL = 1.0 mA

Test conditions

Min.

VCC–2.0

VCC–1.0

VCC = 3.0 to 5.5 V

VT+ – VT–
VT+ – VT–
VT+ – VT–

Hysteresis CNTR0, CNTR1, INT0–INT
Hysteresis RXD, S

CLK1

, S

IN2

, S

Hysteresis RESET

4

CLK2

“H” input current P00–P07, P10–P17, P20–P27,

IIH

IIH
IIH

“H” input current RESET, CNV
“H” input current X

P30–P37, P40–P47, P50–P57,
P60–P6

7

SS

IN

VI = VCC

VI = VCC
VI = VCC

“L” input current P00–P07, P10–P17, P20–P27,

IIL

IIL
IIL
VRAM

“L” input current RESET, CNV
“L” input current X
RAM hold voltage

P30–P37, P40–P47, P50–P57,
P60–P67, RESET, CNV

SS

IN

SS

VI = VSS

VI = VSS
VI = VSS
When clock stopped
f(XIN) = 8 MHz, VCC = 5 V
f(XIN) = 5 MHz, VCC = 5 V
f(XIN) = 2 MHz, VCC = 3 V

When WIT instruction is executed with

ICC

Power source current

f(Xin) = 8MHz,V
When WIT instruction is executed with

f(Xin) = 5MHz,V

CC=5V

CC=5V

When WIT instruction is executed with

Note 1: P4

f(Xin) = 2MHz,V

When STP instruction
is executed with clock
stopped, output
transistors isolated.

5 is measured when the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.

CC=3V

Ta = 25 °C
(Note 2)

Ta = 85 °C
(Note 2)

P51 is measured when the P51/SOUT2 P-channel output disable bit of the serial I/O2 control register (bit 7 of address 001D16) is “0”.

2: With output transistors isolated and A-D converter having completed conversion, and not including current flowing through VREF pin.

Limits

Typ. Max.

0.4

0.5

0.5

4

–4

2.0

6.4
4

0.8

1.5

1

0.2

0.1

2.0

1.0

5.0

5.0

–5.0

–5.0

5.5
13

2.0

10

Unit

V

V

V
V
V

µA

µA
µA

µA

µA
µA

V

8

mA

1

µA

A–D CONVERTER CHARACTERISTICS

(VCC = 3.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 2.0 V to VCC, Ta = –20 to 85 °C, unless otherwise noted)

Symbol Parameter Unit

Resolution

—

Absolute accuracy (excluding quantization error)

—
tCONV
RLADDER
IVREF
II(AD)

Note: When D-A conversion registers (addresses 0036

Conversion time
Ladder resistor
Reference power source input current (Note)
A-D port input current

16 and 003716) contain “0016”.

Test conditions

VREF = 5.0 V 50

Min.

36

Limits
Typ. Max.

±1

±2.5

35

150

0.5

200

5.0

8

50

Bits

LSB

C(φ)

t

kΩ

µA
µA

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

D-A CONVERTER CHARACTERISTICS

(VCC = 3.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 3.0 V to VCC, Ta = –20 to 85 °C, unless otherwise noted)

Symbol Parameter

—

—

su

t
RO
IVREF

Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “00

rents flowing through the A-D resistance ladder.

Resolution
Absolute accuracy
Setting time

Output resistor
Reference power source input current (Note)

VCC = 4.0 to 5.5 V
VCC = 3.0 to 4.0 V

Test conditions

Min.

Limits

1

Typ. Max.

1.0

2.5

2.5

3.2

16”, and excluding cur-

Unit

8

Bits

%

3

µs

4

kΩ
mA

37

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

TIMING REQUIREMENTS 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

125

50
50

200

80
80
80
80

800

370
400
370
400
220
200
100
200

2

Limits

Typ. Max.

Unit

µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Symbol Parameter

tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twH(INT)
twL(CNTR)
twL(INT)
tc(SCLK1)
tc(SCLK2)
twH(SCLK1)
twH(SCLK2)
twL(SCLK1)
twL(SCLK2)
t

su(RXD–S

t

su(S

IN2–SCLK2

t

h(S

CLK1–RX

t

h(S

CLK2–SIN2

Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
INT0 to INT4 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT4 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O2 clock input cycle time
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O2 clock input “H” pulse width
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O2 clock input “L” pulse width
Serial I/O1 input set up time

CLK1

)

Serial I/O2 input set up time

)

Serial I/O1 input hold time

D)

Serial I/O2 input hold time

)

Min.

1000

Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1”. Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0”.

TIMING REQUIREMENTS 2 (VCC = 3.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

500
230
230
230
230

950
950
950
950
400
400
200
300

Limits

2

Typ. Max.

Unit

µs
ns

ns

ns
ns

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Symbol Parameter

tw(RESET)
tc(XIN)

twH(XIN)

twL(XIN)
tc(CNTR)

twH(CNTR)
twH(INT)
twL(CNTR)
twL(INT)
tc(SCLK1)
tc(SCLK2)
twH(SCLK1)
twH(SCLK2)
twL(SCLK1)
twL(SCLK2)
t

su(RXD–S

t

su(S

IN2–SCLK2

t

h(S

CLK1–RX

t

h(S

CLK2–SIN2

Reset input “L” pulse width
External clock input cycle time

External clock input “H” pulse width

External clock input “L” pulse width

0, CNTR1 input cycle time

CNTR
CNTR0, CNTR1 input “H” pulse width
INT0 to INT4 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT4 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O2 clock input cycle time
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O2 clock input “H” pulse width
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O2 clock input “L” pulse width
Serial I/O1 input set up time

CLK1

)

Serial I/O2 input set up time

)

Serial I/O1 input hold time

D)

Serial I/O2 input hold time

)

Min.

500/

(3 VCC–8)

200/

(3 VCC–8)

200/

(3 VCC–8)

2000
2000

Note: When f(XIN) = 2 MHz and bit 6 of address 001A16 is “1”. Divide this value by four when f(XIN) = 2 MHz and bit 6 of address 001A16 is “0”.

38

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

SWITCHING CHARACTERISTICS 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Symbol Parameter

t

wH(SCLK1)

twH(SCLK2)
twL(SCLK1)
twL(SCLK2)
t

d(S

CLK1–TX

t

d(S

CLK2–SOUT2

t

v(S

CLK1–TX

t

v(S

CLK2–SOUT2

tr(SCLK1)
tf(SCLK1)
tr(SCLK2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)

Serial I/O1 clock output “H” pulse width
Serial I/O2 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)

D)

Serial I/O2 output delay time (Note 2)

)

Serial I/O1 output valid time (Note 1)

D)

Serial I/O2 output valid time (Note 2)

)

Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output rising time
Serial I/O2 clock output falling time
CMOS output rising time (Note 3)
CMOS output falling time (Note 3)

Test conditions

Fig. 36

Min.

t

c(S

CLK1

t

c(S

CLK2

t

c(S

CLK1

t

c(S

CLK2

Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.

2: When the P5
3: X

OUT pin is excluded.

1/SOUT2 P-channel output disable bit of the serial I/O2 control register (bit 7 of address 001D16) is “0”.

Limits

Typ. Max.

)/2–30
)/2–160
)/2–30
)/2–160

–30

0

10
10

140
200

30
30
30
40
30
30

Unit

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

SWITCHING CHARACTERISTICS 2 (VCC = 3.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Symbol Parameter

t

wH(SCLK1)

twH(SCLK2)
twL(SCLK1)
twL(SCLK2)
t

d(S

CLK1–TX

t

d(S

CLK2–SOUT2

t

v(S

CLK1–TX

t

v(S

CLK2–SOUT2

tr(SCLK1)
tf(SCLK1)
tr(SCLK2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)

Note1: When the P4

2: When the P5
3: X

Serial I/O1 clock output “H” pulse width
Serial I/O2 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)

D)

Serial I/O2 output delay time (Note 2)

)

Serial I/O1 output valid time (Note 1)

D)

Serial I/O2 output valid time (Note 2)

)

Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output rising time
Serial I/O2 clock output falling time
CMOS output rising time (Note 3)
CMOS output falling time (Note 3)

5/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.

1/SOUT2 P-channel output disable bit of the serial I/O2 control register (bit 7 of address 001D16) is “0”.

OUT pin is excluded.

Test conditions

Fig. 36

Min.

t

c(S

CLK1

t

c(S

CLK2

t

c(S

CLK1

t

c(S

CLK2

Limits

Typ. Max.

)/2–50
)/2–240
)/2–50
)/2–240

–30

0

20
20

350
400

50
50
50
50
50
50

Unit

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

39

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

TIMING REQUIREMENTS 1 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE

(VCC = 4.0 to 5.5 V, VSS = 0 V , Ta = –20 to 85 °C, unless otherwise noted)

–20
–20

60

–20

–20

65

0

0

Limits

Typ. Max.

Unit

ns
ns
ns
ns

ns

ns
ns

ns

Symbol Parameter

tsu(ONW–φ)
th(φ–ONW)
tsu(DB–φ)
th(φ–DB)
tsu

(ONW–RD)

tsu

(ONW–WR)

th(RD–ONW)
th(WR–ONW)

tsu(DB–RD)
th(RD–DB)

Before φ ONW input set up time
After φ ONW input hold time
Before φ data bus set up time
After φ data bus hold time
Before RD ONW input set up time

Before WR ONW input set up time
After RD ONW input hold time

After WR ONW input hold time
Before RD data bus set up time
After RD data bus hold time

Min.

SWITCHING CHARATERISTICS 1 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE

(VCC = 4.0 to 5.5 V, VSS = 0 V , Ta = –20 to 85 °C, unless otherwise noted)

6

6

3

15

0

0

10

0

Limits

Typ. Max.

c(XIN)

2t

20
10
25
10
20
10
10

5

20

t

c(XIN)

–15

t

c(XIN)

–20

5

5
15

40

45

20
10
70

65

200
200

Unit

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

ns

ns

ns

ns

ns
ns

ns
ns
ns

Symbol Parameter

c(φ)

t
twH(φ)
twL(φ)
td(φ–AH)
tv(φ–AH)
td(φ–AL)
tv(φ–AL)
td(φ–SYNC)
tv(φ–SYNC)
td(φ–WR)
tv(φ–WR)
td(φ–DB)
tv(φ–DB)

twL(RD)
twL(WR)

td(AH–RD)
td(AH–WR)

td(AL–RD)
td(AL–WR)

tv(RD–AH)
tv(WR–AH)

tv(RD–AL)
tv(WR–AL)

td(WR–DB)
tv(WR–DB)
t

d

(RESET–RESET

tv(φ–RESET)

φ clock cycle time
φ clock “H” pulse width
φ clock “L” pulse width

After φ AD15–AD8 delay time
After φ AD15–AD8 valid time
After φ AD7–AD0 delay time
After φ AD7–AD0 valid time
SYNC delay time
SYNC valid time
RD and WR delay time
RD and WR valid time
After φ data bus delay time
After φ data bus valid time
RD pulse width, WR pulse width
RD pulse width, WR pulse width

(When one-wait is valid)
After AD15–AD8 RD delay time

After AD15–AD8 WR delay time
After AD7–AD0 RD delay time

After AD7–AD0 WR delay time
After RD AD15–AD8 valid time

After WR AD15–AD8 valid time
After RD AD7–AD0 valid time

After WR AD7–AD0 valid time
After WR data bus delay time
After WR data bus valid time
RESETOUT output delay time (Note 1)

OUT

)

RESETOUT output valid time (Note 1)

Test conditions

Fig. 36

Min.

tc(XIN)–10
tc(XIN)–10

tc(XIN)–10

c(XIN)–10

3t

tc(XIN)–35

tc(XIN)–40

Note 1: The RESETOUT output goes “H” in sync with the rise of the φ clock that is anywhere between about 8 cycle and 13 cycles after

the RESET input goes “H”.

40

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

TIMING REQUIREMENTS 2 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE

(VCC = 3.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Symbol

tsu(ONW–φ)
th(φ–ONW)
tsu(DB–φ)
th(φ–DB)
tsu

(ONW–RD)

tsu

(ONW–WR)

th(RD–ONW)
th(WR–ONW)

tsu(DB–RD)
th(RD–DB)

Before φ ONW input set up time
After φ ONW input hold time
Before φ data bus set up time
After φ data bus hold time
Before RD ONW input set up time

Before WR ONW input set up time
After RD ONW input hold time

After WR ONW input hold time
Before RD data bus set up time
After RD data bus hold time

Parameter

SWITCHING CHARACTERISTICS 2 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE

(VCC = 3.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Symbol Parameter

t

c(φ)

twH(φ)
twL(φ)
td(φ–AH)
tv(φ–AH)
td(φ–AL)
tv(φ–AL)
td(φ–SYNC)
tv(φ–SYNC)
td(φ–WR)
tv(φ–WR)
td(φ–DB)
tv(φ–DB)

twL(RD)
twL(WR)

td(AH–RD)
td(AH–WR)

td(AL–RD)
td(AL–WR)

tv(RD–AH)
tv(WR–AH)

tv(RD–AL)
tv(WR–AL)

td(WR–DB)
tv(WR–DB)
t

d

(RESET–RESET

tv(φ–RESET)

Note1: The RESETOUT output goes “H” in sync with the fall of the φ clock that is anywhere between about 8 cycle and 13 cycles after

φ clock cycle time
φ clock “H” pulse width
φ clock “L” pulse width

After φ AD15–AD8 delay time
After φ AD15–AD8 valid time
After φ AD7–AD0 delay time
After φ AD7–AD0 valid time
SYNC delay time
SYNC valid time
RD and WR delay time
RD and WR valid time
After φ data bus delay time
After φ data bus valid time
RD pulse width, WR pulse width
RD pulse width, WR pulse width

(when one-wait is valid)
After AD15–AD8 RD delay time

After AD15–AD8 WR delay time
After AD7–AD0 RD delay time

After AD7–AD0 WR delay time
After RD AD15–AD8 valid time

After WR AD15–AD8 valid time
After RD AD7–AD0 valid time

After WR AD7–AD0 valid time
After WR data bus delay time
After WR data bus valid time

OUT

)

RESETOUT output delay time (Note 1)
RESETOUT output valid time (Note 1)

the RESET input goes “H”.

Test conditions

Fig. 36

Min.

tc(XIN)–20
tc(XIN)–20

10

10

3

15

tc(XIN)–20

c(XIN)–20

3t

tc(XIN)–145

tc(XIN)–145

5

5

10

0

Min.
–20
–20
180

–20

–20
185

0

0

Limits

Limits

Typ. Max.

Typ. Max.

c(XIN)

2t

150

15

150
15
40
20
15

7

200

10

10

195

300

300

25
15

Unit

ns
ns
ns
ns

ns

ns
ns

ns

Unit

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

ns

ns

ns

ns

ns
ns

ns

ns
ns

41

MITSUBISHI MICROCOMPUTERS

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

ABSOLUTE MAXIMUM RATINGS (Extended operating temperature version)

Symbol Parameter Conditions Ratings

VCC

VI

VI
VI

VO

Pd
Topr
Tstg

Power source voltage
Input voltage P0

Input voltage RESET, XIN
Input voltage CNVSS
Output voltage P00–P07, P10–P17, P20–P27,

Power dissipation
Operating temperature
Storage temperature

0–P07, P10–P17, P20–P27,

P30–P37, P40–P47, P50–P57,
P60–P67,
VREF

P30–P37, P40–P47, P50–P57,
P60–P67,
XOUT

All voltage are based on VSS.
Output transistors are cut off.

Ta = 25 °C

–0.3 to 7.0

–0.3 to V

–0.3 to V

–0.3 to V

1000 (Note)

–65 to 150

3802 Group

Unit

CC +0.3

CC +0.3

–0.3 to 13

CC +0.3

mW

–40 to 85

°C
°C

V

V

V
V

V

RECOMMENDED OPERATING CONDITIONS (Extended operating temperature version)

(VCC = 4.0 to 5.5 V, Ta = –40 to 85 °C, unless otherwise noted)

4.0

2.0

4.0

0
0

0

Limits

Typ. Max.

5.0
0

V
VCC

0

VCC
VCC
VCC

0.2 VCC

0.2 VCC

0.16 V
–80
–80

–40
–40

–10

5.5

CC

80
80

40
40

10

–5

Unit

V
V

V
V

V
V
V
V
V

CC

V
mA
mA
mA
mA
mA
mA
mA
mA

mA

mA

mA

5

mA

8

MHz

Symbol Parameter

VCC
VSS

VREF
AVSS

VIA
VIH
VIH
VIL
VIL

VIL

ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)

IOH(peak)

IOL(peak)

IOH(avg)

IOL(avg)
f(XIN)

Note 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an aver-

2: The peak output current is the peak current flowing in each port.
3: The average output current IOL(avg), IOH(avg) in an average value measured over 100 ms.

Power source voltage (f(XIN) ≤ 2 MHz)
Power source voltage
Analog reference voltage (when A-D converter is used)
Analog reference voltage (when D-A converter is used)
Analog power source voltage
Analog input voltage AN0–AN7
“H” input voltage P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,

“H” input voltage RESET, XIN, CNVSS
“L” input voltage P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,

“L” input voltage RESET, CNVSS
“L” input voltage XIN
“H” total peak output current
“H” total peak output current P40–P47,P50–P57, P60–P67 (Note 1)
“L” total peak output current
“L” total peak output current P40–P47,P50–P57, P60–P67 (Note 1)
“H” total average output current
“H” total average output current P40–P47,P50–P57, P60–P67 (Note 1)
“L” total average output current
“L” total average output current P40–P47,P50–P57, P60–P67 (Note 1)
“H” peak output current P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,

“L” peak output current P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,

“H” average output current P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,

“L” average output current P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,

Internal clock oscillation frequency (VCC = 4.0 to 5.5 V)

age value measured over 100 ms. The total peak current is the peak value of all the currents.

P50–P57, P60–P67

P50–P57, P60–P67

P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)

P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)

P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)

P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)

P50–P57, P60–P67 (Note 2)

P50–P57, P60–P67 (Note 2)

P50–P57, P60–P67 (Note 3)

P50–P57, P60–P67 (Note 3)

Min.

AVSS

0.8 VCC

0.8 VCC

42

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

ELECTRICAL CHARACTERISTICS (Extended operating temperature version)

(VCC = 4.0 to 5.5 V,

Symbol Parameter

Test conditions

“H” output voltage P00–P07, P10–P17, P20–P27,

VOH

P30–P37, P40–P47, P50–P57,

IOH = –10 mA

P60–P67 (Note 1)

“L” output voltage P00–P07, P10–P17, P20–P27,

VOL

VT+ – VT–
VT+ – VT–
VT+ – VT–

P30–P37, P40–P47,P50–P57,
P60–P6

7

Hysteresis CNTR0, CNTR1, INT0–INT
Hysteresis RXD, S

CLK1

, S

IN2

, S

CLK2

Hysteresis RESET

IOL = 10 mA

4

“H” input current P00–P07, P10–P17, P20–P27,

IIH

IIH
IIH

“H” input current
“H” input current X

P30–P37, P40–P47, P50–P57,
P60–P6

7

RESET

, CNV

SS

IN

VI = VCC

VI = VCC
VI = VCC

“L” input current P00–P07, P10–P17, P20–P27,

IIL

IIL
VRAM

“L” input current X

RAM hold voltage

P30–P37, P40–P47, P50–P57,
P60–P67, RESET, CNV

IN

SS

VI = VSS

VI = VSS
When clock stopped
f(XIN) = 8 MHz
f(XIN) = 5 MHz
When WIT instruction is executed

with f(XIN) = 8 MHz

ICC

Power source current

When WIT instruction is executed
with f(XIN) = 5 MHz

When STP instruction
is executed with clock
stopped, output
transistors isolated.

Note 1: P45 is measured when the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.

P51 is measured when the P51/SOUT2 P-channel output disable bit of the serial I/O2 control register (bit 7 of address 001D16) is “0”.

2: With output transistors isolated and A-D converter having completed conversion, and not including current flowing through VREF pin.

VSS = 0 V,

Ta = 25 °C
(Note 2)

Ta = 85 °C
(Note 2)

Ta = –40 to 85 °C, unless otherwise noted)

Limits

Min.

Typ. Max.

VCC–2.0

2.0

0.4

0.5

0.5

5.0

5.0

4

–5.0

–4

2.0

6.4

5.5
13

4

8

1.5

1

0.1

1

10

Unit

V

V

V
V
V

µA

µA
µA

µA

µA

V

mA

µA

A-D CONVERTER CHARACTERISTICS (Extended operating temperature version)

(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 2.0 V to VCC, Ta = –40 to 85 °C, unless otherwise noted)

50

Limits

Typ. Max.

150

Symbol Parameter

—

—
tCONV
RLADDER
IVREF
II(AD)

Resolution
Absolute accuracy (excluding quantization error)
Conversion time
Ladder resistor
Reference power source input current (Note)
A-D port input current

Note: When D-A conversion registers (addresses 0036

Test conditions

VREF = 5.0 V

16 and 003716) contain “0016”.

Min.

±1

35

0.5

±2.5

50

200

5.0

Unit

8

Bits
LSB
tC(φ)

kΩ

µA
µA

43

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

D-A CONVERTER CHARACTERISTICS (Extended operating temperature version)

(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 4.0 V to VCC, Ta = –40 to 85 °C, unless otherwise noted)

1

Limits

Typ. Max.

1.0

2.5

3.2

Unit

8

Bits

%

3

µs

4

kΩ

mA

Symbol Parameter

—

—
tsu
RO
IVREF

Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “0016”, and excluding cur-

rents flowing through the A-D resistance ladder.

Resolution
Absolute accuracy
Setting time
Output resistor
Reference power source input current (Note)

Test conditions

Min.

44

MITSUBISHI MICROCOMPUTERS

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

TIMING REQUIREMENTS 1 (Extended operating temperature version)

(VCC = 4.0 to 5.5 V, VSS = 0 V , Ta = –40 to 85 °C, unless otherwise noted)

Symbol Parameter

tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twH(INT)
twL(CNTR)
twL(INT)
tc(SCLK1)
tc(SCLK2)
twH(SCLK1)
twH(SCLK2)
twL(SCLK1)
twL(SCLK2)
t

su(RXD–S

t

su(S

IN2–SCLK2

t

h(S

CLK1–RX

t

h(S

CLK2–SIN2

Note: When f(X

Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
INT0 to INT4 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT4 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O2 clock input cycle time
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O2 clock input “H” pulse width
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O2 clock input “L” pulse width
Serial I/O1 input set up time

CLK1

)

Serial I/O2 input set up time

)

Serial I/O1 input hold time

D)

Serial I/O2 input hold time

)

IN) = 8 MHz and bit 6 of address 001A16 is “1”. Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0”.

Min.

125

50
50

200

80
80
80
80

800

1000

370
400
370
400
220
200
100
200

3802 Group

Limits

Typ. Max.

2

Unit

µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

SWITCHING CHARACTERISTICS 1

Symbol Parameter

twH(SCLK1)
twH(SCLK2)
twL(SCLK1)
twL(SCLK2)
t

d(S

CLK1–TX

t

d(S

CLK2–SOUT2

t

v(S

CLK1–TX

t

v(S

CLK2–SOUT2

tr(SCLK1)
tf(SCLK1)
tr(SCLK2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)

Note1: When the P4

2: When the P5
3: X

Serial I/O1 clock output “H” pulse width
Serial I/O2 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)

D)

Serial I/O2 output delay time (Note 2)

)

Serial I/O1 output valid time (Note 1)

D)

Serial I/O2 output valid time (Note 2)

)

Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output rising time
Serial I/O2 clock output falling time
CMOS output rising time (Note 3)
CMOS output falling time (Note 3)

5/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
1/SOUT2 P-channel output disable bit of the serial I/O2 control register (bit 7 of address 001D16) is “0”.

OUT pin excluded.

(Extended operating temperature version)

(VCC = 4.0 to 5.5 V, VSS = 0 V , Ta = –40 to 85 °C, unless otherwise noted)

Test conditions

Fig. 36

t
t
t
t

c(S
c(S
c(S
c(S

Min.

CLK1

CLK2

CLK1

CLK2

–30

)/2–30
)/2–160
)/2–30
)/2–160

0

Limits

Typ. Max.

10
10

140
200

30
30
30
40
30
30

Unit

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

45

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

TIMING REQUIREMENTS IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE

(Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)

–20
–20

60

–20

–20

65

0

0

Limits

Typ. Max.

Unit

ns
ns
ns
ns

ns

ns
ns

ns

Symbol Parameter

tsu(ONW–φ)
th(φ–ONW)
tsu(DB–φ)
th(φ–DB)
tsu

(ONW–RD)

tsu

(ONW–WR)

th(RD–ONW)
th(WR–ONW)

tsu(DB–RD)
th(RD–DB)

Before φ ONW input set up time
After φ ONW input hold time
Before φ data bus set up time
After φ data bus hold time
Before RD ONW input set up time

Before WR ONW input set up time
After RD ONW input hold time

After WR ONW input hold time
Before RD data bus set up time
After RD data bus hold time

Min.

SWITCHING CHARACTERISTICS IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE (Extended operating temperature version)

(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)

6

6

3

15

IN

IN

IN

0

0

10

0

)–10

)–10

)–35

Limits

Typ.

2✕t

20
10
25
10
20
10
10

20

t

c(XIN)

c(XIN)

t

15

c(XIN)

5

–15

–20

5

5

Max.

40

45

20
10
70

65

200
200

Unit

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

ns

ns

ns

ns

ns
ns

ns
ns
ns

Symbol Parameter

t

c(φ)

twH(φ)
twL(φ)
td(φ–AH)
tv(φ–AH)
td(φ–AL)
tv(φ–AL)
td(φ–SYNC)
tv(φ–SYNC)
td(φ–WR)
tv(φ–WR)
td(φ–DB)
tv(φ–DB)
twL(RD)

twL(WR)
td(AH–RD)

td(AH–WR)
td(AL–RD)

td(AL–WR)
tv(RD–AH)

tv(WR–AH)
tv(RD–AL)

tv(WR–AL)
td(WR–DB)
tv(WR–DB)
t

d

(RESET–RESET

tv(φ–RESET)

φ clock cycle time
φ clock “H” pulse width
φ clock “L” pulse width

After φ AD
After φ AD

15–AD8 delay time
15–AD8 valid time

After φ AD7–AD0 delay time
After φ AD7–AD0 valid time
SYNC delay time
SYNC valid time
RD and WR delay time
RD and WR valid time
After φ data bus delay time
After φ data bus valid time
RD pulse width, WR pulse width
RD pulse width, WR pulse width

(when one wait is valid)
After AD15–AD8 RD delay time

After AD15–AD8 WR delay time
After AD

7–AD0 RD delay time

After AD7–AD0 WR delay time
After RD AD

15–AD8 valid time

After WR AD15–AD8 valid time
After RD AD

7–AD0 valid time

After WR AD7–AD0 valid time
After WR data bus delay time
After WR data bus valid time

OUT

)

RESET

OUT output delay time

RESETOUT output valid time (Note 1)

Test conditions

Fig. 36

Min.

tc(XIN)–10
tc(XIN)–10

tc(X

3tc(X

tc(X

c(XIN)–40

t

Note 1: The RESETOUT output goes “H” in sync with the rise of the φ clock that is anywhere between about 8 cycle and 13 cycles after

the RESET input goes “H”.

Measurement output pin

100pF

CMOS output

Fig. 36 Circuit for measuring output switching

characteristics

46

TIMING DIAGRAM

(1) Timing Diagram

CNTR0, CNTR

INT0–INT

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

t

C(CNTR)

t

CC

CC

WL(CNTR)

t

WL(INT)

t

WH(CNTR)

0.8 V

0.8 V

CC

t

WH(INT)

CC

0.2 V

0.2 V

1

4

RESET

X

IN

S

CLK1

S

CLK2

RXD

IN2

S

t

W(RESET)

0.8 V

), tWH(S

)

CC

CLK2

)

t

v(S

CLK1-TX

t

v(S

D),

CLK2-SOUT2

)

0.2 V

CC

t

C(XIN)

t

CC

)

t

WH(S

CC

(S

CLK1-RX

(S

CLK2-SIN2

WL(XIN)

CLK1

D),

t

WH(X

IN)

0.8 V

CC

t

C(S

CLK1

t

WL(S

CLK1

), tWL(S

CLK2

t

f

0.2 V

CC

t

su(RXD-S

t

su(S

t

d(S

CLK1-TX

D),td(S

CLK2-SOUT2

)

CLK1

IN2-SCLK2

0.8 V

0.2 V

CC
CC

)

),
)

), tC(S

t

r

0.2 V

CLK2

0.8 V

th
t

h

TXD

OUT2

S

47

MITSUBISHI MICROCOMPUTERS

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(2)Timing Diagram in Memory Expansion Mode and Microprocessor Mode (a)

tC(φ)

tWH(φ)

tWL(φ)

3802 Group

φ

AD15–AD8

AD7–AD0

SYNC

RD,WR

ONW

0.5 VCC

td(φ-AH)

td(φ-AL)

td(φ-SYNC)

0.5 VCC

0.5 VCC

0.5 VCC

tSU(ONW-φ)

0.8 VCC

0.2 VCC

td(φ-WR)

0.5 VCC

tSU(DB-φ)

tv(φ-AH)

tv(φ-AL)

tv(φ-SYNC)

tv(φ-WR)

th(φ-ONW)

th(φ-DB)

DB0–DB7

(At CPU reading)

DB0–DB7

(At CPU writing)

(3)Timing Diagram in Microprocessor Mode

RESET

0.2 VCC

0.8 VCC

φ

td(RESET- RESETOUT)

RESET

OUT

0.5 VCC

td(φ-DB)

0.8 VCC

0.2 VCC

tv(φ-DB)

0.5 VCC

0.5 VCC

tv(φ- RESETOUT)

48

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(4) Timing Diagram in Memory Expansion Mode and Microprocessor Mode (b)

t

WL(RD)

t

WL(WR)

RD,WR

AD15–AD8

AD7–AD0

ONW

(At CPU reading)

RD

DB0–DB

7

0.5 V

0.5 V

t

d(AH-RD)

t

d(AH-WR)

CC

t

d(AL-RD)

t

d(AL-WR)

CC

t

su(ONW-RD)

t

su(ONW-WR)

0.8 V

0.2 V

CC

CC

0.5 V

0.5 V

CC

t

v(RD-AH)

t

v(WR-AH)

t

v(RD-AL)

t

v(WR-AL)

t

h(RD-ONW)

t

h(WR-ONW)

t

WL(RD)

CC

t

0.8 V

0.2 V

SU(DB-RD)

CC
CC

t

h(RD-DB)

(At CPU writing)

WR

DB0–DB

7

t

d(WR-DB)

0.5 V

CC

0.5 V

t

WL(WR)

CC

t

v(WR-DB)

49

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Keep safety first in your circuit designs!

• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of
substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.

Notes regarding these materials

• These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.

• Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples
contained in these materials.

• All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for the latest product information before purchasing a product listed herein.

• Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for
transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.

• The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.

• If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the
approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.

• Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.

© 1997 MITSUBISHI ELECTRIC CORP.
New publication, effective Dec. 1997.
Specifications subject to change without notice.

REVISION DESCRIPTION LIST 3802 GROUP DATA SHEET

Rev. Rev.

No. date

1.0 First Edition 971226

Revision Description

(1/1)