Datasheet M37902FCCHP, M37902FJCHP, M37902FGCHP Datasheet (Mitsubishi)

Page 1

MITSUBISHI MICROCOMPUTERS

M37902FCCHP, M37902FGCHP, M37902FJCHP

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

DESCRIPTION

These are single-chip microcomputers designed with high-performance CMOS silicon gate technology, including the internal flash memory. These microcomputers support the 7900 Series instruction set, which are enhanced and expanded instruction set and are upper-compatible with the 7700/7751 Series instruction set. The CPU of these microcomputers is a 16-bit parallel processor that can also be switched to perform 8-bit parallel processing. Also, the bus interface unit of these microcomputers enhances the memory access efficiency to execute instructions fast. Therefore, these microcomputers are suitable for office, business, and industrial equipment controller that require high-speed processing of large data. For the internal flash memory, single-power-supply programming and erasure, using a PROM programmer or the control by the central processing unit (CPU), is supported. Also, each of these microcomputers has the memory area dedicated for storing a certain software which controls programming and erasure (reprogramming control software). Therefore, on these microcomputers, the program can easily be changed even after they are mounted on the board.

DISTINCTIVE FEATURES

Number of basic machine instructions .................................... 203

•

Memory

•

[M37902FCCHP]

Flash memory (User ROM area) ................................. 120 Kbytes

RAM .............................................................................4096 bytes

[M37902FGCHP]

Flash memory (User ROM area) ................................. 248 Kbytes

RAM .............................................................................6144 bytes

[M37902FJCHP]

Flash memory (User ROM area) ................................. 498 Kbytes

RAM ...........................................................................12288 bytes

[All of the above computers]

Flash memory (Boot ROM area) ................................... 16 Kbytes

Instruction execution time

•

The fastest instruction at 26 MHz frequency ........................ 38 ns

Single power supply .................................................... 5 V ± 0.5 V

•

Interrupts ........... 6 external sources, 16 internal sources, 7 levels

•

Multi-functional 16-bit timer ................................................... 5 + 3

•

Serial I/O (UART or Clock synchronous)..................................... 2

•

10-bit A-D converter ............................................ 8-channel inputs

•

8-bit D-A converter ............................................ 3-channel outputs

•

Real-time output

•

....4 bits × 2 channels, or 6 bits × 1 channel + 2 bits × 1 channel

12-bit watchdog timer

•

Programmable input/output (ports P0–P8, P10, P11) ............... 84

•

Programming/Erase control by software command

•

Maximum number of reprograms ............................................ 100

•

APPLICATION

Control devices for personal computer peripheral equipment such as CD-ROM drives, DVD-ROM drives, hard disk drives, high density FDD, printers

Power supply voltage .................................................. 5 V ± 0.5 V

•

Programming/Erase voltage........................................ 5 V ± 0.5 V

•

Programming method............ Programming in a unit of 256 bytes

•

Erase method ............................................

•

(Data protection per block is enabled.)

Block erase or Total erase

Page 2

M37902FCCHP, M37902FGCHP, M37902FJCHP

M37902FxCHP PIN CONFIGURATION (TOP VIEW)

↔ P11

↔ P0

↔ P11

101112131415161718192021222324

↔

/KI

/RTP1

OUT

/TA2

/TA3

/TA2

/TA3

P10

3/A3 2/A2

P10

1/A1

P10 P100/A0 ↔

7/TXD1

6/RXD1

/CTS1/CLK1 ↔

/CTS1/RTS1/INT4 ↔

3/TXD0

2/RXD0

P81/CTS0/CLK0 ↔

REF

NMI →

P80/CTS0/RTS0/DA2/INT3 ↔

/AN7/AD

TRG

/DA1/(INT2) ↔

/AN6/DA0 ↔

/AN5/(INT4) ↔

/AN4/(INT3) ↔

/AN3 ↔

/AN2 ↔

/AN1 ↔

↔ P10

↔ P11

75747372717069686766656463626160595857565554535251

↔

78 79

↔

81 82 83

↔

85 86 87 88

→

89 90

SS SS

M37902FCCHP M37902FGCHP

M37902FJCHP

92 93 94 95 96 97 98 99 100

123456789 ↔

/AN

↔

/TB2

↔

/TB1

↔

/TB0

↔

/INT

↔

/INT

↔

/INT

↔

/TA4

↔

OUT

/TA4

MITSUBISHI MICROCOMPUTERS

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

/LA

MD1

←

/HOLD ↔

↔ P1

/HLDA ↔

↔ P1

↔

/φ

↔ P1

↔ P13/D3/LA

↔ P14/D4/LA

↔ P15/D5/LA

↔ P16/D6/LA

↔ P17/D7/LA

↔ P20/D

↔ P21/D

↔ P22/D

↔ P23/D

↔ P24/D

↔ P25/D

↔ P26/D

↔ P27/D

→ X

← X

34 33

←

← RESET

←

↔ P30/RDY

↔ P3

/ALE ↔

OUT IN

MD0

BYTE

CONT

/RD

/BLW

/BHW

3 4 5 6

7 8 9 10 11 12 13 14 15

↔ P0

↔

/RTP0

OUT

/TA1

↔ P0

↔

/RTP0

OUT

/TA0

↔ P0

↔

/CS

↔ P0

↔

/CS

↔ P0

↔

/CS

↔

/CS

Outline 100P6Q-A

Page 3

Data bank Register DT (8)

Program Counter PC (16)

Incrementer/Decrementer (24)

Program Bank Register PG (8)

Input Buffer Register IB (16)

Direct Page Register DPR0 (16)

Stack Pointer S (16)

Index Register Y (16)

Index Register X (16)

Arithmetic Logic

Unit (16)

Accumulator B (16)

Accumulator A (16)

Instruction register (8)

Central Processing Unit (CPU)

Incrementer (24)

Program Address Register PA (24)

Data Address Register DA (24)

Bus

Interface

Unit

(BIU)

RESET

MD1

Reference

voltage input

REF

(0V)

AVcc

Vcc

External data bus width

select input

BYTE

Clock Generating Circuit

Clock input

CONT

OUT

Data Buffer DQ0 (8)

Instruction Queue Buffer Q0 (8)

Data Bus (Odd)

Address Bus

A-D converter (10)

UART1 (9)

UART0 (9)

Watchdog timer

Timer TB1 (16)

Timer TB2 (16)

Timer TB0 (16)

D-A

converter (8)

D-A

converter (8)

Timer TA1 (16)

Timer TA2 (16)

Timer TA3 (16)

Timer TA4 (16)

Timer TA0 (16)

RAM

(Note)

P8(8)

Input/Output

port P8

P7(8)

Input/Output

port P7

Input/Output

port P4

P4(8)

P10(8)

Input/Output

port P10

P6(8)

Input/Output

port P6

P5(8)

Input/Output

port P5

P11(8)

Input/Output

port P11

P1(8)

Input/Output

port P1

P2(8)

Input/Output

port P2

P3(4)

Input/Output

port P3

P0(8)

Input/Output

port P0

MD0

(0V)

Vss

Processor Status Register PS (11)

NMI

Flash memory

(Note)

D-A

converter (8)

Data Bus (Even)

Data Buffer DQ

(8)

Data Buffer DQ

(8)

Data Buffer DQ

(8)

Instruction Queue Buffer Q

(8)

Instruction Queue Buffer Q

(8)

Instruction Queue Buffer Q

(8)

Instruction Queue Buffer Q

(8)

Instruction Queue Buffer Q

(8)

Instruction Queue Buffer Q

(8)

Instruction Queue Buffer Q

(8)

Instruction Queue Buffer Q

(8)

Instruction Queue Buffer Q

(8)

Direct Page Register DPR1 (16)

Direct Page Register DPR2 (16)

Direct Page Register DPR3 (16)

Clock output

Reset input

Note:

Flash memory RAM

M37902FCCHP 120 Kbytes 4096 bytes

M37902FGCHP 248 Kbytes 6144 bytes

M37902FJCHP 498 Kbytes 12288 bytes

MITSUBISHI MICROCOMPUTERS

M37902FCCHP, M37902FGCHP, M37902FJCHP

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

BLOCK DIAGRAM

Page 4

M37902FCCHP, M37902FGCHP, M37902FJCHP

FUNCTIONS (Microcomputer mode)

Number of basic machine instructions Instruction execution time External clock input frequency f(XIN) System clock frequency f(fsys) Memory size

Programmable input/output ports Multi-functional timers

Serial I/O A-D converter D-A converter Watchdog timer Chip-select wait control

Flash memory (User ROM area) RAM Flash memory (Boot ROM area) P0–P2, P4–P8, P10, P11 P3 TA0–TA4 TB0–TB2 UART0 and UART1

MITSUBISHI MICROCOMPUTERS

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

FunctionsParameter

203 38 ns (the fastest instruction at f(fsys) = 26 MHz) 26 MHz (Max.) 26 MHz (Max.)

(Note) (Note)

16 Kbytes 8-bit ✕ 10 4-bit ✕ 1 16-bit ✕ 5 16-bit ✕ 3 (UART or Clock synchronous serial I/O) ✕ 2 10-bit successive approximation method ✕ 1 (8 channels) 8-bit ✕ 3 12-bit ✕ 1 Chip select area ✕ 4 (CS0–CS3). A bus cycle type and bus width

can be set for each chip select area.

Real-time output Interrupts

Clock generating circuit

PLL frequency multiplier

Power supply voltage Power dissipation

Ports’ input/output characteristics

Memory expansion Operating ambient temperature range Device structure Package

Note:

Flash memory M37902FCCHP 120 Kbytes (User ROM area) M37902FGCHP 248 Kbytes

RAM M37902FCCHP 4096 bytes

Maskable interrups

Non-maskable interrups

Input/Output withstand voltage Output current

M37902FJCHP 498 Kbytes

M37902FGCHP 6144 bytes M37902FJCHP 12288 bytes

4 bits ✕ 2 channels; or 6 bits ✕ 1 channel + 2 bits ✕ 1 channel 5 external types, 13 internal types. Each interrupt can be set to a

priority level within the range of 0–7 by software. 1 external type, 3 internal types. Built-in (externally connected to a ceramic resonator or quartz

crystal resonator). The following multiplication methods are available: double, triple,

and quadruple. 5 V±0.5 V 150 mW (at f(fsys) = 26 MHz, Typ., PLL frequency multiplier

stopped) 5 V 5 mA Up to 16 Mbytes. Note that bank FF16 is a reserved area. –20 to 85 °C CMOS high-performance silicon gate process 100-pin plastic molded QFP

Page 5

M37902FCCHP, M37902FGCHP, M37902FJCHP

FUNCTIONS (Flash memory mode)

Power supply voltage Programming/Erase voltage Flash memory mode Block division for erasure

Programming method

Erase method

Programming/Erase control Data protection method Number of commands Maximum number of reprograms

User ROM area Boot ROM area

Flash memory parallel I/O mode Flash memory serial I/O mode Flash memory CPU reprogramming mode

MITSUBISHI MICROCOMPUTERS

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

FunctionsParameter

5 V±0.5 V (in the flash memory parallel I/O mode, 3.3 V±0.3 V) 5 V±0.5 V (in the flash memory parallel I/O mode, 3.3 V±0.3 V) 3 modes: parallel I/O, serial I/O, and CPU reprogramming modes

(Note 1)

1 block (16 Kbytes ✕ 1) (Note 2) Programmed per page (in a unit of 256 Kbytes) User ROM area + Boot ROM area User ROM area User ROM area Total erase/Block erase User ROM area + Boot ROM area User ROM area User ROM area Programming/Erase control by software commands Protected per block, by using a lock bit. 8 commands 100

Notes 1:

User ROM area

On shipment, our reprogramming control firmware for the flash memory serial I/O mode has been stored into the boot ROM area.

Note that the boot ROM area can be erased/programmed only in the flash memory parallel I/O mode.

M37902FCCHP 5 blocks (8 Kbytes ✕ 3, 32 Kbytes ✕ 1, 64 Kbytes ✕ 1), total 120 Kbytes M37902FGCHP 7 blocks (8 Kbytes ✕ 3, 32 Kbytes ✕ 1, 64 Kbytes ✕ 3), total 248 Kbytes M37902FJCHP

11 blocks (2 Kbytes ✕ 1, 8 Kbytes ✕ 2, 32 Kbytes ✕ 1, 64 Kbytes ✕ 7), total 498 Kbytes

Page 6

M37902FCCHP, M37902FGCHP, M37902FJCHP

PIN DESCRIPTION (MICROCOMPUTER MODE)

Input/

Output

—

Input

Input Input Input

Output

Input

—

Input

I/O

Apply 5 V±0.5 V to Vcc, and 0 V to Vss. This pin controls the processor mode. Connect this pin to VSS for the single-chip

mode or memory expansion mode, and VCC for the microprocessor mode. Connect this pin to Vss. The microcomputer is reset when “L” level is applied to this pin. These are input and output pins of the internal clock generating circuit. Connect a

ceramic or quartz- crystal resonator between the XIN and XOUT pins. When an external clock is used, the clock source should be connected to the XIN pin, and the XOUT pin should be left open.

This pin determines whether the external data bus has an 8-bit width or 16-bit width for the memory expansion mode or microprocessor mode. The width is 16 bits when “L” signal is input, and 8 bits when “H” signal is input. When BYTE = Vss level, by the register setting, the external data bus for each of areas CS1 to CS3 can have a width of 8 bits.

When using the PLL frequency multiplier, connect this pin to the filter circuit. When not using, this pin should be left open.

Power supply input pins for the A-D converter and the D-A converter. Connect AVcc to Vcc, and AVss to Vss externally.

This is the reference voltage input pin for the A-D converter and the D-A converter.

■ In single-chip mode Port P0 is an 8-bit I/O port. This port has an I/O direction register, and each pin can be programmed for input or output. These pins enter the input mode at reset.

■ In memory expansion and microprocessor modes Address (A16–A23) is output. These pins also function as I/O port pins according to the register setting.

■ In single-chip mode These pins have the same functions as port P0.

■ In memory expansion and microprocessor modes The low-order 8 bits of data (D0–D7) are input/output. When the external data bus has an 8-bit width, address (LA0–LA7) output and data (D0–D7) input/output can be performed with the time-sharing method, according to the register setting.

■ In single-chip mode or When 8-bit external data bus is used in memory expansion mode and microprocessor mode These pins have the same functions as port P0.

■ When the 16-bit external data bus is used in memory expansion or microprocessor mode The high-order 8 bits of data (D8–D15) are input or output.

■ In single-chip mode These pins have the same functions as port P0.

■ In memory expansion mode P30 functions as an I/O port pin; and P31, P32, and P33 function as the output pins of RD, BLW, BHW, respectively. P30 also functions as an output pin of RDY according to the register setting. When the external data bus has a width of 8 bits, the BHW pin functions as an I/O port pin (P33).

■ In microprocessor mode P30 functions as an input pin of RDY; and P31,P32, P33 function as the output pins of RD, BLW, BHW, respectively. P30 also functions as an I/O port pin according to the register setting. When the external data bus has a width of 8 bits, the BHW pin functions as an I/O port pin (P33).

■ In single-chip mode These pins have the same functions as port P0.

■ In memory expansion mode P40–P47 function as I/O port pins. According to the register setting, these pins function as output pins or input pins of ALE, φ1, HLDA, HOLD, CS0–CS3, respectively.

■ In microprocessor mode P40–P44 function as output or input pins of ALE, φ1, HLDA, HOLD, CS0, and P45–P47 as I/O port pins, respectively. According to the register setting, P40–P43 also function as I/O port pins, and P45–P47 as output pins of CS1–CS3.

Vcc, Vss MD0

MD1 RESET XIN XOUT

BYTE

VCONT

AVcc, AVss

VREF P00–P07

P10–P17

P20–P27

P30–P33

P40–P47

NamePin Power supply input MD0

MD1 Reset input Clock input Clock output

External data bus width select input

Filter circuit connection

Analog power supply input

Reference voltage input I/O port P0

I/O port P1

I/O port P2

I/O port P3

I/O port P4

MITSUBISHI MICROCOMPUTERS

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Functions

Page 7

MITSUBISHI MICROCOMPUTERS

M37902FCCHP, M37902FGCHP, M37902FJCHP

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

P50–P57

P60–P67

P70–P77

P80–P87

P100–P107

P110–P117

NMI

NamePin

I/O port P5

I/O port P6

I/O port P7

I/O port P8

I/O port P10

I/O port P11

Non-maskable interrupt

Input/

Output

I/O

Input

Functions

In addition to having the same functions as port P0 in the single-chip mode, these pins also function as I/O pins for timers A0–A3, output pins for the real-time output, and input pins for the key-input interrupt.

In addition to having the same functions as port P0 in the single-chip mode, these pins also function as I/O pins for timer A4, input pins for external interrupt inputs

____ ____

INT0–INT2, and input pins for timers B0–B2. In addition to having the same functions as port P0 in the single-chip mode, these

pins also function as input pins for the A-D converter, output pins for the D-A converter, and input pins for INT2, INT3, and INT4.

In addition to having the same functions as port P0 in the single-chip mode, these pins also function as I/O pins for UART0, UART1, output pins for D-A converter, and input pins for INT3 and INT4.

■ In single-chip mode These pins have the same functions as port P0.

■ In memory expansion and microprocessor modes Address (A0–A7) is output.

■ In single-chip mode These pins have the same functions as port P0.

■ In memory expansion and microprocessor modes Address (A8–A15) is output. Also, these pins function as I/O port pins according to the register setting.

This pin is for a non-maskable interrupt.

Page 8

M37902FCCHP, M37902FGCHP, M37902FJCHP

PIN DESCRIPTION (FLASH MEMORY SERIAL I/O MODE)

VCC, VSS MD0 MD1

_____

RESET XIN XOUT BYTE VCONT AVcc, A Vss VREF P00–P07 P10–P17 P20–P27 P30–P33 P40, P44– P47 P41 P42 P43 P50–P57 P60–P67 P70–P77 P80–P87 P100–P107 P110–P117 NMI

Name

Power supply input MD0 MD1 Reset input Clock input Clock output BYTE Filter circuit connection Analog supply input Reference voltage input Input port P0 Input port P1 Input port P2 Input port P3 Input port P4

SCLK input SDA I/O BUSY output Input port P5 Input port P6 Input port P7 Input port P8 Input port P10 Input port P11 Non-maskable interrupt

Input

/Output

—

Input Input Input Input

Output

Input

— —

Input Input Input Input Input Input

Input

I/O

Output

Input Input Input Input Input Input Input

Apply 5 V ± 0.5 V to Vcc, and 0 V to Vss. Connect this pin to Vss. Connect this pin to Vss via a resistor of 10 kΩ to 100 kΩ. The reset input pin. Connect a ceramic resonator between the XIN and XOUT pins, or input an external clock from the XIN pin with the XOUT pin left open. Connect this pin to Vcc or Vss. (This is not used in the flash memory serial I/O mode.) Connect this pin to the filter circuit, or leave this pin open. (This is not used in the flash memory serial I/O mode.) Connect AVcc to Vcc, and AVss to Vss. Input an arbitrary level within the range of VSS–VCC. (This is not used in the flash memory serial I/O mode.) Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)

This is an input pin for a serial clock. This is an I/O pin for serial data. Connect this pin to VCC via a resistor (about 1 kΩ). This is an output pin for the BUSY signal. Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H”, or leave this pin open.

MITSUBISHI MICROCOMPUTERS

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Functions

Page 9

MITSUBISHI MICROCOMPUTERS

M37902FCCHP, M37902FGCHP, M37902FJCHP

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

BASIC FUNCTION BLOCKS

These microcomputers contain the following devices on the single chip: the flash memory, RAM, CPU, bus interface unit, and peripheral devices such as the interrupt control circuit, timers, serial I/O, A-D converter, D-A converter, I/O ports, clock generating circuit, etc.

MEMORY

Figures 1 to 3 show the memory maps. The address space is 16 Mbytes from addresses 016 to FFFFFF16. The address space is divided into 64-Kbyte units called banks. The banks are numbered from 016 to FF16. Bank FF16 is a reserved area for the development support tool. Therefore, do not use bank FF16.

000000

Bank 0

Bank 1

•

Bank FE

Bank FF

00FFFF 010000

01FFFF

FE0000

FEFFFF FF0000

FFFFFF

16 16

Reserved area

for development

support tool

000000 0000FF

000800

0017FF 001800

001FFF 002000

00FFC0 00FFFF

Internal flash memory and internal RAM are assigned as shown in Figures 1 to 3. Addresses FFC016 to FFFF16 contain the RESET and the interrupt vector addresses, and the interrupt vectors are stored there. For details, refer to the section on interrupts. Assigned to addresses 016 to FF16 are peripheral devices such as I/O ports, A-D converter, D-A converter, UART, timers, interrupt control registers, etc. Figures 7 and 8 show the location of SFRs. For the flash memory in the boot ROM area, refer to the section on the flash memory mode.

Peripheral devices

control registers

Internal RAM

4096 bytes

16 16

Internal flash memory

120 Kbytes

(User ROM area)

00FFC0

00FFFE

Interrupt vector table

Reserved area Reserved area Reserved area Reserved area Reserved area

Address matching detect

Reserved area Reserved area

INT INT

A-D conversion

UART1 transmit

UART1 receive

UART0 transmit

UART0 receive

Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0

INT INT INT

NMI

Watchdog timer

DBC

BRK instruction

Zero divide

RESET

4 3

2 1 0

Fig. 1 Memory map of M37902FCCHP (Single-chip mode)

Page 10

Bank 0

Bank 1

Bank 2

Bank 3

•

Bank FE

Bank FF

MITSUBISHI MICROCOMPUTERS

M37902FCCHP, M37902FGCHP, M37902FJCHP

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

000000

00FFFF 010000

01FFFF 020000

02FFFF

030000

03FFFF

FE0000

FEFFFF FF0000

FFFFFF

Reserved area

for development

support tool

000000 0000FF

000800

001FFF 002000

00FFC0 00FFFF

Peripheral devices

control registers

Internal RAM

6144 bytes

16 16

Internal flash memory

248 Kbytes

(User ROM area)

00FFC0

00FFFE

Interrupt vector table

Reserved area Reserved area Reserved area Reserved area Reserved area

Address matching detect

Reserved area Reserved area

INT INT

A-D conversion

UART1 transmit

UART1 receive

UART0 transmit

UART0 receive

Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0

INT INT INT NMI

Watchdog timer

DBC

BRK instruction

Zero divide

RESET

4 3

2 1 0

Fig. 2 Memory map of M37902FGCHP (Single-chip mode)

000000

Bank 0

Bank 1

Bank 2

Bank 3

Bank 4

Bank 5

Bank 6

Bank 7

•

Bank FE

Bank FF

00FFFF 010000

01FFFF 020000

02FFFF 030000

03FFFF 040000

04FFFF 050000

05FFFF 060000

06FFFF 070000

07FFFF

FE0000

FEFFFF FF0000

FFFFFF

Reserved area

for development

support tool

000000 0000FF

000800

0037FF 003800

00FFC0 00FFFF

Peripheral devices

control registers

Internal RAM 12288 bytes

16 16

Internal flash memory

498 Kbytes

(User ROM area)

00FFC0

00FFFE

Interrupt vector table

Reserved area Reserved area Reserved area Reserved area Reserved area

Address matching detect

Reserved area Reserved area

INT INT

A-D conversion

UART1 transmit

UART1 receive

UART0 transmit

UART0 receive

Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0

INT INT INT NMI

Watchdog timer

DBC

BRK instruction

Zero divide

RESET

4 3

2 1 0

Fig. 3 Memory map of M37902FJCHP (Single-chip mode)

Page 11

MITSUBISHI MICROCOMPUTERS

M37902FCCHP, M37902FGCHP, M37902FJCHP

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Address (Hexadecimal notation) 000000

000001 000002 000003 000004 000005 000006 000007 000008

000009 00000A 00000B 00000C 00000D 00000E 00000F

000010

000011

000012

000013

000014

000015

000016

000017

000018

000019 00001A 00001B 00001C 00001D 00001E 00001F

000020

000021

000022

000023

000024

000025

000026

000027

000028

000029 00002A 00002B 00002C 00002D 00002E 00002F

000030

000031

000032

000033

000034

000035

000036

000037

000038

000039 00003A 00003B 00003C 00003D 00003E 00003F

Reserved area (Note)

Reserved area (Note) Port P0 register

Port P1 register

16 16

Port P0 direction register

Port P1 direction register

Port P2 register

Port P3 register Port P2 direction register

16 16

Port P3 direction register

Port P4 register

Port P5 register

Port P4 direction register

Port P5 direction register

Port P6 register

Port P7 register

Port P6 direction register

Port P7 direction register

Port P8 register

16 16

Port P8 direction register

16 16

Port P10 register

Port P11 register

Port P10 direction register

Port P11 direction register

16 16 16 16 16

A-D control register 0

A-D control register 1

A-D register 0

16 16

A-D register 1

16 16

A-D register 2

16 16

A-D register 3

16 16

A-D register 4

16 16

A-D register 5

16 16

A-D register 6

16 16

A-D register 7

16 16

UART0 transmit/receive mode register

UART0 baud rate register (BRG0)

UART0 transmit buffer register

16 16

UART0 transmit/receive control register 0

UART0 transmit/receive control register 1

UART0 receive buffer register

16 16

UART1 transmit/receive mode register

UART1 baud rate register (BRG1)

UART1 transmit buffer register

16 16

UART1 transmit/receive control register 0

UART1 transmit/receive control register 1

UART1 receive buffer register

Address (Hexadecimal notation)

Count start register

000040 000041

000042 000043 000044 000045 000046 000047 000048 000049 00004A

00004B 00004C 00004D 00004E

00004F

000050

000051

000052

000053

000054

000055

000056

000057

000058

000059 00005A 00005B 00005C 00005D 00005E

00005F

000060

000061

000062

000063

000064

000065

000066

000067

000068

000069 00006A 00006B 00006C 00006D 00006E

00006F

000070

000071

000072

000073

000074

000075

000076

000077

000078

000079 00007A 00007B 00007C 00007D 00007E

00007F

One-shot start register

16 16

Up-down register

Timer A clock division select register

16 16

Timer A0 register

16 16

Timer A1 register

16 16

Timer A2 register

16 16

Timer A3 register

16 16

Timer A4 register

16 16

Timer B0 register

16 16

Timer B1 register

16 16

Timer B2 register

Timer A0 mode register

Timer A1 mode register

Timer A2 mode register

Timer A3 mode register

Timer A4 mode register

Timer B0 mode register

16 16

Timer B1 mode register

Timer B2 mode register Processor mode register 0

16 16

Processor mode register 1

Watchdog timer register Watchdog timer frequency select register

16 16

Particular function select register 0 Particular function select register 1

16 16

Particular function select register 2

Reserved area (Note)

Debug control register 0 Debug control register 1

16 16

Address comparison register 0

16 16 16

Address comparison register 1

16 16 16

interrupt control register

INT

interrupt control register

A-D conversion interrupt control register

16 16

UART0 transmit interrupt control register UART0 receive interrupt control register

16 16

UART1 transmit interrupt control register

UART1 receive interrupt control register

Timer A0 interrupt control register

Timer A1 interrupt control register

Timer A2 interrupt control register

Timer A3 interrupt control register

Timer A4 interrupt control register

Timer B0 interrupt control register Timer B1 interrupt control register

16 16

Timer B2 interrupt control register

INT

interrupt control register

INT

interrupt control register

Fig. 7 Location of SFRs (1)

Note: Do not write to this address.

Page 12

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Address (Hexadecimal notation)

000080 000081 000082 000083 000084 000085 000086 000087 000088

000089 00008A 00008B

00008C 00008D

00008E 00008F

000090

000091

000092

000093

000094

000095

000096

000097

000098

000099 00009A 00009B

00009C 00009D

00009E 00009F 0000A0 0000A1 0000A2 0000A3 0000A4 0000A5 0000A6 0000A7 0000A8 0000A9

0000AA 0000AB 0000AC 0000AD 0000AE 0000AF

0000B0 0000B1 0000B2 0000B3 0000B4 0000B5 0000B6 0000B7 0000B8 0000B9

0000BA 0000BB 0000BC 0000BD 0000BE 0000BF

control register L

control register H

control register L

control register H

control register L

control register H

control register L

control register H

16 16

Area

16 16

Area

16 16

Area

16 16

Area

16 16

Port function control register

16 16

External interrupt input control register

External interrupt input read-out register

D-A control register

16 16

D-A register 0

16 16

D-A register 1

D-A register 2

16 16

Reserved area (Note)

Flash memory control register

16 16

Real-time output control register

Pulse output data register 0

16 16

Pulse output data register 1

16 16 16 16 16 16 16 16 16

Serial I/O pin control register

16 16 16 16 16 16 16 16 16 16 16 16 16

Reserved area (Note)

16 16

Clock control register

Reserved area (Note)

start address register

Address (Hexadecimal notation)

0000C0

0000C1

0000C2

0000C3

0000C4

0000C5

0000C6

0000C7

0000C8

0000C9

0000CA

0000CB

0000CC

0000CD

0000CE

0000CF

0000D0

0000D1

0000D2

0000D3

0000D4

0000D5

0000D6

0000D7

0000D8

0000D9

0000DA

0000DB

0000DC

0000DD

0000DE

0000DF

0000E0

0000E1

0000E2

0000E3

0000E4

0000E5

0000E6

0000E7

0000E8

0000E9

0000EA

0000EB

0000EC

0000ED

0000EE

0000EF

0000F0

0000F1

0000F2

0000F3

0000F4

0000F5

0000F6

0000F7

0000F8

0000F9

0000FA

0000FB

0000FC

0000FD

0000FE

0000FF

Note: Do not write to this address.

Fig. 8 Location of SFRs (2)

Page 13

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CENTRAL PROCESSING UNIT (CPU)

The CPU has 13 registers and is shown in Figure 9. Each of these registers is described below.

ACCUMULATOR A (A)

Accumulator A is the main register of the microcomputer. It consists of 16 bits and the low-order 8 bits can be used separately. Data length flag m determines whether the register is used as 16-bit register or as 8-bit register. It is used as a 16-bit register when flag m is “0” and as an 8-bit register when flag m is “1”. Flag m is a part of the processor status register (PS) which is described later. Data operations such as calculations, data transfer, input/output, etc., are executed mainly through accumulator A.

ACCUMULATOR B (B)

Accumulator B has the same functions as accumulator A, but the use of accumulator B requires more instruction bytes and execution cycles than accumulator A.

ACCUMULATOR E

Accumulator E is a 32-bit register and consists of accumulator A (low-order 16 bits) and accumulator B (high-order 16 bits). It is used for 32-bit data processing.

INDEX REGISTER X (X)

Index register X consists of 16 bits and the low-order 8 bits can be used separately. Index register length flag x determines whether the register is used as 16-bit register or as 8-bit register. It is used as a 16-bit register when flag x is “0” and as an 8-bit register when flag x is “1”. Flag x is a part of the processor status register (PS) which is described later. In index addressing modes in which register X is used as the index register, the contents of this address are added to obtain the real address. Index register X functions as a pointer register which indicates an address of data table in instructions MVP, MVN, RMPA (Repeat MultiPly and Accumulate).

INDEX REGISTER Y (Y)

Index register Y consists of 16 bits and the low-order 8 bits can be used separately. The index register length flag x determines whether the register is used as 16-bit register or as 8-bit register. It is used as a 16-bit register when flag x is “0” and as an 8-bit register when flag x is “1”. Flag x is a part of the processor status register (PS) which is described later. In index addressing modes in which register Y is used as the index register, the contents of this address are added to obtain the real address. Index register Y functions as a pointer register which indicates an address of data table in instructions MVP, MVN, RMPA (Repeat MultiPly and Accumulate).

15 7 0

PG Program bank register PG

Fig. 9 Register structure

Accumulator B

Data bank register DTDT

Accumulator A

15 7 0

Accumulator E

1570

15 0

00000

DPR0 to DPR3

IPL2IPL1IPL

7 NVmxD I ZC

Index register X

Index register Y

Stack pointer S

Program counter PC

Direct page registers DPR0 to DPR3

Processor status register PS Carry flag

Zero flag Interrupt disable flag Decimal mode flag Index register length flag Data length flag Overflow flag Negative flag Processor interrupt priority level IPL

Page 14

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STACK POINTER (S)

Stack pointer (S) is a 16-bit register. It is used during a subroutine call or interrupts. It is also used during stack, stack pointer relative, or stack pointer relative indirect indexed Y addressing mode.

PROGRAM COUNTER (PC)

Program counter (PC) is a 16-bit counter that indicates the low-order 16 bits of the next program memory address to be executed. There is a bus interface unit between the program memory and the CPU, so that the program memory is accessed through bus interface unit. This is described later.

PROGRAM BANK REGISTER (PG)

Program bank register is an 8-bit register that indicates the high-order 8 bits of the next program memory address to be executed. When a carry occurs by incrementing the contents of the program counter, the contents of the program bank register (PG) is increased by 1. Also, when a carry or borrow occurs after adding or subtracting the offset value to or from the contents of the program counter (PC) using the branch instruction, the contents of the program bank register (PG) is increased or decreased by 1, so that programs can be written without worrying about bank boundaries.

DATA BANK REGISTER (DT)

Data bank register (DT) is an 8-bit register. With some addressing modes, the data bank register (DT) is used to specify a part of the memory address. The contents of data bank register (DT) is used as the high-order 8 bits of a 24-bit address. Addressing modes that use the data bank register (DT) are direct indirect, direct indexed X indirect, direct indirect indexed Y, absolute, absolute bit, absolute indexed X, absolute indexed Y, absolute bit relative, and stack pointer relative indirect indexed Y.

DIRECT PAGE REGISTERS 0 to 3 (DPR0 to DPR3)

The direct page register is a 16-bit register. An addressing mode of which name includes ‘direct’ generates an address of data to be accessed, regarding the contents of this register as the base address. The 7900 Series has been expanded direct page registers up to 4 (DPR0 to DPR3), in comparison to the 7700 Series which has the single direct page register. Accordingly, the 7900 Series’s direct ad- dressing method which uses direct page registers differs from that of the 7700 Series. However, the conventional direct addressing method, using only DPR0, is still be selectable, in order to make use of the 7700 Series software property. For more details, refer to the section on the direct page.

PROCESSOR STATUS REGISTER (PS)

Processor status register (PS) is an 11-bit register. It consists of flags to indicate the result of operation and CPU interrupt levels. Branch operations can be performed by testing the flags C, Z, V , and N. The details of each bit of the processor status register are described below.

1. Carry flag (C)

The carry flag contains the carry or borrow generated by the ALU after an arithmetic operation. This flag is also affected by shift and rotate instructions. This flag can be set and reset directly with the SEC and CLC instructions or with the SEP and CLP instructions.

2. Zero flag (Z)

The zero flag is set if the result of an arithmetic operation or data transfer is zero and reset if it is not. This flag can be set and reset directly with the SEP and CLP instructions.

3. Interrupt disable flag (I)

When the interrupt disable flag is set to “1”, all interrupts except watchdog timer, NMI, and software interrupt are disabled. This flag is set to “1” automatically when an interrupt is accepted. It can be set and reset directly with the SEI and CLI instructions or SEP and CLP instructions.

___

4. Decimal mode flag (D)

The decimal mode flag determines whether addition and subtraction are performed as binary or decimal. Binary arithmetic is performed when this flag is “0”. If it is “1”, decimal arithmetic is performed with each word treated as 2- or 4- digit decimal. Arithmetic operation is performed using four digits when data length flag m is “0” and with two digits when it is “1”. Decimal adjust is automatically performed. (Decimal operation is possible only with the ADC and SBC instructions.) This flag can be set and reset with the SEP and CLP instructions.

Page 15

M37902FCCHP, M37902FGCHP, M37902FJCHP

5. Index register length flag (x)

The index register length flag determines whether index register X and index register Y are used as 16-bit registers or as 8-bit registers. The registers are used as 16-bit registers when flag x is “0” and as 8bit registers when it is “1”. This flag can be set and reset with the SEP and CLP instructions.

6. Data length flag (m)

The data length flag determines whether the data length is 16-bit or 8-bit. The data length is 16 bits when flag m is “0” and 8 bits when it is “1”. This flag can be set and reset with the SEM and CLM instructions or with the SEP and CLP instructions.

7. Overflow flag (V)

The overflow flag is valid when addition or subtraction is performed with a word treated as a signed binary number. If data length flag m is “0”, the overflow flag is set when the result of addition or subtraction is outside the range between –32768 and +32767. If data length flag m is “1”, the overflow flag is set when the result of addition or subtraction is outside the range between –128 and +127. It is reset in all other cases. The overflow flag can also be set and reset directly with the SEP, and CLV or CLP instructions. Additionally, the overflow flag is set when a result of unsigned/signed division exceeds the length of the register where the result is to be stored; the flag is also set when the addition result is outside range of –2147483648 to +2147483647 in the RMPA operation.

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8. Negative flag (N)

The negative flag is set when the result of arithmetic operation or data transfer is negative (If data length flag m is “0”, data’s bit 15 is “1”. If data length flag m is “1”, data’s bit 7 is “1”.) It is reset in all other cases. It can also be set and reset with the SEP and CLP instructions.

9. Processor interrupt priority level (IPL)

The processor interrupt priority level (IPL) consists of 3 bits and determines the priority of processor interrupts from level 0 to level 7. Interrupt is enabled when the interrupt priority of the device requesting interrupt (set using the interrupt control register) is higher than the processor interrupt priority . When an interrupt is enabled, the current processor interrupt priority level is saved in a stack and the processor interrupt priority level is replaced by the interrupt priority level of the device requesting the interrupt. Refer to the section on interrupts for more details. Note: Fix bits 11 to 15 of the processor status register (PS) to “0”.

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BANK

In order to effectively use the integrated hardware on the chip, this CPU core uses an address generating method with a 24-bit address split into high-order 8 bits and low-order 16 bits. In other words, the 64 Kbytes specified by the low-order 16 bits are one unit (referred to as “bank”), and the address space is divided into 256 banks (016 to FF16) specified by the high-order 8 bits. In the program area on the address space, the bank is specified by the program bank register (PG), and the address in the bank is specified by the program counter (PC). As for each bank boundary, when an overflow has occurred in PC, the contents of PG are incremented by 1. When a borrow has occurred in PC, the contents of PG are decremented by 1. Under the normal conditions, therefore, programming without concern for the bank boundaries is possible. Furthermore, as for the data area on the address space, the bank is specified by the data bank register (DT), and the address in the bank is specified by the operation result by using the various addressing modes (Note).

Note: Some addressing modes directly specify a bank.

DIRECT PAGE

The internal memory and control registers for internal peripheral devices, etc. are assigned to bank 016 (addresses 016 to FFFF16). The direct page and direct addressing modes have been provided for the effective access to bank 016. In the 7900 Series, two types of direct addressing modes are available: the conventional direct addressing mode which uses only DPR0, as in the 7700 Series, and the expanded direct addressing mode, which uses up to 4 direct page registers as selected by the user. The addressing mode is selected according to the contents of bit 1 of the processor mode register 1. This bit 1 is cleared to “0” at reset. (In other words, the conventional direct addressing mode is selected.) However, once this bit 1 has been set to “1” by software, this bit cannot be cleared to “0” again, except by reset. That is to say , when one of these two direct addressing modes has been selected just after reset, the selected addressing mode cannot be switched to another one while the program is running.

Refer to “7900 Series Software Manual” for details concerning the various addressing modes which use the direct page area.

Instruction Set

The CPU core of the 7900 Series has an expanded instruction set based on the existing 7700/7751 Series’ CPU core. In addition, its source code (mnemonic) has the complete upper compatibility with the 7700 Series instruction set. For details concerning addressing modes and instruction set, refer to “7900 Series Software Manual”.

■ Conventional direct addressing mode The direct page area consists of 256-byte space. Its bank address is “0016”, and the base address of its low-order 16-bit address is specified by the contents of the direct page register 0 (DPR0). In this conventional direct addressing modes, a value (1 byte) just after an instruction code is regarded as an offset value for the DPR0 contents, and the CPU accesses each address in the direct page area.

■ Expanded direct addressing mode The direct page area consists of four 64-byte spaces. Their bank address is “0016”, and the four base addresses of their low-order 16bit addresses are respectively specified by the contents of four direct page registers. In this expanded direct addressing mode, a value (1 byte) just after an instruction code is regarded as follows:

• High-order 2 bits: regarded as a selection field for DPR0 to DPR3.

• Low-order 6 bits: regarded as an offset value for the selected direct

page register.

Then, the CPU accesses each address in each direct page area:

Page 17

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BUS INTERFACE UNIT

Data transfer between the central processing unit (CPU) and internal memory, internal peripheral devices, or external areas is always performed via the bus interface unit (BIU), which is located between the CPU and the internal buses. Figure 10 shows the BIU and the bus structure. The CPU and BIU are connected by a dedicated bus, and any transfer between the CPU and BIU is controlled by this dedicated bus. On the other hand, data transfer between the BIU and internal peripheral devices uses the following internal common buses: 32-bit code bus, 16-bit data bus, 24-bit address bus, and control signals. The bus control method where the code bus and the data bus separate out (hereafter, this method is referred to as the separate code/

M37902

Central

Processing

Unit

(CPU)

CPU bus

Bus

Interface

Unit

(BIU)

Internal code bus (CB0 to CB31) Internal data bus (DB0 to DB15)

Internal address bus (AD0 to AD23)

Internal control signal

data bus method) is employed in order to improve data transfer capabilities. As a result, the internal memory is connected to both the code bus and the data bus, and registers of all other internal peripheral devices are connected only to the data bus. Each width of external buses are as follows: a 24-bit address bus, 16-bit data bus. The external data bus transfers instruction codes and data. When the code or data access occurs for the external, the external access is performed via the bus conversion circuit. For details of the connection with the external devices, refer to the section on the processor modes and chip select wait controller described later.

Internal buses

Internal

memory

Hold request

SFR : Special Function Register ❈ The CPU bus, internal bus, and external bus separate out independently.

Fig. 10 BIU and bus structure

Internal

peripheral

devices

(SFR)

conversion

circuit

Bus

External bus

A0 to A

D0 to D7 (LA0 to LA7)

to D

D Control signal

HOLD

HLDA

External

devices

Page 18

M37902FCCHP, M37902FGCHP, M37902FJCHP

BIU structure

The BIU consists of four registers shown in Figure 11. Table 1 lists the functions of each register.

Table 1. Functions of each register

Name

Program address register Instruction queue buffer Data address register Data buffer

Indicates a storage address for an instruction to be next taken into an instruction queue buffer. Temporarily stores an instruction which has been taken from a memory. Consists of 10 bytes. Indicates an address where data will be next read from or written to. Temporarily stores data which has been read from internal memory, internal peripheral devices, and

external areas by the BIU; or temporarily stores data which is to be written to internal memory, internal peripheral devices, and external areas by the CPU. Consists of 32 bits.

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Functions

Fig.11 Register structure of BIU

b23

b7 b0

b23 b0

b31 b0

Program address register

Instruction queue buffer

Data address register

Data buffer

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BIU Functions (1) Instruction prefetch

The BIU has ten instruction queue buffers; each buffer consists of 1 byte. When there is an opening in the bus and the instruction queue buffer, an instruction code is read from the program memory (in other words, the memory where a program is stored) and prefetched into an instruction queue buffer. The prefetched instruction code is transferred from the BIU to the CPU, in response to a request from the CPU, via a dedicated bus. When a branch occurs as a result of a branch instruction (JMP, BRA, etc.), subroutine call, or interrupt, the contents of the instruction queue buffer are initialized and the BIU reads a new instruction from the branch destination address. Note that the operations of the BIU instruction prefetch also differ depending on the store addresses for instructions. The store addresses for instructions to be prefetched are categorized as listed in Table 2.

(2) Data read operation

When executing an instruction for reading data from the internal memory, internal peripheral devices, or external areas, at first, the CPU informs the BIU’s data address register of the address where the data has been located. Next, the BIU reads the above data from the specified address, passes it to the data buffer, and then, transfers it to the CPU.

[Instruction prefetch]

• Whether the address area locates in the internal area or the external area.

• When the address area locates in the external area

➀ Whether the external bus width = 16 bits or 8 bits:

(a) When the external bus width = 16 bits:

whether the start address for access locates at a 4byte boundary or at an 8-byte boundary.

(b) When the external bus width = 8 bits:

whether the start address for access locates at an even address, a 4-byte boundary or at the 8-byte bound ary.

➁ Whether the prefetch operation is generated by a branch, or

not.

➂ Number of waits ➃ Whether the burst ROM access is specified or not.

Table 2. Store addresses for instructions to be prefetched

Low-order 3 bits of store address for instruction

AD1 (A1)

AD0 (A0)

0 0 0

Even address 4-byte boundary 8-byte boundary

X: 0 or 1

AD2 (A2)

X X 0

(3) Data write operation

When executing an instruction for writing data into the internal memory, internal peripheral devices, or external area, at first, the CPU informs the BIU’s data address register of the address where the data has been located. Next, the BIU passes the above data to the data buffer register, and then, writes it into the specified address.

(4) Bus cycle

In order for the BIU to execute the above operations (1) through (3), the 24-bit address bus, 32-bit code bus, 16-bit data bus and internal control signals must be appropriately controlled during data transfer between the BIU and internal memory, internal peripheral devices, external areas. This operation is called “bus cycle”. The bus cycle is affected by the following conditions at instruction prefetch and data access.

[Data Access]

• Whether the address area locates in the internal area or the external area.

• Length of data to be transferred: byte, word, double word

• When the address area locates in the external area:

➀ Whether the external bus width = 16 bits or 8 bits: ➁ Number of waits

The BIU controls the bus cycle depending on the above conditions. Figures 12 to 16 show the bus cycle waveform examples for instruction prefetch and data access.

Page 20

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Access to internal area

Access to external area

When address locates at 4-byte boundary or when branched:

double consecutive access

When branched or at instruction

prefetch

When external data bus width = 16 bits When external data bus width = 8 bits

BIU

Internal address bus

Internal code bus

to CB

Code

to A

to D

ALE

BLW

BHW

to D

Address Address + 2

When address of instruction to be prefetched locates at 8-byte boundary:

quadruple consecutive access

to A

to D

ALE

BLW

BHW

to D

Address Address + 2

Address + 4 Address + 6

When address is even address or when branched:

double consecutive access

to A

to D

ALE

BLW

BHW

to D

Address Address + 1

When address of instruction to be prefetched locates at 4-byte boundary or

8-byte boundary: quadruple consecutive access

to A

to D

ALE

BLW

BHW

to D

Address Address + 1

Address + 2 Address + 3

Address

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SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Fig. 12 Bus cycle waveform example for instruction prefetch

Page 21

8-bit

data

read

8-bit

data

written

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Access starting from even address Access starting from odd address

Internal address bus

Internal data bus

DB0 to DB7

DB8 to DB15

BIU

Internal address bus

Internal data bus

DB0 to DB7

DB8 to DB15

BIU

Address

D0 to D7

Invalid

Address

D0 to D7

Internal address bus

BIU

Internal data bus

DB0 to DB7

DB8 to DB15

BIU

Internal data bus

DB0 to DB7

DB8 to DB15

Address

Invalid

D8 to D

BIU

16-bit

data

read

Access to internal area

16-bit

data

written

32-bit

data read

32-bit

data

written

Internal address bus

Internal data bus

DB0 to DB7

DB8 to DB15

A0 to A23

D0 to D7

D8 to D15

BIU

Internal address

bus

Internal data bus

DB0 to DB7

DB8 to DB15

BIU

Internal address

bus

Internal data bus

DB0 to DB7

DB8 to DB15

Address

D8 to D

D0 to D7

D8 to D

D0 to D7

D8 to D

Address + 2

D0 to D7D0 to D7

D8 to D

D0 to D7D0 to D7

D8 to D

BIU

D8 to D

Invalid

Address + 1

D0 to D7

D8 to D

D0 to D7

D8 to D

D0 to D7

Invalid

D0 to D7

Address + 3

D0 to D7

Invalid

Address + 3

D0 to D7

Internal address bus

Internal data bus

DB0 to DB7

DB8 to DB15

A0 to A23

D0 to D7

D8 to D15

BIU

Internal address

bus

Internal data bus

DB0 to DB7

DB8 to DB15

Internal address

bus

Internal data bus

DB0 to DB7

DB8 to DB15

BIU

Address

Address Address + 1

Invalid

D8 to D

Address Address + 1

D8 to D

Fig. 13 Bus cycle waveform example for data access (access to internal area)

Page 22

8-bit

data read

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Access starting from even address Access starting from odd address

A0 to A

D0 to D

D8 to D

BHW

ALE

BLW

Address

D0 to D

Invalid

A0 to A

D0 to D

D8 to D

BHW

ALE

BLW

Address

D8 to D

Invalid

A0 to A

D0 to D

D8 to D

BHW

A0 to A

D0 to D

D8 to D

BHW

A0 to A

D0 to D

D8 to D

BHW

ALE

BLW

ALE

BLW

ALE

BLW

8-bit

data

written

16-bit

External data bus width = 16 bits

data read

16-bit

data

written

Address

D0 to D

Address

D7 to D

D8 to D

Address

D0 to D

D8 to D

A0 to A

D0 to D

D8 to D

BHW

A0 to A

D0 to D

D8 to D

BHW

A0 to A

D0 to D

D8 to D

BHW

ALE

BLW

ALE

BLW

ALE

BLW

Address

D8 to D

Address Address + 1

Invalid

D8 to D

D0 to D

Invalid

Address Address + 1

D0 to D

D8 to D

Fig. 14 Bus cycle waveform example for data access (access to external area) (1)

Page 23

32-bit

data read

MITSUBISHI MICROCOMPUTERS

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Access starting from even address Access starting from odd address

A0 to A

D0 to D

D8 to D

BHW

ALE

BLW

Address Address + 2

D0 to D

D8 to D

D0 to D

D8 to D

A0 to A

D0 to D

D8 to D

BLW

BHW

ALE

Address Address + 1 Address + 3

Invalid

D8 to D

D0 to D

D8 to D

D0 to D

Invalid

A0 to A

D0 to D

D8 to D

BLW

BHW

ALE

A0 to A

D0 to D

32-bit

External data bus width = 16 bits

data

written

D8 to D

BHW

ALE

BLW

Address Address + 2

D0 to D

D8 to D

D0 to D

D8 to D

Fig. 15 Bus cycle waveform example for data access (access to external area) (2)

Address Address + 1 Address + 3

D0 to D

D8 to D

D0 to D

Page 24

32/16/

8-bit

data read

A0 to A

D0 to D

D8 to D

BHW

MITSUBISHI MICROCOMPUTERS

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SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Access starting from even or odd address

ALE

BLW

(Note)

Address Address + 1 Address + 2 Address + 3

D0 to D

8-bit data access

16-bit data access

32-bit data access

D0 to D

A0 to A

D0 to D

D8 to D

External data bus width = 8 bits

32/16/

8-bit

data

written

ALE

BLW

BHW

(Note)

Address Address + 1 Address + 2 Address + 3

D0 to D

8-bit data access

16-bit data access

32-bit data access

Note: When the voltage level at pin BYTE = “L”, functions as pins D8 to D15 are valid. However, when 8-bit width is selected

as the external bus width by the chip select wait controller, the functions as pins D

8 to D15 = floating, BHW = “H” output.) When the voltage level at pin BYTE = “H”, these pins function as programmable

(D I/O port (P2, P3

3) pins.

Fig. 16 Bus cycle waveform example for data access (access to external area) (3)

D0 to D

8 to D15 and BHW become invalid.

Page 25

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● Number of bus cycles

Figure 17 shows the bus cycle waveform at access to the internal area. Bit 7 of the processor mode register 1 (address 5F16) selects the number of bus cycles for the internal ROM: 3φ or 2φ. (This bit 7 is the internal ROM bus cycle select bit.) The internal RAM, SFRs (in-

1 bus cycle = 3φ (Note)

(Internal ROM bus cycle select bit = 0)

1 bus cycle = 3φ

BIU

ROM

RAM

Internal address bus

Internal data bus

Internal code bus

Address

Data

Internal address bus

BIU

ternal peripheral devices’ control registers) are always accessed with 1 bus cycle = 2φ. Figure 18 shows the bus cycle waveform at access to the external area. The bus cycle select bits 0, 1 (See the note in Figure 18.) select the number of the bus cycles for each CSi area

___

from 8 types of numbers.

1 bus cycle = 2φ

(Internal ROM bus cycle select bit = 1)

1 bus cycle = 2φ

BIU

Internal address bus

Internal data bus

Internal code bus

1 bus cycle = 2φ

Address

Data

SFR

Internal data bus

Internal code bus

Data

Note: When reprogramming the internal flash memory in the CPU reprogramming mode, select the bus cycle = 3φ.

Fig. 17 Bus cycle waveform at access to internal area

Page 26

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Bus cycle

select bit 0

0 0

0 1

1 0

Bus cycle select bit 1 = 0

Bus cycle 1φ + 1φ

1 bus cycle = 2φ

φ1

External address

External data bus

Bus cycle 1φ + 2φ

External address

External data bus

Bus cycle 1φ + 3φ

External address

External data bus

bus

CSi

BLW,BHW

ALE

bus

CSi

BLW,BHW

ALE

bus

CSi

BLW,BHW

ALE

φ1

Address

Data

1 bus cycle = 3φ

Address

1 bus cycle = 4φ

Address

Data

Bus cycle 2φ + 3φ

❈

External data bus

Bus cycle 2φ + 4φ

❈

External data bus

Bus cycle 3φ + 3φ

❈

External data bus

External address

bus

BLW,BHW

ALE

bus

BLW,BHW

ALE

bus

BLW,BHW

ALE

Bus cycle select bit 1 = 1

1 bus cycle = 5φ

2φ

φ1

Address

CSi RD

1 bus cycle = 6φ

φ1

CSi RD

1 bus cycle = 6φ

φ1

CSi RD

❈

3φ

Data

❈

4φ2φ

Address

Data

3φ3φ

Address

Data

Bus cycle 2φ + 2φ

1 bus cycle = 4φ

φ1

External address

1 1

Notes 1: The bus cycle type is determined by the following bits:

• Areas out of area CS

• Area CS

External data bus

i : area CSi bus cycle select bit 0 (bits 0 and 1 at addresses 8016, 8216, 8416, 8616)

2: ❈ indicates the bus cycle, where the burst ROM access specification is enabled.

bus

CSi

BLW,BHW

ALE

i : external bus cycle select bit 0 (bits 2 and 3 at address 5E16)

external bus cycle select bit 1 (bit 0 at address 5F area CS

Address

i bus cycle select bit 1 (bit 3 at addresses 8116, 8316, 8516, 8716)

Fig. 18 Bus cycle types at access to external area

Data

Bus cycle 3φ + 4φ

φ1

External address

External data bus

16)

bus

BLW,BHW

ALE

CSi RD

3φ

1 bus cycle = 7φ

4φ

Address

Data

Page 27

MITSUBISHI MICROCOMPUTERS

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● Recovery cycle

A recovery cycle which is equivalent to 1 or 2 cycles of φ1 can be inserted after each area CSi’s access cycle. Whether the recovery cycle is inserted or not is determined by the recovery cycle insert select bit of each CSi control register L (bit 6 at addresses 8016, 8216,

φ1

❈

to A

ALE

access

At double consecutive

❈❈

At instruction prefetch

A0 to A

ALE

access

At quadruple consecutive

At data access

___

Recovery cycle = 1 cycle of φ1 Recovery cycle = 2 cycles of φ1

Recovery

Next access

Instruction prefetch

Address Address + 2

❈ When address locates at 4-byte boundary, or when branched.

Address Address + 2 Address + 4

❈❈ When address locates at 8-byte boundary.

Access cycle

A0 to A

Address

ALE RD,

BLW, BHW

cycle

Instruction prefetch

Recovery

Next access

cycle

Address + 6

Recovery

cycle

Next access

8416, 8616). Also, the number of the recovery cycles is selected by the recovery-cycle-insert-number select bit of the processor mode register 1 (bit 6 at address 5F16). Figure 19 shows a waveform example when a recovery cycle is inserted.

Next access

cycle

Next access

cycle

Recovery cycle

Address + 6

cycle

A0 to A

Instruction prefetch

Address Address + 2

ALE

Address Address + 2 Address + 4

ALE

Access cycle

A0 to A

ALE RD,

BLW, BHW

Address

Recovery cycle

Instruction prefetch

Recovery cycle

Next access

cycle

Notes 1: The recovery cycle insert is specified by the recovery cycle insert select bit and the recovery-cycle-insert-number select bit (bits 4 and 6 at address 5F16).

Recovery cycle insertion is valid only at access to area CS

2: The above is applied when 1 bus cycle = 2φ.

Fig. 19 Waveform example when recovery cycle is inserted

Page 28

MITSUBISHI MICROCOMPUTERS

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● Burst ROM access

When ROM supporting the burst ROM access has been allocated to

___

area CSi, the burst ROM access can be specified. The burst ROM access is specified by each burst ROM access select bit of the CSi control register L (bit 5 at addresses 8016, 8216, 8416, 8616). The burst ROM access is valid only when the external data bus width = 16 bits with an instruction prefetched. In the other cases, the normal access is performed regardless of the contents of the burst ROM access select bit. The burst ROM access can be specified only in the case of ❈ in Figure 18.

(a)

External address bus

to A23)

External data bus

to D7)

External data bus

(D8 to D15)

At quadruple consecutive accessAt double consecutive access

___

Address Address Address Address

Figure 20 shows a waveform example at burst ROM access. When an instruction is prefetched from the burst ROM, 8 bytes are fetched starting from an 8-byte boundary (the low-order 3 bits of address, A2, A1, A0 = “000”) in waveform (a). When branched, regardless of the 8-byte boundary of the branch destination address, access starting from the 4-byte boundary (the low-order 2 bits of address, A1, A0 = “00”) is performed in waveform (b). Once the 8-byte boundary has been selected, instructions will be prefetched in waveform (a) until a branch.

Data

(Instruction)

Data

(Instruction)

Data

(Instruction)

Data

(Instruction)

Data

(Instruction)

Data

(Instruction)

Data

(Instruction)

Data

(Instruction)

Note: The above is applied when 1 bus cycle = 2φ.

(b)

External address bus

(A0 to A23)

External data bus

to D7)

External data bus

to D15)

Note: The above is applied when 1 bus cycle = 2φ.

Notes 1: The burst ROM access is selected by the burst ROM access select bit (bit 5 at addresses 80

2: The burst ROM access can be selected only in the case of ❈ in Figure 18.

Fig. 20 Waveform example at burst ROM access

Address Address

Data

(Instruction)

Data

(Instruction)

Data

(Instruction)

Data

(Instruction)

, 8216, 8416, 8616).

Page 29

MITSUBISHI MICROCOMPUTERS

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SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

● Address output selection

As shown in Figure 21, the unnecessary state change of address output pins (A0 to A23) can be avoided, without outputting an address at access to the internal area. When the address output select bit of the particular function select register 1 (bit 4 at address 6316) is set to “1”, an address is output only at access to the external area. Also, at access to the internal

Address output select bit = 0

Address output select bit = 1

(Address waveform changes only when external access is generated.)

A0 to A

BLW,BHW

A0 to A

BLW,BHW

area, the address at the preceding access to the external area is retained. The address output start timing in this case is the half cycle of φ1 later than that at the normal access (when the address output select bit = “0”). For the bit structure of the particular function select register 1, refer to the section on the standby function. Also, at the normal access, an address is output at both of the access to the internal and external areas.

Access to external area

Address

RD,

Access to external area

Address

Access to internal area

Unde-

fined

Address

Unde-

fined

Fig. 21 Waveform example depending on address output function selection

Page 30

MITSUBISHI MICROCOMPUTERS

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SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

● Area multiplication

When area CS2’s external data bus width = 8 bits with the multiplexed bus select bit of the CS2 control register H (bit 5 at address

8516) = “1”, the external bus type can be changed to the multiplexed bus type only at access to area CS2. In this case, the low-order 8 bits

___

Area CS2 bus cycle select bit 0

___

Bus cycle

select bit 0

Multiplexed bus select bit = 1

Bus cycle 2φ + 2φ

φ1

External address bus

At write, LA0/D0 to LA7/D7

1 1

At read, LA0/D0 to LA7/D7

CSi

RD,

BLW

ALE

Bus cycle 3φ + 3φ

φ1

External address bus

1 0

At write, LA0/D0 to LA7/D7

At read, LA0/D0 to LA7/D7

CSi RD,

BLW

ALE

of an address (LA0 to LA7) are output, and the low-order 8 bits of data (D0 to D7) are input/output with the time-sharing method, respectively. Figure 22 shows a waveform example of area multiplication for each bus cycle. Do not select the area multiplication function for a bus cycle not shown in Figure 22.

1 bus cycle = 4φ

2φ 2φ

Address

LA0 to LA7

LA0 to LA7 LA0 to LA7

D0 to D7

1 bus cycle = 6φ

3φ3φ

Address

D0 to D7

Bus cycle 3φ + 4φ

φ1

External address bus

Notes 1: The number of bus cycles is determined by the following bits:

Area multiplication is specified by the multiplexed bus select bit (bit 5 at address 8516).

2: Do not select the area multiplication function for a bus cycle not shown in Figure 22.

1 1

• Area CS2 bus cycle select bit 0 (bits 0 and 1 at address 8416)

• Area CS2 bus cycle select bit 1 (bit 3 at address 8516)

At write, LA0/D0 to LA7/D7

At read, LA0/D0 to LA7/D7

CSi RD,

BLW

ALE

Fig. 22 Waveform example of area multiplication for each bus cycle

LA0 to LA7

1 bus cycle = 7φ

4φ3φ

Address

D0 to D7

Page 31

MITSUBISHI MICROCOMPUTERS

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PROCESSOR MODES

Any of the three processor modes (single-chip mode, memory expansion mode, microprocessor mode) can be selected with the following:

• Processor mode bits of the processor mode register 0 (bits 1 and 0 at address 5E16; Figure 24)

• Voltage level applied to pin MD0

Table 3 lists the selection method of a processor mode. The memory map which the CPU can access depends on the selected processor mode. Figure 23 shows the memory maps in three processor modes. Also, the functions of ports P0 to P4, P10, P11 depend on the selected processor mode. For details, see Tables 5 and 6. Figures 24 to 26 show the bit configurations of the processor mode registers 0, 1, and port function control register. In the single-chip mode, ports P0 to P4, P10, P11 function as I/O ports. (While the internal peripheral devices are used, these ports

Single-chip mode

Unused area

Internal RAM

SFR area

area

Memory expansion mode

function as these devices’ I/O pins.) In this mode, only the internal area (SFRs, internal RAM, internal ROM) is accessible. In the memory expansion and microprocessor modes, external devices assigned in the external memory area can be connected via buses. Therefore, ports P0 to P4, P10, P11 function as I/O pins for the address bus, data bus, bus control signals. (Some port functions are selectable.) Table 4 lists each bus control signal’s function. In the memory expansion mode, all of the internal area (SFRs, internal RAM, internal ROM) and external area are accessible. In the microprocessor mode, the internal area except for the internal ROM (in other words, SFRs and internal RAM) and the external area are accessible. Note that, when the external devices are located to an area where the internal area and external area overlap, only the internal area can be read/written; the external area cannot be read/written.

Microprocessor mode

SFR area

Internal RAM

area

SFR area

Internal RAM

area

Unused area

Internal ROM

SFR area : Internal peripheral devices’ control registers are allocated here.

External area : Access to this area enables the access to the devices which

Note: Do not access this area (bank FF

Fig. 23 Memory maps in three processor modes

area

Internal ROM

area

FEFFFF

FF0000

Reserved area

FFFFFF

are connected with the external.

(Note)

Reserved area

(Note)

Page 32

M37902FCCHP, M37902FGCHP, M37902FJCHP

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Table 3. Selection method of processor mode

MD0 Processor mode bits

VSS

VCC

Notes 1: Processor mode bits = bits 0 and 1 of the processor mode register 0 (address 5E16)

2: While the Vcc level voltage is applied to pin MD0, the processor mode bits are fixed to “10”.

Table 4. Each bus control signal’s function

Signal

I/O

Output

01 10 10

Read signal. Outputs “L” at read from the external area.

(Note 1)

(Note 2)

Processor mode

Single-chip mode

Memory expansion mode

Microprocessor mode Microprocessor mode

Function

After reset is removed, the single-chip mode is selected. By changing the processor mode bits’ contents by software, the memory expansion mode or microprocessor mode can be selected.

After reset is removed, the microprocessor mode is selected.

MITSUBISHI MICROCOMPUTERS

Description

Remarks

BLW BHW

ALE

RDY

HOLD

HDLA

CS0–CS3

BYTE

Output

Write signal. Outputs “L” at write to the external area.

Output

Address latch enable signal. Outputs “H” level pulse in the period just before signals RD, BLW, BHW become “L”. This is used to latch an address in an external circuit.

Output

Internal standard clock’s output. Outputs system clock (fsys).

Input

Ready signal. The “L” level period of the last cess cycle for the external area (in other words, “L” level period of RD, BLW, BHW) will be extended while “L” level voltage is applied to this pin.

Input

Hold request signal. Appliance of “L” level voltage will generate a hold request; appliance of “H” level voltage will request to terminate the hold state.

Output

Hold acknowledge signal. Outputs “L” in the hold state.

Output

Chip select signal. Outputs “L” in access to the specified chip select area.

Input

Input signal to select the external data bus width. When this pin’s level = Vss, 16-bit width will be selected; and when Vcc, 8-bit width will be selected.

1 in the ac-

For operation differences between BLW and BHW depending on the external data bus width, see Table 5.

In order to latch an address with signal ALE, do as follows:

• While ALE = “H”, be sure to open a latch, so the address will pass it.

• While ALE = “L”, be sure to hold the address.

Acceptance and termination of a hold request is performed at completion of the bus cycle while the BIU operates. In the hold state, A0–A23, D0–D15, RD, BLW, BHW, ALE, CS0–CS3 enter the floating state. At termination of the hold state, simultaneously with the timing when HLDA becomes “H” level, the above floating state is terminated. Then, bus access will be restarted 1 cycle of In the hold state, also, the CPU operates with access to the internal area. If the CPU accesses the external area, in the hold state, the CPU stops its operation.

For details, refer to the section on the chip select wait controller.

When BYTE = Vss level, by the register setting, each chip select area (CS1 to CS3) can have the 8-bit data bus, independently.

For details, refer to the section on the chip select wait controller.

1 after.

Page 33

M37902FCCHP, M37902FGCHP, M37902FJCHP

Table 5. Relationship between processor modes, memory area, and port function (1)

Mode

(Note 1)

Port pins P100 to P107 Port pins P110 to P117

Port pins P00 to P07

Port pins

P10 to P17

Port pins

P20 to P27

Port pin

P32

Port pin

P33

Pin MD0

Processor mode

bits (Note 2)

SFR area Internal RAM area Internal ROM area

Other area

Memory area

External data bus

width = 16 bits

External data bus

width = 8 bits

External data bus

width = 16 bits

External data bus

width = 8 bits Port pin P30 Port pin P31

External data bus

width = 16 bits

External data bus

width = 8 bits

External data bus

width = 16 bits

External data bus

width = 8 bits

Single-chip mode

VSS level voltage is applied

SFR area Internal RAM area Internal ROM area

(Do not access.) I/O port pins P100 to P107 I/O port pins P110 to P117

I/O port pins P00 to P07

I/O port pins P10 to P17

I/O port pins P20 to P27

I/O port pin P30

I/O port pin P31 I/O port pin P32

I/O port pin P33

Memory expansion mode

VSS level voltage is applied

SFR area Internal RAM area Internal ROM area

External memory area Low-order address (A0 to A7) is output. Middle-order address (A8 to A15) is

output. I/O port pins P110 to P117 (Note 3) High-order address (A16 to A23) is out-

put. I/O port pins P00 to P07 (Note 3) Low-order data (D0 to D7, data at

even address) is input/output. Low-order data (D0 to D7, data at

even/odd address) is input/output. Low-order address (LA0 to LA7) is out-

put. Low-order data (D0 to D7, data at even/odd address) is input/output (Note 4).

High-order data (D8 to D15, data at odd address) is input/output.

I/O port pins P20 to P27 (Note 5)

I/O port pin P30 Ready signal RDY is input (Note 6). Read signal RD is output. Write signal BLW (write to even ad-

dress) is output. Write signal BLW (write to even/odd

address) is output. Write signal BHW (write to odd ad-

dress) is output. I/O port pin P33 (Note 5)

MITSUBISHI MICROCOMPUTERS

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Microprocessor mode

VCC level voltage is applied

SFR area

Internal RAM area External memory area External memory area

Low-order address (A0 to A7) is output. Middle-order address (A8 to A15) is

output. I/O port pins P110 to P117 (Note 3) High-order address (A16 to A23) is out-

put. I/O port pins P00 to P07 (Note 3) Low-order data (D0 to D7, data at

even address) is input/output. Low-order data (D0 to D7, data at

even/odd address) is input/output. Low-order address (LA0 to LA7) is out-

put. Low-order data (D0 to D7, data at even/odd address) is input/output (Note 4).

High-order data (D8 to D15, data at odd address) is input/output.

I/O port pins P20 to P27 (Note 5)

Ready signal RDY is input. I/O port pin P30 (Note 6) Read signal RD is output Write signal BLW (write to even ad-

dress) is output. Write signal BLW (write to even/odd

address) is output. Write signal BHW (write to odd ad-

dress) is output. I/O port pin P33 (Note 5)

Page 34

MITSUBISHI MICROCOMPUTERS

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Table 6. Relationship between processor modes, memory area, and port function (2)

Single-chip mode

I/O port pin P40

Port pin P40

Port pin P41 Port pin P42

Port pin P43

Port pin P44

Port pins P45 to P47

Notes 1: For details of the processor mode setting, see Table 3.

2: Processor mode bits = bits 0 and 1 of the processor mode register 0 (address 5E 3: The middle-order/high-order address output pins in the memory expansion or microprocessor mode can be switched to I/O port pins by the address/port

switch select bits of the port function control register (bits 2 to 0 at address 92 4: When the external data bus width for the chip select area, CS

of the CS2 control register H (bit 5 at address 8516), a multiplexed bus which performs the following operations with the time-sharing method is realized:

• Output of address LA

• Input/Output of data D0 to D7

5: When one of areas CS1/CS2/CS3 is accessed under the following conditions, pins D8 to D15 enter the floating state, and pin BHW outputs “H” level.

(They do not become I/O port pins.)

• Pin BYTE is at Vss level.

• One of bit 2s at addresses 82

width = 8 bits). 6: In the memory expansion mode, by the corresponding select bits of the processor mode register 0 and 1 (addresses 5E

P43 can operate as pins for RDY input, ALE output,

In the microprocessor mode, by the above select bits, the above pins (RDY, ALE,

tively. In the single-chip mode, port pin P4 7: In the memory expansion mode, port pin P4

16).

80 8: In the memory expansion and microprocessor modes, port pins P45 to P47 can operate as the CS1/CS2/CS3 output pins by the CSi output select bits (i =

1 to 3) (bit 7s at addresses 82

I/O port pin P41 Clock

1 is output (Note 6).

I/O port pin P42

I/O port pin P43

I/O port pin P44

I/O port pins P45 to P47

0 to LA7

16, 8416, 8616 (the external data bus width select bit of the CS1/CS2/CS3 control register L) is set to “1” (external data bus

1 can operate as the φ1 output pin by the above select bits.

16, 8416, 8616).

1 output, HLDA output, HOLD input, respectively.

4 can operate as the CS0 output pin by the CS0 output select bit of the CS0 control register L (bit 7 at address

Memory expansion mode

I/O port pin P40

Microprocessor mode

Address latch enable signal ALE is output.

Address latch enable signal

I/O port pin P4

0 (Note 6)

ALE is output (Note 6). I/O port pin P41 Clock

1 is output (Note 6).

I/O port pin P42

Clock

1 is output.

I/O port pin P41 (Note 6) Hold acknowledge signal HLDA is output.

Hold acknowledge signal

I/O port pin P42 (Note 6) HLDA is output (Note 6). I/O port pin P43

Hold request signal

Signal HOLD is input. Hold request signal

I/O port pin P43 (Note 6) HOLD is input (Note 6). I/O port pin P44

Chip select signal CS0 is output. Chip select signal CS0 is output

(Note 7). I/O port pins P45 to P47 Chip select signals CS1 to CS3 are

output (Note 8).

16).

2, has been set to 8 bits, only in the access to area CS2, by the multiplexed bus select bit

16).

1, HLDA, HOLD) can operate as port pins P30, P40 to P43, respec-

I/O port pin P45 to P47

Chip select signals CS1 to CS3 are

output (Note 8).

16, 5F16), port pins P30, P40 to

Page 35

MITSUBISHI MICROCOMPUTERS

M37902FCCHP, M37902FGCHP, M37902FJCHP

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

76543210

Processor mode register 0

Processor mode bits (Note 1)

0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode 1 1 : Do not select.

External bus cycle select bit 0 (Note 2) See Figure 18.

Interrupt priority detection time select bits

0 0 : 7 cycles of f 0 1 : 4 cycles of fsys 1 0 : 2 cycles of fsys 1 1 : Do not select.

Software reset bit By a write of “1” to this bit, the microcomputer will be reset, and then, restarted.

1 output select bit (Note 3)

Clock φ

1 output is disabled. (P41 functions as an programmable I/O port pin.)

0 : φ

1 output is enabled. (P41 functions as the clock φ1 output pin.)

1 : φ

Notes 1: While VSS level voltage is applied to pin MD0, this bit’s state is cleared to “0” at reset. While VCC level voltage is applied

to pin MD0, on the other hand, this bit’s state is set to “1” at reset. (Fixed to “1”.)

2: These bits are valid to the external area except for chip select area (area CS

by the corresponding area CS

3: While V

SS level voltage is applied to pin MD0, this bit’s state is cleared to “0” at reset. While VCC level voltage is applied

to pin MD0, on the other hand, this bit’s state is set to “1” at reset.

i bus cycle select bits 0, 1.

sys

Address

i). The bus cycle of area CSi is selected

Fig. 24 Bit configuration of processor mode register 0

Page 36

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

76543210

Processor mode register 1

External bus cycle select bit 1 (Note 1) See Figure 18.

Direct page register switch bit (Note 2)

0 : Only DPR0 is used. 1 : DPR0 to DPR3 are used.

RDY input select bit (Notes 3 to 5)

0 : RDY input is disabled. (P3 1 : RDY input is enabled. (P3

ALE output select bit (Notes 3 and 4)

0 : ALE output is disabled. (P4 1 : ALE output is enabled. (P4

Recovery cycle insert select bit (Notes 3 and 4)

0 : No recovery cycle is inserted at access to the external area. 1 : Recovery cycle is inserted at access to the external area.

HOLD input, HLDA output select bit (Notes 3 to 5)

0 : HOLD input and HLDA output are disabled.

and P42 function as programmable I/O port pins.)

(P4

1 : HOLD input and HLDA output are enabled.

and P42 function as pins HOLD and HLDA, respectively.)

(P4

Recovery-cycle-insert number select bit (Note 6)

0 : 1 cycle 1 : 2 cycles

Address

functions as a programmable I/O port pin.)

functions as pin RDY.)

functions as a programmable I/O port pin.)

functions as pin ALE.)

Notes 1: This bit is valid to the external area except for chip select areas (area CSi), and the bus cycle of area CSi is independent

of this bit’s contents. The bus cycle of area CS

, 8416, 8616; bit 3 at addresses 8116, 8316, 8516, 8716).

2: After reset, this bit’s contents can be switched only once. During the software execution, be sure not to switch this bit’s contents. 3: In the single-chip mode, these bits’ functions are disabled regardless of these bits’ contents. 4: While V

5: In the memory expansion or microprocessor mode, if this bit’s contents is switched from “1” to “0”, this bit will be cleared to “0”. 6: The program which switches this bit’s contents must be assigned to the internal area.

7: In the microprocessor mode, this bit is invalid.

to pin MD0, on the other hand, each of these bits is “1” at reset. After this clearance, this bit cannot return to “1”. If it is necessary to set this bit to “1”, be sure to reset the microcomputer.

When the internal flash memory is reprogrammed in the CPU reprogramming mode, be sure to clear this bit to “0”.

level voltage is applied to pin MD0, each of these bits is “0” at reset. While VCC level voltage is applied

is selected by the corresponding area CSi bus cycle select bits 0, 1 (bits 0, 1 at addresses 8016,

Fig. 25 Bit configuration of processor mode register 1

Internal ROM bus cycle select bit (Note 7)

0 : 3φ 1 : 2φ

Page 37

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

76543210

Port function control register

Address/Port switch select bits

Address

to A23 (16 Mbytes)

000 : A

to A21, P06, P07 (4 Mbytes)

001 : A

to A19, P04 to P07 (1 Mbytes)

010 : A

to A17, P02 to P07 (256 Kbytes)

011 : A

to A15, P00 to P07 (64 Kbytes)

100 : A 101 : Do not select.

to A11, P00 to P07, P114 to P117 (4 Kbytes)

110 : A

to A7, P00 to P07, P110 to P117 (256 bytes)

111 : A

Port P0 input level select bit

0 : V

= 0.7VCC, VIL = 0.2V

1 : VIH = 0.43VCC (Note 1), VIL = 0.16V

–P47 pullup select bit (Notes 2 and 3)

Pins P4

0 : Pins P4 1 : Pins P4

–P47 are pulled up.

–P47 are not pulled up.

Fix these bits to “0”.

Pin NMI pullup select bit (Note 2)

0 : Pin NMI is pulled up. 1 : Pin NMI is not pulled up.

At reset

Notes 1: For the M37902FxM (power source voltage = 3.3 V±0.3 V), VIH = 0.5VCC.

2: When MD1 = V

and MD0 = VCC (flash memory parallel I/O mode), pins P44 to P47 and NMI are

not pulled up, regardless of these bits’ contents.

3: When MD1 = V

and MD0 = VCC (microprocessor mode), pin CS0 (P44) is not pulled up, regardless of the bit’s contents.

Fig. 26 Bit configuration of port function control register

Page 38

M37902FCCHP, M37902FGCHP, M37902FJCHP

Chip select wait controller

By the control of the chip select wait controller (CSWC), the chip select function for the maximum of 4 blocks can be set at the bus access to the external area. Also, by the setting of the CSWC, port pins P44 to P47 can operate as chip select output pins (CS0 to CS3). Figure 27 shows a chip select output waveform example. This chip select function determines the following items of the chip select area: start address, address’s block size, wait number, external data bus width, RDY control validity, burst ROM specification, recovery cycle insertion validity, and area multiplication validity. For the external area except for areas CS0 to CS3, the processor mode registers 0, 1 determine the above items. After reset is removed, when the microcomputer starts it’s operation in the microprocessor mode, area CS0 is automatically selected. Table 7 lists the function of areas CS0 to CS3. Figure 28 shows the bit configuration of the CS0/CS1/CS2/CS3 control register Ls. These registers determine the following items of a device to be connected: wait number, external data bus width (Note: The external data bus width of area CS0 is determined by pin BYTE’s level.), RDY control validity, burst ROM access specification, recovery cycle insertion validity, and output validity of CS0 to CS3. Figure 29 shows the bit configuration of the CS0/CS1/CS2/CS3 control register Hs. These registers determine block size, etc. of an external area to be connected. For areas CS0 to CS2, by selecting mode 1 with the area CSk setting mode select bit, an chip select area can be set to the external area in bank 0. Figures 30 shows the bit configuration of the area CS0/CS1/CS2/CS3 start address registers. For details of these addresses’ setting, see Figures 31 to 33.

MITSUBISHI MICROCOMPUTERS

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

When area CSi is accessed

One access

cycle

A0 to A23

ALE

RD,

BLW, BHW

When the same area CSi is accessed sequentially

A0 to A23

ALE

RD,

BLW, BHW

Fig. 27 Chip select output waveform example

Address

One access

cycle

Address

One access

cycle

Address + 2

Page 39

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Table 7. Function of areas CS0 to CS

Space where start address can be set

Block size

Banks 216 to FE16

128 Kbytes, 256 Kbytes, 512 Kbytes, 1 Mbytes, 2 Mbytes, 4 Mbytes, or 8 Mbytes

Bus cycle

Bus cycle:

•1φ + 1φ

•1φ + 2φ

•1φ + 3φ

•2φ + 2φ

•2φ + 3φ

•2φ + 4φ

•3φ + 3φ

•3φ + 4φ

(Selected by bits 0, 1 at address 8016 and bit 3 at address 8116.)

Mode 0

CS0

Bank 016

128 Kbytes, 256 Kbytes, 512 Kbytes, 1 Mbytes, 2 Mbytes, 4 Mbytes, or 8 Mbytes

Mode 1

CS1, CS2

Mode 0

Banks 216 to FE16

128 Kbytes, 256 Kbytes, 512 Kbytes, 1 Mbytes, 2 Mbytes, 4 Mbytes, or 8 Mbytes

Bus cycle:

•1φ + 1φ

•1φ + 2φ

•1φ + 3φ

•2φ + 2φ

•2φ + 3φ

•2φ + 4φ

•3φ + 3φ

•3φ + 4φ

(Selected by bits 0, 1 at addresses 8216, 8416 and bit 3 at addresses 8316, 8516.)

External data bus width

Determined by pin BYTE’s level.

When BYTE = VSS level, 8-bit width or 16-bit width can be selected arbitrary (Note 1). (Selected by bit 2 at addresses 8216, 8416.)

RDY control

Valid (Selected by bit 2 at address 5F16 and bit 3 at address 8016.)

Valid (Selected by bit 2 at address 5F16 and bit 3 at addresses 8216,

8416.)

Burst ROM access

Available.

(Notes 2, 3)

Recovery cycle

Available.

insertion Area multiplexed bus

access (Note 3) Address output

Not available.

Available.

CS1: Not available. CS2: Available. (Note 4)

Available.

selection (Note 5)

Notes 1: When BYTE = Vcc level, the external data bus width is fixed to 8 bits.

2: Burst ROM access is valid only when the external data bus width is 16 bits at instruction prefetch. 3: Burst ROM access and area multiplexed bus access cannot be used at the same time. 4: Valid only when area CS 5: Selected by the address output select bit (bit 4 at address 63

2 is accessed with the 8-bit external data bus width.

16). The address output selection for each area is not available.

Mode 1

Bank 016

4 Kbytes or 8 Kbytes

CS3

Banks 216 to FE16

128 Kbytes, 256 Kbytes, 512 Kbytes, 1 Mbytes, 2 Mbytes, 4 Mbytes, or 8 Mbytes

Bus cycle:

•1φ + 1φ

•1φ + 2φ

•1φ + 3φ

•2φ + 2φ

•2φ + 3φ

•2φ + 4φ

•3φ + 3φ

•3φ + 4φ

(Selected by bits 0, 1 at address 8616 and bit 3 at address 8716.)

When BYTE = VSS level, 8-bit width or 16-bit width can be selected arbitrary (Note 1). (Selected by bit 2 at address 8616.)

Valid (Selected by bit 2 at address 5F16 and bit 3 at address 8616.)

Available.

Not available.

Available.

External area except for CS0 to CS

Bus cycle:

•1φ + 1φ

•1φ + 2φ

•1φ + 3φ

•2φ + 2φ

•2φ + 3φ

•2φ + 4φ

•3φ + 3φ

•3φ + 4φ

(Selected by bits 2, 3 at address 5E16 and bit 0 at address 5F16.)

Determined by pin BYTE’s level

Valid (Selected by bit 2 at address 5F16.)

Not available.

Available.

Not available.

Available.

Page 40

MITSUBISHI MICROCOMPUTERS

M37902FCCHP, M37902FGCHP, M37902FJCHP

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

76543210

control register L

bus cycle select bit 0

Area CS

See Figure 18.

External data bus width select bit (Note 1)

0 : 16-bit width 1 : 8-bit width

RDY control bit (Note 2)

0 : RDY control is valid. 1 : RDY control is invalid.

“0” at read. Burst ROM access select bit (Note 3)

0 : Normal access 1 : Burst ROM access

Recovery cycle insert select bit

0 : No recovery cycle is inserted at access to area CS 1 : Recovery cycle is inserted at access to area CS

CS0 output select bit (Notes 4, 5)

output is disabled. (P44 functions as a programmble I/O port pin.)

0 : CS

output is enabled. (P44 functions as pin CS0.)

1 : CS

Notes 1: While V

level voltage is applied to pin BYTE, this bit’s state is cleared to “0” at reset. While VCC level voltage is

applied to pin BYTE, on the other hand, this bit’s state is set to “1” at reset.

2: This bit is valid when the RDY input select bit (bit 2 at address 5F

3: While V

level voltage is applied to pin BYTE, the normal access is selected regardless of this bit’s contents.

4: In the single-chip mode, this bit’s contents are invalid. (CS

5: While V

level voltage is applied to pin MD0, this bit’s state is cleared to “0” at reset. While VCC level voltage is

applied to pin MD0, on the other hand, this bit’s state is set to “1” at reset. (Fixed to “1”.)

Address

) = “1”.

output is disabled.)

At reset

76543210

control register L

Area CS

bus cycle select bit 0 (j = 1 to 3)

Address

82 84

See Figure 18.

External data bus width select bit

0 : 16-bit width 1 : 8-bit width (Note 1)

RDY control bit (Note 2)

0 : RDY control is valid. 1 : RDY control is invalid.

“0” at reading.

Burst ROM access select bit (Note 3)

0 : Normal access 1 : Burst ROM access

Recovery cycle insert select bit

0 : No recovery cycle is inserted at access to area CS 1 : Recovery cycle is inserted at access to area CS

CSj output select bit (j = 1 to 3) (Note 4)

output is disabled. (P45 to P47 function as programmable I/O port pins.)

0 : CS

output is enabled. (P45 to P47 function as pin CSj.)

1 : CS

Notes 1: While VCC level voltage is applied to pin BYTE, this bit is fixed to “1” (8-bit width).

2: This bit is valid when the RDY input select bit (bit 2 at address 5F 3: When only the external data bus width select bit (bit 2) = “1” or while V

) = “1”.

level voltage is applied to pin BYTE, the

normal access is selected regardless of this bit’s contents.

4: In the single-chip mode, this bit’s contents are invalid. (CS

output is disabled.)

42 42

Fig. 28 Bit configuration of CS0/CS1/CS2/CS3 control register Ls

Page 41

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

76543210

control register H

Area CS

block size select bit

When mode 0 is selected

0 0 0 : 0 byte (Area CS 0 0 1 : 128 Kbytes 0 1 0 : 256 Kbytes 0 1 1 : 512 Kbytes 1 0 0 : 1 Mbytes 1 0 1 : 2 Mbytes 1 1 0 : 4 Mbytes 1 1 1 : 8 Mbytes

bus cycle select bit 1

Area CS

See Figure 18.

Address

is invalid.)

At reset

When mode 1 is selected

0 0 0 : 0 byte (Area CS 0 0 1 : 128 Kbytes 0 1 0 : 256 Kbytes 0 1 1 : 512 Kbytes 1 0 0 : 1 Mbytes 1 0 1 : 2 Mbytes 1 1 0 : 4 Mbytes 1 1 1 : 8 Mbytes

is invalid.)

“0” at read. Area CS0 setting mode select bit

0 : Mode 0 (A block can be set to 16-Mbyte space.) 1 : Mode 1 (Area CS

control register H

Area CS

block size select bit

When mode 0 is selected

0 0 0 : 0 byte (Area CS 0 0 1 : 128 Kbytes 0 1 0 : 256 Kbytes 0 1 1 : 512 Kbytes 1 0 0 : 1 Mbytes 1 0 1 : 2 Mbytes 1 1 0 : 4 Mbytes 1 1 1 : 8 Mbytes

bus cycle select bit 1

Area CS

See Figure 18.

start address can be set to bank 0.)

Address

is invalid.)

At reset

When mode 1 is selected

0 0 0 : 0 byte (Area CS 0 0 1 : Do not select. 0 1 0 : Do not select. 0 1 1 : Do not select. 1 0 0 : 4 Kbytes 1 0 1 : 8 Kbytes 1 1 0 : Do not select. 1 1 1 : Do not select.

is invalid.)

“0” at read. Must be fixed to “0”. Area CS1 setting mode select bit

0 : Mode 0 (A block can be set to 16-Mbyte space in a unit of 128 Kbytes.) 1 : Mode 1 (A block can be set to bank 0 in a unit of 4 Kbytes.)

76543210

control register H

block size select bit

Area CS

When mode 0 is selected

0 0 0 : 0 byte (Area CS 0 0 1 : 128 Kbytes 0 1 0 : 256 Kbytes 0 1 1 : 512 Kbytes 1 0 0 : 1 Mbytes 1 0 1 : 2 Mbytes 1 1 0 : 4 Mbytes 1 1 1 : 8 Mbytes

Area CS2 bus cycle select bit 1

See Figure 18.

is invalid.)

Address

At reset

When mode 1 is selected

0 0 0 : 0 byte (Area CS 0 0 1 : Do not select. 0 1 0 : Do not select. 0 1 1 : Do not select. 1 0 0 : 4 Kbytes 1 0 1 : 8 Kbytes 1 1 0 : Do not select. 1 1 1 : Do not select.

is invalid.)

“0” at read.

Multiplexed bus select bit

0 : Separated bus (D 1 : Multiplexed bus (When the CS

with area CS

Area CS

setting mode select bit 0 : Mode 0 (A block can be set to 16-Mbyte space in a unit of 128 Kbytes.) 1 : Mode 1 (A block can be set to bank 0 in a unit of 4 Kbytes.)

control register H

Area CS

block size select bit 0 0 0 : 0 byte (Area CS 0 0 1 : 128 Kbytes 0 1 0 : 256 Kbytes 0 1 1 : 512 Kbytes 1 0 0 : 1 Mbytes 1 0 1 : 2 Mbytes 1 1 0 : 4 Mbytes 1 1 1 : 8 Mbytes

Area CS3 bus cycle select bit 1

See Figure 18.

to D7 are input/output.)

accessed, LA0/D0 to LA7/D7 are input/output.)

external data bus width = 8 bits

Address

is invalid.)

At reset

“0” at read.

Fig. 29 Bit configuration of CS0/CS1/CS2/CS3 control register Hs

Page 42

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

76543210

Area CS

start address register

Address

“0” at read. When mode 0 is selected, these bits determine A

When mode 1 is selected, these bits determine A

16 8

Any of the following values can be set to these bits: “10 (Bits 0 to 3 are always “0” at read.)

Note: Do not set a value other than “1016”, “2016”, “4016”, and “8016”. See Figure 31.

76543210

Area CS

start address register

Area CS

Address

8C 8E

“0” at read. When mode 0 is selected, these bits determine A

When mode 1 is selected, these bits determine A

16 8

(Bit 0 is always “0” at read.)

Note: The start address setting depends on the block size, which has been selected by the area CS

(bits 0 to 2 at address 83

76543210

, bits 0 to 2 at address 8516). See Figures 32 and 33.

Address

Area CS

start address register

“0” at read. These bits determine A

to A23 of the area CS3 start address.

(Bit 0 is always “0” at read.)

At reset

to A23 of the area CS0 start address.

to A15 of the area CS0 start address.

”, “2016”, “4016”, and “8016”.

At reset

00 00

to A23 of the area CS1/CS2 start address.

to A15 of the area CS1/CS2 start address.

/CS2 block size select bits

At reset

Note: The start address setting depends on the block size, which has been selected by the area CS3 block size select bits

(bits 0 to 2 at address 87

). See Figure 33.

Fig. 30 Bit configuration of area CS0/CS1/CS2/CS3 start address registers

Page 43

MITSUBISHI MICROCOMPUTERS

128K

bytes

512K

bytes

128K

bytes

512K

bytes

256K

bytes

1000

1FFFF

7FFFF

FFFFF

128K

bytes

512K

bytes

Start address : 1000

Value to be set to area CS

start

address register = “10

”

Block size

2000

Start address : 2000

Value to be set to area CS

start

address register = “20

”

4000

Start address : 4000

Value to be set to area CS

start

address register = “40

”

8000

128K

bytes

Start address : 8000

Value to be set to area CS

start

address register = “80

”

Area CS

cannot be assigned here.

Note: When an area where area CS

and the internal area overlap is accessed, the internal area will be accessed. In this case,

pin CS

outputs “H” level.

3FFFF

256K

bytes

1FFFFF

bytes

512K

bytes

256K

bytes

3FFFFF

7FFFFF

Block size

256K

bytes

M37902FCCHP, M37902FGCHP, M37902FJCHP

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Fig. 31 Area CS0 (mode 1)

Page 44

MITSUBISHI MICROCOMPUTERS

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Block size : 4 Kbytes

Addresses which can be start address (Address FFFF16 is not included; Note 1)

016

100016

200016

300016

400016

500016

600016

700016

800016

F00016

(FFFF16)

Block size : 8 Kbytes

Addresses which can be start address (Address FFFF16 is not included; Note 1)

016

4 Kbytes

200016

400016

600016

800016 E00016

(FFFF16)

8 Kbytes

Notes 1: Only A8 to A15 of one of these addresses

can be set to the area CS

1/CS2 start address

2: When an area where area CS

1/CS2 and the

internal area overlap is accessed, the internal area will be accessed. In this case, pin CS outputs “H” level.

1/CS2

Fig. 32 Area CS1/CS2 (mode 1)

Page 45

Notes 1: Only A

to A

of one of these addresses can be set to the area CS

/CS

start

address register. Do not set another address not shown here.

2: When an area where area CS

/CS

and the internal area overlap is accessed,

the internal area will be accessed. In this case, pin CS

/CS

outputs “H” level.

Block size : 128 Kbytes

Addresses which can

be start address

(Addresses 0

and

FF0000

to FFFFFF

are not included;

Note 1)

: Area CS

/CS

cannot be assigned here.

)

20000

40000

60000

80000

A0000

C0000

E0000

100000

F60000

F80000

FA0000

FC 0000

FE0000

(FF0000

)

(FFFFFF

)

120000

Block size : 256 Kbytes

Addresses which can

be start address

(Addresses 0

and

FF0000

to FFFFFF

are not included;

Note 1)

)

40000

80000

C0000

100000

F80000

FC 0000

(FF0000

)

(FFFFFF

)

Block size : 512 Kbytes

Addresses which can

be start address

(Addresses 0

and

FF0000

to FFFFFF

are not included;

Note 1)

)

80000

100000

F80000

(FF0000

)

(FFFFFF

)

Block size : 1 Mbytes

Addresses which can

be start address

(Addresses 0

and

FF0000

to FFFFFF

are not included;

Note 1)

)

100000

200000

300000

400000

500000

600000

700000

800000

B00000

C00000

D00000

E00000

F00000

(FF0000

)

(FFFFFF

)

900000

A00000

Block size : 2 Mbytes

Addresses which can

be start address

(Addresses 0

and

FF0000

to FFFFFF

are not included;

Note 1)

)

200000

400000

600000

800000

C00000

E00000

(FF0000

)

(FFFFFF

)

A00000

Block size : 4 Mbytes

Addresses which can

be start address

(Addresses 0

and

FF0000

to FFFFFF

are not included;

Note 1)

)

400000

800000

C00000

(FF0000

)

(FFFFFF

)

Block size : 8 Mbytes

Addresses which can

be start address

(Addresses 0

and

FF0000

to FFFFFF

are not included;

Note 1)

)

800000

(FF0000

)

(FFFFFF

)

: Reserved area. Do not access this area.

MITSUBISHI MICROCOMPUTERS

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Fig. 33 Area CS0/CS1/CS2 (mode 0) and area CS

Page 46

MITSUBISHI MICROCOMPUTERS

76543210

Note: When the key input interrupt select bit (bit 0 at address 9416) = “1”,

the status of pin INT

cannot be read out.

INT

read bit

INT

read bit

INT

read bit

INT

read bit (Note)

INT

read bit NMI read bit Undefined at read.

External interrupt input read register

Address

M37902FCCHP, M37902FGCHP, M37902FJCHP

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

INTERRUPTS

Table 8 shows the interrupt sources and the corresponding interrupt vector addresses. Reset is also handled as a type of interrupt in this section, too. DBC and BRK instruction are interrupts used only for debugging. Therefore, do not use these interrupts. Interrupts other than reset, watchdog timer, zero divide, NMI, and address matching detection all have interrupt control registers. Table 9 shows the addresses of the interrupt control registers and Figure 35 shows the bit configuration of the interrupt control register. The interrupt request bit is automatically cleared by the hardware during reset or when processing an interrupt. Also, interrupt request bits other than watchdog timer and NMI can be cleared by software. An NMI interrupt request is a non-maskable interrupt by an external input and is accepted at the falling edge of an input to pin NMI. Also, pin NMI has the pullup function. For more details, refer to the section on input/output pins. An INTi (i = 0 to 4) interrupt request is generated by an external input. INT0 to INT2 are external interrupts; whether to cause an interrupt at the input level (level sense) or at the edge (edge sense) can be selected with the level/edge select bit. Furthermore, the polarity of the interrupt input can be selected with the polarity select bit. For INT3 and INT4, the interrupt signal’s polarity can be change by the polarity select bit. (This is valid only in the edge sense.) By pins INT2 to INT4 select bits (bits 4 to 6 at address 9416; see Figure 40.), pin position of INT2 to INT4 can be changed. When using the following pins as external interrupt input pins, clear the direction registers of the corresponding multiplexed ports to “0”: pins P62/INT0, P63/INT1, P64(P77)/INT2, P80(P74)/INT3, and P84(P75)/INT4. Furthermore, the INT3 interrupt can function as the key input interrupt. For details, refer to the section on the key input interrupt. When the external interrupt input read register (address 9516) is read out, the status of pins INT0 to INT4 and NMI can directly be read. Timer and UART interrupts are described in the respective section. The priority of interrupts when multiple interrupt requests are caused simultaneously is partially fixed by hardware, but, it can also be adjusted by software as shown in Figure 36. The hardware priority is fixed as the following: reset > NMI > watchdog timer > other interrupts

Table 8. Interrupt sources and interrupt vector addresses

Interrupts Address matching detection interrupt INT4 external interrupt INT3 external interrupt A-D conversion UART1 transmit UART1 receive UART0 transmit UART0 receive Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 INT2 external interrupt INT1 external interrupt INT0 external interrupt NMI external interrupt Watchdog timer DBC (Do not select.) Break instruction (Do not select.) Zero divide Reset

Vector addresses 00FFCA16 00FFCB16 00FFD016 00FFD116 00FFD216 00FFD316 00FFD416 00FFD516 00FFD616 00FFD716 00FFD816 00FFD916 00FFDA16 00FFDB16 00FFDC16 00FFDD16 00FFDE16 00FFDF16 00FFE016 00FFE116 00FFE216 00FFE316 00FFE416 00FFE516 00FFE616 00FFE716 00FFE816 00FFE916 00FFEA16 00FFEB16 00FFEC16 00FFED16 00FFEE16 00FFEF16 00FFF016 00FFF116 00FFF216 00FFF316 00FFF416 00FFF516 00FFF616 00FFF716 00FFF816 00FFF916 00FFFA16 00FFFB16 00FFFC16 00FFFD16 00FFFE16 00FFFF16

Fig. 34 Bit configuration of external interrupt input read register

Page 47

M37902FCCHP, M37902FGCHP, M37902FJCHP

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

76543210

Interrupt priority level select bits (Note 1) Interrupt request bit 0 : No interrupt requested 1 : Interrupt requested

Interrupt control register bit configuration for A-D converter, UART0, UART1, timer A0 to timer A4, and timer B0 to timer B2.

76543210

Interrupt priority level select bits (Notes 1, 2) Interrupt request bit 0 : No interrupt requested 1 : Interrupt requested Polarity select bit 0 : Interrupt request bit is set to “1” at “H” level when level sense is selected;

this bit is set to “1” at falling edge when edge sense is selected.

1 : Interrupt request bit is set to “1” at “L” level when level sense is selected;

this bit is set to “1” at rising edge when edge sense is selected. Level/Edge select bit 0 : Edge sense 1 : Level sense

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Interrupt control register bit configuration for INT

76543210

Interrupt control register bit configuration for INT

Notes 1: Use the MOVM (MOVMB) instruction or the STA (STAB, STAD) instruction for writing to this bit.

2: Interrupt request bits of INT

Fig. 35 Bit configuration of interrupt control register

– INT

Interrupt priority level select bits Interrupt request bit (Note 1) 0 : No interrupt requested 1 : Interrupt requested Polarity select bit 0 : Interrupt request bit is set to “1” at falling edge. 1 : Interrupt request bit is set to “1” at rising edge.

and INT

to INT2 are invalid when the level sense is selected.

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Table 9. Addresses of interrupt control registers

Interrupt control registers INT3 interrupt control register INT4 interrupt control register A-D interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register INT2 interrupt control register

Addresses

00006E16

00006F16 00007016 00007116 00007216 00007316 00007416 00007516 00007616 00007716 00007816

00007916 00007A16 00007B16 00007C16 00007D16 00007E16

00007F16

Interrupts caused by the address matching detection and when dividing by zero are software interrupts and are not included in Figure

36. Other interrupts previously mentioned are A-D converter, UART, etc. interrupts. The priority of these interrupts can be changed by changing the priority level in the corresponding interrupt control register by software. Figure 37 shows a diagram of the interrupt priority detection circuit When an interrupt is caused, each interrupt device compares its own priority with the priority from above and if its own priority is higher, then it sends the priority below and requests the interrupt. If the priorities are the same, the one above has priority. This comparison is repeated to select the interrupt with the highest priority among the interrupts that are being requested. Finally the selected interrupt is compared with the processor interrupt priority level (IPL) contained in the processor status register (PS) and the request is accepted if it is higher than IPL and the interrupt disable flag I is “0”. The request is not accepted if flag I is “1”. The reset, NMI, and watchdog timer interrupts are not affected by the interrupt disable flag I. When an interrupt is accepted, the contents of the processor status register (PS) is saved to the stack and the interrupt disable flag I is set to “1”. Furthermore, the interrupt request bit of the accepted interrupt is cleared to “0” and the processor interrupt priority level (IPL) in the processor status register (PS) is replaced by the priority level of the accepted interrupt. Therefore, multi-level priority interrupts are possible by resetting the interrupt disable flag I to “0” and enable further interrupts. For reset, watchdog timer, zero divide, NMI, and address match detection interrupts, which do not have an interrupt control register, the processor interrupt level (IPL) is set as shown in Table 10.

The interrupt request bit and the interrupt priority level of each interrupt source are sampled and latched at each operation code fetch cycle while fsys is “H”. However, no sampling pulse is generated until the cycles whose number is selected by software has passed, even if the next operation code fetch cycle is generated. The detection of an interrupt which has the highest priority is performed during that time.

Priority is determined by hardware

➃

A-D converter, UART, etc. interrupts Priority can be changed by software inside ➃.

➂➁➀

Watchdog

timer

NMI



Reset

Fig. 36 Interrupt priority

Level 0

INT

A-D

Interrupt request

Reset

NMI

Watchdog timer

Interrupt disable flag I

IPL

UART1 transmit

UART1 receive

UART0 transmit

UART0 receive

Timer B2

Timer B1

Timer B0

Timer A4

Timer A3

Timer A2

Timer A1

Timer A0

INT

Fig. 37 Interrupt priority detection

Page 49

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As shown in Figure 38, there are three different interrupt priority detection time from which one is selected by software. After the selected time has elapsed, the highest priority is determined and is processed after the currently executing instruction has been completed. The time is selected with bits 4 and 5 of the processor mode register 0 (address 5E16) shown in Figure 24. Table 11 shows the relationship between these bits and the number of cycles. After a reset, the processor mode register 0 is initialized to “0016.” Therefore, the longest time is automatically set, however, the shortest time must be selected by software.

sys

Operation code fetch cycle

Table 10.

Reset Watchdog timer NMI Zero divide Address matching detection

Value loaded in processor interrupt level (IPL) during an interrupt

Interrupt types

Setting value

0 7

7 Not change value of IPL. Not change value of IPL.

T able 11. Relationship between interrupt priority detection time select

bit and number of cycles

Priority detection time select bit

Bit 5

0 0 1

Bit 4

0 1 0

Number of cycles (Note)

7 cycles of fsys 4 cycles of fsys 2 cycles of fsys

Note: For system clock fsys, refer to the section on the clock gener-

ating circuit.

Sampling pulse

Priority detection time Select one between 00 to

10 with bits 4 and 5 of processor mode register 0

Fig. 38 Interrupt priority detection time

(Note)

b5b4



0 0

    

0 1

    

1 0



Note: This pulse resides when 2 cycles of f

sys is selected.

Page 50

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Key Input Interrupt

The INT3 interrupt can function as the key input interrupt by setting bits 1 to 3 of the external interrupt input control register (address

9416). The key input interrupt uses inputs KI0 to KI3. Figure 39 shows the block diagram of the INT3/key input interrupt input circuit, and Figure 40 shows the bit configuration of the external interrupt input control register. When bit 0 of the external interrupt input control register (key input interrupt select bit)= “0”, a signal from pin INT3 is connected to the INT3 interrupt control circuit, and INT3 external interrupt is normally performed. When bit 0 = “1”, signals from pins KI0 to KI3, which correspond to ports P54 to P57 pins, are inverted, and then, the logical sum of these signals is connected to the INT3 interrupt control regis-

Pin INT3

P80/INT3

P74/(INT3)

Pullup transistor

select bit

Port P57 direction register Key input interrupt pin

pullup select bit

3 enable signal (Note)

ter. In this case, the external interrupt which uses pins KI0 to KI3 is performed. Bits 2 and 3 of the external interrupt input control register are the key input interrupt pin select bits. By setting these bits, the combination of key input interrupt pins can be selected. The interrupt vector addresses and interrupt control register of the key input interrupt are common to those of the INT3 interrupt. Additionally, pullup resistors (transistors) can be added to pins KI0 to KI4 by setting as follows:

• Set bit 1 of the external interrupt input control register to “1”.

• Next, select the key input interrupt pins by bits 2 and 3 of the exter-

nal interrupt input control register.

• Then, clear the contents of the port direction register which corresponds to the selected pins to “0”.

Key input interrupt select bit

Interrupt control circuit

INT3 interrupt control register

INT3 interrupt request

P57/KI3

Pullup transistor

P56/KI2

Pullup transistor

P55/KI1

Pullup transistor

P54/KI0

Port P56 direction register

Key input interrupt pin pullup select bit

KI2 enable signal (Note)

Port P5

5 direction register

Key input interrupt pin pullup select bit

KI1 enable signal (Note)

Port P54 direction register

Key input interrupt pin pullup select bit

KI0 enable signal (Note)

Fig. 39 Block diagram of INT3/key input interrupt input circuit

Note: KI

i enable signal (i = 0 to 3) means a signal which becomes

“1” when the key input interrupt select bit = “1” and pin KI selected by the key input interrupt pin select bits.

• Port P5j direction register : bit j (j = 4 to 7) at address D

• INT3 interrupt control register : address 6E16

• Key input interrupt select bit : bit 0 at address 9416

•

Key input interrupt pin pullup select bit

• Pin INT3 select bit : bit 5 at address 9416

: bit 1 at address 9416

i is

Page 51

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76543210 0

External interrupt input control register

Key input interrupt select bit 0: INT

interrupt

1: Key input interrupt Key input interrupt pin pullup select bit

0: Pins KI 1: Pins KI

to KI3 are not pulled up.

to KI3 are pulled up.

Key input interrupt pin select bits (Note 1)

to KI

3 2

to P64.

to P77 (Note 2).

0 0: Pins KI 0 1: Pins KI0 to KI 1 0: Pins KI0 and KI 1 1: Pin KI

select bit

Pin INT 0: Allocate pin INT 1: Allocate pin INT

Pin INT3 select bit (Note 3)

0: Allocate pin INT 1: Allocate pin INT

to P80.

to P74.

Pin INT4 select bit

0: Allocate pin INT 1: Allocate pin INT

to P84.

to P75 (Note 4).

Fix this bit to “0”.

Address

At reset

Notes 1: When using pin KIi, do not select timer A’s output pins and pulse output pins which are multiplexed with pin KIi.

2: When pin INT

address 96

3: When pin INT

When pin INT

4: When pin INT

is allocated to P77, do not use pin AN7/AD

) to “0” (output disabled).

is allocated to P80, clear the D-A2 output enable bit (bit 2 at address 9616) to “0” (output disabled).

is allocated to P74, do not use pin AN4.

is allocated to P75, do not use pin AN5.

Fig. 40 Bit configuration of external interrupt input control register

TRG

. Additionally, clear the D-A1 output enable bit (bit 1 at

Page 52

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

TIMER

There are eight 16-bit timers. They are divided by type into timer A(5) and timer B(3). The timer I/O pins are multiplexed with I/O pins for port P5 and P6. To use these pins as timer input pins, the port direction register bit corresponding to the pin must be cleared to “0” to specify input mode.

TIMER A

Figure 41 shows a block diagram of timer A. Timer A has four modes: timer mode, event counter mode, one-shot pulse mode, and pulse width modulation mode. The mode is selected with bits 0 and 1 of the timer Ai mode register (i = 0 to 4). Each of these modes is described below. Figure 42 shows the bit configuration of the timer A clock division select register. Timers A0 to A4 use the count source which has been

Timer A clock division select bit

512

4096

Count source select bits

• Timer

• One-shot pulse

• Pulse width

selected by bits 0 and 1 of this register.

(1) Timer mode [00]

Figure 43 shows the bit configuration of the timer Ai mode register during timer mode. Bits 0, 1 and 5 of the timer Ai mode register must be “0” in timer mode. The timer A’s count source is selected by bits 6 and 7 of the timer Ai mode register and the contents of the timer A clock division select register. (See Table 12.) The counting of the selected clock starts when the count start bit is “1” and stops when it is “0”. Figure 44 shows the bit configuration of the count start bit. The counter is decremented, an interrupt is caused and the interrupt request bit in the timer Ai interrupt control register is set when the contents becomes 000016. At the same time, the contents of the reload register is transferred to the counter and count is continued.

Data bus (odd)

Data bus (even)

(Low-order 8 bits) (High-order 8 bits)

Reload register(16)

Polarity

OUT

selection

Pulse output

TAi (i = 0–4)

TAi

(i = 0–4)

Fig. 41 Block diagram of timer A

Timer (gate function)

Event counter

External trigger

Count start register

(Address 40

Up-down register

(Address 44

Toggle flip-flop

)

Countdown

Counter (16)

Countup/Countdown switching

“Countdown” is always selected when not in the event counter mode.

Timer A0 4716 46 Timer A1 4916 48 Timer A2 4B16 4A

)

Timer A3 4D16 4C Timer A4 4F16 4E

Addresses

16 16

Page 53

M37902FCCHP, M37902FGCHP, M37902FJCHP

Clock source select bits

(bits 7 and 6 at addresses

to 5A16)

1 0

0 0 0 1

Timer A clock division select bits

(bits 1 and 0 at address 45

)

1 1 f

512

4096

512

4096

Do not select.

Note: Timers A0 to A4 use the same clock, which is selected by the

timer A clock division select bits.

When bit 2 of the timer Ai mode register is “1”, the output is generated from TAiOUT pin. The output is toggled each time the contents of the counter reaches to 000016. When the contents of the count start bit is “0”, “L” is output from TAiOUT pin. When bit 2 is “0”, TAiOUT can be used as a normal port pin. When bit 4 is “0”, TAiIN can be used as a normal port pin. When bit 4 is “1”, counting is performed only while the input signal from the T AiIN pin is “H” or “L” as shown in Figure 45. Therefore, this can be used to measure the pulse width of the TAiIN input signal. Whether to count while the input signal is “H” or while it is “L” is determined by bit 3. If bit 3 is “1”, counting is performed while the TAiIN pin input signal is “H” and if bit 3 is “0”, counting is performed while it is “L”. Note that, the duration of “H” or “L” on the TAiIN pin must be 2 or more cycles of the timer count source. When data is written to timer Ai register with timer Ai halted, the same data is also written to the reload register and the counter. When data is written to timer Ai which is busy, the data is written to the reload register, but not to the counter. The new data is reloaded from the reload register to the counter at the next reload time and counting continues. The contents of the counter can be read at any time. When the value set in the timer Ai register is n, the timer frequency division ratio is 1/(n+1).

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76543210

Timer A clock division select register

Timer A clock division select bit (See Table 12.)

“0” at read.

Fig. 42 Bit configuration of timer A clock division select register

Table 12. Relationship between timer A clock division select bits,

clock source select bits, and count source

Address

6543210

Note: When using pins TA2

Because they are key input interrupt pins and are multiplexed with pins TA2

0 0 : Always “00” in timer mode 0 : No pulse output (TAi

1 : Pulse output (TAi 0

1 0 : Count only while TAi 1 1 : Count only while TAi

0 : Always “0” in timer mode. Clock source select bits

See Table 12.

OUT and TA3OUT as pulse output pins, do not select pins KI0 and KI2.

Fig. 43 Bit configuration of timer Ai mode register during timer mode

Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register

OUT is pulse output pin.) (Note)

: No gate function (TAiIN is normal port pin.)

Addresses

56 5716 5816 5916

5A16

OUT is normal port pin.)

IN input is “L”. IN input is “H”.

OUT and TA3OUT.

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76543210

Fig. 44 Bit configuration of count start register

Selected clock source fi

Count start register (Stop at “0”, Start at “1”)

Timer A0 count start bit Timer A1 count start bit Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit Timer B0 count start bit Timer B1 count start bit Timer B2 count start bit

Address

TAi

Timer mode register

Bit 4 Bit 3

Timer mode register

Bit 4 Bit 3

Fig. 45 Count waveform when gate function is available

Page 55

M37902FCCHP, M37902FGCHP, M37902FJCHP

(2) Event counter mode [01]

Figure 46 shows the bit configuration of the timer Ai mode register during event counter mode. In event counter mode, bit 0 of the timer Ai mode register must be “1” and bits 1 and 5 must be “0”. The input signal from the TAiIN pin is counted when the count start bit shown in Figure 44 is “1” and counting is stopped when it is “0”. Count is performed at the fall of the input signal when bit 3 is “0” and at the rise of the signal when it is “1”. In event counter mode, whether to increment or decrement the count can be selected with the up-down bit or the input signal from the TAiOUT pin. When bit 4 of the timer Ai mode register is “0”, the up-down bit is used to determine whether to increment or decrement the count (decrement when the bit is “0” and increment when it is “1”). Figure 47 shows the bit configuration of the up-down register. When bit 4 of the timer Ai mode register is “1”, the input signal from the TAiOUT pin is used to determine whether to increment or decrement the count. However, note that bit 2 must be “0” if bit 4 is “1.” It is because if bit 2 is “1”, TAiOUT pin becomes an output pin to output pulses. The count is decremented when the input signal from the T AiOUT pin is “L” and incremented when it is “H”. Determine the level of the input signal from the TAiOUT pin before a valid edge is input to the TAiIN pin. An interrupt request signal is generated and the interrupt request bit in the timer Ai interrupt control register is set when the counter reaches 000016 (decrement count) or FFFF16 (increment count). At the same time, the contents of the reload register is transferred to the counter and the count is continued. When bit 2 is “1,” each time the counter reaches 000016 (decrement count) or FFFF16(increment count), the waveform’s polarity is reversed and is output from TAiOUT pin. If bit 2 is “0”, TAiOUT pin can be used as a normal port pin. However, if bit 4 is “1” and the TAiOUT pin is used as an output pin, the output from the pin changes the count direction. Therefore, bit 4 must be “0” unless the output from the T AiOUT pin is to be used to select the count direction.

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Timer A0 mode register Timer A1 mode register Timer A2 mode register

76543210

××

Note: When using pins TA2OUT and TA3OUT as pulse output pins, do

not select pins KI pins and are multiplexed with pins TA2

Timer A3 mode register Timer A4 mode register

100

0 1 : Always “01” in event counter mode 0 : No pulse output

1 : Pulse output 0 : Count at the falling edge of input signal

1 : Count at the rising edge of input signal

0 : Increment or decrement according to up/down bit 1 : Increment or decrement according to TAi

0 : Always “0” in event counter mode × × : Not used in event counter mode

0 and KI2. Because they are key input interrupt

OUT pin input signal level

Fig. 46 Bit configuration of timer Ai mode register during event counter mode

76543210

Up-down register Timer A0 up-down bit

Timer A1 up-down bit Timer A2 up-down bit Timer A3 up-down bit Timer A4 up-down bit Timer A2 two-phase pulse signal

processing select bit 0 : Two-phase pulse signal processing disabled 1 : Two-phase pulse signal processing mode

Timer A3 two-phase pulse signal processing select bit 0 : Two-phase pulse signal processing disabled 1 : Two-phase pulse signal processing mode

Timer A4 two-phase pulse signal processing select bit 0 : Two-phase pulse signal processing disabled 1 : Two-phase pulse signal processing mode

Addresses

56 5716 5816 5916 5A16

OUT and TA3OUT.

Address

Fig. 47 Bit configuration of up-down register

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Data write and data read are performed in the same way as for timer mode. That is, when data is written to timer Ai halted, it is also written to the reload register and the counter. When data is written to timer Ai which is busy, the data is written to the reload register, but not to the counter. The counter is reloaded with new data from the reload register at the next reload time. The counter can be read at any time. In event counter mode, whether to increment or decrement the counter can also be determined by supplying two kinds of pulses of which phases differ by 90° to timer A2, A3, or A4. There are two types of two-phase pulse processing operations. One uses timers A2 and A3, and the other uses timer A4. In both processing operations, two pulses described above are input to the TAjOUT (j = 2 to 4) pin and TAjIN pin respectively. When timers A2 and A3 are used, as shown in Figure 48, the count is incremented when a rising edge is input to the TAkIN pin after the level of TAkOUT(k=2, 3) pin changes from “L” to “H”, and when the falling edge is input, the count is decremented. For timer A4, as shown in Figure 49, when a phase-related pulse with a rising edge input to the TA4IN pin is input after the level of TA4OUT pin changes from “L” to “H”, the count is incremented at the respective rising edge and falling edge of the T A4OUT pin and TA4IN pin. When a phase-related pulse with a falling edge input to the TA4OUT pin is input after the level of TA4IN pin changes from “H” to “L”, the count is decremented at the respective rising edge and falling edge of the TA4IN pin and TA4OUT pin. When performing this two-phase pulse signal processing, timer Aj mode register bit 0 and bit 4 must be set to “1” and bits 1, 2, 3, and 5 must be “0”. Bits 6 and 7 are ig-

nored. (See Figure 50.) Note that bits 5, 6, and 7 of the up-down register (address 4416) are the two-phase pulse signal processing select bits for timers A2, A3 and A4 respectively. Each timer operates in normal event counter mode when the corresponding bit is “0” and performs two-phase pulse signal processing when it is “1”. Count is started by setting the count start bit to “1”. Data write and read are performed in the same way as for normal event counter mode. Note that the direction register of the input port must be set to input mode because two kinds of pulse signals, described above, are input. Also, there can be no pulse output in this mode.

Addresses

58 5916 5A16

76543210

××

100010

Timer A2 mode register Timer A3 mode register Timer A4 mode register

0 1 : Always “01” in event counter mode 0 1 0 0 : Always “0100” when processing

two-phase pulse signal × × : Not used in event counter mode

Fig. 50 Bit configuration of timer Aj mode register when performing

two-phase pulse signal processing in event counter mode

TAkOUT

TAkIN

(k = 2, 3)

Incrementcount

Decrementcount

Fig. 48 Two-phase pulse processing operation of timers A2 and A3

TA4

OUT



Decrement-count at each edgeIncrement-count at each edge

TA4



Decrement-count at each edgeIncrement-count at each edge

Fig. 49 Two-phase pulse processing operation of timer A4

Decrementcount



Page 57

M37902FCCHP, M37902FGCHP, M37902FJCHP

(3) One-shot pulse mode [10]

Figure 51 shows the bit configuration of the timer Ai mode register during one-shot pulse mode. In one-shot pulse mode, bit 0 and bit 5 must be “0” and bit 1 and bit 2 must be “1”. The trigger is enabled when the count start bit is “1”. The trigger can be generated by software or it can be input from the TAiIN pin. Software trigger is selected when bit 4 is “0” and the input signal from the TAiIN pin is used as the trigger when it is “1“. Bit 3 is used to determine whether to trigger at the fall of the trigger signal or at the rise. The trigger is at the fall of the trigger signal when bit 3 is “0” and at the rise of the trigger signal when it is “1”. Software trigger is generated by setting “1” to a bit in the one-shot start register. Each bit corresponds to each timer. Figure 52 shows the bit configuration of the one-shot start register. As shown in Figure 53, when a trigger signal is received, the counter counts the clock selected by bits 6 and 7 and the contents of the timer A clock division select register. (Set Table 12.) If the contents of the counter is not 000016, the TAiOUT pin goes “H” when a trigger signal is received. The count direction is decrement. When the counter reaches 000116, the TAiOUT pin goes “L” and count is stopped. The contents of the reload register is transferred to the counter. At the same time, an interrupt request signal is generated and the interrupt request bit in the timer Ai interrupt control register is set. This is repeated each time a trigger signal is received. The output pulse width is

pulse frequency of the selected clock

× (counter’s value at the time of trigger).

If the count start flag is “0”, T AiOUT goes “L”. Therefore, the value corresponding to the desired pulse width must be written to timer Ai before setting the timer Ai count start bit. As shown in Figure 54, a trigger signal can be received before the operation for the previous trigger signal is completed. In this case, the contents of the reload register is transferred to the counter by the trigger and then that value is decremented. Except when retriggering while operating, the contents of the reload register are not transferred to the counter by triggering. When retriggering, there must be at least one timer count source cycle before a new trigger can be issued. Data write is performed in the same way as for timer mode. When data is written in timer Ai halted, it is also written to the reload register and the counter. When data is written to timer Ai which is busy, the data is written to the reload register, but not to the counter. The counter is reloaded with new data from the reload register at the next reload time. Undefined data is read when timer Ai is read.

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Timer A0 mode register Timer A1 mode register Timer A2 mode register

76543210

0110

Timer A3 mode register Timer A4 mode register

1 0 : Always “10” in one-shot pulse mode 1 : Always “1” in one-shot pulse mode 0 × : Software trigger

1 0 : Trigger at the falling edge of TAi input 1 1 : Trigger at the rising edge of TAi input 0 : Always “0” in one-shot pulse mode

Clock source select bits (See Table 12.)

Fig. 51 Bit configuration of timer Ai mode register during one-shot

pulse mode

76543210

One-shot start register Timer A0 one-shot start bit

Timer A1 one-shot start bit Timer A2 one-shot start bit Timer A3 one-shot start bit Timer A4 one-shot start bit Must be fixed to “0”.

Fig. 52 Bit configuration of one-shot start register

Addresses

56 57

Address

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Selected clock source fi

TAi

(rising edge)

TAi

OUT

Example when the contents of the reload register is 000316

Fig. 53 Pulse output example when external rising edge is selected

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Selected clock source fi

TAi (rising edge)

TAiOUT

Example when the contents of the reload register is 000416

Fig. 54 Example when trigger is re-issued during pulse output

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

(4) Pulse width modulation mode [11]

Figure 55 shows the bit configuration of the timer Ai mode register during pulse width modulation mode. In pulse width modulation mode, bits 0, 1, and 2 must be set to “1”. Bit 5 is used to determine whether to perform 16-bit length pulse width modulator or 8-bit length pulse width modulator. 16-bit length pulse width modulator is selected when bit 5 is “0” and 8-bit length pulse width modulator is selected when it is “1”. The 16-bit length pulse width modulator is described first. The pulse width modulator can be started with a software trigger or with an input signal from a TAiIN pin (external trigger). The software trigger mode is selected when bit 4 is “0”. Pulse width modulator is started and a pulse is output from TAiOUT when the count start bit is set to “1”. The external trigger mode is selected when bit 4 is “1”. Pulse width modulation starts when a trigger signal is input from the TAiIN pin when the count start bit is “1”. Whether to trigger at the fall or rise of the trigger signal is determined by bit 3. The trigger is at the fall of the trigger signal when bit 3 is “0” and at the rise when it is “1”. When data is written to timer Ai with the pulse width modulator halted, it is written to the reload register and the counter. Then when the count start bit is set to “1” and a software trigger or an external trigger is issued to start modulation, the waveform shown in Figure 56 is output continuously. Once modulation is started, triggers are not accepted. If the value in the reload register is m, the duration “H” of pulse is

The low-order 8 bits function as a prescaler and the high-order 8 bits function as the 8-bit length pulse width modulator. The prescaler counts the clock selected by bits 6, 7, and the contents of the timer A clock division select register. (See Table 12.) A pulse is generated when the counter reaches 000016 as shown in Figure 57. At the same time, the contents of the reload register is transferred to the counter and count is continued.

Addresses

56 57

input

76543210

111

Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register

1 1 : Always “11” in pulse width modulation mode 1 : Always “1” in pulse width modulation mode 0 × : Software trigger 1 0 : Trigger at the falling of TAi 1 1 : Trigger at the rising of TAi

0 : 16-bit pulse width modulator 1 : 8-bit pulse width modulator

Clock source select bits (See Table 12.)

selected clock frequency

× m

and the output pulse period is

selected clock frequency

× (216 –1).

An interrupt request signal is generated and the interrupt request bit in the timer Ai interrupt control register is set at each fall of the output pulse. The width of the output pulse is changed by updating timer data. The update can be performed at any time. The output pulse width is changed at the rise of the pulse after data is written to the timer. The contents of the reload register are transferred to the counter just before the rise of the next pulse so that the pulse width is changed from the next output pulse. Undefined data is read when timer Ai is read. The 8-bit length pulse width modulator is described next. The 8-bit length pulse width modulator is selected when the timer Ai mode register bit 5 is “1”. The reload register and the counter are both divided into 8-bit halves.

Fig. 55 Bit configuration of timer Ai mode register during pulse width

modulation mode

Page 60

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Therefore, if the low-order 8 bits of the reload register are n, the period of the generated pulse is

selected clock frequency

× (n+1).

The high-order 8 bits function as an 8-bit length pulse width modulator using this pulse as input. The operation is the same as for 16-bit length pulse width modulator except that the length is 8 bits. If the

1/fi × (2

Selected clock source fi

TAi (rising edge)

This trigger is not accepted

1/fi × (m)

TAi

OUT

high-order 8 bits of the reload register are m, the duration “H” of pulse is

selected clock frequency

And the output pulse period is

selected clock frequency

– 1)

× (n+1) × m.

× (n+1) × (28–1).

Example when the contents of the reload register is 0003

Fig. 56 16-bit length pulse width modulator output pulse example

Selected clock source fi

TAi (falling edge)

1/fi × (n + 1)

Prescaler output (when n = 2)

8-bit length pulse width modulator output (when m = 2)

1/fi × (n + 1) × (2

1/fi × (n + 1) × (m)

– 1)

Fig. 57 8-bit length pulse width modulator output pulse example

Page 61

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

TIMER B

Figure 58 shows a block diagram of timer B. Timer B has three modes: timer mode, event counter mode, and pulse period measurement/pulse width measurement mode. The mode is selected with bits 0 and 1 of the timer Bi mode register (i=0 to 2). Each of these modes is described below.

(1) Timer mode [00]

Figure 59 shows the bit configuration of the timer Bi mode register during timer mode. Bits 0 and 1 of the timer Bi mode register must always be “0” in timer mode. Bits 6 and 7 are used to select the clock source. The counting of the selected clock starts when the count start bit is “1” and stops when “0”.

Count source select bits

512

• Timer mode

• Pulse period measurement/Pulse

width measurement mode

• Event counter

mode

TBiIN

Polarity selection

and edge pulse

generator

Timer B2 clock source select bit (Note 2)

As shown in Figure 44, the timer Bi count start bit is at the same address as the timer Ai count start bit. The count is decremented, an interrupt occurs, and the interrupt request bit in the timer Bi interrupt control register is set when the contents becomes 000016. At the same time, the contents of the reload register is stored in the counter and count is continued. Timer Bi does not have a pulse output function or a gate function like timer A. When data is written to timer Bi halted, it is written to the reload register and the counter. When data is written to timer Bi which is busy, the data is written to the reload register, but not to the counter. The new data is reloaded from the reload register to the counter at the next reload time and counting continues. The contents of the counter can be read at any time.

Data bus (odd)

Data bus (even)

(Low-order 8 bits) (High-order 8 bits)

Reload register (16)

Counter (16)

Timer B0 51

Count start register

(Address 40

)

Timer B1 5316 52 Timer B2 5516 54

Addresses

16 16 16

Timer B2 clock source select bit : Bit 6 at address 63

Notes 1: Perform a write and read to/from timer Bi register in the condition of 16-bit data length : data length flag (m) = “0”.

2: Only for timer B2, a count source in the event counter mode can be selected.

Fig. 58 Block diagram of timer B

Counter reset

circuit

Page 62

M37902FCCHP, M37902FGCHP, M37902FJCHP

(2) Event counter mode [01]

Figure 60 shows the bit configuration of the timer Bi mode register during event counter mode. In event counter mode, bit 0 in the timer Bi mode register must be “1” and bit 1 must be “0”. The input signal from the TBiIN pin is counted when the count start bit is “1” and counting is stopped when it is “0”. Count is performed at the fall of the input signal when bits 2, and 3 are “0” and at the rise of the input signal when bit 3 is “0” and bit 2 is “1”. When bit 3 is “1” and bit 2 is “0”, count is performed at the rise and fall of the input signal. Data write, data read and timer interrupt are performed in the same way as for timer mode. Only for timer B2, when the timer B2 clock source select bit of the particular function select register 1 (bit 6 at address 6316) = “1” in the event counter mode, fX32 can be selected. (When this bit is “0”, an input signal from pin TB2IN becomes the count source as described above.) For the bit configuration of the particular function select register 1, refer to the section on the standby function. Note: fX32 = f(XIN)/32

(3) Pulse period measurement/Pulse width

measurement mode [10]

Figure 61 shows the bit configuration of the timer Bi mode register during pulse period measurement/pulse width measurement mode. In pulse period measurement/pulse width measurement mode, bit 0 must be “0” and bit 1 must be “1”. Bits 6 and 7 are used to select the clock source. The selected clock is counted when the count start bit is “1” and counting stops when it is “0”. The pulse period measurement mode is selected when bit 3 is “0”. In pulse period measurement mode, the selected clock is counted during the interval starting at the fall of the input signal from the TBiIN pin to the next fall or at the rise of the input signal to the next rise; the result is stored in the reload register. In this case, the reload register acts as a buffer register. When bit 2 is “0”, the clock is counted from the fall of the input signal to the next fall. When bit 2 is “1“, the clock is counted from the rise of the input signal to the next rise. In the case of counting from the fall of the input signal to the next fall, counting is performed as follows. As shown in Figure 62, when the fall of the input signal from TBiIN pin is detected, the contents of the counter is transferred to the reload register. Next, the counter is cleared and count is started from the next clock. When the fall of the next input signal is detected, the contents of the counter is transferred to the reload register once more, the counter is cleared, and the count is started. The period from the fall of the input signal to the next fall is measured in this way. After the contents of the counter is transferred to the reload register, an interrupt request signal is generated and the interrupt request bit in the timer Bi interrupt control register is set. However, no interrupt request signal is generated when the contents of the counter is transferred first to the reload register after the count start bit is set to “1”. When bit 3 is “1”, the pulse width measurement mode is selected. Pulse width measurement mode is the same as the pulse period measurement mode except that the clock is counted from the fall of the TBiIN pin input signal to the next rise or from the rise of the input signal to the next fall as shown in Figure 63.

MITSUBISHI MICROCOMPUTERS

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

76543210

×××

Timer B0 mode register Timer B1 mode register Timer B2 mode register

0 0 : Always “00” in timer mode × × : Not used in timer mode and

may be any Not used in timer mode Clock source select bits 0 0 : Select f 0 1 : Select f 1 0 : Select f 1 1 : Select f

2 16 64 512

Fig. 59 Bit configuration of timer Bi mode register during timer mode

76543210

×××

Timer B0 mode register Timer B1 mode register Timer B2 mode register

0 1 : Always “01” in event counter mode 0 0 : Count at the falling edge of input signal 0 1 : Count at the rising edge of input signal 1 0 : Count at the both falling edge and rising edge of input signal

× × × : Not used in event counter mode

Fig. 60 Bit configuration of timer Bi mode register during event

counter mode

76543210

Timer B0 mode register Timer B1 mode register Timer B2 mode register

1 0 : Always “10” in pulse period measurement/pulse width measurement mode 0 0 : Count from the falling edge of input signal to the next falling one 0 1 : Count from the rising edge of input signal to the next rising one 1 0 : Count from the falling edge of input signal to the next rising one and from the rising edge to the next falling one Timer Bi overflow flag Clock source select bits 0 0 : Select f 0 1 : Select f 1 0 : Select f 1 1 : Select f

2 16 64 512

Fig. 61 Bit configuration of timer Bi mode register during pulse period

measurement/pulse width measurement mode

Addresses

5B 5C

Addresses

Page 63

M37902FCCHP, M37902FGCHP, M37902FJCHP

When timer Bi is read, the contents of the reload register is read. Note that in this mode, the interval between the fall of the TBiIN pin input signal to the next rise or from the rise to the next fall must be at least two cycles of the timer count source. Timer Bi overflow flag which is bit 5 of timer Bi mode register is set to “1” when the timer Bi counter reaches 000016, which indicates that a pulse width or pulse period is longer than that which can be measured by a 16-bit length. This flag is cleared by writing data to the corresponding timer Bi mode register. This flag is set to “1”at reset.

Selected clock source fi

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

TBi

Reload register ← Counter

Counter ← 0

Count start bit

Interrupt request signal

Fig. 62 Pulse period measurement mode operation (example of measuring the interval between the falling edge to next falling one)

Selected clock source fi

TBi

Reload register ← Counter

Counter ← 0

Count start bit

Interrupt request signal

Fig. 63 Pulse width measurement mode operation

Page 64

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

SERIAL I/O PORTS

Two independent serial I/O ports are provided. Figure 64 shows a block diagram of the serial I/O ports. Bits 0 to 2 of the UARTi(i = 0,1) transmit/receive mode register shown in Figure 65 are used to determine whether to use port P8 as a programmable I/O port, clock synchronous serial I/O port, or asyn-

RXD

CTSi/CLK

CTS

/RTS

BRG count source select bits

512

n = a value set into the UARTi baud rate register (BRGi)

BRGi

1/(n + 1) divider

Clock synchronous (when internal clock selected)

CLK

CTS

1/16 divider

Clock synchronous

1/16 divider

Clock synchronous

1/2 divider

chronous (UART) serial I/O port which uses start and stop bits. Figures 66 and 67 show the block diagrams of the receiver/transmitter . Figure 68 shows the bit configuration of the UARTi transmit/receive control register. Each communication method is described below.

Data bus (odd)

Data bus (even)

UART

(Internal clock)

Clock synchronous

(External clock)

000000

Receive

control

circuit

Transmit

control

circuit

7D6D5D4D3D2D1

UARTi receive register

Transfer clock

UARTi transmit register

D7D8D6D5D4D3D2D1D

Data bus (odd)

Data bus (even)

Bit converter

UART0 (Addresses 37 UART1 (Addresses 3F

Bit converter

UARTi

receive buffer register

16, 3616 16

XDi

UARTi

UART0 (Addresses 33 UART1 (Addresses 3B

transmit buffer register

, 3E16)

, 3216)

)

, 3A16)

Fig. 64 Block diagram of serial I/O port

76543210

Note: In the clock synchronous serial I/O mode, bits 4 to 6 are invalid. (Each of them may be “0” or “1”.) Furthermore, fix bit 7 to “0”.

UART 0 Transmit/Receive mode register UART 1 Transmit/Receive mode register

Serial I/O mode select bits 0 0 0 : Serial I/O is invalid. (Port P8 functions as a programmable I/O port.) 0 0 1 : Clock synchronous 1 0 0 : 7-bit UART 1 0 1 : 8-bit UART 1 1 0 : 9-bit UART Internal/External clock select bit 0 : Internal clock 1 : External clock Stop bit length select bit (Valid in UART mode.) 0 : 1 stop bit 1 : 2 stop bits Odd/Even parity select bit (Valid in UART mode with the parity enable bit = “1”.) (Note) 0 : Odd parity 1 : Even parity Parity enable bit (Valid in UART mode) (Note) 0 : No parity 1 : With parity Sleep select bit (Valid in UART mode) (Note) 0 : No sleep 1 : Sleep

Fig. 65 Bit configuration of UARTi transmit/receive mode register

Addresses

30 38

Page 65

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Data bus (odd)

Data bus (even)

UARTi receive buffer register

0D1D2D3D4D5D6D7D8

0000000

8-bit UART

2SP

XDi

SP PAR

1SP

Parity

No parity

UART

9-bit UART

7-bit UART 8-bit UART Synchronous

9-bit UART Synchronous

7-bit UART

UARTi receive register

Synchronous

SP : Stop bit PAR : Parity bit

Fig. 66 Block diagram of receiver

2SP

SP PAR

1SP

Parity

No parity

UART

Synchronous

Data bus (odd)

Data bus (even)

7-bit UART 9-bit UART Synchronous

8-bit UART

8-bit UART 9-bit UART Synchronous

7-bit UART

UARTi receive transmit register

XDi

UARTi transmit register

SP : Stop bit PAR : Parity bit

Fig. 67 Block diagram of transmitter

Page 66

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

76543210

MSB /LSB

CPL

EPTY

R/C CS1CS

76543210

RERIOERFERPERSUM TI TE

Address

UART0 transmit/receive control register 0

UART1 transmit/receive control register 0

34 3C

BRG count source select bits

00 : f 01 : f

10 : f

11 : f

512

CTS/RTS function select bit (Note 1) 0 : CTS function is selected. 1 : RTS function is selected. Transmit register empty flag 0 : Data is present in the transmit register. (Transmission is in progress.) 1 : No data is present in the transmit register. (Transmission is completed.) CTS/RTS enable bit 0 : CTS, RTS function is enabled. 1 : CTS, RTS function is disabled. UARTi receive interrupt mode select bit 0 : Reception interrupt 1 : Reception error interrupt CLK polarity select bit (This bit is used in the clock synchronous serial I/O mode.) (Note 2) 0 : At the falling edge of a transfer clock, transmit data is output;

at the rising edge, receive data is input. When not in transfer, pin CLK’s level is “H”.

1 : At the rising edge of a transfer clock, transmit data is output;

at the falling edge, receive data is input.

When not in transfer, pin CLK’s level is “L”. Transfer format select bit (This bit is used in the clock synchronous serial I/O mode.) (Note 2) 0 : LSB (Least Significant Bit) first 1 : MSB (Most Significant Bit) first

Address UART0 transmit/receive control register 1 UART1 transmit/receive control register 1

Transmit enable bit Transmit buffer empty flag Receive enable bit Receive complete flag Overrun error flag Framing error flag (Note 3) Parity error flag (Note 3) Error sum flag (Note 3)

Notes 1: Valid when the CTS/RTS enable bit (bit 4) = “0”.

2: Fix these bits to “0” in UART mode or when serial I/O is invalid. 3: Valid in UART mode.

Fig. 68 Bit configuration of UARTi transmit/receive control register

Page 67

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

CLOCK SYNCHRONOUS SERIAL COMMUNICATION

A case where communication is performed between two clock synchronous serial I/O ports as shown in Figure 69 will be described. (The transmission side will be denoted by subscript j and the receiving side will be denoted by subscript k.) Bit 0 of the UARTj transmit/receive mode register and UARTk transmit/receive mode register must be set to “1” and bits 1 and 2 must be “0”. The length of the transmission data is fixed at 8 bits. Bit 3 of the UARTj transmit/receive mode register of the clock sending side is cleared to “0” to select the internal clock. Bit 3 of the UARTk transmit/receive mode register of the clock receiving side is set to “1” to select the external clock. Bits 4, 5 and 6 are ignored in clock synchronous mode. Bit 7 must always be “0”. The clock source is selected by bit 0 (CS0) and bit 1 (CS1) of the clock-sending-side UARTj transmit/receive control register 0. As shown in Figure 64, the selected clock is divided by (n+1), then by 2, is passed through a transmission control circuit, and is output as transmission clock CLKj. Therefore, when the selected clock is fi,

Bit Rate = fi/ {(n + 1) × 2}

On the clock receiving side, the CS0 and CS1 bits of the UARTk transmit/receive control register 0 are ignored because an external clock is selected. Both of UART0 and UART1 can use CTS and RTS functions. Bit 4 of the UARTi transmit/receive control register 0 is used to determine whether to use CTS or RTS signal. Bit 4 must be “0” when

_______ _______ _______ _______

CTS or RTS signal is used. Bit 4 must be “1” when CTS and RTS signals are not used. When CTS and RTS signals are not used, CTS/

_______

RTS pin can be used as a normal port pin. When using pin CTS/RTS, :

• If bit 2 of the UARTi transmit/receive control register 0 is cleared to

_______

“0”, CTS input is selected.

• If bit 2 is set to “1”, RTS output is selected.

The case using CTS and RTS signals are explained below. As

_______ _______

_______ _______ _______

_______ _______

_______

_______ _______

shown in Figure 76, bits 2 and 3 of the serial I/O pin control register can determine whether port pins P83 and P87 are used as pins TxDi or as port pins. When bits 2 and 3 are “0”, P83 and P87 function as pins TxDi; when bits 2 and 3 are “1”, P83 and P87 function as port pins. Therefore, in the input-only system where pins TxDi are not used, pins TxDi can function as port pins.

UARTj transmit register

UARTj transmit buffer register

UARTj receive buffer register

UARTj receive register

UARTj Transmit/Receive mode register

000

UARTj Transmit/Receive control

MSB

CPL CPL

/LSB

UARTj Transmit/Receive control

SUM TI TE

EPTY

1 CS0

RERIOERFERPER

TxDj

RxDj

CLKj

CTSj

TxDk

RxDk

CLKk

RTSk

UARTk transmit register

UARTk transmit buffer register

UARTk receive buffer register

UARTk receive register

UARTk Transmit/Receive mode register

0110

UARTk Transmit/Receive control

MSB /LSB

UARTk Transmit/Receive control

EPTY

RERIOERFERPERSUM TI TE

Fig. 69 Clock synchronous serial communication

Page 68

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Transmission

Transmission is started when bit 0 (TEj flag: transmit enable bit) of UARTj transmit/receive control register 1 is “1”, bit 1 (TIj flag) of one is “0”, and CTSj input is “L”. The TIj flag indicates whether the transmit buffer register is empty or not. It is cleared to “0” when data is written in the transmit buffer register ; it is set to “1” when the contents of the transmit buffer register is transferred to the transmit register and the transmit buffer register becomes empty. When all of the transmit conditions are satisfied, the transmit data in the transmit buffer register are transferred to the transmit register, and transmission starts. As shown in Figure 70, data is output from TXDj pin each time when transmission clock CLKj changes from “H” to “L”. (In the clock synchronous serial I/O mode, the polarity of a transfer clock can be changed. For details, refer to the section on the selection of the transfer clock polarity.) The data is output from the least significant bit. When the transmit register becomes empty after the contents has been transmitted, data is transferred automatically from the transmit buffer register to the transmit register if the next transmission start condition is satisfied. The next transmission is performed succeedingly. Once transmission has started, the TEj flag, TIj flag, and CTSj signals are ignored until data transmission completes. Therefore, transmission is not interrupt when CTSj input is changed to “H” during transmission. The transmission start condition indicated by TEj flag, TIj flag, and

________

CTSj is checked while the TENDj signal (shown in Figure 70) is “H”. Therefore, data can be transmitted continuously if the next transmission data is written in the transmit buffer register and TIj flag is cleared to “0” before theTENDj signal goes “H”. Bit 3 (TXEPTYj flag) of UARTj transmit/receive control register 0 changes to “1” at the next cycle just after the TENDj signal goes “H” and changes to “0” when transmission starts. Therefore, this flag can be used to determine whether data transmission has completed. When the TIj flag changes from “0” to “1”, the interrupt request bit in the UARTj transmit interrupt control register is set to “1”.

________

next data reception becomes enabled. Bit 4 (OERk flag) of UARTk transmit/receive control register 1 is set to “1” when the next data is transferred from the receive register to the receive buffer register while RIk flag is “1”, and indicates that the next data was transferred to the receive register before the contents of the receive buffer register was read. (In other words, this indicates that an overrun error has occurred.) RIk flag is automatically cleared to “0” when the low-order byte of the receive buffer register is read or when the REk flag is cleared to “0”. The OERk flag is cleared when the REk flag is cleared. Bit 5 (FERk flag), bit 6 (PERk flag), and bit 7 (SUMk flag) are ignored in clock synchronous mode. As shown in Figure 64, with clock synchronous serial communication, data cannot be received unless the transmitter is operating because the receive clock is created from the transmission clock. Therefore, the transmitter must be operating even when there is no need to sent data from UARTk to UARTj.

Receive

When bit 2 of the UARTk transmit/receive control register 1 is set to “1”, reception becomes enabled. In this case, when the CLKk signal is input, the receive operation starts simultaneously with this signal.

__________

The RTSk output is “H” when the REK flag is “0”. When the REK flag is set to “1”, the RTSk output becomes “L”. This informs the transmitter side that reception becomes enabled. When the receive operation starts, the RTSk output automatically becomes “H”. When the receive operation starts, the receiver takes data from pin RxDk each time when the transmit clock (CLKj) turns from “L” to “H”. Simultaneously with reception, the contents of the receiver register is shifted bit by bit. (Note that, in the clock synchronous serial communication, the polarity of a transfer clock can be inverted. For details, refer to the section on the polarity of the transfer clock.) When an 8-bit data is received, the contents of the receive register is transferred to the receive buffer register and bit 3 (RIk flag) of UARTk transmit/receive control register 1 is set to “1”. In other words, the setting “1” to the RIk flag indicates that the receive buffer register contains the received data. At this time, if the low-order byte of the UARTk receive buffer register is read out, the RTSk output turns back to “L”. This indicates that the

__________

_____

Page 69

Transmission clock

CTS

CLK

ENDj

M37902FCCHP, M37902FGCHP, M37902FJCHP

Write in transmit buffer register

× (n + 1) × 2

1/f

1/fi × (n + 1) × 2

Transmit register ←Transmit buffer register

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Stopped because TE

= “0”

TXD

TXEPTY

0D1D2D3D4D5D6D7

Fig. 70 Clock synchronous serial I/O timing

Interrupt request at completion of reception

When the RIk flag changes from “0” to “1”, in other words, when the receive operation is completed, the interrupt request bit of the UARTk receive interrupt control register can be set to “1”. The timing when this interrupt request bit is to be set to “1” can be selected from the following:

• Each reception

• When an error occurs at reception

If bit 5 of the UARTk transmit/receive control register 0 (UART receive interrupt mode select bit) is cleared to “0”, the interrupt request bit is set to “1” at each reception. If bit 5 is set to “1”, the interrupt request bit is set to “1” only when an error occurs. (In the clock synchronous serial communication, only when an overrun error occurs, the interrupt request bit is set to “1”.)

Polarity of transfer clock

In the clock synchronous serial communication, by bit 6 of the UARTj transmit/receive control register 0 (CPL), the polarity of a transfer clock can be selected. As shown in Figure 71, when bit 6 = “0”, the polarity is as follows:

• In transmission, transmit data is output at the falling edge of CLKj.

• In reception, receive data is input at the rising edge of CLKk.

• When not in transfer, CLKi is at “H” level. When bit 6 = “1”, the polarity is as follows:

• In transmission, transmit data is output at the rising edge of CLKj.

• In reception, receive data is input at the rising edge of CLKk.

• When not in transfer, CLKi is at “L” level.

D1D2D3D4D5D6D

D0D1D2D3D4D5D6D

Page 70

■ CLK polarity select bit = 0

CLKi

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TxDi

RxDi

❇ Transmit data is output to pin TxDi at the falling edge of transfer clock, and receive data is input from pin

RxDi at the rising edge of transfer clock. When not in transfer, pin CLKi’s level is “H”.

D0 D1 D2 D3 D4 D5 D6 D7

■ CLK polarity select bit = 1

CLKi

TxDi

D0 D1 D2 D3 D4 D5 D6 D7

RxDi

❇ Transmit data is output to pin TxDi at the rising edge of transfer clock, and receive data is input from pin

RxDi at the falling edge of transfer clock. When not in transfer, pin CLKi’s level is “L”.

Fig. 71 Polarity of transfer clock

D0 D1 D2 D3 D4 D5 D6 D7

Page 71

M37902FCCHP, M37902FGCHP, M37902FJCHP

Selection of transfer format

In clock synchronous serial communication, transfer format can be selected by bit 7 of the transmit/receive control register 0. When bit 7 is “0”, transfer format is LSB first. When bit 7 is “1”, transfer format is MSB first. This function is realized by changing connection relation between

MITSUBISHI MICROCOMPUTERS

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

the transmit buffer register and the receive buffer register when writing transmit data to the transmit buffer register or reading receive data from the receive buffer register. Accordingly, the transmitter’s operation is the same in both transfer formats. Figure 72 shows the connection relation.

Bit 7 in transmit/receive

control register 0

(LSB first)

(MSB first)

Data bus

DB DB DB DB DB DB DB DB

Data bus

DB DB DB DB DB DB DB DB

Write to transmit

buffer register

Transmit buffer

Read from receive

buffer register

Data bus

Receive buffer

Fig. 72 Connection relation between transmit buffer register, receive buffer register, and data bus

Precautions for clock synchronous serial communication

When using pin CTS0/RTS0, be sure to clear the D-A2 output enable bit (bit 2 at address 9616) to “0” (output disabled). Also, in the clock synchronous serial communication, the separate function for CTSi/

_______

RTSi cannot be selected. Furthermore, when an internal clock is se-

_______ _______

lected, RTS output is undefined. Therefore, do not use the RTS function. Before transmit operation is performed, be sure to clear bits 2 and 3 of the serial I/O pin control register (address AC16) to “00”.

________ ________

_______

Page 72

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ASYNCHRONOUS SERIAL COMMUNICATION

Asynchronous serial communication can be performed using 7-, 8-, or 9-bit length data. The operation is the same for all data lengths. The following is the description for 8-bit asynchronous communication. With 8-bit asynchronous communication, bit 0 of UARTi transmit/receive mode register is “1”, bit 1 is “0”, and bit 2 is “1”. Bit 3 is used to select an internal clock or an external clock. If bit 3 is “0”, an internal clock is selected and if bit 3 is “1”, then external clock is selected. If an internal clock is selected, bit 0 (CS0) and bit 1 (CS1) of UARTi transmit/receive control register 0 are used to select the clock source. When an internal clock is selected for asynchronous serial communication, the CLKi pin can be used as a normal I/O pin. The selected internal or external clock is divided by (n+1), then by 16, and is passed through a control circuit to create the UART transmission clock or UART receive clock. Therefore, the transmission speed can be changed by changing the contents (n) of the bit rate generator. If the selected clock is an internal clock Pfi or an external clock fEXT,

Bit Rate = (fi or fEXT) / {(n+1)×16}

(1/fi or 1/f

EXT

) × (n + 1) × 16

Transmission clock

Bit 4 is the stop bit length select bit to select 1 stop bit or 2 stop bits. Bit 5 is a select bit of odd parity or even parity. In the odd parity mode, the parity bit is adjusted so that the sum of 1s in the data and parity bit is always odd. In the even parity mode, the parity bit is adjusted so that the sum of the 1s in the data and parity bit is always even. Bit 6 is the parity bit select bit which indicates whether to add parity bit or not. Bits 4 to 6 must be set or reset according to the data format used in the communicating devices. Bit 7 is the sleep select bit. The sleep mode is described later. Figure 76 shows the bit configuration of the serial I/O pin control register. By bits 0 and 1 of the serial I/O pin control register (CTSi/RTSi separate select bits), the function of the CTS/RTS pin can be sepa-

_______ _______

________ ________

rated into two functions, and each function can be assigned to two different pins. When bits 0 and 1 = “11”, the above separation is performed. When bits 0 and 1 = “00”, no separation is performed. Table 13 lists the selection methods of the CTS/RTS function.

_______ _______

CTS

ENDi

TXD

TXEPTY

Written in transmit buffer register

Start bit Parity bit Stop bit

D0D

D2D3D4D5D6D7PSPSTD0D1D2D3D4D5D6D7PSP STD0D

Transmit register ← Transmit

buffer register

Fig. 73 Transmit timing example when 8-bit asynchronous communication with parity and 1 stop bit selected

(1/fi or 1/fEXT) × (n + 1) × 16

Transmission clock

TIi

TENDi

TXDi

Written in transmit buffer register

Start bit Stop bit Stop bit

D0 D1ST D2 D3 D4 D5 D6 D7 D8 SPSP ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D2D1

Transmit register ← Transmit

buffer register

Stopped because TE

= “0”

i = “0”

TXEPTYi

Fig. 74 Transmit timing example when 9-bit asynchronous communication with no parity and 2 stop bits selected

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Transmission

Transmission is started when bit 0 (TEi flag transmit enable flag) of UARTi transmit/receive control register 1 is “1”, bit 1 (TIi flag) is “0”,

________

and CTSi input (in other words, transmit enable signal input from receiver) is “L.” The TIi flag indicates whether the transmit buffer is empty or not. It is cleared to “0” when data is written in the transmit buffer; it is set to “1” when the contents of the transmit buffer register is transferred to the transmit register. When all of the transmission conditions are satisfied, transmit data is transferred to the transmit register, and transmit operation starts. As shown in Figures 73 and 74, data is output from the TXDi pin with the stop bit or parity bit specified by bits 4 to 6 of UARTi transmit/receive mode register. The data is output from the least significant bit. When the transmit register becomes empty after the contents has been transmitted, data is transferred automatically from the transmit buffer register to the transmit register if the next transmit start condition is satisfied. Then, the next transmission is performed succeedingly.

or f

EXT

RXD

Receive clock

Start bit

Check to be “L” level

Starting at the falling edge of start bit

Once transmission has started, the TEi flag, TIi flag, and CTSi signal are ignored until data transmission is completed. Therefore, transmission does not stop until it completes event if, during transmission, the TEi flag is cleared to “0” or CTSi input is set to “1”. The transmission start condition indicated by TEi flag, TIi flag, and

________

CTSi is checked while the TENDi signal shown in Figure 73 is “H”. Therefore, data can be transmitted continuously if the next transmission data is written in the transmit buffer register and TIi flag is cleared to “0” before the TENDi signal goes “H”. Bit 3 (TXEPTYi flag) of UARTi transmit/receive control register 0 changes to “1” at the next cycle just after the TENDi signal goes “H” and changes to “0” when transmission starts. Therefore, this flag can be used to determine whether data transmission is completed. When the TIi flag changes from “0” to “1”, the interrupt request bit of the UARTi transmit interrupt control register is set to “1”.

Stop bit Start bit

Data fetched

________

RTS

Fig. 75 Receive timing example when 8-bit asynchronous communication with no parity and 1 stop bit selected

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Table 13. Selection methods of CTS/RTS function

CTS/RTS

enable bit

✕: It may be “0” or “1”.

Notes 1: When using the CTS0/RTS0 pin, be sure to clear the D-A2 output enable bit (bit 2 at address 9616) to “0”.

2: When using the CTS function, be sure to clear the corresponding bit of the port P8 direction register to “0”. 3: When CTSi and RTSi has been separated, the CLKi pin cannot be used. Therefore, in the clock synchronous serial communication, CTSi and RTSi

cannot be separated. Also, when CTSi and RTSi are separated in UART mode, be sure to select an internal clock.

CTSi/RTS

separate select bit

0 1

CTS/RTS

function select bit

0 1

✕ ✕

Pin P80/CTS0/RTS0 (Note 1)

CTS RTS

RTS

Pin P81/CTS0/CLK

P81 or CLK P81 or CLK

CTS0 (Notes 2 and 3)

P81 or CLK

Receive

76543210

Serial I/O pin control register

CTS0/RTS0 separate select bit 0 : CTS 1 : CTS

CTS 0 : CTS 1 : CTS

TxD 0 : Functions as TxD 1 : Functions as P8

TxD1/P87 switch bit 0 : Functions as TxD 1 : Functions as P8

/RTS0 are used together.

/RTS0 are separated.

/RTS1 separate select bit

/RTS1 are used together.

/RTS1 are separated.

/P83 switch bit

Address

Fig. 76 Bit configuration of serial I/O pin control register

At reset

Receive is enabled when bit 2 (REi flag) of UARTi transmit/receive control register 1 is set to “1.” As shown in Figure 75, the frequency divider circuit (1/16) at the receiving side begin to work when a start bit arrives and the data is received.

________

If RTSi output is selected by setting bit 2 of UARTi transmit/receive control register 0 to “1”, the RTSi output is “H” when the REi flag is “0”. When the REi flag changes to “1”, the RTSi output goes “L” to inform the receiver that reception has become enabled. When the receive operation starts, the RTSi output automatically becomes “H”. The entire transmission data bits are received when the start bit passes the final bit of the receive block shown in Figure 66. At this point, the contents of the receive register is transferred to the receive buffer register and bit 3 (Rli flag) of UARTi transmit/receive control register 1 is set to “1.” In other words, the RIi flag indicates that the receive buffer register contains data when it is set to “1.” At this time, when the low-order byte of the UARTk receive buffer register is read

________

out, RTSi output goes back to “L” to indicate that the register is ready to receive the next data. Bit 4 (OERi flag) of UARTi transmit/receive control register 1 is set to “1” when the next data is transferred from the receive register to the receive buffer register while the RIi flag is “1”, in other words, when an overrun error occurs. If the OERi flag is “1”, it indicates that the next data has been transferred to the receive buffer register before the contents of the receive buffer register has been read. Bit 5 (FERi flag) is set to “1” when the number of stop bits is less than required (framing error). Bit 6 (PERi flag) is set to “1” when a parity error occurs. Bit 7 (SUMi flag) is set to “1” when either the OERi flag, FERi flag, or the PERi flag is set to “1.” Therefore, the SUMi flag can be used to determine whether there is an error. The setting of the RIi flag, OERi flag, FERi flag, and the PERi flag is performed while transferring the contents of the receive register to the receive buffer register.

Functions

Pin P84/CTS1/RTS

CTS

RTS

________

Pin P85/CTS1/CLK

CTS1 (Notes 2 and 3)

________

P85 or CLK P85 or CLK

P85 or CLK

1 1

Page 75

M37902FCCHP, M37902FGCHP, M37902FJCHP

The FERi, PERi, and SUMi flags are cleared to “0” when reading the low-order byte of the receive buffer register or when writing “0” to the REi flag. The OERi flag is cleared to “0” when writing “0” to the REi flag.

Interrupt request at completion of reception

• Each reception

• When an error occurs at reception

If bit 5 of the UARTk transmit/receive control register 0 (UART receive interrupt mode select bit) is cleared to “0”, the interrupt request bit is set to “1” at each reception. If bit 5 is set to “1”, the interrupt request bit is set to “1” only when an error occurs. (In the clock asynchronous serial communication, when an overrun error, framing error, or parity error occurs, the interrupt request bit is set to “1”.)

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Sleep mode

The sleep mode is used to communicate only between certain microcomputers when multiple microcomputers are connected through serial I/O. The microcomputer enters the sleep mode when bit 7 of UARTi transmit/receive mode register is set to “1.” The operation of the sleep mode for an 8-bit asynchronous communication is described below. When sleep mode is selected, the contents of the receive register is not transferred to the receive buffer register if bit 7 (bit 6 if 7-bit asynchronous communication and bit 8 if 9-bit asynchronous communication) of the received data is “0”. Also the RIi, OERi, FERi, PERi, and the SUMi flags are unchanged. Therefore, the interrupt request bit of the UARTi receive interrupt control register is also unchanged. Normal receive operation takes place when bit 7 of the received data is “1”. The following is an example of how the sleep mode can be used. The main microcomputer first sends data: bit 7 is “1” and bits 0 to 6 are set to the address of the subordinate microcomputer to be communicated with. Then all subordinate microcomputers receive this data. Each subordinate microcomputer checks the received data, clears the sleep bit to “0” if bits 0 to 6 are its own address and sets the sleep bit to “1” if not. Next, the main microcomputer sends data with bit 7 cleared. Then the microcomputer which cleared the sleep bit will receive the data, but the microcomputers which set the sleep bit to “1” will not. In this way , the main microcomputer is able to communicate only with the designated microcomputer.

Precautions for clock asynchronous (UART) serial communication

When using pin CTS0/RTS0, be sure to clear the D-A2 output enable bit (bit 2 at address 9616) to “0” (output disabled). Also, when CTSi

_______

and RTSi are separated, pin CLKi cannot be used. Therefore, when

_______ _______

CTSi and RTSi are separated in UART mode, be sure to select an internal clock. Before transmit operation is performed, be sure to clear bits 2 and 3 of the serial I/O pin control register (address AC16) to “00”.

________ ________

_______

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A-D CONVERTER

The A-D converter is a 10-bit successive approximation converter. Figure 77 shows the block diagram of the A-D converter, Figure 78 shows the bit configuration of the A-D control register 0 (address

16), and Figure 79 shows the bit configuration of the A-D control

1E register 1 (address 1F

16).

A-D conversion accuracy

Bit 3 of A-D control register 1 is used to select whether to regard the conversion result as 10-bit or as 8-bit data. The conversion result is regarded as 10-bit data when bit 3 is “1” and as 8-bit data when bit 3 is “0”. When the conversion result is used as 10-bit data, the low-order 8 bits of the conversion result is stored in the even address of the corresponding A-D register and the high-order 2 bits are stored in bits 0 and 1 at the odd address of the corresponding A-D register. Bits 2 to 7 of the A-D register odd address are “0000002” when read.

REF

connection select bit

REF

Resistor ladder network

ref

When the conversion result is used as 8-bit data, the conversion result are stored in even address of the corresponding A-D register. In this case, the value at the A-D register’s odd address is “0016” when read.

A-D conversion frequency

An operation clock ( 7 of the A-D control register 0 and bit 4 of the A-D control register 1. When bit 4 of the A-D control register 1 is “0”, when bit 7 of the A-D control register 0 is “0”, bit 7 of the A-D control register 0 is “1”. When bit 4 of the A-D control register 1 is “1”, bit 7 of the A-D control register 0 is “0”, the A-D control register 0 is “1”. Note that the fastest speed) can be selected only in the 8-bit mode.

AD during A-D conversion must be 250 kHz or more because the

comparator uses a capacity coupling amplifier.

1/2

AD) of an A-D converter can be selected with bit

AD becomes f2/4

AD becomes f2/2 when

AD becomes f2 when

AD becomes f1 when bit 7 of

AD = f1 (in other words,

A-D conversion frequency selection

(1,1)

(1,0)

1/2

(0,1)

(0,0)

A-D conversion frequency (φAD) select bit 1,0

Successive approximation register

Data bus (odd)

AN AN AN AN AN AN AN

AN7/AD

Fig. 77 Block diagram of A-D converter

0 1 2 3 4 5 6

TRG

A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 A-D register 5 A-D register 6 A-D register 7

Data bus (even)

A-D control register 1

A-D control register 0

Comparator

Decoder

Selector

Page 77

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Trigger

A-D conversion can be started by an internal trigger or by an external trigger. An internal trigger is selected when bit 5 of A-D control register 0 is “0” and an external trigger is selected when it is “1”. When trigger is selected, A-D conversion is started when bit 6 (A-D conversion start bit) is set to “1.” When an external trigger is selected, the polarity of a trigger input can be selected by bit 5 of the A-D control register 1. When bit 5 = “0”, a falling edge is selected, and when bit 5 = “1”, a rising edge is selected. A-D conversion starts when the A-D conversion start bit is “1” and the

______

ADTRG input changes from “H” to “L” (or “L” to “H.”) In this case, the pins that can be used for A-D conversion are AN0 to AN6 because the

______

ADTRG pin is multiplexed with an analog voltage input pin, AN7. If an

76543210

A-D control register 0 Analog input select bits (Note 1)

(Valid in the one-shot and repeat modes.) 0 0 0 : Select AN

0 0 1 : Select AN 0 1 0 : Select AN 0 1 1 : Select AN 1 0 0 : Select AN4 (Note 2) 1 0 1 : Select AN5 (Note 3)

1 1 0 : Select AN

1 1 1 : Select AN7 (Note 5) A-D operation mode select bits 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode Trigger select bit 0 : Internal trigger 1 : External trigger due to AD A-D conversion start bit (Note 7) 0 : Stop A-D conversion 1 : Start A-D conversion A-D conversion frequency (φ

external trigger is selected, even when the A-D conversion is completed, the A-D conversion start bit keeps “1”. Also, a retrigger can be available even when A-D conversion is in progress.

VREF connection

Whether to connect the reference voltage input (VREF) with the resistor ladder network or not depends on bit 6 of the A-D control register

1. The VREF pin is connected when bit 6 is “0” and is disconnected when bit 6 is “1” (High impedance state). When A-D conversion is not performed, current from the VREF pin to the resistor ladder network can be cut off by disconnecting resistor ladder network from the VREF pin. Before starting A-D conversion, wait for 1 µs or more after clearing bit 6 to “0”.

Address

0 1 2 3

(Note 4)

TRG

input (Note 6)

) select bit 0

Notes 1: Ignored in the single sweep and repeat sweep modes. (Each of these bits may be “0” or “1”.)

2: When using the AN 3: When using the AN 4: When using the AN 5: When using the AN

output enable bit (bit 1 at address 96

6: When using an external trigger, be sure to clear the INT

enable bit (bit 1 at address 96

7: For writing to this bit, use the MOVM (MOVMB) instruction, or the STA (STAB, STAD) instruction. 8: Rewriting to each bit of the A-D control register 0 (except for bit 6) must be performed while A-D conversion is stopped.

pin, be sure to clear the INT3 pin select bit (bit 5 at address 9416) to “0”.

pin, be sure to clear the INT4 pin select bit (bit 6 at address 9416) to “0”.

pin, be sure to clear the D-A0 output enable bit (bit 0 at address 9616) to “0” (output disabled).

pin, be sure to clear both of the INT2 pin select bit (bit 4 at address 9416) and the D-A1

Fig. 78 Bit configuration of A-D control register 0

) to “0”.

pin select bit (bit 4 at address 9416) and D-A1 output

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76543210

A-D conversion frequency (

Bit 1

0 0 1 1

Address

A-D control register 1 A-D sweep pin select bits (Note 1)

(Valid in the single sweep mode and repeat sweep mode.) 0 0 : AN

, AN 0 1 : AN0–AN 1 0 : AN0–AN 1 1 : AN0–AN Must be “0”. Resolution select bit 0: 8-bit mode 1: 10-bit mode A-D conversion frequency (φ External trigger polarity select bit (Valid when external trigger is selected.) 0: Falling edge of input signal to the AD 1: Rising edge of input signal to the AD

REF

V 0 : V 1 : V “0” at read.

AD) select bit

1 3 5 7

connection select bit (Note 6)

REF

is connected.

REF

is not connected.

Bit 0

0 1

(2 pins) (4 pins) (6 pins) (Notes 2, 3) (8 pins) (Notes 2 to 5)

AD) select bit 1

TRG pin

f2/4

(Selectable only in 8-bit mode)

Notes 1: Ignored in the one-shot and repeat modes. (Each of these bits may be “0” or “1”.)

2: When using the AN 3: When using the AN 4: When using the AN

“0” (output disabled).

5: When using the AN

and the D-A the AN

6: Once this bit is cleared from “1” to “0”, it is necessary to wait for 1 µs or more before the A-D or

D-A conversion starts.

7: Rewriting to each bit of the A-D control register 1 must be performed while A-D conversion is stopped.

1 output enable bit (bit 1 at address 9616) to “0”. When an external trigger is selected,

7 pin cannot be used as an analog input pin.

Fig. 79 Bit configuration of A-D control register 1

4 pin, be sure to clear the INT3 pin select bit (bit 5 at address 9416) to “0”. 5 pin, be sure to clear the INT4 pin select bit (bit 6 at address 9416) to “0”. 6 pin, be sure to clear the D-A0 output enable bit (bit 0 at address 9616) to

7 pin, be sure to clear both of the INT2 pin select bit (bit 4 at address 9416)

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Operation mode

The operation mode is selected by bits 3 and 4 of A-D control register 0. The available operation modes are one-shot, repeat, single sweep, and repeat sweep. Analog input port pins are multiplexed with port P7 pins. Therefore, bits which correspond to pins for A-D conversion must be “0” (input mode).

(1) One-shot mode

One-shot mode is selected when bits 3 and 4 of A-D control register 0 are “0” is “0”. The A-D conversion pins are selected with bits 0 to 2 of A-D control register 0. A-D conversion can be started by a software trigger or by an external trigger. When an internal trigger is selected, A-D conversion is started when bit 6 (A-D conversion start bit) is set to “1.” When bit 3 of the A-D control register 1 is “1”, A-D conversion ends after 59 φAD cycles, and the interrupt request bit of the A-D interrupt control register is set to “1.” At the same time, A-D control register 0 bit 6 (A-D conversion start bit) is cleared to “0” and A-D conversion stops. The result of A-D conversion is stored in the A-D register corresponding to the selected pin. If an external trigger is selected, A-D conversion starts when the A-D conversion start bit is “1” and a valid edge is input to the ADTRG pin, This operation is the same as that for internal trigger except that the A-D conversion start bit is not cleared after A-D conversion and a retrigger can be available during A-D conversion.

(2) Repeat mode

Repeat mode is selected when bit 3 of A-D control register 0 is “1” and bit 4 is “0”. The operation of this mode is the same as the operation of one-shot mode except that when A-D conversion of the selected pin is complete and the result is stored in the A-D register, conversion does not stop, but is repeated. No interrupt request is generated in this mode. Furthermore, if an external trigger is selected, the A-D conversion start bit is not cleared. The contents of the A-D register can be read at any time.

When A-D conversion of all selected pins end, the interrupt request bit of the A-D conversion interrupt control register is set to “1.” At the same time, A-D conversion start bit is cleared to “0” and A-D conversion stops. When an external trigger is selected, A-D conversion starts when the A-D conversion start bit is “1” and a valid edge is input to the ADTRG pin. In this case, the A-D conversion result which is stored in the A-D register 7 becomes invalid. The operation by external trigger is the same as that by an internal trigger except that the A-D conversion start bit is not cleared to “0” after A-D conversion and a retrigger can be available during A-D conversion.

(4) Repeat sweep mode

Repeat sweep mode is selected when bit 3 of A-D control register 0 is “1” and bit 4 is “1”. The difference from the single sweep mode is that A-D conversion does not stop after conversion for all selected pins, but repeats again from the AN0 pin. The repeat is performed among the selected pins. Also, no interrupt request is generated. Furthermore, if an internal trigger is selected, the A-D convension start bit is not cleared. The A-D register can be read at any time.

Precautions for A-D conversion interrupt function

Clear the interrupt request bit of the A-D interrupt control register (bit 3 at address 7016) before using the A-D interrupt. It is because the interrupt request bit is undefined just after reset.

(3) Single sweep mode

Single sweep mode is selected when bit 3 of A-D control register 0 is “0” and bit 4 is “1”. In the single sweep mode, the number of analog input pins to be swept can be selected. Analog input pins are selected by bits 1 and 0 of the A-D control register 1 (address 1F16). Two pins, four pins, six pins, or eight pins can be selected as analog input pins, depending on the contents of these bits. A-D conversion is performed only for selected input pins. After A-D conversion is performed for input of AN0 pin, the conversion result is stored in A-D register 0, and in the same way, A-D conversion is performed for selected pins one after another. After A-D conversion is performed for all selected pins, the sweep is stopped. A-D conversion can be started with an internal trigger or with an external trigger input. An internal trigger is selected when bit 5 of the AD control register 0 (address 1E16) is “0” and an external trigger is selected when it is “1”. When an internal trigger is selected, A-D conversion is started when A-D control register 0 bit 6. (A-D conversion start bit) is set to “1.”

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D-A CONVERTER

Three independent D-A converters are included in this microcomputer, and each D-A converter adopts an 8-bit R-2R method. Figure 80 shows the block diagram of the D-A converter, Figure 81 shows the bit configuration of the A-D control register 1, and Figure 82 shows the bit configuration of the D-A control register. D-A conversion is performed by writing a value to the corresponding D-A register i. Whether to output the analog voltage or not is determined by bits 0 to 2 of the D-A control register. When any of bits 0 to 2 = “1”, the corresponding pin (D-A0 to D-A2) outputs the analog voltage. This analog voltage (V) is determined according to value n. (“n” = decimal number. This has been set in the D-A register.)

V = VREF ✕ n/256 (n = 0 to 255)

VREF : Reference voltage

The contents of the corresponding D-A output enable bit and D-A register are cleared to “0” at reset. Whether to connect the reference voltage input (VREF) with the ladder network or not depends on bit 6 of the A-D control register 1. Pin VREF is connected with the ladder network when bit 6 = “0” and is disconnected when bit 6 = “1” (high impedance state). When not performing the A-D or D-A conversion, current from pin VREF to the ladder network can be cut off by disconnecting ladder network from pin VREF. Before starting A-D or D-A conversion, be sure to clear bit 6 to “0”, and then, insert a waiting time of 1 µs or more. An external buffer is necessary when connecting a low impedance load with the D-A converter. It is because that a D-A output pin doesn’t include a buffer. Pin D-Ai is multiplexed with I/O port pins, analog input pins, serial I/O pins, and external interrupt input pins. When a D-Ai output enable bit = “1” (in other words, output is enabled.), however, the corresponding pin cannot function as another I/O pin, which is multiplexed

with pin D-Ai. Also, when not using the D-A converter , be sure to clear the contents of the corresponding D-A output enable bit and D-A register to “0”.

76543210

✕✕✕✕✕

✕✕

Note: When bit 6 has been cleared to “0” from “1”, insert a waiting time

of 1 µs or more, and then, start the D-A or A-D conversion.

A-D control register 1

Not used for D-A converter. V

REF

connection select bit (Note) 0: Connected. 1: Disconnected.

Address

Fig. 81 Bit configuration of A-D control register 1

76543210

Note: Pin D-Ai is multiplexed with I/O port pins, analog input pins, serial

I/O pins, and external interrupt input pins. When a D-Ai output enable bit = “1” (in other words, output is enabled.), however, the corresponding pin cannot function as another I/O pin, which is multiplexed with pin D-Ai.

D-A control register

D-A0 output enable bit (Note)

0: Output is disabled. 1: Output is enabled.

D-A1 output enable bit (Note)

0: Output is disabled. 1: Output is enabled.

D-A2 output enable bit (Note)

0: Output is disabled. 1: Output is enabled.

Address

Fig. 82 Bit configuration of D-A control register

REF

Fig. 80 Block diagram of D-A converter

REF

connection

select bit

Data bus

R-2R ladder

network

Pin D-A

D-A register i (i = 0 to 2) (Addresses 9816 to 9A16)

D-Ai output enable bit

Page 81

MITSUBISHI MICROCOMPUTERS

M37902FCCHP, M37902FGCHP, M37902FJCHP

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

REAL-TIME OUTPUT

The real-time output function enables to change the output level of several pins simultaneously with a specified timer’s counting. Whether to use the real-time output function is decided by the waveform output select bits of the 8-bit real-time output control register (bits 0 and 1 at address A016). (See Figure 83.) Also, the real-time output controlled by the pulse output mode select bit of the real-time output control register (bit 2 at address A016) and is used in one of the following ways:

• 4 bits ✕ 2 channels

• 6 bits ✕ 1 channel + 2 bits ✕ 1 channels

(1) Pulse mode 0

When the pulse output mode select bit is cleared to “0”, the microcomputer enters pulse output port is controlled by 2 groups of 4 bits. Figures 84 and 85 show the bit configuration of the pulse output data register 0/1 (address A216/A416) and real-time output structure in pulse mode 0, respectively. When the waveform output select bits are set to “01” (bit 1 = “0” and bit 0 = “1”), RTP03 to RTP00 become pulse output port pins, in other words, RTP0 is selected. When the waveform output select bits are set to “10” (bit 1 = “1” and bit 0 = “0”), RTP13 to RTP10 become pulse output port pins, in other words, RTP1 is selected. When the waveform output select bits are set to “11” (bit 1 = “1” and bit 0 = “1”), two groups consisting of RTP13 to RTP10 and RTP03 to RTP00 become pulse output port pins, in other words, RTP1 and RTP0 are selected. When the waveform output select bits are set to “00” (bit 1 = bit 0 = “0”), port P5 pins become normal programmable I/O port pins. The contents of the pulse output data register 1 (high-order 4 bits at address A416), which corresponds to RTP13 to RTP10, is output to these ports each time when the contents of timer A1 counter becomes “000016”. The contents of the pulse output data register 0

(low-order 4 bits at address A216), which corresponds to RTP03 to RTP00, is output to these ports each time when the contents of timer A0 counter becomes “000016”. When “0” is written to a specified bit of the pulse output data register, a low-level signal is output to a pulse output port if the counter contents of the timer which corresponds to the bit becomes “000016”: when “1” is written to the bit, a high-level signal is output to a pulse output port which corresponds to the bit at the same timing.

76543210

Real-time output register A0 Waveform output select bits

00 : Programmable I/O port 01 : RTP0 selected When pulse mode 0 is selected: RTP0 When pulse mode 1 is selected: RTP0 10 : RTP1 selected When pulse mode 0 is selected: RTP1 When pulse mode 1 is selected: RTP1, RTP0 11 : RTP1 and RTP0 selected When pulse mode 0 is selected: RTP1 and RTP0 When pulse mode 1 is selected: RTP1, RTP0 RTP0

Pulse output mode select bit 0 : Pulse mode 0 1 : Pulse mode 1

“0” at read.

, RTP0

RTP0

, RTP0

Address

RTP02 and

Fig. 83 Bit configuration real-time output control register

76543210

Pulse output data register 0

0 pulse output data bit

RTP0

1 pulse output data bit

RTP0

2 pulse output data bit (Note 1)

RTP0

3 pulse output data bit (Note 1)

RTP0

Note 1: Used only in pulse mode 0

2: Used only in pulse mode 1

Fig. 84 Bit configuration of pulse output data register

Address

76543210

Pulse output data register 1

RTP0

2 pulse output data bit (Note 2) 3 pulse output data bit (Note 2)

RTP0

0 pulse output data bit

RTP1

1 pulse output data bit

RTP1

2 pulse output data bit

RTP1

3 pulse output data bit

RTP1

Address

Page 82

M37902FCCHP, M37902FGCHP, M37902FJCHP

Timer A2

Pulse output data register 1 (Address A4

)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Pulse output mode select bit (Address A0

)

MITSUBISHI MICROCOMPUTERS

Data bus (Even)

Pulse output data register 0 (Address A216)

Timer A0

a a

a a a a

Port P5i latch

(i = 7 to 0)

(Address B

P57/RTP1 P56/RTP1 P55/RTP1 P54/RTP1

Waveform output select bit (Address A016) bit 1

P53/RTP0 P52/RTP0 P51/RTP0 P50/RTP0

Waveform output select bit (Address A016) bit 0

Port P5i direction register

(Address D16)

“1”

“0”

)

Fig. 85 Real-time output structure in pulse mode 0

(2) Pulse mode 1

When the pulse output mode select bit is set to “1”, the microcomputer enters pulse mode 1, and a pulse output port pins are separately controlled (6 bits and 2 bits). Figures 86 shows the real-time output structure in pulse mode 1. When the waveform output select bits are set to “01” (bit 1 = “0” and bit 0 = “1”), RTP13 to RTP10, RTP03, and RTP02 become programmable I/O port pins. Simultaneously, RTP01 and RTP00 become pulse output port pins. When the waveform output select bits are set to “10” (bit 1 = “1” and bit 0 = “0”), RTP13 to RTP10, RTP03, and R TP02 become pulse output port pins. At this time, RTP01 and R TP00 become programmable I/O port pins. When the waveform output select bits are set to “11” (bit 1 = bit 0 =

“1”), pulse output port pins are divided into two groups; one consists of RTP13 to RTP10, RTP03, RTP02 and the other consists of R TP01 and RTP00. When the waveform output select bits are set to “00” (bit 1 = bit 0 = “0”), port P5 pins become normal programmable I/O port pins. RTP13 to RTP10, RTP03, and RTP02 are controlled by timer A2. Also, RTP01 and RTP00 are controlled by timer A0. The contents of the pulse output data register 1 (high-order 6 bits at address A416), which corresponds to RTP13 to RTP10, RTP03, and RTP02, are output to this port each time when the contents of timer A2 counter becomes “000016”. The contents of the pulse output data register 0 (low-order 2 bits at address A216), which corresponds to RTP01 and RTP00, are output to this port each time when the contents of timer A0 counter become “000016”.

Page 83

M37902FCCHP, M37902FGCHP, M37902FJCHP

Timer A2

Pulse output data register 1 (Address A4

)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Pulse output mode select bit (Address A016)

MITSUBISHI MICROCOMPUTERS

Data bus (Even)

Pulse output data register 0 (Address A2

)

Timer A0

a a

(i = 7 to 0)

Port P5i latch

(Address B

P57/RTP1 P56/RTP1 P55/RTP1 P54/RTP1 P53/RTP0

P52/RTP0

Waveform output select bit (Address A0

P51/RTP0 P50/RTP0

Waveform output select bit (Address A016) bit 0

Port P5i direction register

(Address D

“0”

)

“1”

)

) bit 1

Fig. 86 Real-time output structure in pulse mode 1

Table 14 lists the port P5/RTP pin output when all of the port P5 direction registers are set to the output mode.

Precautions for real-time output function

After reset, the port P5 direction register is set to the input mode, and port P5i (i = 0 to 7) pins function as normal I/O port pins. When using these pins as real-time output port pins, set the corresponding bits of the port P5 direction register to the output mode. Additionally, by reading the real-time output port’s value from the port P5 register, output level of pins can be read out.

Table 14 Port P5/RTP pin output

Real-time output

control register (Address A0

bit

0 0

1 1 0 0

1 1

16)

bit

Store address for port P5/RTP pin output data

bit

0B 0B A4 A4 0B 0B A4 A4

0 0

1 0 1 0 1 0 1

bit

0B 0B A4 A4 0B 0B A4 A4

bit

0B 0B A4 A4 0B 0B A4 A4

Address 0B16: Port P5 Address A216: Pulse output data register 0 Address A416: Pulse output data register 1

bit

0B A2 0B A2 0B 0B A4 A4

bit2bit

0B A2 0B A2 0B 0B A4 A4

0B A2 0B A2 0B A2 0B A2

bit

0 0B A2 0B

A2 0B A2 0B A2

Page 84

MITSUBISHI MICROCOMPUTERS

M37902FCCHP, M37902FGCHP, M37902FJCHP

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

WATCHDOG TIMER

The watchdog timer is used to detect unexpected execution sequence caused by software runaway and others. Figure 87 shows the block diagram of the watchdog timer. The watchdog timer consists of a 12-bit binary counter. The watchdog timer counts clock Wf32, which is obtained by dividing the peripheral devices’ clock f2 by 16; or clock Wf512, which is obtained by doing it by 256. Bit 0 of the watchdog timer frequency select register (watchdog timer frequency select bit) shown in Figure 88 selects which clock is to be counted. Wf512 is selected when this bit 0 is “0”, and Wf32 is selected when bit 0 is “1”. Bit 0 is cleared to “0” after reset. FFF16 is set in the watchdog timer when “L” level voltage is applied to pin RESET, STP instruction is executed, data is written to the watchdog timer register (address 6016), or the most significant bit of the watchdog timer becomes “0”. After FFF16 is set in the watchdog timer, when the watchdog timer counts Wf32 or Wf512 by 2048 counts, the most significant bit of watchdog timer becomes “0”, the watchdog timer interrupt request bit is set to “1”, and FFF16 is set again in the watchdog timer. In program coding, make sure that data is written in the watchdog timer before the most significant bit of the watchdog timer becomes “0”. If this routine is not executed owing to unexpected program execution or others, the most significant bit of the watchdog timer be-

comes “0” and an interrupt is generated. The microcomputer can generate a reset pulse by writing “1” to bit 6 (software reset bit) of processor mode register 0 in an interrupt routine and can be restarted. The watchdog timer can also be used to return from the STP state, where a clock has stopped its operation owing to the STP instruction execution. For details, refer to the sections on the clock generating circuit and standby function. The watchdog timer stops its operation in the following cases, and at this time, input to the watchdog timer is disabled:

• When the external area is accessed in the hold state

• In the wait mode

• In the stop mode

76543210

Fig. 88

Bit configuration of watchdog timer frequency select register

Watchdog timer frequency select register

Watchdog timer frequency select bit

512

0 : Wf 1 : Wf

Watchdog timer clock source select bits at STP state termination

0 0 : fX 0 1 : fX

1 0 : fX

128

1 1 : fX

Address

Access to external area

HLDA

Wait mode

Divided f(XIN)

fX16 fX32 fX64

fX128

Watchdog timer clock source select bits at STP state termination

• Watchdog timer register: address 60

• Watchdog timer frequency select register: bit 0 at address 61

• Watchdog timer clock source select bits at STP state termination: bits 6, 7 at address 61 ❈ When the most significant bit of the watchdog timer becomes “0”, this signal will be generated.

Note: During the stop mode and until the stop mode is terminated, setting for disabling the

1/16

Disables watchdog

timer (Note).

Writing to watchdog

timer register

RESET

STP instruction

watchdog timer is ignored.

Wf32

Wf512

Watchdog timer frequency select bit

Stop mode

Watchdog timer

“FFF

Watchdog timer interrupt request

❈

” is set.

Fig. 87 Block diagram of watchdog timer

Page 85

M37902FCCHP, M37902FGCHP, M37902FJCHP

How to disable watchdog timer

When not using the watchdog timer, it can be disabled. When the watchdog timer is disabled, it’s operation stops and no watchdog timer interrupt has been generated. Setting for disabling the watchdog timer is possible by writing “7916” and “5016” to the particular function select register 2 (address 6416) sequentially with the following instructions:

• MOVMB/STAB instruction, or

• MOVM/STA instruction (m = 1)

If any method other than above has been adopted in order to access (in other words, read/write) the particular function select register 2, the watchdog timer will not be disabled until reset operation is performed. (Also, reset is the only one method to remove the setting for disabling the watchdog timer.) Moreover, this setting for disabling the watchdog timer is ignored at return from the STP mode, and the watchdog timer operates. (For details, refer to the section on the standby function.)

MITSUBISHI MICROCOMPUTERS

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Page 86

MITSUBISHI MICROCOMPUTERS

M37902FCCHP, M37902FGCHP, M37902FJCHP

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

INPUT/OUTPUT PINS

Ports P0 to P8, P10, P11 all have the direction register, and each bit can be programmed for input or output. A pin becomes an output pin when the corresponding bit of direction register is “1”, and an input pin when it is “0”. When a pin is programmed for output, the data is written to its port latch and it is output to the output pin. When a pin is programmed for output, the contents of the port latch is read instead of the value of the pin. Accordingly, a previously output value can be read correctly even when the output “H” voltage is lowered or the output “L” voltage is raised owing to an external load, etc. A pin programmed as an input pin is in the flooting state, and the value input to the pin can be read. When a pin is programmed as an input pin, the data is written only in the port latch and the pin remains floating. Each of Figures 89 and 90 shows the block diagram for each port pin and pin NMI. Figure 91 shows the bit configuration of the port function control register. Bit 3 of the port function control register serves as the port P0 input level select bit, which selects the VIH/VIL level under the condition that port P0 is used as an input port. Bit 4 of the port function control register serves as the P44–P47

76543210

Port function control register

pullup connection select bit. This bit determines whether port pins P44–P47, which are multiplexed with chip select pins, are to be pulled up or not. At reset, this bit 4 = “0” and P4–P47 are pulled up. The pullup function is valid only when the corresponding port is used an input port. Bit 7 of the port function control register serves as the NMI pullup connection select bit. At reset, this bit 7 = “0” and pin NMI is pulled up. The pullup function is valid only when the corresponding port is used as an input port. When using port pins P54–P57 as the key input interrupt input pins (KI0 to KI3), the pullup function can be selected, also. For details, refer to the section on interrupts. When using a port pin as an internal peripheral device’s input pin, clear the corresponding port direction register’s bit to “0”. When using a port pin as an internal peripheral device’s output pin, the port direction register’s bit may be “0” or “1”. In the memory expansion or microprocessor mode, port pins of P0 to P4, P10, P11 become I/O pins, and the their functions as I/O port pins are invalid. Note that, however, some port pins can function as port pins by the special setting. For details, refer to the section on the processor modes.

Address 92

At reset

Address/Port switch bits

to A23 (16 Mbytes)

000 : A

to A21, P06, P07 (4 Mbytes)

001 : A

to A19, P04 to P07 (1 Mbytes)

010 : A

to A17, P02 to P07 (256 Kbytes)

011 : A

to A15, P00 to P07 (64 Kbytes)

100 : A 101 : Do not select.

to A11, P00 to P07, P114 to P117 (4 Kbytes)

110 : A

to A7, P00 to P07, P110 to P117 (256 bytes)

111 : A

Port P0 input level select bit

0 : V

= 0.7VCC, VIL = 0.2V

1 : VIH = 0.43VCC (Note 1), VIL = 0.16V

–P47 pullup connection select bit (Notes 2 and 3)

Pins P4

0 : Pins P4 1 : Pins P4

Fix these bits to “0”.

Pin NMI pullup connection select bit (Note 2)

0 : Pin NMI is pulled up. 1 : Pin NMI is not pulled up.

Notes 1: For the M37902FxM (power source voltage = 3.3 V±0.3 V), VIH = 0.5VCC.

2: When MD1 = V

not pulled up, regardless of these bits’ contents.

3: When MD1 = V

and MD0 = VCC (flash memory parallel I/O mode), pins P44 to P47 and NMI are

and MD0 = VCC (microprocessor mode), pin CS0 (P44) is not pulled up, regardless of the bit’s contents.

–P47 are pulled up.

–P47 are not pulled up.

Fig. 91 Bit configuration of port function control register

Page 87

MITSUBISHI MICROCOMPUTERS

M37902FCCHP, M37902FGCHP, M37902FJCHP

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

[Inside dotted-line not included] P0

to P07, P10 to P17, P20 to P27,

to P33, P100 to P107,

P11

to P11

[Inside dotted-line included] P3

/RDY, P43/HOLD,

/TA4IN,

/INT0, P63/INT1, P64/INT2,

/TB0IN, P66/TB1IN, P67/TB2IN,

2/RXD0

, P86/RXD

[Inside dotted-line not included] P4

/ALE, P41/φ1, P42/HLDA,

3/TXD0

, P87/TXD

[Inside dotted-line included] P6

/TA4

OUT

[Shaded area included] P4

/CS0, P45/CS1,

/CS2, P47/CS

Data bus

Direction register

Port latch

Direction register

Output(Internal peripheral devices)

Port latch

Pullup selection

Pullup transistor

[Shaded area not included] P5

/TA0IN/RTP01,

/TA1IN/RTP0

[Shaded area included] P5

/TA2IN/RTP11/KI1,

/TA3IN/RTP13/KI

[Shaded area not included] P5

/TA0

OUT

/RTP00,

/TA1

OUT

/RTP0

[Shaded area included] P5

/TA2

OUT

/RTP10/KI0,

/TA3

OUT

/RTP12/KI

Data bus

Direction register

Port latch

Latch T Q

Timer underflow signal

Direction register

Output

Port latch

Latch T Q

Timer underflow signal

Pullup selection

(Internal peripheral devices)

Pullup selection

Pullup transistor

Fig. 89 Block diagram for each port pin and pin NMI (1)

Page 88

MITSUBISHI MICROCOMPUTERS

M37902FCCHP, M37902FGCHP, M37902FJCHP

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

[Inside dotted-line not included]

/AN0, P71/AN1,

P7 P7

/AN2, P73/AN

[Inside dotted-line included] P7

/AN4/(INT3),

/AN5/(INT4)

P81/CTS0/CLK0, P8

/CTS1/RTS1/INT4,

/CTS1/CLK

[Inside dotted-line not included] P7

/AN6/DA

[Inside dotted-line included] P7

/AN7/AD

TRG

/DA1/(INT2)

Data bus

Direction register

Port latch

Direction register

Output

(Internal peripheral devices)

Port latch

Direction register

Port latch

Analog input

1 0

P80/CTS0/RTS0/DA2/INT

NMI

Analog input

Analog output

Direction register

Output

(Internal peripheral devices)

Data bus

Port latch

Pullup selection

1 0

Analog output

Pullup transistor

Enable D-A output

Fig. 90 Block diagram for each port pin and pin NMI (2)

Page 89

M37902FCCHP, M37902FGCHP, M37902FJCHP

RESET CIRCUIT

While the power source voltage satisfies the recommended operating condition, reset state is removed if pin RESET’s level returns from the stabilized “L” level to the “H” level. As a result, program execution starts from the reset vector address. This reset vector address is expressed as shown below:

• A23 to A16 = 0016

• A15 to A8 = Contents at address FFFF16

• A7 to A0 = Contents at address FFFE16

Figures 92 and 93 show the microcomputer internal register’s status at reset, and Figure 94 shows an operation example of the reset circuit. Apply “L” level voltage to pin RESET for a period (2 µs or more) under the following conditions:

• Pin Vcc’s level satisfies the recommended operating condition.

• Oscillator’s operation has been stabilized.

MITSUBISHI MICROCOMPUTERS

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

VCC level

RESET

Power on

Fig. 94 Operation example of reset circuit (Note that proper evalua-

tion is necessary in the system development stage.)

0.2V

level

2 µs

Oscillation stabilized

control register L

control register H

control register L

control register H

control register L

control register H

control register L

control register H

start address register

External interrupt input control register

Address

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(Note 2)

···

···CS

···Area CS

)

···Area CS

···Port function control register

0000

···

···D-A control register

(Note 3)

010

01 001

(Note 3)

010010

000 000

(Note 3)

010010 000 000

(Note 3)

010010

0000 00010 000 00000 000 00000 000 00000 000

000

00000 0000

Processor status register PS Program bank register PG Program counter PC Program counter PC Direct page registers DPR0 to DPR3 Data bank register DT Stack pointer

000

Address

(

)

···D-A register 0

(

)

···D-A register 1

)

(

···D-A register 2

(

)

···Flash memory control register

(

)

···Real-time output control register

(

)

···Serial I/O pin control register

)

(

···Clock control register

000

Contents at address FFFF Contents at address FFFE

0000

FFF

000 001

0000 00000 111 000??

000

1??

Notes 1: The contents of the other registers and RAM are undefined at reset and must be initialized by software.

2: While Vss level voltage is applied to pin MD0, this bit is “0”. While Vcc level voltage is applied to pin MD0, on the other hand, this bit is “1”. 3: While Vss level voltage is applied to pin BYTE, these bits are “0”. While Vcc level voltage is applied to pin BYTE, on the other hand, these bits are “1”.

Fig. 93 Microcomputer internal register’s status at reset (2)

Page 90

MITSUBISHI MICROCOMPUTERS

M37902FCCHP, M37902FGCHP, M37902FJCHP

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Address

Port P0 direction register Port P1 direction register Port P2 direction register

Port P3 direction register Port P4 direction register Port P5 direction register Port P6 direction register Port P7 direction register Port P8 direction register Port P10 direction register Port P10 direction register

A-D control register 0 A-D control register 1

UART 0 Transmit/Receive mode register UART 1 Transmit/Receive mode register UART 0 Transmit/Receive control register 0 UART 1 Transmit/Receive control register 0 UART 0 Transmit/Receive control register 1 UART 1 Transmit/Receive control register 1 Count start register

One-shot start register Up-down register Timer A clock frequency select register Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register

Timer A4 mode register Timer B0 mode register

(

)

···

)

···

)

···

)

···

)

···

)

··· 00

)

···

)

···

)

···

)

··· 00

)

··· 00

)

···

)

···

)

··· 00

)

··· 00

)

···

)

···

)

···

)

···

)

··· 00

)

···

)

···

)

···

)

··· 00

)

··· 00

)

··· 00

)

··· 00

)

··· 00

)

···

0000

00000 ??? 0000 011

100 000 100 000 00000 010 00000 010

00 000

00?0 000

Address

Timer B1 mode register Timer B2 mode register

Processor mode register 0

Processor mode register 1 Watchdog timer

Watchdog timer frequency select register Particular function select register 0

Particular function select register 1 Debug control register 0

Debug control register 1

interrupt control register

INT INT

interrupt control register A-D conversion interrupt control register UART 0 transmit interrupt control register UART 0 receive interrupt control register UART 1 transmit interrupt control register UART 1 receive interrupt control register Timer A0 interrupt control register

Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register

Timer B0 interrupt control register Timer B1 interrupt control register

Timer B2 interrupt control register

INT

interrupt control register INT

interrupt control register INT2 interrupt control register

(

)

···

(

)

···

)

···

)

···

)

···

)

···

)

···

)

···

)

···

)

···

)

···

)

···

)

···

)

···

)

···

)

···

)

···

)

···

)

···

)

···

)

···

)

···

)

···

)

···

)

···

)

···

)

···

)

···

(Note 2)

00?0 000 00?0 000 1000

(Note 2)

0000

FFF

010000

(Note 3)

0000

(Note 3)

?000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 000 000 000 000

000

(Note 3)

Notes 1: The contents of the other registers and RAM are undefined at reset and must be initialized by software.

2: While Vss level voltage is applied to pin MD0, these bits are “0”. While Vcc level voltage is applied to pin MD0, on the other hand, these bits are “1”. 3: At power-on reset, these bits are clear to “0”. At hardware or software reset, on the other hand, these bits retain the value just before reset.

Fig. 92 Microcomputer internal register’s status at reset (1)

Page 91

M37902FCCHP, M37902FGCHP, M37902FJCHP

OUT

M37902

OSCILLATION CIRCUIT

An oscillation circuit locates between pins XIN and XOUT, and Figure 95 shows a circuit example with a oscillator (an external ceramic resonator or quartz crystal oscillator). The constants such as capacitance etc. depend on a oscillator. Therefore, for these constants, adopt the oscillator manufacturer’s recommended values. Figure 96 shows a circuit example with an external clock source. When an external clock is input, be sure to leave pin XOUT open. Also, in this case, when the external clock input select bit (bit 1 of the particular function select register 0; See Figure 100.) is set to “1”, the oscillation circuit stops it’s operation, and the current dissipation is reduced. Moreover, this bit has another function, which selects the return condition from the stop mode. For details, refer to the section on the standby function. On the other hand, the PLL (Phase Locked Loop) frequency multiplier (hereafter, referred as PLL circuit.) is included, also. This PLL circuit uses an clock input from pin XIN and generates a multiplied clock. When using the PLL circuit, be sure to connect pin VCONT with an external filter circuit. (See Figure 97.) When not using the PLL circuit, be sure to leave pin VCONT open. When not using the PLL circuit, be sure to clear the PLL circuit operation enable bit (bit 1 of the clock control register; See Figure 99.), so that the PLL circuit will stop it’s operation.

MITSUBISHI MICROCOMPUTERS

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Fig. 95 Circuit example with external ceramic resonator or quartz crystal oscillator

M37902

OUT

Left open.

External clock source

Vcc Vss

Fig. 96 Circuit example with external clock source

M37902

VCONT

1 KΩ

220 pF

0.1 µF

Note: Make the wiring length as short as possible,

and shield it with the GND line which

Fig. 97 Circuit example with pin V

surrounds this circuit. Also, for the clock supply to pin X

IN, see Figures 95 and 96.

and PLL circuit

CONT

Page 92

MITSUBISHI MICROCOMPUTERS

M37902FCCHP, M37902FGCHP, M37902FJCHP

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

CLOCK GENERATING CIRCUIT

Figure 98 shows the block diagram of the clock generating circuit. The clock generating circuit consists of the clock oscillation circuit, PLL frequency multiplier (PLL circuit), system clock switch circuit, peripheral devices’ clock switch circuit, clock divider , standby control circuit, etc. As control registers for the clock generating circuit, also, the clock control register (address BC16), particular function select register 0 (address 6216) are provided. (See Figures 99 and 100.) As shown in Figure 98, clocks used in the CPU, BIU, peripheral devices, watchdog timer (in other words, clocks Wf32, Wf512) are made from system clock fsys. System clock fsys can be selected between fXIN (in other words, a clock input from pin XIN) and fPLL (in other words, an output clock generated by the PLL circuit). By setting the clock

1 output select bit (bit 7 of the processor

mode register 0) to “1”, also, system clock fsys can be output from port pin P41, as clock

The PLL circuit’s operation, system clock (fsys) selection, and divide ratio selection for peripheral devices’ clocks (f1 to f4096) are controlled by the clock control register. The following describes about these control. Bit 1 of the clock control register (the PLL circuit operation enable bit) selects the PLL circuit’s operation (stopped/active). When this bit is set to “1”, pin VCONT will becomes valid, and the PLL circuit will operate. At reset, the PLL circuit operation enable bit becomes “1”. (In this case, the PLL circuit operates.) When not using the PLL circuit, be sure to clear the PLL circuit operation enable bit to “0” (stopped). At the STP instruction execution or while the flash memory parallel I/O mode is set, the PLL circuit stops its operation, and pin VCONT is in-

CPU, φBIU, f1 to f4096,

valid, regardless of this bit 1’s status. Bits 2 and 3 of the clock control register (the PLL multiplication ratio select bits) select the ratio of fPLL/fXIN. The PLL multiplication ratio must be set so that the frequency of the PLL output clock (fPLL) must be in the range from 10 MHz to 26 MHz. At reset, the PLL multiplication ratio select bits become “0,1” (✕ 2). The change of the multiplication ratio must be performed while input clock fXIN is set as system clock. (In this case, bit 5 of the clock control register = “0”.) After that, be sure to wait that the operation-stabilizing time of the PLL circuit has passed, and switch the system clock to the PLL output clock (fPLL). (In other words, set bit 5 to “1”.) Note that, after reset, the PLL multiplication ratio select bits are allowed to be changed only once. Bit 5 of the clock control register is the system clock select bit, and fXIN is selected as the system clock when bit 5 = “0”. On the other hand, when bit 5 = “1”, the PLL output clock (fPLL) is selected. At reset, the system clock select bit becomes “0”. When selecting fPLL, be sure that the PLL circuit’s operation has been stabilized properly , and then, set the system clock select bit to “1”. Also, when the PLL circuit operation enable bit is cleared to “0” (the PLL circuit is stopped.), the system clock select bit will automatically be cleared to “0”. Note that a value of “1” cannot be written to the system clock select bit while the PLL circuit operation enable bit =“0”. Table 15 lists the fsys selection. Bits 6 and 7 of the clock control register are the peripheral devices’ clock select bits 0, 1, and these bits select the multiplication ratio of (f1 to f4096)/(fsys). Table 16 lists the internal peripheral devices’ operation clock frequency. At reset, these bits become “0, 0”.

Table 15. f

System clock select bit

sys

(Bit 5)

selection

PLL circuit operation enable bit

(Bit 1)

PLL multiplication ratio select bits

(Bits 3, 2) (Note)

01 (✕ 2)

10 (✕ 3) 11 (✕ 4)

Note: The PLL multiplication ratio must be set so that the frequency of the PLL output clock (f

) means the frequency of the input clock from pin XIN (fXIN). After reset, the PLL multiplication ratio select bits are allowed to be

f(X changed only once.

Table 16. Internal peripheral devices’ operation clock frequency

Internal peripheral devices’

operation clock

512

4096

Note: When selecting the peripheral devices’ clock select bits 1, 0 = “01

sys

Peripheral devices’ clock select bits 1, 0 (bits 7, 6)

0 0

sys

/16

/64

/512

/4096

0 1 (Note)

sys

/32

sys

/256

sys

/2048

”, be sure that system clock f

System clock f

Clock source

fXIN

fPLL

PLL

) must be in the range from 10 MHz to 26 MHz.

1 0

sys

f f f

sys sys sys

/32

/128 /1024 /8192

sys

does not exceed 13 MHz.

Do not select.

sys

Frequency (Note)

f(XIN)

f(X

IN) ✕ 2

f(X

IN) ✕ 3

f(X

IN) ✕ 4

1 1

Page 93

512

4096

STP

instruction

BIU

(Clock for BIU)

CPU

(Clock for CPU)

CPU wait request

1/4

1/8

Reset

• Watchdog timer frequency select bit : bit 0 at address 61

•

Watchdog timer clock source select bit at stop state termination :

bits 6, 7 at address 61

• External clock input select bit : bit 1 at address 62

• System clock stop select bit at WIT : bit 3 at address 63

• PLL circuit operation enable bit : bit 1 at address BC

• PLL multiplication ratio select bits : bits 2, 3 at address BC

• System clock select bit : bit 5 at address BC

• Peripheral device

’s clock select bit 0, 1

: bits 6, 7 at address BC

1/8

1/2

1/16

Watchdog

timer

512

Peripheral device

’s clocks

Watchdog timer

frequency select bit

OUT

System clock stop select bi at WIT

1/16

Access to

external area

HLDA

Watchdog timer clock source select

bit at stop state termination

Wait mode

1/2

Wait mode

System clock

frequency select bit

PLL frequency

multiplier

PLL

CONT

Wait mode

External clock

input select bit

STP

instruction

Interrupt

request

WIT

instruction

Interrupt

request

Wait mode

PLL circuit operation enable bit

PLL multiplication ratio select bits

f/n

128

Peripheral

device’s clock

select bit 0

Peripheral

device’s clock

select bit 1

BIU : Bus interface Unit

CPU : Central Processing Unit

❈ : Signal generated when the watchdog timer

’s most significant bit becomes

“0”.

sys

System clock frequency select bit

❈

Operating clock for

serial I/O, timer B

A-D conversion frequency

(φ

) clock source

Operating clock for timer A

External clock input select bit

Interrupt

request

MITSUBISHI MICROCOMPUTERS

M37902FCCHP, M37902FGCHP, M37902FJCHP

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Fig. 98 Block diagram of clock generating circuit

Page 94

MITSUBISHI MICROCOMPUTERS

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

76543210

Notes 1: When not using the PLL frequency multiplier, clear this bit to “0”. In the stop mode or in

the flash memory parallel I/O mode, the PLL circuit stops it’s operation regardless of this bit’s contents; at this time, pin V

2: When rewriting this bit, be sure to clear bit 5 to “0” simultaneously. Also, after this bit is

rewritten, insert a waiting time of 2 ms, and then set bit 5 to “1”.

3: When the PLL circuit operation enable bit (bit 1) has been cleared to “0”, this bit will also

be cleared to “0”. Also, bit 1 = “0”, nothing can be written to this bit. (Fixed to be “0”.)

Clock control register

Fix this bit to “1”.

PLL circuit operation enable bit (Note 1)

0: PLL frequency multiplier is stopped, and pin V 1: PLL frequency multiplier is operating, and pin V

PLL multiplication ratio select bits (Note 2)

00: Do not select. 01: Double 10: Triple 11: Quadruple

Fix this bit to “0”.

System clock select bit (Note 3)

0: fX

1: f

PLL

Peripheral device’s clock select bits 1, 0 See Table 16.

CONT

is invalid.

Address

At reset

CONT

is invalid (floating state).

CONT

is valid.

Fig. 99 Bit configuration of clock control register

76543210 0 0

Note:

Writing to these bits requires the following procedure:

• Write “55

• Succeedingly, write “0” or “1” to each bit.

Also, use the MOVM (MOVMB) instruction or STA (STAB, STAD) instruction

” to this register. (The bit status does not change only by this writing.)

Particular function select register 0

STP instruction invalidity select bit (Note) 0: STP instruction is valid. 1: STP instruction is invalid.

External clock input select bit (Note) 0: Oscillation circuit is active. (Oscillator is connected.) Watchdog timer is used at stop mode termination. 1: Oscillation circuit is inactive. (External clock is input.) When the system clock select bit = “0”, watchdog timer is not used at stop mode termination. When the system clock select bit = “1”, watchdog timer is used at stop mode termination.

Fix this bit to “0”.

Fig. 100 Bit configuration of particular function select register 0

Address

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MITSUBISHI MICROCOMPUTERS

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

STANDBY FUNCTION

The standby function provides the stop (hereafter called STP) and the wait (hereafter called WIT) mode. These modes are used to save the power dissipation of the system, by stopping oscillation or system clock in the case that the CPU needs not be operating. The microcomputer enters the STP or WIT mode by executing the STP or WIT instruction, and either mode is terminated by acceptance of an interrupt request or reset. To terminate the STP or WIT mode by an interrupt request, the interrupt to be used for termination of the STP or WIT mode must be enabled in advance to execution of the STP or WIT instruction. The interrupt priority level of this interrupt is required to be higher than the processor interrupt priority level (IPL) of the routine where the STP or WIT instruction will be executed. Figures 100 to 102 show the bit configurations of the particular function select registers 0, 1, and watchdog timer frequency select register respectively. Setting the STP instruction invalidity select bit (bit 0 of the particular function select register 0) to “1” invalidates the STP instruction, and the STP instruction will be ignored. Since the above bit is cleared to “0” after reset is removed, however, the STP instruction is valid. The STP- or the WIT-instruction-execution status bit (bit 0 or 1 of the particular function select register 1) is set to “1” by the execution of the STP or the WIT instruction, and so, after the STP or WIT mode has been terminated, each bit will indicate that the STP or WIT instruction has been executed. Accordingly, each of these bits must be cleared to “0” by software at termination of the STP or the WIT mode. T able 17 explains the microcomputer’s operation in the STP and WIT modes. The external bus fixation function can also be provided. This function enables the user to specify the states of the external bus and the bus control signals in the memory expansion and the microprocessor mode in the STP or WIT mode. For more information, refer to the section on the power saving function.

STP mode

The execution of the STP instruction stops the oscillation circuit and PLL circuit. It also stops input clock fXIN, system clock fsys,

CPU, and peripheral devices’ clocks f1 to f4096, Wf32 and Wf512 in

the “L” state, and divide clocks fX16 to fX128 in the “H” state. In the watchdog timer, “FFF16” is automatically set. As shown in Figure 98, any one of divide clocks fX16 to fX128, which is selected by the watchdog timer clock source select bits at STP termination (bits 6 and 7 of the watchdog timer frequency select register), becomes the watchdog timer’s clock source. In the STP mode, the A-D converter and watchdog timer, which uses peripheral devices’ clocks f1 to f4096, Wf32 and Wf512, are stopped. At this time, timers A and B operate only in the event counter mode, and serial I/O communication is active while an external clock is selected. The STP mode is terminated by acceptance of an interrupt request or reset, and the oscillation circuit and PLL circuit restart their operations. Input clock fXIN, system clock fsys, and peripheral devices’ clocks f1 to f4096, Wf32 and Wf512 are also supplied. When the STP mode is terminated by reset, supply of

starts immediately after the oscillation circuit and PLL circuit restart their operations. Therefore, the reset input must be raised “H” after the operation-stabilizing time for these circuits has passed. The following two modes are available in order to terminate the STP mode by an interrupt: (1) The watchdog timer is used in order to measure the period from

the operation restart of the oscillation circuit and PLL circuit until the supply start of

(2) The supply of

BIU and φCPU.

BIU and φCPU is started immediately after the op-

eration restart of the oscillation circuit and PLL circuit. When the external clock input select bit (bit 1 of the particular function select register 0) = “0” or the system clock select bit (bit 5 of the clock control register) = “1”, the watchdog timer will start counting

BIU,

BIU and φCPU

Table 17. Microcomputer’s operation in STP and WIT modes

Mode

System clock stop select bit at WIT

Oscillation circuit

PLL circuit

Operations of function while WIT, STP modes

sys

, φ1,

to f

4096

, Wf

512

BIU

, φ

CPU

Peripheral devices using f

Timers A, B: Operation is enabled only in the event

counter mode.

STP

—

Stopped

(“L”)

Stopped

(“L”)

Stopped

(“L”)

Serial I/O: Operation is enabled only while an external

clock is selected. A-D converter: Stopped. (Watchdog timer: Stopped.)

“0”

Active

(Note 1)

Active

(Note 2)

Active

Stopped

(“L”)

Stopped

(“L”)

Timers A, B, Serial I/O, A-D converter: Operation is enabled.

(Watchdog timer: Stopped.) Timers A, B: Operation is enabled only in the event

WIT

“1”

Active

(Note 1)

Active

(Note 2)

Stopped

(“L”)

Stopped

(“L”)

Stopped

(“L”)

Serial I/O: Operation is enabled only while an external

counter mode.

clock is selected. A-D converter: Stopped. (Watchdog timer: Stopped.)

Notes 1: When the external clock input select bit = “1”, the oscillation circuit stops. Also, clock input from pin X

2: When the PLL operation enable bit = “0”, the PLL circuit stops.

is available.

to f

4096

, Wf32, Wf

512

Page 96

M37902FCCHP, M37902FGCHP, M37902FJCHP

down with one of the above divide clocks, fX16 to fX128, after the oscillation circuit and PLL circuit have been restarted their operations owing to an interrupt. The most significant bit of the watchdog timer reaching “0”, supply of On the other hand, when the external clock input select bit = “1 ” and the system clock select bit = “0”, supply of immediately after the oscillation circuit has been restarted their operations owing to an interrupt. (In actual fact, after the selected one of the above divide clocks, fX16 to fX128, has been changed from “H” to “L”, this supply will restart.)

BIU and φCPU restarts.

BIU and φCPU will restart

MITSUBISHI MICROCOMPUTERS

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

76543210

Particular function select register 1

STP-instruction-execution status bit (Note 1)

0: Normal operation. 1: STP instruction has been executed.

WIT-instruction-execution status bit (Note 1)

0: Normal operation. 1: WIT instruction has been executed.

Standby state select bit

0: External bus 1: Programmable I/O port

System clock stop select bit at WIT (Note 2)

0: In wait mode, system clock f 1: In wait mode, system clock f

Address output select bit

0: Address changes depending on bus access. 1: Address changes only at access to external address.

Timer B2 clock source select bit In event counter mode:

0: Clock input from pin TB2

32 (f(XIN)/32) is counted.

1: fX

Notes 1: At power-on reset, this bit becomes “0”. At hardware reset or software reset, this bit

retains the value just before reset. Even when “1” is written, the bit status will not change.

2: Setting this bit to “1” must be performed just before execution of the WIT instruction.

Also, after the wait state is terminated, this bit must be cleared to “0” immediately.

Address

sys is active. sys is stopped.

IN is counted.

Fig. 101 Bit configuration of particular function select register 1

76543210

Watchdog timer frequency select register

Watchdog timer frequency select bit

Watchdog timer clock source select bits at STP termination

Fig. 102 Bit configuration of watchdog timer frequency select register

0 : Select Wf 1 : Select Wf32

0 0 : fX 0 1 : fX16 1 0 : fX128 1 1 : fX64

512

Address

Page 97

M37902FCCHP, M37902FGCHP, M37902FJCHP

WIT mode

When the WIT instruction is executed with the system clock stop select bit at WIT (bit 3 of the particular function select register 1 in Figure 101) being “0”, stopped in the “L“ state. However, the oscillation circuit, PLL circuit, input clock fXIN, system clock fsys, f1 to f4096 remain operating. Therefore, BIU and CPU are stopped, whereas timers A and B, serial I/O, and the A-D converter, which use the peripheral devices’ clocks f1 to f4096, are still operating. Note that the watchdog timer is stopped. On the other hand, when the WIT instruction is executed with the system clock stop select bit at WIT being “1”, the oscillation circuit, PLL circuit, and input clock fXIN are operating, while system clock fsys,

BIU, φCPU, and peripheral devices’ clocks stop operating. As a

result, the A-D converter and watchdog timer, which use peripheral devices’ clocks f1 to f4096, Wf32 and Wf512, are stopped. At this time, timers A and B operate only in the event counter mode, and serial I/O communication is active only while an external clock is selected. If the internal peripheral devices are not used in the WIT mode, the latter is better because the current dissipation is more saved. Note that the system clock stop select bit at WIT is to be set to “1” immediately before execution of the WIT instruction and cleared to “0” immediately after the WIT mode is terminated. The WIT state is terminated by acceptance of an interrupt request, and then, supply of circuit, PLL circuit, and clock input fXIN are operating in the WIT mode, an interrupt processing can be executed just after the WIT mode termination.

BIU, φCPU, and divide clocks Wf32 and Wf512 are

1, and peripheral devices’ clock

BIU and φCPU will restart. Since the oscillation

MITSUBISHI MICROCOMPUTERS

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

POWER SAVING FUNCTION

The following functions can save the power dissipation of the whole system.

(1) External bus fixation in standby state

By setting the standby state select bit (bit 2 of the particular function select register 1) to “1”, in the stop or wait mode, the I/O pins of the external buses and bus control signals can be switched to programmable I/O port pins. By setting these pins’ state with the corresponding port registers and port direction registers, unnecessary current will not flow between the microcomputer and external devices. As a result, in the stop or wait mode, the power dissipation of the whole system can be lowered. Table 18 lists the correspondence between the external buses, bus control signals, and programmable I/O port pins. This function is valid only in the stop or wait mode. At termination of the stop or wait mode, the original function of external buses and bus control signals become valid.

Table 18. Correspondence between external buses, bus control sig-

nals, and programmable I/O port pins

External buses, Bus control signals

A0 to A7,

to A15,

to A

to D7,

to D

A D D RD, BLW, BHW CS

Note: When the external data bus width = 8 bits (BYTE = VCC level),

this becomes a programmable I/O port pin, regardless of the standby state select bit’s contents.

Standby state select bit

to A7,

to A15,

A A

to A

D0 to D7,

to D15 (Note)

RD, BLW, BHW (Note)

P100 to P107,

to P117,

P11

to P0

P10 to P17,

to P2

P31, P32, P3

mode, owing to an interrupt request occurrence. Therefore, an instruction can be executed just after the termination of the stop mode. For details, refer to the section on the clock generating circuit and standby function.

(4) Disconnection from pin VREF

When not using the A-D converter and D-A converter, by setting the VREF connection select bit (bit 6 of the A-D control register 1) to “1”, the resistor ladder network of the A-D converter will be disconnected from the reference voltage input pin (VREF). In this case, no current flows from pin VREF to the resistor ladder network, and the power dissipation can be saved. Note that, after the VREF connection select bit changes from “1” (VREF disconnected) to “0” (VREF connected), be sure that a waiting time of 1 µs of more has passed before the A-D conversion starts. For details, refer to the sections on the A-D converter and D-A converter.

(5) Address output selection

In the memory expansion mode or microprocessor mode, when the address output select bit (bit 4 of the particular function select register 1) becomes “1”, the unnecessary change of address pins’ state will be avoided, without output of an address at access to the internal area. For details, refer to the section on the BIU.

(2) Stop of system clock in wait mode

In the wait mode, if the internal peripheral devices need not to operate, the system clock stop select bit at WIT (bit 3 of the particular function select register 1) = “1”, both of system clock fsys and peripheral devices’ clock stop their operations, and the power dissipation can be saved. For details, refer to the section on the standby function.

(3) Stop of oscillation circuit

When an externally-generated-stable clock is input to pin XIN, the power dissipation can be saved if both of the following conditions are met:

• the external clock input select bit (bit 1 of the particular function select register 0) = “1”.

• the oscillation driver between pins XIN and XOUT stops its operation.

At this time, the output level at pin XOUT is fixed to “H”. When not using a PLL output clock, also, the supply of their operations just after the microcomputers returns from the stop

BIU and φCPU restarts

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

DEBUG FUNCTION

When the CPU fetches an instruction code, an interrupt request will be generated if a selected condition is satisfied, as a resultant of comparison between a specified address and the start address where the instruction code is stored (the contents of PG and PC). The decision whether this condition is satisfied or not is called address matching detection, and the interrupt generated by this detection is called an address matching detection interrupt. (For interrupt vector addresses, refer to the section on interrupts.) In the address matching detection, a non-maskable interrupt routine is proceeded without execution of the original instruction which has been allocated to the target address. The debug function provides the following two modes:

• the address matching detection mode, which is used to avoid the

area where program exists or modify a program.

• the out-of-address-area detection mode, which is used to detect a

program runaway. Figures 103 shows the block diagram of the debug function. Figures 104 and 105 show the bit configurations of the debug control registers 0, 1, and address compare registers 0,1, respectively. The detect condition select bits of the debug control register 0 can select one condition between the following 4 conditions. When the selected address condition is satisfied, an address matching detection interrupt request will be generated: (1) Address matching detection 0

The contents of PG and PC match with the address which has

been set in the address compare register 0. (2) Address matching detection 1

The contents of PG and PC match with the address which has

been set in the address compare register 1. (3) Address matching detection 2

The contents of PG and PC match with the address which has

been set in either of the address compare register 0 or address

compare register 1. (4) Out-of-address-area detection

The contents of PG and PC are less than the address which has

been set in the address compare register 0 or larger than the address which has been set in the address compare register 1.

By setting the detect enable bit of the debug control register 0 to “1”, an address matching detection interrupt request will be generated if any one of the above address conditions is satisfied. Clearing the detect enable bit to “0” generates no interrupt request even if any of the above address conditions is satisfied. The address compare register access enable bit of the debug control register 1 must be set to “1” by the instruction just before the access operation (read/write). Then, this bit must be cleared to “0” (disabled) by the next instruction. While this bit = “0”, the address compare registers 0, 1 cannot be accessed. The address-matching-detection 2 decision bit of the debug control register 1 decides, whether the address which has been set in the address compare register 0 or 1 matches with the contents of PG, PC, when the address matching detection 2 is selected. The contents of this bit is invalid when address matching detection 0 or 1 is selected. In order to use the debug function to avoid the area where program exists or modify a program, perform the necessary processing within an address matching interrupt routine. As a result, the contents of PG, PC, PS at acceptance of an address matching detection interrupt request (i.e. the address at which an address matching detection condition is satisfied) have been pushed on to the stack. If a return destination address after the interrupt processing is to be altered, rewrite the contents of the stack, and then return by the RTI instruction. To use the debug function to detect a program runaway, set an address area where no program exists into the address compare registers 0 and 1 by using the out-of-address-area detection. When the CPU fetches instruction codes from this address area and executes them, an address matching detection interrupt request will be generated. The above debug function cannot be evaluated by a debugger, so that the debug function must not be used while a debugger is running.

Address compare register 0 Address compare register 1

Matching • Compare register Matching • Compare register

Fig 103. Block diagram of debug function

Internal data bus (DB0 to DB15)

CPU bus (Address)

Debug control register 0

Debug control register 1

Address matching detect circuit

Address matching detection interrupt

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

76543210 1

76543210 0

010

Address

Debug control register 0

Detect condition select bits (Note 1)

000: Do not select. 001: Address matching detection 0 010: Address matching detection 1 011: Address matching detection 2 100: Do not select. 101: Out-of-address-area detection 110: Do not select. 111: Do not select

Fix this bit to “0” (Note 1).

Detect enable bit (Note 1)

0: Detection disabled. 1: Detection enabled.

Fix this bit to “0” (Note 1).

“1” at read.

Debug control register 1

Fix this bit to “0” (Note 1). “0” at read (Note 1). Address compare register access enable bit (Note 2)

0: Disabled

1: Enabled Fix this bit to “1” when using the debug function. Fix this bit to “0” (Note 1). While debugger is not used, “0” at read.

While debugger is used, “1” at read. Address-matching-detection 2 decision bit

❈ Valid when address matching detection 2 is selected.

0: Matches with the contents of the address compare register 0.

1: Matches with the contents of the address compare register 1. “0” at read.

Notes 1: At power-on reset, these bits = “0”; at hardware reset or software reset, these bits retain

the value just before reset.

2: Set this bit to “1” with the instruction just before the address compare register 0, 1

(addresses 68 just after the access.

16 to 6D16) is accessed. And then, clear this bit to “0” with the instruction

Fig. 104 Bit configuration of debug control register 0, 1

(23)

(16)

(15)

The address to be detected (in other words, the start address of instruction) is set here.

(8)

Fig. 105 Bit configuration of address compare register 0, 1

100

Address compare register 0 Address compare register 1

Address

, 6916, 6A

6B16, 6C16, 6D

Datasheet M37902FCCHP, M37902FJCHP, M37902FGCHP Datasheet (Mitsubishi)

Specifications and Main Features

Frequently Asked Questions

User Manual

DESCRIPTION

DISTINCTIVE FEATURES

APPLICATION

M37902FxCHP PIN CONFIGURATION (TOP VIEW)

BLOCK DIAGRAM

FunctionsParameter

BASIC FUNCTION BLOCKS

MEMORY

CENTRAL PROCESSING UNIT (CPU)

BANK

DIRECT PAGE

Instruction Set

BUS INTERFACE UNIT

BIU structure

PROCESSOR MODES

Chip select wait controller

INTERRUPTS

Key Input Interrupt

TIMER

TIMER A

TIMER B

SERIAL I/O PORTS

ASYNCHRONOUS SERIAL COMMUNICATION

A-D CONVERTER

A-D conversion accuracy

A-D conversion frequency

Operation mode

D-A CONVERTER

REAL-TIME OUTPUT

Precautions for real-time output function

WATCHDOG TIMER

How to disable watchdog timer

INPUT/OUTPUT PINS

RESET CIRCUIT

OSCILLATION CIRCUIT

CLOCK GENERATING CIRCUIT

STANDBY FUNCTION

STP mode

WIT mode

POWER SAVING FUNCTION

DEBUG FUNCTION