Datasheet M36WT864TF, M36WT864BF Datasheet (SGS Thomson Microelectronics)

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64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory

and 8 Mbit (512K x16) SRAM, Multiple Memory Product

FEATURES SUMMARY

■ SUPPLY VOLTAGE

–V –V –V

■ ACCESS TIME: 70, 85, 100ns

■ LOW POWER CONSUMPTION

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h – Top Device Code, M36WT864TF: 8810h – Bottom Device Code, M36W T864 BF : 8811h

FLASH MEMORY

■ PROGRAMMING TIME

– 8µs by Word typical for Fast Factory Program – Double/Quad ruple Word P rogram option – Enhanced Factory Pro gram options

■ MEMORY BLOCKS

– Multiple Bank Memory Array: 4 Mbit Banks – Parameter Blocks (Top or Botto m locati o n )

■ DUAL OPERATIONS

– Program Erase in one Bank while Read in

– No delay between Read and Write operations

■ BLOCK LOCKING

– All blocks locked at Power up – Any combination of blocks can be locked –WP

■ SECURITY

– 128 bit user programmable OTP cells – 64 bit unique device number – One parameter block permanent ly lockable

■ COMMON FLASH INTERFACE (CFI)

■ 100,000 PROGRAM/ERASE CYCL ES per

BLOCK

= 1.65V to 2.2V

DDF

= V

DDS

= 12V for Fast Program (optional)

PPF

= 2.7V to 3.3V

DDQF

others

for Block Lock-Down

M36WT864TF

M36WT864BF

PRODUCT PREVIEW

SRAM

■ 8 Mbit (512K x 16 bit)

■ EQUAL CYCLE and ACCESS TIMES: 70ns

■ LOW STANDBY CURRENT

■ LOW V

■ TRI-STATE COMMON I/O

■ AUTOMATIC POWER DOWN

Figure 1. Packages

DATA RETENTION: 1.5V

DDS

FBGA

Stacked LFBGA96 (ZA)

8 x 14mm

July 2002

This is preliminary information on a new product now in development. Details are subject to change without notice.

1/92

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M36WT864TF, M36WT864BF

TABLE OF CONTENTS

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. LFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Address Inputs (A0-A18). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Address Inputs (A19-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Flash Chip Enable (EF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Flash Output Enable (GF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Flash Write Enable (WF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Flash Write Protect (WPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Flash Reset (RPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Flash Latch Enable (LF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Flash Clock (KF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Flash Wait (WAITF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SRAM Chip Enable (E1S, E2S). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SRAM Write Enable (WS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SRAM Output Enable (GS).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SRAM Upper Byte Enable (UBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SRAM Lower Byte Enable (LBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

DDF

and V

DDQF

Program Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

PPF

SSF ,VSSQF

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

DDS

and V

Grounds.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

SSS

FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 2. Main Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Flash Memory Componen t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

SRAM Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 3. Flash Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4

Figure 5. Flash Block Add re sse s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

FLASH BUS OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Address Latch.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

FLASH COMMAND INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

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Table 4. Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

COMMAND INTERFACE - STANDARD COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Read Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Read Electronic Signature Comma nd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7

Clear Status Regist e r Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7

Bank Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8

Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Program/Erase Suspend Comm and . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Program/Eras e Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Protection Regi ste r Pr o g ra m Comman d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Set Configuratio n Regi ste r Comman d. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Block Lock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Block Lock-Down Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 5. Flash Standard Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 6. Electronic Signature Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figu r e 6 . Flash Security Bl o c k and Pr o tection Re g ister M e mory M a p . . . . . . . . . . . . . . . . . . . . . . 22

COMMAND INTERFACE - FACTORY PROGRAM COMMANDS. . . . . . . . . . . . . . . . . . . . . . . . . 23

Double Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Quadruple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Enhanced Factory Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Setup Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Program Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Verify Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Exit Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Quadruple Enhanced Factory Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Setup Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Load Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Program and Verify Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Exit Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 7. Flash Facto ry Pr o g ra m Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

FLASH STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Program/Erase Controller Status Bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Erase Suspend Status Bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Erase Status Bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Program Status Bit (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Status Bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

PPF

Program Suspend Status Bit (SR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Block Protection Status Bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8

Bank Write/Multiple Word Program Status Bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 8. Flash Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

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FLASH CONFIGURATION REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Read Select Bit (CR15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

X-Latency Bits (CR13- CR1 1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Wait Polarity Bit (CR10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Data Output Configura tion Bit (CR9). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Wait Configurat ion Bit (CR8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Burst Type Bit (CR7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Valid Clock Edge Bit (CR6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Wrap Burst Bit (CR3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Burst length Bits ( CR2- CR0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 9. Flash Confi g u ra tion Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 10. Burs t Type Def ini tion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 7. X-Latency and Dat a Outpu t Confi g u ra tion Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 8. Wait Configura tion Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

FLASH READ MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Asynchronous Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Synchronous Burst Read Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Single Synchronous Read Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

FLASH DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE. . . . . . . . . . . . . . . . . . . . . . 36

Table 11. Dual Oper at ions Allowed In Other Bank s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 12. Dual Operations Allowed In Same Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

FLASH BLOCK LOCKING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Reading a Block’s Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Unlocked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Lock-Down State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Locking Operatio n s Durin g Erase Su sp e nd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 13. Flash Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

FLASH PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES. . . . . . . . . . . . . . . . . . . . . . . 39

Table 14. Flash Program, Erase Times and Endurance Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

SRAM OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Standby/Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 15. Absolu te Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4/92

Page 5

M36WT864TF, M36WT864BF

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 16. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 9. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 10. AC Measure men t L o ad Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 17. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 18. Flas h DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 19. Flash DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 20. SRAM DC Character istics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Figure 11. Flash Asynchronous Random Access Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . 45

Figure 12. Flash Asynchronous Page Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 21. Flash Asynchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 13. Flash Synchronous Burst Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 14. Flash Single Synchronous Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 15. Flash Clock input AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 22. Flash Synchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 16. Fla sh Wri te AC Wavefo r ms, Wri te Enabl e Contro lled . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 23. Flas h Write AC Charac te r i stics, Write Enable Contro l led . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 17. Flash Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 24. Flash Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 18. Fla sh Reset and Po we r- u p AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 25. Flas h Reset and Power-up AC Characteristi c s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 19. SRAM Address Controlled, Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Figure 20. SRAM Chip Enable or Output Enable Controlled, Read AC Waveforms. . . . . . . . . . . . 56

Figure 21. SRAM Chip Enable or UBS/LBS Controlled, Standby AC Waveforms . . . . . . . . . . . . . 57

Table 26. SRAM Read and Standby AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 22. SRAM Write AC Waveforms, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 23. SRAM Write AC Waveforms, Chip Enable Contro l led . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 24. SRAM Write AC Waveforms, UB/LB Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 27. SRAM Write AC Chara cte ristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 25. SRAM Low VDD Data Retention AC Waveform s, E1S Control l e d. . . . . . . . . . . . . . . . . 61

Figure 26. SRAM Low VDD Data Retention AC Waveform s, E2 S Control led. . . . . . . . . . . . . . . . . 61

Table 28. SRAM Low VDD Data Retention Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 27. Stacked LFBGA96 - 8x14mm, 8x10ball array, 0.8mm pitch, Bottom View Package Outline 62

Table 29. Stacked LFBGA96 - 8x14mm, 8x10 ball array, 0.8mm pitch, Package Mechanical Data62

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 30. Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 31. Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

APPENDIX A. FLASH BLOCK ADDRESS TABLES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5/92

Page 6

M36WT864TF, M36WT864BF

Table 32. Flash Top Boot Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 33. Flash Bottom Boot Block Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

APPENDIX B. FLASH COMMON FLASH INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 34. Query Stru cture Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Table 35. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Table 36. CFI Query System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 37. Device Geome try Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Table 38. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 39. Protection Register Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Table 40. Burst Read Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 41. Bank and Erase Block Region Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 42. Bank and Erase Block Region 1 Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 43. Bank and Erase Block Region 2 Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

APPENDIX C. FLASH FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 28. Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 29. Double Word Program Flowchart and Pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 30. Quadruple Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 31. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 79

Figure 32. Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 33. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 34. Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 35. Protection Register Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 83

Figure 36. Enhanced Factory Program Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Enhanced Factory Program Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 37. Quadruple Enhanced Factory Program Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Quadruple Enhanced Factory Program Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

APPENDIX D. FLASH COMMAND INTERFACE STATE TABLES. . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 44. Command Inte rface States - Modify Tab l e , Next Sta te. . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 45. Command Interface States - Modify Tab l e , Next Outpu t. . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 46. Command Inte rface States - Lock Table, Next State . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 47. Command Interface States - Lock Table, Next Output . . . . . . . . . . . . . . . . . . . . . . . . . . 91

6/92

Page 7

SUMMARY DESCRIPTION

The M36WT864 is a low voltage M ultiple Me mory Product which combines two memory devices ; a 64 Mbit Multiple Bank Flash memory and an 8 Mbit SRAM. Recommended operating conditions do not allow both the F lash and the S RAM t o be active at the same time.

The memory is offered in a Stacked LFBGA96 (8 x 14mm, 0.8 mm pitch) package and is supplied with all the bits erased (set to ‘1’).

M36WT864TF, M36WT864BF

Table 1. Signal Names

A0-A18 Address Inputs A19-A21 Address Inputs for Flash Chip only DQ0-DQ15 Data Input/Output V V

DDF

DDQF

Flash Power Supply Flash Power Supply for I/O Buffers

Figure 2. Logic Diagram

DDQF

DDF

A0-A21

RPF

WPF

E1S E2S

UBS

LBS

M36WT864TF M36WT864BF

PPF

DDS

DQ0-DQ15

WAITF

PPF

SSF

SSQF

DDS

SSS

NC Not Connected Internally DU Do Not Use as Internally Connected

Flash control functions

LF EF GF WF RPF WPF KF Flash Burst Clock WAITF Wait Data in Burst Mode

SRAM control function s

Flash Optional Supply Voltage for Fast Program & Erase

Flash Ground Flash Ground for I/O Buffers SRAM Power Supply SRAM Ground

Latch Enable input Chip Enable input Output Enable input Write Enable input Reset input Write Protect input

SSF

SSQF

SSS

AI06270

, E2S Chip Enable inputs

E1S GS WS UBS LBS

Output Enable input Write Enable input Upper Byte Enable input Lower Byte Enable input

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Page 8

M36WT864TF, M36WT864BF

Figure 3. LFBGA Connections (Top view through package)

87654321

NCNC

A21KF

NCV

A9V

A10A20

A14A8

WAITF

E2SV

DDF

LFWPFNCA7

WFRPUBSA6

DQ5DQ10DQ2DQ8

DDS

SSF

DQ13

A19A18

NCLBS

NCA17

SSS

PPF

A11

A12

A13

A15

A16

8/92

E1S

SSS

SSQF

DQ1DQ0

DUDU

DDQF

DQ3

DDS

DDF

DQ12

DQ4DQ11DQ9GF

DDS

SSS

SSQF

DQ7DQ14

DQ15DQ6

DDQF

SSF

SSS

AI06271

Page 9

SIGNAL DESCRIPTIONS

See Figure 2 Logic Diagram and T able 1,Signal Names, for a brief overview of the signals connected to this de vice.

Address Inputs (A0-A18). Addresses A0-A18 are common inputs for the Flash an d the SRAM components. The Address Inputs select the cells in the memory array to access during Bu s Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. The Flash memory is accessed through the Chip Enable ( Enable (WF

) signals, while the SRAM is accessed through two Chip Enable signals (E1S and the Write Enable signal (WS

EF) and Write

and E2S)

Address Inputs (A19-A21). Addresses A19-A21 are inputs for the Flash component only. The Flash memory is acc essed through the Chip E nable (EF

) and Write Enable (WF) signals.

Data Input/Output (DQ0-DQ15). The Data I/O outputs the data stored at the selected address during a Bus Read operation or inputs a command or the data to be programmed durin g a Write Bus operation.

Flash Chip Enable (EF

). The Chip Enable input

activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at V tive mode. When Chip Enable is at V

andReset is at VIH the device is in ac-

the memory is deselected, the outputs are high impedance and the power consumption is reduced to the stand-b y l e v el.

Flash Output Enable (GF

). The Output Enable

controls data outputs during the Bus Read operati on of the memo ry.

Flash Write Enable (

WF). The Write Enable

controls the Bus Write operation of the memory’s Command Interface. The data and address inputs are latched on the rising ed ge of Chip Enable or Write Enable whichever occurs first.

Flash Write Protect (WPF

). Write Protect is an

input that gives an additional hardware protection for each block. When Write Protect is at V

, the Lock-Down is enabled and the protection status of the Locked-Down blocks cannot be changed. When Write Protect is at V

, the Lock-Down is

disabled and the Locked-Down blocks can be locked or unlocked. (refer to Table 13, Lock Status).

Flash Reset (RPF

). The Reset input provides a

hardware reset of the memory. When Re set is at V

, the memory is in reset mode: the outputs are

high impedance and the current consumption is reduced to the Reset Supply Current I

. Refer to

DD2

Table 2, DC Characteristics - Currents for the value of I

After Reset all blocks are in the Locked

DD2.

state and the Configuration Register is reset.

M36WT864TF, M36WT864BF

When Reset is at V eration. Exiting reset mode the device enters asynchronous read mod e, but a negative transition of Chip Enable or Lat ch E nable is required to ensure valid data outputs.

The Reset pin can be interfaced with 3V logic without any additional circuitry . It can be t ied to V (refer to Table 19, DC Characteristics).

Flash Latc h En abl e (LF

the address bits on its rising edge. The address latch is transparent when Latch Enable is at V and it is inhibited when Latch Enable is at VIH. Latch Enable can be kept Low (also at board level) when the Latch Enable function is not required or supported.

Flash Clock (KF). The clock input synchronizes the Flash memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, acc ording to the configuration settings) when L atch Enable is at VIL. Clock is don't care during asynchronous read and in write operations.

Flash Wait ( WAITF). Wait is a Flash output signal used during synchronous read to indicate whether the data on the output bus are valid. This output is high impedance when Flash Chip Enable is at V or Flash Reset is at VIL. It can be configured to be active during the wait cycle or one clock cycle in advance. The WAITF signal is not gated by Output Enable.

SRAM Chip Enable (E1S

able inputs activate the SRAM memory control logic, input buffers and decoders. E1S E2S at V

deselects the memory and reduces the

power consumption to the standby level. E1S E2S can also be used to control writing to the SRAM memory array, while WS is not allowed to set EF

at the same time.

at V

SRAM Write Enable (WS

put controls writing to the SRA M memory array. WS

is active low.

SRAM Output Enable (GS)

gates the outputs through the data buffers during a read operation of t he S RAM mem ory. GS tive low.

SRAM Upper Byte Enable (UBS)

Byte Enable input enables the upper byte for SRAM (D Q8-D Q15). U BS

SRAM Lower Byte Enable (LBS

Byte Enable input enables the lower byte for SRAM (DQ0- D Q 7). L BS

Supply Voltage. V

DDF

supply to the internal core of the Flash memory de-

, the device is in normal op-

). Latch Enable latches

, E2S). The Chip En-

at VIH or

remains at V

at V

E1S at VIL and E2S

IL,

). The Write Enable in-

. The Output Ena ble

is ac-

. The Upper

is active low .

). The Lower

is active low.

provides the power

DDF

RPH

and

IL.

9/92

Page 10

M36WT864TF, M36WT864BF

vice. It is the main power supply for all Flash operations (Read, Program and Erase).

DDQF

and V

Supply Voltage. V

DDS

DDQF

provides the power supply for the Flash mem ory I/O pins and V

provides the power supply for the

DDS

SRAM control and I/O pins. This allows all Outputs to be powered independently from t he Flash core power supply, V

DDF

. V

can be tied to V

DDQF

DDS

it can use a separate supply.

Program Supp ly Vol tage. V

PPF

is both a

PPF

Flash control input and a Flash power supply pin. The two functions are selected by the voltage range applied to the pin.

is kept in a low voltage range (0V to V

If V

PPF

is seen as a control input. In this case a volt-

PPF

age lower than V

gives an absolute protec-

PPLKF

tion against program or erase, while V

PPF

> V

DDQF

PP1F

enables these functions (s ee Tables 18 and 19, DC Characteristics for the relevant values). V

PPF

is only sampled at the b eginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue.

If V

is in the range of V

PPF

supply pin. In this condition V

it acts as a power

PPHF

must be stable

PPF

until the Program/Erase algorithm is completed.

SSF ,VSSQF

and V

SSS

and V

are the ground references for all voltage

Grounds. V

SSS

SSF

measurements in the Flash (core and I/O Buffers) and SRAM chips, respectively.

Note: Each device in a system should have

and V

DDF

capacitor close to the pin (high frequency, in-

)

decoupled with a 0.1µF ceramic

PPF

herently low inductance ca pacitors should b e as close as possible to the package). See Figure 10, AC Measurement Load Circuit. The PCB trace widths shou ld be sufficien t to ca rry the required V

program and erase currents.

PPF

, V

SSQF

10/92

Page 11

FUNCTIONAL DESCRIPTION

The Flash and SRAM components have separate power supplies and grounds and are distinguished by three chip enable inputs: EF ory and, E1S

and E2S for the SRAM.

for the Flash mem-

Recommended operating conditions do not allow both the Flash and the SRAM to be in active mode at the same time. The most common example is

Figure 4. Func ti onal Block Di a gram

M36WT864TF, M36WT864BF

simultaneous read operations on the Flash and the SRAM which would resul t in a data bus contention. Therefore it is recommended to put the SRAM in the h igh impedance state whe n reading the Flash and vice versa (see Table 2 Main Operation Modes for details).

RPF

WPF

WAITF

A19-A21

A0-A18

E1S E2S

UBS

LBS

DDF

Flash Memory

64 Mbit (x16)

DDS

8 Mbit (x 16)

DDQF

SRAM

SSQF

PPF

SSF

DQ0-DQ15

SSS

AI06272

11/92

Page 12

M36WT864TF, M36WT864BF

Table 2. Main Operation Modes

Operation Mode EF GF WF LF RPF WAITF E1S E2S GS WS UBS, LBS DQ15-DQ0

Bus Read Bus Write Address

Latch

ILVILVIH

ILVIHVIL V

(2)

SRAM must be disabled Data Output SRAM must be disabled Data Input

SRAM must be disabled

Data Output

or Hi-Z

(3)

Output Disable

Flash Memory

Standby

ILVIHVIH

XX X

Reset X X X X

Hi-Z Any SRAM mode is allowed Hi-Z Hi-Z Any SRAM mode is allowed Hi-Z

Read Flash must be disabled

Write Flash must be disabled

Standby/ Power Down

SRAM

Data

Any Flash mode is allowable

Retention Output

Disable

Note: 1. X = Don' t care.

can be tied to VIH if the valid address has been previously latched.

2. L

3. Depends on G

4. WAIT signal pol arity is conf i gured using t he Set Confi guration Register command.

Any Flash mode is allowable

SRAM must be disabled Hi-Z

VIHVILV

X X X X Hi-Z

X X X Hi-Z

XXXX

X X X Hi-Z

VIHVIHV

X Hi-Z

Data out

Word Read

Data in

Word Write

Hi-Z

12/92

Page 13

M36WT864TF, M36WT864BF

Flash Memory Component

The Flash memory is a 64 Mbit (4Mbit x16) nonvolatile Flash memory that may be erased electrically at block level and programmed in-system on a Word-by-Word basis using a 1.65V to 2.2V V supply for the circuitry and a 1.65V to 3.3V V

DDQ

supply for the Input/Output pins. An optional 12V V

power supply is provided to s peed up cus-

PPF

tomer programming. The device features an asymmetr ical block archi-

tecture with an array of 135 blo cks divided into 4 Mbit banks. There are 15 banks each containing 8 main blocks of 32 KWords, and one parameter bank containing 8 parameter blocks of 4 KWords and 7 main blocks of 32 KWords. The Multiple Bank Architecture allows Dual Operations, while programming or erasing in one bank, Read operations are possible in other banks. Only one bank at a time is allowed to be in Program or Erase mode. It is possible to perform burst reads that cross bank boundaries. The bank architecture is summarized in Table 3, and the memory maps are shown in Figure 5. The Parameter Blocks are located at the top of t he m em ory ad dres s s pace f or the M36WT864TF, and at the bottom for the M36WT864BF.

Each block can be erased separately. Erase can be suspended, in order to perform program in any other block, and then resum ed. Program can be suspended to read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles using the supply voltage V

. There are two Enhanced Factory

programming commands available to speed up programming.

Program and Erase command s are written to the Command Interface of the memory. An internal Program/Erase Controller takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards.

The device supports synchronous burst read and asynchronous read from all blocks of the me mory array; at power-up the device is configured for asynchronous read. In synchronous burst mode, data is output on each clock cycle at frequencies of up to 54MHz.

The device features an Aut oma tic Standby m ode. During asynchronous read operations, after a bus inactivity of 150ns, the device automatically switches to the Automatic Standby m ode. In this condition the power consumption is reduced to the standby value I

and the outputs are still driven.

DD4

The Flash memory features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When V

PPF

≤ V

all blocks are protected

PPLK

against program or erase. All blocks are locked at Power- Up.

The device includes a Protection Re gister and a Security Block to increase the protectio n of a s ystem’s design. The Protection Register is divided into two segments: a 64 bit segment c ontaining a unique device number written by ST, and a 128 bit segment One-Time-Programmable (OTP) by the user. The user programmable segment can be permanently protected. The Security Block, parameter block 0, can be permanently protected by the user. Figure 6, shows the Security Block and Protection Register Memory Map.

SRAM Comp onent

The SRAM is an 8 Mbit (512Kb x16) asynchronous random access memory which features a super low voltage operation and low current consumption with an access time of 70ns. The memory operations can be performed using a single low voltage supply, 2.7V to 3.3V.

13/92

Page 14

M36WT864TF, M36WT864BF

Table 3. Flash Bank Architecture

Number Bank Size Parameter Blocks Main Blocks

Parameter Bank 4 Mbits 8 blocks of 4 KWords 7 blocks of 32 KWords

Bank 0 4 Mbits - 8 blocks of 32 KWords Bank 1 4 Mbits - 8 blocks of 32 KWords Bank 2 4 Mbits - 8 blocks of 32 KWords

----

Bank 13 4 Mbits - 8 blocks of 32 KWords Bank 14 4 Mbits - 8 blocks of 32 KWords

Figure 5. Flash Block Addresses

Top Boot Block

Address lines A21-A0

Bank 14

Bank 2

Bank 1

Bank 0

Parameter

Bank

000000h

007FFFh

038000h

03FFFFh

300000h

307FFFh

338000h

33FFFFh

340000h

377FFFh

378000h

37FFFFh

380000h

387FFFh

3D8000h

3BFFFFh

3C0000h

3C7FFFh

3F0000h 3F7FFFh 3F8000h

3F8FFFh

3FF000h

3FFFFFh

32 KWord

4 KWord

----

8 Main Blocks

7 Main Blocks

8 Parameter

Blocks

Parameter

Bank

Bank 0

Bank 1

Bank 2

Bank 14

----

000000h

000FFFh

007000h

007FFFh

008000h

00FFFFh

038000h

03FFFFh

040000h

047FFFh

078000h

07FFFFh

080000h

087FFFh

0B8000h

0BFFFFh

0C0000h

0C7FFFh

0F8000h

0FFFFFh

3C0000h

3C7FFFh

3F8000h

3FFFFFh

Bottom Boot Block

Address lines A21-A0

4 KWord

4KWord

32 KWord

----

8 Parameter

Blocks

7 Main Blocks

8 Main Blocks

14/92

AI06273

Page 15

FLASH BUS OPERATIONS

There are six standard bus operations that control the Flash device. These are Bus Read, Bus Write, Address Latch, Ou tput Disable, Standby and Reset. See Table 2, Main Operating Modes, for a summary.

Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect Bus Write operations.

Bus Read. Bus Read operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the Common Flash Interface. Both Chip Enable and Output Enable must be at V

in order to perform a

read operation. The Chip Enable input should be used to enable the device. Out put Enable should be used to gate data onto the output. The data read depends on the previous command written to the memory (see Command Interface section). See Figures 11, 12, 13 and 14 Read AC Waveforms, and Tables 21 and 22 Read AC Characteristics, for details of when the output becomes valid.

Bus Write. Bus Write operations write Commands to the memory or latch Input Data to be programmed. A bus write operation is initiated when Chip Enable and Write Enable are at V Output Enable at V

. Commands, Input Data and

with

Addresses are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. The addresses can also be latched prior to the write operation by toggling Latch E nable. In this case

M36WT864TF, M36WT864BF

the Latch Enable shoul d be t ied to V bus write operation.

See Figures 16 and 17, Write AC Waveforms, and Tables 23 and 24, Write AC Characteristics, for details of the timing requirements.

Address Latch. Address latch operations input valid addresses. Both Chip enable and Latch Enable must be at V

during address latch opera-

tions. The addresses are latched on the rising edge of Latch Enable.

Output Disa bl e . The outputs are high impedance when the Output Enable is at V

Standby. Standby di sables most of the internal circuitry allowing a substantial reduction of the current consumption. The memory is in stand-by when Chip Enable and Reset are at V er consumption is reduced to the stand-by level and the outputs are s et to high impedan ce, independently from the Output Enable or Write Enable inputs. If Chip Enable switches to V gram or erase operation, the device enters Standby mode when finished.

Reset. During Reset mode the memory is deselected and the outputs are high impedance. The memory is in Reset mode when Reset is at V The power consumption is reduced to the Standby level, independently from the Chip Enable, Output Enable or Write Enable inputs. If Reset is pulled to V

during a Program or Erase, this operation is

aborted and the memory content is no longer valid.

during the

. The pow-

during a pro-

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M36WT864TF, M36WT864BF

FLASH COMMAND INTERFACE

All Bus Write operations t o the me mory are in terpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles all timings and verifies the correct execution of the Program and Erase commands. The Program/Erase Controller provides a Status Regi ster whose output may be read at any ti me to monitor the progress or the result of the operation.

The Command Interface is reset to read mode when power is first applied, when exiting from Reset or whenever V mand sequences must be followed exactly. Any invalid combination of commands will reset the device to read mode.

Refer to Table 4, Command C odes and Appendix D, Tables 44, 45, 46 and 47, Command I nterface States - Modify and Lock Tables, for a summary of the Command Interface.

The Command Interface is split into two type s of commands: Standard commands and Factory Program commands. The following sections explain in detail how to perform each command.

is lower than V

LKO

. Com-

Table 4. Command Codes

Hex Code Command

01h Block Lock Confirm 03h Set Configuration Register Confirm 10h Alternative Program Setup 20h Block Erase Setup 2Fh Block Lock-Down Confirm 30h Enhanced Factory Program Setup 35h Double Word Program Setup 40h Program Setup 50h Clear Status Register 56h Quadruple Word Program Setup

Block Lock Setup, Block Unlock Setup,

60h

70h Read Status Register

75h

80h Bank Erase Setup 90h Read Electronic Signature

Block Lock Down Setup and Set Configuration Register Setup

Quadruple Enhanced Factory Program Setup

98h Read CFI Query B0h Program/Erase Suspend C0h Protection Register Program

Program/Erase Resume, Block Erase

D0h

FFh Read Array

Confirm, Bank Erase Confirm, Block Unlock Confirm or Enhanced Factory Program Confirm

16/92

Page 17

COMMAND INTERFACE - STANDARD COMMANDS

The following commands are the basic commands used to read, write to and configure the device. Refer to Table 5, Standard Commands, in conjunction with the following text descriptions.

Read Array Command

The Read Array command re turns the addressed bank to Read Array mode. One Bus Write cycle is required to issue the Read Array command and return the addressed bank to Read Array mode. Subsequent read operations will read the addressed location and output t he data. A Read Array command can be issued in one bank while programming or erasing in another bank. However if a Read Array command is issued to a bank currently executing a Program or Erase operation the command will be e xecuted but the output da ta is not guaranteed.

Read Status Register Command

The Status Register indi cates when a Program or Erase operation is complete and the success or failure of operation itself. Issue a Read Status Register command to read the Status Register content. The Read Status Register com man d c an be issued at any time, even during Program or Erase operations.

The following read operations output the content of the Status Register of the addressed bank. The Status Register is latched on the falling edge of E or G signals, and c an b e read until E or G returns to V

. Either E or G must be toggled to update the

latched data. See Table 8 for the description of the Status Register Bits. This mode supports asynchronous or single synchronous reads only.

Read Electronic Signature Command

The Read Electronic Signature command reads the Manufacturer and Device Codes, the Block Locking Status, the Protection Register, and the Configuration Register.

The Read Electronic Signature command consists of one write cycle to an address within one o f the banks. A subsequent Read ope ra tion in the sam e bank will output the Manufacturer Code, the Device Code, the protection Status of the blocks in the targeted bank, the Protection Register, or the Configuration Register (see Table 6).

If a Read Electronic Signature command is issued in a bank that is executing a Program or Erase operation the bank will go into Read Electronic Signature mode, subsequent Bus Read cycles will output the Electronic Sign ature data an d the Program/Erase controller will continue t o program or erase in the background. This mode supports asynchronous or single synchronous reads only, it does not support page mode or synchronous burst reads.

M36WT864TF, M36WT864BF

Read CFI Query Command

The Read CFI Query command is used to read data from the Common Flash Interface (CFI). The Read CFI Query Command consists of one Bus Write cycle, to an address within one of the banks. Once the command is issued subsequent Bus Read operations in the sam e bank read from the Common Flash Interface.

If a Read CFI Query command is issued in a bank that is executing a Program or Erase operation the bank will go into Read CFI Query mo de, subsequent Bus Read cycles will output the CFI data and the Program/Erase con troller will continue to Program or Erase in the background. This m ode supports asynchronous or single synchronous reads only, it does not support page mode or synchronous burst reads.

The status of the other banks is not affected by the command (see Table 11). After issuing a Read CFI Query command, a Read Array command should be issued to t he address ed bank to return the bank to Read Array mode.

See Appendix C, Common Flash Interface, Tables 34, 35, 36, 37, 38, 40, 41, 42 and 43 for details on the information contained in the Common Flash Interface memory area.

Clear Status Register Command

The Clear Status Register comm and can be used to reset (set to ‘0’) error bits 1, 3, 4 and 5 in the Status Register. One bus write cycle is required to issue the Clear Status Register command. After the Clear Status Register command the bank returns to read mode.

The error bits in the Status Regi ster do not automatically return to ‘0’ when a new command is issued. The error bits in the Status Register should be cleared before attempting a new Program or Erase command.

Block Erase Command

The Block Erase com mand can be used to erase a block. It sets all the bits within the selected block to ’1’. All previous data in the b lock is lost. If the block is protected then the Erase operation will abort, the data in the block will not be changed and the Status Register will output the error. The Block Erase command can be issued at any moment, regardless of whether the block has been programmed or not.

Two Bus Write cycles are required to issue the command.

■ The first bus cycle sets up the Erase command.

■ The second latches the block address in the

internal state machine and starts the Program/ Erase Controller.

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M36WT864TF, M36WT864BF

If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits 4 and 5 are set and the command aborts. Erase aborts if Reset turns to

. As data integrity cannot be guaranteed when

the Erase operation is aborted, the block m ust be erased again.

Once the command is issued the device outputs the Status Register data when any address within the bank is read. At the end o f the operation the bank will remain in Read Status Register mode until a Read Array, Read CFI Query or Read Electronic Signature command is issued.

During Erase operations the bank containing the block being erased will only accept the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend command, all other commands will be ignored. Refer to Dual Operations section for detailed information about simultaneous operations allowed in banks not being e rased. Typical Erase times are given in Table 14, Program, Erase Times and Program/Erase Endurance Cycles.

See Appendix C, Figure 32, Block Erase Flowchart and Pseudo Code, for a suggested flowchart for using the Block Erase command.

Bank Erase Command

The Bank Erase command can be used to erase a bank. It sets all the bits within the selected bank to ’1’. All previous data in the bank is lost. The B ank Erase command will igno re any protected blocks within the bank. If all blocks in the bank are protected then the Bank Erase operation will abort and the data in the bank wi ll not b e changed. The Status Register will not output any error.

Two Bus Write cycles are required to issue the command.

■ The first bus cycle sets up the Bank Erase

command.

■ The second latches the bank address in the

internal state machine and starts the Program/ Erase Controller.

If the second bus cycle is not Write Bank Erase Confirm (D0h), Status Register bits SR4 and S R5 are set and the command aborts. Erase aborts if Reset turns to V

. As data integrity cannot be

guaranteed when the Erase operation is aborted, the bank must be erased again.

Once the command is issued the device outputs the Status Register data when any address within the bank is read. At the end o f the operation the bank will remain in Read Status Register mode until a Read A rray, Read CFI Query o r Read Electronic Signature command is issued.

During Bank Erase operations the bank being erased will only accept the Read Array, Read Status Register, Read Electronic Signature and Read

CFI Query command, all other commands will be ignored. A Bank Erase operation ca nnot be suspended.

Refer to Dual Operations section for detailed information about simultaneous operations allowed in banks not being erased. Typical Erase times are given in Table 14, Program, Erase Times and Program/Erase Endurance Cycles.

Program Command

The memory array can be programmed word-byword. Only one Word in one bank can be programmed at any one time. Two bus write cycles are required to issue the Program Command.

■ The first bus cycle sets up the Program

command.

■ The second latches the Address and the Data to

be written and starts the Program/Erase Controller.

After programming has started, read operations in the bank being programmed output the Status Register content.

During Program operations the bank being programmed will only accept the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspen d command. Refer to Dual Operations section for detailed information about simultaneous operations allowed in banks not bei ng programmed. Typical Program times are given in Table 14, Program, Erase Times and Program/Erase Endurance Cycles .

Programming aborts if Reset goes to V

. As data

integrity cannot be guaranteed when the program operation is aborted, the memory location must be reprogrammed.

See Appendix C, Figure 28, Program Flowchart and Pseudo Code, for the f lowchart for using the Program command.

Program/Erase Suspend Command

The Program/Erase Suspend command is used to pause a Program or Block Erase operation. A Bank Erase operation cannot be suspended.

One bus write cycle is required to issue the P rogram/Erase command. O nce the Program/Erase Controller has paused bits SR7, SR6 and/ or SR2 of the Statu s Regist er will be s et to ‘1’. Th e command can be addressed to any bank.

During Program/Erase Suspend the Command Interface will accept the Program/Erase Resume, Read Array (cannot read the suspended block), Read Status Register, Read Electronic S ignature and Read CFI Q uery commands. Additionally, if the suspend operation was Erase then the Clear status Register, Program, Block Lock, Block LockDown or Block Unlock commands will also be accepted. The block being erased may be protected

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M36WT864TF, M36WT864BF

by issuing the Block Lock, Block Lock-Down or Protection Register Program commands. Only the blocks not being erased may be read or programmed correctly. When the Program/Erase Resume command is issued the operation will complete. Refer to the Dual Operations section for detailed information about simultaneous operations allowed during Program/Erase Suspend.

During a Program/Erase Suspend, the device can be placed in standby mode by taking Chip Enable

. Program/Erase is aborted if Reset turns to

to V

See Appendix C, Figure 31 , Program Suspend & Resume Flowchart and Pseudo Code, and Figure 33, Erase Suspend & Resume Flowchart and Pseudo Code for flowcharts for using the Program/ Erase Suspend command.

Program/Erase Resume Command

The Program/Erase Resume command can be used to restart the Program/Erase Controller after a Program/Erase Suspen d command has paused it. One Bus Write cycle is required to issue the command. The command can be written to any address.

The Program/Erase R esume command d oes not change the read m ode of the banks. If the s uspended bank was in Read Status Register, Read Electronic signature or Read CFI Query mode the bank remains in that m ode and outputs the corresponding data. If the bank was in Read Array mode subsequent read operations will output invalid data.

If a Program command is issued during a Block Erase Suspend, then the erase cannot be resumed until the programming operation has completed. It is possible to accumulate suspend operations. For example: suspend an eras e operation, start a programming operation, suspend the programming operation then read the array. See Appendix C, Figure 31, Program Susp end & Resume Flowchart and Pseudo Code, and Figure 33, Erase Suspend & Resume Flowchart and Pseudo Code for flowcharts for using the Program/Erase Resume command.

Prot e ction R e gister P rogram C om m and

The Protection Register Program command is used to Program the 128 bit user O ne-Time-Programmable (OTP) segment of the Protection Register and the Protection Register Lock. The segment is programmed 16 bits at a time. When shipped all bits in the segment are set to ‘1’. The user can only program the bits to ‘0’.

Two write cycles are required to issue the Protection Register Program command.

■ The first bus cycle sets up the Protection

■ The second latches the Address and the Data to

be written to the Protection Register and starts the Program/Erase Controller.

Read operations output the Status Register content after the programming has started.

The segment can be protected by programming bit 1 of the Protection Lock Register. Bit 1 of the Protection Lock Register also protects bit 2 of the Protection Lock Register. Programming bit 2 of the Protection Lock Register will result in a permanent protection of Parameter B lock #0 (see Figure 6, Security Block and Protection Register Memory Map). Attempting to program a previously protected Protection Register will result in a Status Register error. The protection of the Protection Register and/or the Security Block is not reversible.

The Protection Register Program cannot be suspended. See Appendix C, Figure 35, Protection Register Program Flowchart and Pseudo Code, for a flowchart for using the Protection Register Program command.

Set Configuration Regi s te r C om m and.

The Set Configuration Register command is used to write a new value to the Burst Configuration Control Register which defines the burst length, type, X latency, Synchronous/Asynchronous Read mode and the valid Clock edge configuration.

Two Bus Writ e cycle s are required to issue th e Se t Configuration Register command.

■ The first cycle writes the setup command and

the address corresponding to the Configuration Register content.

■ The second cycle writes the Configuration

Once the command is issued the memory returns to Read mode.

The value for the Configuration Register is always presented on A0-A15. CR0 is on A0, C R1 on A1, etc.; the other address bits are ignored.

Block Lock Command

The Block Lock command is used to lock a block and prevent Program or Erase operations from changing the data in it. All blocks are locked at power-up or reset.

Two Bus Write cycles are required to issue the Block Lock command.

■ The first bus cycle sets up the Block Lock

command.

■ The second Bus Write cycle latc hes the blo ck

address.

The lock status can be monitored for each block using the Read Electronic Signature command. Table. 13 shows the Lock Status after issuing a Block Lock command.

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M36WT864TF, M36WT864BF

The Block Lock bits are volatile, once set they remain set until a hardware reset or power-down/ power-up. They are cleared by a Block Unlock command. Refer to the section, Block Locking, for a detailed explanation. See Appendix C, Figure 34, Locking Operations Flowchart and Pseudo Code, for a flowchart for using the Lock command.

Block Unlock Command

The Block Unlock command is used to unlock a block, allowing the block to be programmed or erased. Two Bus Write cycles are requ ired to issue the Block Unlock command.

■ The first bus cycle sets up the Block Unlock

command.

■ The second Bus Write cycle latc hes the blo ck

address.

The lock status can be monitored for each block using the Read Electronic Signature command. Table 13 shows the protection status after issuing a Block Unlock command. Refer to the section, Block Locking, for a detailed expla nation and A ppendix C, Figure 34, Locking Operations Flowchart and Pseudo Code, f or a flowchart for using the Unlock command.

Block Lock-Down Command

A locked or unlocked block can be locked-down by issuing the Block Lock-Down command. A lockeddown block cannot be programm ed or erased, or have its protection status changed when WP low, V

. When WP is high, V

the Lock-Down

IH,

function is disabled and the lock ed blocks can be individually unlocked by the Block Unlock command.

Two Bus Write cycles are required to issue the Block Lock-Down command.

■ The first bus cycle sets up the Block Lock

command.

■ The second Bus Write cycle latc hes the blo ck

address.

The lock status can be monitored for each block using the Read Electronic Signature command. Locked-Down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. Table. 13 shows the Lo ck Statu s after issuing a Block Lock-Down command. Refer to the section, Block Locking, for a detailed explanation and Appendix C, Fi gure 34, Locking Operations Flowchart and Pseudo Code, for a flowchart for using the Lock-Down command.

20/92

Page 21

Table 5. Flash Standard Commands

M36WT864TF, M36WT864BF

Bus Operations

Commands

Cycles

Read Array 1+ Write BKA FFh Read St atus Register 1+ Write BKA 70h Read Read Electro nic Signature 1+ Write BKA 90h Read Read CFI Query 1+ Write BKA 98h Read Clear Status Register 1 Write BKA 50h

Block Erase 2 Write BKA 20h Write BA D0h Bank Erase 2 Write BKA 80h Write BKA D0h Program 2 Write BKA 40h or 10h Write WA PD Program/Erase Suspend 1 Write X B0h Program/Erase Resume 1 Write X D0h Protection Register Program 2 Write PRA C0h Write Set Configuration Register 2 Write CRD 60h Write Block Lock 2 Write BKA 60h Write Block Unlock 2 Write BKA 60h Write Block Lock-Down 2 Write BKA 60h Write

Note: 1. X = Don't Care, WA=Word Address in targeted bank, RD=Read Data, SRD=Status Register Data, ESD=Electronic Signature Data,

QD=Query Dat a, BA=Bl ock Address, BK A= Ban k Address , PD= Program Data, PR A=Prot ectio n Regist er Addre ss, PRD =Prote ction Register Dat a, CRD=Configurat ion Regist er Data.

2. Must be same bank as in the first cycle. The signatur e addresses are listed in Table 6.

Op. Add Data Op. Add Data

1st Cycle 2nd Cycle

Read

WA RD

(2)

BKA

(2)

BKA

(2)

BKA

PRA

CRD 03h

BA 01h BA BA

SRD ESD

PRD

D0h 2Fh

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M36WT864TF, M36WT864BF

Table 6. Electronic Signature Codes

Code Address (h) Data (h)

Manufacturer Code Bank Address + 00 0020

Device Code

Top Bank Address + 01 8810 Bottom Bank Address + 01 8811 Lock

0001

Unlocked 0000

Block Protection

Block Address + 02

Locked and Locked-Down 0003

Unlocked and Locked-Down 0002 Reserved Bank Address + 03 Reserved Configuration Register Bank Address + 05 CR

ST Factory Default

0006

Security Block Permanently Locked 0002 Protection Register Lock

OTP Area Permanently Locked 0004

Security Block and OTP Area Permanently

Locked

Bank Address + 80

Bank Address + 81 Bank Address + 84

0000

Unique Device

Number

Protection Register

Bank Address + 85 Bank Address + 8C

Note: CR=Con figuration Register.

OTP Area

Figure 6. Flash Security Block and Protection Register Memo ry Ma p

22/92

SECURITY BLOCK

Parameter Block # 0

8Ch

85h 84h

81h 80h

PROTECTION REGISTER

User Programmable OTP

Unique device number

Protection Register Lock 2 1 0

AI06181

Page 23

COMMAND INTERFACE - FACTORY PROGRAM COMMANDS

The Factory Program commands are used to speed up programming. They require V V

. Refer to Table 7, Factory Program Com-

PPH

PPF

to be at

mands, in conjunction with the following text descrip tion s.

Double Word Program Command

The Double Word Program command improves the programming throughput by writing a page of two adjacent words in parallel. The two words must differ only for the address A0.

Programming should not be attempted when V is not at V V

is below V

PPF

. The command can be executed if

PPH

but the result is not guaran-

PPH

PPF

teed . Three bus write cycles are necessary to issue the

Double Word Program command.

■ The first bus cycle sets up the Double Word

Program Command.

■ The second bus cycle latches the Address and

the Data of the first word to be written.

■ The third bus cycle latches the Address and the

Data of the second word to be written and starts the Program/Erase Controller.

Read operations in the bank bei ng programmed output the Status Register content after the programming has started.

During Double Word Program operations the bank being programmed will only ac cept the Read Array, Read Status Register, Read Electronic Signature and Read CFI Query command, all other commands will be ignored. Dual operations are not supported during Double Word Program operations and it is not recommended to suspend a Double Word Program operation. Typical Program times are given in Table 14, Program, Erase Times and Program/Erase Endurance Cycles.

Programming aborts if Reset goe s to V

. As data

integrity cannot be guaranteed when the program operation is aborted, the memory locations mu st be reprogrammed.

See Appendix C, Figure 29, Double Word Program Flowchart and Pseudo Code, for the flowchart for using the Double Word Program command.

Quadruple Word Program Command

The Quadruple Word Program command improves the programming throughput by writing a page of four adjacent words in parallel. The four words must differ only for the addresses A0 and A1.

Programming should not be attempted when V is not at V V

is below V

PPF

. The command can be executed if

PPH

but the result is not guaran-

PPH

PPF

teed .

Five bus write cycles are necessary to issue the Quadruple Word Program command.

■ The first bus cycle sets up the Double Word

Program Command.

■ The second bus cycle latches the Address and

the Data of the first word to be written.

■ The third bus cycle latches the Address and the

Data of the second word to be written.

■ The fourth bus cycle latches the Address and

the Data of the third word to be written.

■ The fifth bus cycle latches the Ad dr es s and th e

Data of the fourth word to be written and starts the Program/Erase Controller.

Read operations to the bank being programmed output the Status Register content after the programming has started.

Programming aborts if Reset goes to V integrity cannot be guaranteed when the program operation is aborted, the memory locations m ust be reprogrammed.

During Quadruple Word Program operations the bank being programmed will only accept the Read Array, Read Status Register, Read Electronic Signature and Read CFI Query command, all other commands will be ignored.

Dual operations are not supported during Quadruple Word Program operations and it is not recommended to suspend a Quadrupl e Word Program operation. Typical Program times are given in Table 14, Program, Erase Times and Program/Erase Endurance Cycles.

See Appendix C, Figure 30, Quadruple Word Program Flowchart and Pseudo Code, for the flowchart for using the Quadruple Word Program command.

Enhanced Factory Program Command

The Enhanced Factory Program command can be used to program large streams of dat a within any one block. It greatly reduces the total programming time when a large number of Words are written to a block at any one time.

The use of the Enha nced Factory Program command requires certain operating conditions.

■ V

■ Ambient temperature, T

■ The targeted block must be unlocked

must be set to V

PPF

must be within operating range

Dual operations are not s upported during the Enhanced Factory Program operation an d the command cannot be suspended.

For optimum performance the Enhanc ed Factory Program commands should be limited to a maximum of 10 program/erase cycles per block. If this

M36WT864TF, M36WT864BF

. As data

PPH

must be 25°C ± 5°C

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M36WT864TF, M36WT864BF

limit is exceeded the in ternal algorithm will cont inue to work properly but some degradation in performance is possible. Typical Program times are given in Table 14.

The Enhanced Factory Program command has four phases: the Setup Phase, the Program Phase to program the data to the memory, the Verify Phase to check that the data has been correctly programmed and reprogram if necessary a nd the Exit Phase. Refer to Table 7, Enhanced Factory Program Command and Figure 36, Enhanced Factory Program Flowchart.

Setup Phase. The Enhanced Factory Program command requires two Bus Write operations to initiate the command.

■ The first bus cycle sets up the Enhanced

Factory Program command.

■ The second bus cycle confirms the command.

The Status Register P/E.C. Bit 7 should be read to check that the P/E.C. is ready. After the confirm command is issued, read operations output the Status Register data. The read Status Register command must not be issued as it will be interpreted as data to program.

Program Phase. The Program Phase requires n+1 cycles, wh ere n is the n umber of Words (refer to Table 7, Enhanced Factory Program Command and Figure 36, Enhanced Factory Program Flowchar t).

Three successive steps are required to issue and execute the Program Phase of the command.

1. Use one Bus Write operation to latch the Start Address and the first Word to be programmed. The Status Register Bank Write Status bit SR0 should be read to check that the P/E.C. is ready for the next Word.

2. Each subsequent Word to be programmed is latched with a new Bus Write operation. The address can either remain the Start Address, in which case the P/E.C. increments the address location or the address can be incremented in which case the P/E.C. jumps to the new address. If any address that is not in the same block as the Start Address is given with data FFFFh, the Program Phase terminates and the Verify Phase begins. The Status Register bit SR0 should be read between each Bus Write cycle to check that the P/E.C. is ready for the next Word.

3. Finally, after all Words have been programmed, write one Bus Write operation with data FFFFh to any address outside the bloc k contain ing the Start Address, to terminate the programming phase. If the data is not FFFFh, the command is ignored.

The memory is now set to enter the Verify Phase.

Verify Phase. Th e Verify Phase is sim ilar to the Program Phase in that all Words must be resent to the memory for them to be che cked against the programmed data. The Program/Erase Controller checks the stream of da ta with the data that was programmed in the Program Phase and reprograms the memory location if necessary.

Three successive steps are required to execute the Verify Phase of the command.

1. Use one Bus Write operation to latch the Start Address and the first Word, to be verified. The Status Register bit SR0 should be read to check that the Program/Erase Controller is ready for the next Word.

2. Each subsequent Word to be verified is latched with a new Bus Write operation. The Words must be written in the same order as in the Program Phase. The address can remain the Start Address or be incremented. If any address that is not in the same block as the Start Address is given, the Verify Phase terminates. Status Register bit SR0 should be read to check that the P/E.C. is ready for the next Word.

3. Finally, after all Words have been verified, write one Bus Write operation with data FFFFh to any address outside the block containing the Start Address, to terminate the Verify Phase.

If the Verify Phase is successfully completed the memory returns to the Read mode. If the Pr ogram/ Erase Controller fails to reprogram a given location, the error will be signaled in the Status Register.

Exit Phase. Status Register P/E.C. bit SR7 set to ‘1’ indicates that the device has ret urned to Read mode. A full Status Register check should be done to ensure that the block has been successfully programmed. See the s ect ion on the Status Register for more details.

Quadruple Enhanced Factory Program Command

The Quadruple Enhanced Factory Program command can be used to program one or more pages of four adjacent words in parallel. The four words must differ only for the addresses A0 and A1. V must be set to V

during Quadruple Enhanced

PPH

PPF

Factory Program. It has four phases: the Setup Phase, the Load

Phase where the data is loaded into the buffer, the combined Program and Verify Phase where the loaded data is programmed to the memory and then automatically checked and reprogrammed if necessary and the Exit Phase. Unlike the Enhanced Factory Program it is not necess ary to resubmit the data for the Verify Phase. The Load Phase and the Program and Verify Phas e can be repeated to program any number of pag es within the block.

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M36WT864TF, M36WT864BF

Setup Phase. The Q uadruple Enhan ced F actory

Program command requires one Bus Write operation to initiate the load phase. After the setup command is issued, read operations output the Status Register data. Th e Read Status Register command must not be issued as it will be interpreted as data to program.

Load Phase. The Loa d Phase requires 4 cycles to load the data (refer to Table 7, Factory Program Commands and Figure 37, Qu adruple Enhanced Factory Program Flowchart). Once the first Word of each Page is written it is impossible to exit the Load phase until all four Words have been written.

Two successive steps are required to issue and execute the Load Phase of the Quadruple Enhanced Factory Program command.

1. Use one Bus Write operation to latch the Start Address and the first Word of the first Page to be programmed. For subsequent Pages the first Word address can remain the Start Address (in which case the next Page is programmed) or can be any address in the same block. If any address is given that is not in the same block as the Start Address, the device enters the Exit Phase. For the first Load Phase Status Register bit SR7 should be read after the first Word has been issued to check that the command has been accepted (bit 7 set to ‘0’). This check is not required for subsequent Load Phases. Status Register bit SR0 should be read to check that the P/E.C. is ready for the next Word.

2. Each subsequent Word to be programmed is latched with a new Bus Write operation. The address is only checked for the first Word of each Page as the order of the Words to be programmed is fixed. The Status Register bit SR0 should be read between each Bus Write

cycle to check that the P/E.C. is ready for the next Word.

The memory is now set to enter the Program and Verify Phas e .

Program and Verify Phase. In the Program and Verify Phase the four Words that were loaded in the Load Phase are programmed in the memory array and then verified by the Program/Erase Controller. If any errors are found the Program/Erase Controller reprograms the location. During this phase the Status Register shows that the Program/Erase Controller is busy, Status Register bit SR7 set to ‘0’, and that the device is not waiting for new data, Status Register bit SR0 set to ‘1’. When Status Register bit SR0 is set t o ‘0’ the Program and Verify phase has terminated.

Once the Verify Phase has successfully completed subsequent pages i n the same block can be loaded and programmed. The device returns to the beginning of the Load Phase by issuing one Bus Write operation to latch the Addres s and the first of the four new Words to be programmed.

Exit Phase. Finally, after all the pages have been programmed, write one Bus Write operation with data FFFFh to any address outside the block containing the Start Address, to terminate the Load and Program and Verify Phases.

If the Program and Verify Phase has successfully completed the memory returns to Read m ode. If the P/E.C. fails to program and reprogram a given location, the error will be signaled in the Status Register.

Status Register bit SR7 set to ‘1’ and bit 0 set to ‘0’ indicate that the device has returned to Read mode. A full Status Register check should be done to ensure that the block has been successfully programmed. See the s ect ion on the Status Register for more details.

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M36WT864TF, M36WT864BF

Table 7. Flash Factory Program Comman ds

Bus Write Operations

Command Phase

Cycles

(4)

Double Word Program Quadruple Word

Program

(5)

Enhanced

Factory

Setup, Program

3 BKA 35h WA1 PD1 WA2 PD2

+n+1BKA 30h BA D0h

Program

(6)

Verify, Exit

Setup, first Load

First

Quadruple

Enhanced

Factory

Program

(5,6)

Program & Verify

Subsequent Loads

Subsequent Program &

Automatic

Verify

Exit 1

Note: 1. WA=Word Addres s in t arget ed bank, BKA= Bank A d dress, P D=Pro gram Data , B A =Block Address .

2. WA1 is the Start Address. NOT WA1 is any address that is not in the sam e bl ock as W A1.

3. Address ca n remain Start i ng Address WA1 or be incremented.

4. Word Addresses 1 and 2 mus t be consecuti ve Addresses differing only for A0.

5. Word Addresses 1,2,3 and 4 m ust be consecutive Addresses dif fe ri ng only for A0 and A1.

6. A Bus Read m ust b e d one bet we en eac h Wr ite cyc le where t he da t a is p rog ra mmed or verif ied to rea d the St atus Reg ist er an d check that the memory is ready to accept the next data. n = number of Wo rds, i = number of Pages to be programmed .

7. Address is o nly che ck ed for the fir st Wo rd o f each Page a s the o rder t o pro gram the Wo rds i n each pag e is fixe d so subs equent Words in each Page can be written to any address.

1st 2nd 3rd Final -1 Final

Add Data Add Data Add Data Add Data Add D ata

BKA 56h WA1 PD1 WA2 PD2 WA3 PD3 WA4 PD4

NOT

WA1

NOT

WA1

WA4

WA4i

(7)

(2)

WA1

BKA 75h

WA1i

(2)

PD1

PD1i

WA2

WA1

WA2i

(7)

(3)

(2)

PD2

PD1

PD2i

WA1

WA3

WA2

WA3i

(7)

(2)

(3)

(7)

PD1

PD3

PD2

PD3i

WAn

WA3

(3)

(7)

PAn

PD3

NOT WA1

FFFFh

(2)

(7)

FFFFh

PD4

PD4i

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Page 27

FLASH STATUS REGISTER

The Flash memory contains a Status Register which provides information on the current or previous Program or Erase operations. Issue a Read Status Register command to read the contents of the Status Register, refer to Read Status Register Command section for more details. To output the contents, the Status Register is latched and updated on the falling edge of the Chip Enable or Output Enable signals and can be read until Chip Enable or Output Enable returns t o V

. The Status Reg-

ister can only be read using single asynchronous or single synchronous reads. Bus Read operations from any address within the bank, always read the Status Register during Program and Erase operations.

The various bits convey information about the status and any errors of the operation. Bits SR7, SR6, SR2 and SR0 give information on the status of the device and are set and reset by the device. Bits SR5, SR4, SR3 and SR1 give inform ation on errors, they are set by the device but must be reset by issuing a Clear Status Register command or a hardware reset. If an error bit is set to ‘1’ the Status Register should be reset before issuing another command. SR7 to SR1 refer to the status of the device while SR0 refers to the status of the addressed bank.

The bits in the Status Register are summarized in Table 8, Status Register Bits. Refer to Table 8 in conjunction with the following text descriptions.

Program/Erase Controller Status Bit (SR7).

The Program/Erase Controller Status bit indicates whether the Program/Erase Con troller is active or inactive in any bank. When the Program/Erase Controller Status bit is Low (set to ‘0’), the Program/Erase Controller is active; when the bit is High (set to ‘1’), the Program/Erase Controller is inactive, and the device is ready to process a new command.

The Program/Erase Controller Status is Low immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is High.

During Program, Erase, operations the Program/ Erase Controller Status bit can be polled to find the end of the operation. Other bits in the Status Register should not be tested until the Program/Erase Controller completes the operation and the bit is High.

After the Program/Erase Cont roller completes its operation the Erase Status, Program Status, V

PPF

Status and Block Lock Status bits should be tested for errors.

Erase Suspend Status Bit (SR6). The Erase Suspend Status bit indicates that an Erase opera-

M36WT864TF, M36WT864BF

tion has been suspended or is going to be suspended in the addressed block. When the Eras e Suspend Status bit is High (set to ‘1’), a Program/ Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command.

The Erase Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). SR7 is set within the Erase Suspend Latency time of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode.

When a Program/Erase Re sume command is issued the Erase Suspend Status bit returns Low.

Erase Status Bit (SR5). The Erase Status bit can be used to identify if the memory has failed to verify that the block or bank has erased correctly. When the Erase Status b it is High (set to ‘1’), the Program/Erase Controller has applied the maximum number of pulses to the block or bank and still failed to verify that it has erased correctly. The Erase Status bit should be read once the Program/ Erase Controller Status bit is High (Program/Erase Controller inactive).

Once set High, the Erase Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail.

Program Status Bit (SR4). The Program Status bit is used to identify a Program f ailure. Wh en t he Program Status bit is High (set to ‘1’), the Program/Erase Controller has applied the maximum number of pulses to the byte and still failed to verify that it has programmed correctly. The Program Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive).

Once set High, the Program Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail.

Status Bit (SR3). The V

PPF

be used to identify an invalid voltage o n the V pin during Program and Erase operations. The V

pin is only sampled at the beginning of a Pro-

PPF

gram or Erase operation. Indeterminate results can occur if V

becomes invalid during an oper-

PPF

ation. When the V

voltage on the V voltage; when the V ‘1’), the V

Status bit is Low (set to ‘0’), the

PPF

pin has a voltage that is below the

PPF

pin was sampled at a valid

PPF

Status bit is High (set to

PPF

Status bit can

PPF

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M36WT864TF, M36WT864BF

Lockout Voltage, V

PPF

tected and Program and Erase operations cannot be performed.

Once set High, the V

PPF

set Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail.

Program Suspend Status Bit (SR2). The Program Suspend Status bit indicates that a Program operation has been suspended in the addressed block. When the Program Suspend Status bit is High (set to ‘1’), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). SR2 is set within the Program Suspend Latency time of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode.

When a Program/Erase Re sume command is issued the Program Suspend Status bit returns Low.

Block Protection Status Bit (SR1). The Block Protection Status bit can be used to identify if a Program or Block Erase operation has tried to modify the contents of a locked block.

When the Block Protection S tatus bit is High (set to ‘1’), a Program or Erase operation has been attempted on a locked block.

, the memory is pro-

PPLK

Status bit can only be re-

Once set High, the Block Protection Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail.

Bank Wri te/Multiple Wor d Program Sta tus Bit (SR0). The Bank Write Status bit indicates wheth-

er the addressed bank is programming or erasing. In Enhanced Factory Program m ode the Multiple Word Program bit shows if a Word has finished programming or verifying depending on the phase. The Bank Write Status bit should only be considered valid when the Pro gr a m/Erase Controller Status SR7 is Low (set to ‘0’).

When both the Pro gra m/Erase Controller Status bit and the Bank Write Status bit are Low (set to ‘0’), the addressed bank is executing a Program or Erase operation. When the Program/Erase Controller Status bit is Low (set to ‘0’) and the Bank Write Status bit is High (set to ‘1’), a Program or Erase operation is being executed in a bank other than the one being addressed.

In Enhanced Factory Program mode if Multiple Word Program Status bit is Low (set to ‘0’), the device is ready for the next Word, if the Multiple Word Program Status bit is High (set to ‘1’) the device is not ready for the next Word.

Note: Refer to Appendix C, Flowcharts and Ps eudo Codes, for using the Status Register.

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M36WT864TF, M36WT864BF

Table 8. Flash Status Register Bits

Bit Name T ype Logic Level Definition

SR7 P/E.C. Status Status

SR6 Erase Suspend Status Status

SR5 Erase Status Error

SR4 Program Status Error

SR3

PPF

Status

Error

SR2 Program Suspend Status Status

SR1 Block Protection Status Error

Bank Write Status Status

SR0

Multiple Word Program Status (Enhanced

Status

Factory Program mode)

Note: Logic level '1' is High, '0' is Low.

'1' Ready '0' Busy '1' Erase Suspended '0' Erase In progress or Completed '1' Erase Error '0' Erase Success '1' Program Error '0' Program Success

V V

PPF

Invalid, Abort OK

'1' '0' '1' Program Suspended '0' Program In Progress or Completed '1' Program/Erase on protected Block, Abort '0' No operation to protected blocks

SR7 = ‘0’ Program or erase operation in addressed bank

'0'

SR7 = ‘1’ No Program or erase operation in the device

'1'

SR7 = ‘0’

Program or erase operation in a bank other than

the addressed bank SR7 = ‘1’ Not Allowed SR7 = ‘0’ the device is NOT ready for the next word

'1'

SR7 = ‘1’

Not Allowed SR7 = ‘0’ the device is ready for the next Word

'0'

SR7 = ‘1’ the device is exiting from EFP

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M36WT864TF, M36WT864BF

FLASH CONFIGURATION REGISTER

The Flash memory contains a Configuration Register which is used to configure the type of bus access that the m em ory w ill pe rform . Ref er to Rea d Modes section for details on read operations.

The Configuration Register is set through the Command Interface. After a Reset or Power-Up the device is configured for asynchronous page read (CR15 = 1). The Configu ration Register bits are described in Table 9. They spe cify the selection of the burst length, burst type, burst X latency and the Read operation. Refer to Figures 7 and 8 for examples of synchronous burst configurations.

Read Select Bit (CR15)

The Read Select bit, CR15, is used to switch between asynchronous an d sync hronous B us Read operations. When the Read Se lect bit is s et to ’1’, read operations are asynchronous; when the Read Select bit is set to ’0’, read operations are synchronous. Synchronous Burst Read is supported in both parameter and main blocks and can be performed across banks.

On reset or power-up the Read Sel ect bit is set to’1’ for asynchronous access.

X-Latency Bits (CR13-CR11)

The X-Latency bits are used during Synchronous Read operations to set the number of clock cycles between the address bei ng latched and the first data becoming available. For correct operation the X-Latency bits can only assume the values in Table 9, Configuration Register.

The correspondence be tween X-Latency settings and the maximum sustainable freq uency must be calculated taking into account some system parameters. Two conditions must be satisfied:

1. Depending on whether t

AVK_CPU

or t supplied either one of the following two equations must be satisfied:

(n + 1) t

(n + 2) tK≥ t

ACC ACC

- t

AVK_CPU

+ t

DELAY

+ t

QVK_CPU

≥ t

2. and also > t

KQV

+ t

QVK_CPU

where n is the chosen X-Latency configuration code

is the clock period

AVK_CPU

is clock to address valid, L Low, or E

Low, whichever occurs last t

is address valid, L Low, or E Low to clock,

DELAY

whichever occurs last t

QVK_CPU

is the data setup time required by the

system CPU, t

is the clock to data valid time

KQV

is the random access time of the device.

ACC

DELAY

Refer to Figure 7, X-Latency and Data Output Configuration Example.

Wait Polarity Bit (CR10)

In synchronous burst mode the W ait signal indicates whether the output data are valid or a WAIT state must be inserted. The Wait Polarity bit is used to set the po larity of the Wait signal. When the Wait Polarity bit is set to ‘0’ the Wait signal is active Low. When the Wait P ola rity bit is set to ‘ 1’ the Wait signal is active High (default).

Data Output Configuration Bit (CR9)

The Data Output Configuration bit determines whether the output remains valid for one or two clock cycles. When the Data Output Configuration Bit is ’0’ the output data is valid for one clock cycle, when the Data Output Configuration Bit is ’1’ the output data is valid for two clock cycles.

The Data Output Configuration depends on the condition:

■ t

> t

where tK is the clock period, t setup time required by the s ystem CPU and t

KQV

+ t

QVK_CPU

is the data

KQV

is the clock to data valid time. If this condition is not satisfied, the Data Output Configuration bit should be set to ‘1’ (two clock cycles). Refer to Figure 7, X-Latency and Data Output Configuration Example.

Wait Confi guration Bit (C R 8)

In burst mode the Wait bit controls the timing of the Wait output pin, WAIT. When the Wait bit is ’0’ the Wait output pin is asserted during the wait s tate. When the Wait bi t is ’1’ (default) the W ait output pin is asserted one clock cycle before the wait state.

WAIT is asserted during a continuous burst and also during a 4 or 8 burst length if no-wrap configuration is selected. WAIT is not asserted during asynchronous reads, single synchronous reads or during latency in synchronous reads.

Burst Type Bit (CR7)

The Burst Type bit is used to configure the sequence of addres ses read as sequential or interleaved. When the Burst Type bit is ’0’ the memory outputs from interleaved addresses; when the Burst Type bit is ’1’ (default) the memory outputs from sequential addresses. Se e Tables 10, Burst Type Definition, for the sequence of addresses output from a given starting address in each mode.

Valid Clock Edge Bit (CR6)

The Valid Clock Edge bit, CR6, is used to configure the active edge of the Clock, K, during Synchronous Burst Read operations. When the Valid Clock Edge bit is ’0’ the falling edge of the Clock is

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M36WT864TF, M36WT864BF

the active edge; when the V alid Clock Edge bit is ’1’ the rising edge of the Clock is active.

Wrap Burst Bit (CR3)

The burst reads can be confined inside the 4 or 8 Word boundary (wrap) or overcome the boundary (no wrap). The Wrap Burst bit is used to select between wrap and no wrap. When the Wrap Burst bit is set to ‘0’ the burst read wraps; when it is set to ‘1’ the burst read does not wrap.

Burst length Bits (CR2-CR0)

The Burst Length bits se t the n umb er of Words t o be output during a Synchronous Burst Read operation as result of a single address latch cycle. They can be set for 4 words, 8 words or continuous burst, where all the words are read sequentially.

In continuous burst mode the burs t sequ ence c an cross bank boundaries.

In continuous burst mode or in 4, 8 words no-wrap, depending on the starting add ress, the dev ice asserts the WAIT output to i ndicate that a delay is necessary before the data is output.

If the starting address is aligned to a 4 word boundary no wait states are needed and the WAIT output is not asserted.

If the starting address is shifted by 1,2 or 3 positions from the four word boundary, WAIT will be asserted for 1, 2 or 3 clock cycles when the burst sequence crosses the first 64 word b oundary, to indicate that the device needs an internal delay to read the successive words in the array. WAIT will be asserted only once during a continuous burst access. See also Table 10, Burst Type Definition.

CR14, CR5 and CR4 are reserved for future use.

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M36WT864TF, M36WT864BF

Table 9. Flash Configuration Register

Bit Description V alue Description

CR15 Read Select

CR14 Reserved

CR13-CR11 X-Latency

CR10 Wait Polarity

CR9

CR8 Wait Configuration

CR7 Burst Type

CR6 Valid Clock Edge

Data Output Configuration

0 Synchronous Read 1 Asynchronous Read (Default at power-on)

010 2 clock latency 011 3 clock latency 100 4 clock latency 101 5 clock latency 111 Reserved Other configurations reserved 0 WAIT is active Low 1 WAIT is active high (default) 0 Data held for one clock cycle 1 Data held for two clock cycles 0 WAIT is active during wait state 1 WAIT is active one data cycle before wait state (default) 0 Interleaved 1 Sequential (default) 0 Falling Clock edge 1 Rising Clock edge

CR5-CR4 Reserved

CR3 Wrap Burst

CR2-CR0 Burst Length

0 Wrap 1 No Wrap 001 4 words 010 8 words 111 Continuous (CR7 must be set to ‘1’)

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Page 33

Table 10. Burst Type Definition

Start

Address 4 Words 8 Words

Mode

Sequential Interleaved Sequential Interleaved

0 0-1-2-3 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6... 1 1-2-3-0 1-0-3-2 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 1-2-3-4-5-6-7... 2 2-3-0-1 2-3-0-1 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 2-3-4-5-6-7-8... 3 3-0-1-2 3-2-1-0 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 3-4-5-6-7-8-9...

...

7 7-4-5-6 7-6-5-4 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 7-8-9-10-11-12-13...

Wrap

... 60 60-61-62-63-64-65-66... 61 61-62-63-WAIT-64-65-66... 62 62-63-WAIT-WAIT-64-65-66...

M36WT864TF, M36WT864BF

Continuous Burst

Sequential Interleaved Sequential Interleaved

0 0-1-2-3 0-1-2-3-4-5-6-7 1 1-2-3-4 1-2-3-4-5-6-7-8 2 2-3-4-5 2-3-4-5-6-7-8-9... 3 3-4-5-6 3-4-5-6-7-8-9-10

...

7 7-8-9-10 7-8-9-10-11-12-13-14

...

No-wrap

60 60-61-62-63

61 61-62-63-WAIT-64

62-63-WAIT-

WAIT-64-65

63-WAIT-WAITWAIT-64-65-66

60-61-62-63-64-65-66-

61-62-63-WAIT-64-65-

66-67-68

62-63-WAIT-WAIT-64-

65-66-67-68-69

63-WAIT-WAIT-WAIT64-65-66-67-68-69-70

63-WAIT-WAIT-WAIT-64-65-

66...

Same as for Wrap

(Wrap /No Wrap has no effect on

Continuous Burst )

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M36WT864TF, M36WT864BF

Figure 7. X-Latency and Data Output Configura tion E x a m pl e

X-latency

1st cycle 2nd cycle 3rd cycle 4th cycle

A21-A0

tDELAY

DQ15-DQ0

Note. Settings shown: X-latency = 4, Data Output held for one clock cycle

VALID ADDRESS

tAVK_CPU tKtQVK_CPU

tACC

Figure 8. Wai t Co nf i gu r at io n E xa mple

A21-A0

VALID ADDRESS

tKQV

VALID DATA

tQVK_CPU

VALID DATA

AI06182

DQ15-DQ0

WAIT CR8 = '0' CR10 = '0'

WAIT CR8 = '1' CR10 = '0'

WAIT CR8 = '0' CR10 = '1'

WAIT CR8 = '1' CR10 = '1'

34/92

VALID DATA

VALID DATA NOT VALID VALID DATA

AI06972

Page 35

FLASH READ MODES

Flash Read operations can be performe d in two different ways depending on the settings in the Configuration Register. If the clock signal is ‘don’t care’ for the data output, the read operation is Asynchronous; if the data output is synchronized with clock, the read operation is Synchronous.

The Read mode and data output format are determined by the Configuration Register. (See Configuration Register section for details). All banks supports both asynchronous and synchronous read operations. The Multiple Bank architecture allows read operations in one bank, while write operations are being executed in anoth er (see Tables 11 and 12).

Asynchronous Read Mode

In Asynchronous Read operations the clock signal is ‘don’t care’. The device outpu ts the dat a corresponding to the address latched, that is the mem ory array, Status Register, Common Flash Interface or Electronic Signature depending on the command issued. CR15 in the Configuration Register must be set to ‘1’ for Asynchronous operations .

In Asynchronous Read mode a Page of data is internally read and stored in a Page Buffer. The Page has a size of 4 Words and is addressed by A0 and A1 address inputs. The address inputs A0 and A1 are not gated by Latch Enable in Asynchronous Read mode.

The first read operation within the Page has a longer access time (T

, Random access time),

acc

subsequent reads within the same Page have much shorter access times. If the Page changes then the normal, longer timings apply again.

Asynchronous Read operations can be performed in two different ways, Asynchronous Random Access Read and Asynchronous Page Read. Only Asynchronous Page Read takes full advant age of the internal page s torage so different t imings are applied.

See Table 21, Asynchronous Read AC Characteristics, Figure 11, Asynchronous Random Access Read AC Waveform and Figure 12, Asynchronous Page Read AC Waveform for details.

Synchron ous Burst Read Mode

In Synchronous Burst Read mode t he data is output in bursts synchronized with the clock. It is possible to perform burst reads across bank boundaries.

Synchronous Burst Read mode can onl y be used to read the memory array. For other read operations, such as Read Status Register, Read CFI and Read Electronic Signature, Single Synchronous Read or Asynchronous Random Access Read must be used.

M36WT864TF, M36WT864BF

In Synchronous Burst Read mode the flow o f the data output depends on param eters that are configured in the Configuration Register.

A burst sequence is started at t he first clock e dge (rising or falling depending on Valid Clock Edge bit CR6 in the Configuration Register) after the falling edge of Latch Enable. Addresses are internally incremented and after a delay of 2 to 5 clock cycles (X latency bits CR13-CR11) the corresponding data are output on each clock cycle.

The number of Words to be out put during a Synchronous Burst Read operation can be configured as 4 or 8 Words or Continuous (Burst Length bits CR2-CR0). The data can be configured to remain valid for one or two clock cycles (Data Output Configur a tion bi t C R9).

The order of the data output can be modified through the Burst Type and the Wrap Burst bits in the Configuration Register. The burst sequence may be configured to be seq uential or i nterleaved (CR7). The burst reads can be confined inside the 4 or 8 Word boundary (Wrap) or overcome the boundary (No Wrap). If the starting address is aligned to a 4 Word Page the wrapped configuration has no impact on the output sequence. In terleaved mode is not allowed in Continuous B urst Read mode or with No Wrap sequences.

A WAIT signal may be asserted to ind icate to the system that an output delay will occur. This delay will depend on the starting address of the burst sequence; the worst case delay will occur w hen the sequence is crossing a 64 word boundary and the starting address was at the end of a four word boundary.

WAIT is asserted during X latency and the Wait state and is only deasserted when output data are valid. In Continuous Burst Read mode a Wait state will occur w hen crossing the first 6 4 W ord boundary. If the burst starting address is aligned to a 4 Word Page, the Wait state will not occur.

The WAIT signal can be configured to be active Low or active High (default) by setting CR10 in the Configuration Register. The WAIT signal is meaningful only in Synchronous Burst Read mode, in other modes, WAIT is always asserted (except for Read Array mode).

See Table 22, Synchronous Read AC Characteristics and Figure 13, Synchronous Burst Read AC Waveform for details.

Single Synchronous Read Mo de

Single Synchronous Read op erations are similar to Synchronous Burst Read operations except that only the first data output after the X latency is valid. Other Configuration Register parameters have no effect on Single Synchronous Read operations.

35/92

Page 36

M36WT864TF, M36WT864BF

Synchronous Single Reads are used to read the Electronic Signature, S tatus Register, CFI, Block Protection Status, Configuration Register Status or Protection Register. When t he add ressed bank is in Read CFI, Read Status Register or Read

Electronic Signature mode, the WAIT signal is always asserted.

See Table 22, Synchronous Read AC Characteristics and Figure 14, Single Synchronous Read AC Waveform for details.

FLASH DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE

The Multiple Bank Architecture of the Flash memory provides flexibility for software developers by allowing code and data to be split with 4Mbit granularity. The Dual Operations feature sim plifies the software management of the device and allows code to be executed from on e bank whil e another bank is being programmed or erased.

The Dual operations feature means that while programming or erasing in one bank, Read operations are possible in another bank with zero latency (only one bank at a time is allowed to be in Program or Erase mode). If a Read operation is required in a bank which is programming or erasing, the Program or Erase operation can be s uspend-

then a Program command can be issued to another block, so the device can have one block in Erase Suspend mode, one programm ing and other banks in Read mode. Bus Read operations are allowed in another bank between setup an d confirm cycles of program or erase operations. The combination of these features means that read operations are possible at any moment.

Tables 11 and 12 show the dual operations possible in other banks and in the same bank. Note that only the commonly used commands are represented in these table s. For a c om plete l ist of possible commands refer to Appendix D, Command Interface State Tables.

ed. Also if the suspended operation was Erase

Table 11. Dual Operations Allowed In Other Banks

Commands allowed in another bank

Status of bank

Idle Yes Yes Yes Yes Yes Yes Yes Yes Programming Yes Yes Yes Yes – – Yes – Erasing Yes Yes Yes Yes – – Yes – Program Suspended Yes Yes Yes Yes – – – Yes Erase Suspended Yes Yes Yes Yes Yes – – Yes

Read

Array

Read

Status

Read

CFI

Query

Read Electronic Signature

Program Erase

Program/

Erase

Suspend

Program/

Erase

Resume

Table 12. Dual Operations Allowed In Same Bank

Commands allowed in same bank

Status of bank

Idle Yes Yes Yes Yes Yes Yes Yes Yes Programming

Erasing Program Suspended Erase Suspended

Note: 1. Not al l owed in the Block or Word that is being erased or programme d.

2. The Read Array command is accepted but the data output is not guaranteed unt i l the Program or Erase has com pl eted.

Read Array

(2)

–

(2)

–

(1)

Yes

(1)

Yes

Read

Status

Yes Yes Yes – – Yes – Yes Yes Yes – – Yes – Yes Yes Yes – – – Yes Yes Yes Yes

Read

CFI Query

Read

Electronic

Signature

Program Erase

Yes

(1)

––Yes

Program/

Erase

Suspend

Program/

Erase

Resume

36/92

Page 37

FLASH BLOCK LOCKING

The Flash memory features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection.

■ Lock/Unlock - this first level allows software-

only control of block locking.

■ Lock-Down - this second level requires

hardware interaction before locking can be changed.

■ V

PPF

≤ V

- the third level offers a complete

PPLK

hardware protection against program and erase on all blocks.

The protection status of each block can be set to Locked, Unlocked, and Lock-Down. Table 13, defines all of the possible protection states (WP DQ1, DQ0), and Appendi x C, Figure 34, shows a flowchart for the locking operations.

Reading a Block’s Lock Status

The lock status of every block can be read in the Read Electronic Signature mode of the device. To enter this mode write 90h t o the device. Subsequent reads at the addres s specified in Table 6, will output the p rotectio n status of that block. The lock status is represented by DQ0 and DQ1. DQ 0 indicates the Block Lock/Unlock s tatus and is set by the Lock comm and and cleared by the Unlock command. It is also autom atically set when en tering Lock-Down. DQ1 indicates the Lock-Down status and is set by the Lock-Down command. It cannot be cleared by software, only by a hardware reset or power-down.

The following sections explain the operation of the locking system.

Locked State

The default status of all blocks on power-up or after a hardware reset is Locked (states (0,0,1) or (1,0,1)). Locked blocks are fully protected from any program or erase. Any program or erase operations attempted on a locked block will return an error in the Status Register. The Status of a Locked block can be changed to Unlocked or Lock-Down using the appropriate software commands. An Unlocked block can be Locked by issuing the Lock command.

Unlocked State

Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. All unlocked blocks return to the Locked state a ft er a hardware reset or when the device is powered-down. The status of an unlocked block can be changed to

M36WT864TF, M36WT864BF

Locked or Locked-Down using the appropriate software commands. A locked block can be unlocked by issuing the Unlock command.

Lock-Down State

Blocks that are Locked-Down (state (0,1,x))are protected from program and erase operations (as for Locked blocks) but their protection status cannot be changed using software comma nds alone. A Locked or Unlocked block can be Locked-Down by issuing the Lock-Down command. LockedDown blocks revert to the Locked state when the device is reset or powered-down.

The Lock-Down function is depen dent on the WP input pin. When WP=0 (VIL), the blocks in the Lock-Down state (0,1,x) are protected from program, erase and protection status changes. When

=1 (VIH) the Lock-Down function is disabled

WP (1,1,x) and Locked-Down blocks can be individually unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. These blocks can then be re-locked (1,1,1) and unlocked (1,1,0) as desired while WP remains high. When WP is low , blocks that were previously Locked-Down return to the Lock-Down state (0,1,x) regardless of any changes made while WP

was high. Device reset or power-down resets all blocks , including those in Lock-Down, to the Locked state.

Locking Operations During Erase Suspend

Changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. This is useful in the case when another block needs to be updated while an erase operation is in progress.

To change block locking during an erase operation, first write the Erase Suspend command, then check the status register until it indicates that the erase operation has been suspended. Next write the desired Lock com mand sequence to a block and the lock status will be changed. After completing any desired lock, read, or program operations, resume the erase operation with the Erase Resume command.

If a block is locked or l ocked-down during an erase suspend of the same block, the locking status bits will be changed immediately, b ut when the erase is resumed, the erase operation will complete. Locking operations cannot be performed du ring a program suspend. Refer to Appendix , Comm and Interface State Table, for detailed information on which commands are valid during erase suspend.

37/92

Page 38

M36WT864TF, M36WT864BF

Table 13. Flash Lock Status

Protection Status

(WP, DQ1, DQ0)

Current State

Current

Program/Erase

(1)

Allowed

After

Block Lock

Command

Next Protection Status

(WP, DQ1, DQ0)

After

Block Unlock

Command

1,0,0 yes 1,0 ,1 1,0,0 1,1,1 0,0,0

1,0,1

(2)

no 1,0,1 1,0,0 1,1,1 0,0,1

1,1,0 yes 1,1 ,1 1,1,0 1,1,1 0,1,1 1,1,1 no 1,1,1 1,1,0 1,1,1 0,1,1 0,0,0 yes 0,0 ,1 0,0,0 0,1,1 1,0,0

0,0,1

(2)

no 0,0,1 0,0,0 0,1,1 1,0,1

0,1,1 no 0,1,1 0,1,1 0,1,1

Note: 1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block) as read

in the Read El ectronic Si gnature command with A1 = V

2. All blocks ar e l ocked at power-up, so the default con figuration i s 001 or 101 according to WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.

3. A WP

and A0 = VIL.

(1)

After Block Lock-Down

Command

status.

After

transition

1,1,1 or 1,1,0

(3)

38/92

Page 39

FLASH PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES

The Program and Erase times and the number of Program/ Er as e cycles per block a r e sho wn in Ta-

of Program/ Erase cycles depends on the voltage supply used.

ble 14. In the Flash memory the maximum number

Table 14. Flash Program, Eras e Times and Enduran ce Cycl es

Parameter Condition Min Typ

Parameter Block (4 KWord) Erase

(2)

M36WT864TF, M36WT864BF

T ypical after

100k W/E

Max

Cycles

0.3 1 2.5 s

Unit

Main Block (32 KWord) Erase

Preprogrammed 0.8 3 4 s Not Preprogrammed 1.1 4 s Preprogrammed 3 s

Bank (4Mbit) Erase

Not Preprogrammed 4.5 s

Parameter Block (4 KWord) Program

= V

Main Block (32 KWord) Program

PPF

Word Program

(3)

40 ms

300 ms

10 10 100 µs

Program Suspend Latency 5 10 µs Erase Suspend Latency 5 20 µs

Main Blocks 100,000 cycles

Program/Erase Cycles (per Block)

Parameter Blocks 100,000 cycles

Parameter Block (4 KWord) Erase

0.3 2.5 s Main Block (32 KWord) Erase 0.9 4 s Bank (4Mbit) Erase 3.5 s Bank (4Mbit) Program (Quad-Enhanced Factory Program)

t.b.a.

(4)

4Mbit Program Quadruple Word 510 ms

PPH

Word/ Double Word/ Quadruple Word Program

= V

Parameter Block (4 KWord)

PPF

Program

(3)

Quadruple Word 8 ms Word 32 ms

(3)

8 100 µs

Quadruple Word 64 ms

Main Block (32 KWord) Program

(3)

Word 256 ms Main Blocks 1000 cycles

Program/Erase Cycles (per Block)

Parameter Blocks 2500 cycles

Note: 1. TA = –40 to 85°C; VDD = 1.65V to 2.2V; V

2. The differe nce betwee n Pr eprogrammed and not pr eprogrammed is not significant (‹3 0m s).

3. Excludes t he t i m e needed to execute the command sequence.

4. t.b.a. = to be announced

= 1.65V to 3.3V .

DDQ

39/92

Page 40

M36WT864TF, M36WT864BF

SRAM OPERATIONS

There are five standard operations that control the SRAM component. These are Bus Read, Bus Write, Standby/Power-down, Data Retention and Output Disable. A summary is shown in Table 2, Main Operation Modes

Read. Read operations are used to output the contents of the SRAM Array. The data is output either by x8 (DQ0-DQ7) or x16 (DQ0-DQ15) depending on which of the LBS enabled. The SRAM is in Read mode whenever Chip Enable, E2S, and Write Enable, WS V

, and Output Enable, GS, and Chip Enable E1S

are at VIL. Valid data will be available on the output pins after

a time of t

after the last stable address. If the

AVQV

Chip Enable or Output Enable ac cess times are not met, data access will be measured fro m the limiting parameter (t

ELQV

than the address. Da ta out m ay be indeterm inate at t ways be valid at t

ELQX

, t

GLQX

and t

AVQV

BLQX

and 20). Write. Write o perations are used to write data to

the SRAM. The SRAM is in Write mode whenever Write Enable, WS

, and Chip Enable, E2S, is at VIH.

, and Chip Enable, E1S, are at

Either the Chip Enable input, E1S able input, WS

, must be deasserted during ad-

dress transitions for subsequent write cycles. A Write operation is initiated when E1S

E2S is at V

and WS is at VIL. When UBS or LBS

are Low, the data is latch ed on the falling edge of E1S

, or WS, whichever occurs first.When UBS or

and UBS signals are

, are at

, t

EHQV

, or t

GLQV

) rather

, but data lines wi ll al-

(see Table 26, Figures 19

or the Write En-

is at VIL,

LBS are High, the data is latched on the falling edge of UBS

, or LBS , whichever occurs first.

The Write cycle is terminated on the ri sing edge of E1S

, WS , UBS or LBS, whichever occurs first.

If the Output is enabled (E1S GS

and UBS=LBS=VIL), then WS will return

the outputs to high imped ance within t

=VIL, E2S=VIH,

of its

WLQZ

falling edge. Care must be taken to avoid bus contention in this type of operation. The Data input must be valid for t Write Enable, for t E1S

or for t

LBS

, whichever occurs first, and remain valid for

WHDX

, t

EHDX

DVBH

and t

before the rising edge of

DVWH

before the rising edge of

DVEH

before the rising edge of UBS/

respectively.

BHDX

(see Table 27, Figure 22, 23 and 24). Standby/Power-Down . The SRAM component

has a chip enabled power-down feature wh ich invokes an automatic standby mode (see Table 26, Figure 19). The SRAM is in Standby mode whenever either Chip Enable is deasserted, E1S

at V

or E2S at VIL. Data Retention. The SRAM data retention per-

formances as V in Table 28 and Figures 25 and 26. In E1S

go down to VDR are described

DDS

controlled data retention mode, the minimum standby current mode is entered when E1S and E2S ≤ 0.2V or E2S ≥ V

≥ V

DDS

– 0.2V. In E2S

DDS

–0.2V

controlled data retention mode, m inimum st andby current mode is entered when E2S ≤ 0.2V.

Output Disa bl e . The SRAM is in the output disable state when GS

and WS are both at VIH, refer

to Table 2 for more details.

40/92

Page 41

M36WT864TF, M36WT864BF

MAXIMUM RATIN G

Stressing the device above the rating l isted in the Absolute Maximum Ratings table m ay cause permanent damage to the device. These are stress ratings only and operation of the device at t hese or any other conditions ab ove those i ndicated in t he Operating sections of this specificat ion is not im-

Table 15. Absolute Maximum Ratings

Symbol Parameter Min Max Unit

DDQF

BIAS

STG

DDF

PPF

VPPFH

/ V

Ambient Operating Temperature –40 85 °C Temperature Under Bias –40 125 °C Storage Temperature –65 155 °C Input or Output Voltage –0.5 Supply Voltage –0.2 2.45 V Input/Output Supply Voltage –0.2 3.3 V

DDS

Program Voltage –0.2 14 V Output Short Circuit Current 100 mA Time for V

PPF

at V

PPFH

plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.

Value

+0.6

DDQF

100 hours

41/92

Page 42

M36WT864TF, M36WT864BF

DC AND AC PARAMETERS

This section summarizes t he operating meas urement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement

Table 16. Operating and AC Measurement Conditions

Conditions summarized in Table 16, Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters.

SRAM F lash Memo ry

Parameter

Min Max Min Max

Supply Voltage

DDQ

Supply Voltage (Factory environment)

PPF

Supply Voltage (Application environment)

PPF

– – 1.65 2.2 V

2.7 3.3 2.7 3.3 V

11.4 12.6 V +0

-0.4

DDQ

.4 Ambient Operating Temperature – 40 85 – 40 85 °C Load Capacitance (C

)

30 30 pF Input Rise and Fall Times 2 5 ns Input Pulse Voltages Input and Output Timing Ref. Voltages

Figure 9. AC Measurement I/O Waveform

DDF

Note: V

DDF

= V

DDS

DDF

AI06110

0 to V

DDF

/2 V

DDF

Figure 10. AC Measureme nt Load Circui t

DDQF

DDF

0 to V

DEVICE

UNDER

TEST

DDQ

DDQF

16.7kΩ

Units70 70/ 85/ 100

V V

0.1µF

CL includes JIG capacitance

Table 17. Device Capacitance

Symbol Parameter Test Condition Min Max Unit

OUT

Note: Sampled o nl y, not 100% test ed.

Input Capacitance Output Capacitance

42/92

OUT

= 0V

68pF 812pF

16.7kΩ

AI06274

Page 43

M36WT864TF, M36WT864BF

Table 18. Flash DC Characteristics - Currents

Symbol Parameter Test Condition Min Typ Max Unit

Input Leakage Current

Output Leakage Current

Supply Current Asynchronous Read (f=6MHz)

Supply Current

DD1

Synchronous Read (f=40MHz)

Supply Current Synchronous Read (f=54MHz)

DD2

DD3

DD4

Supply Current (Reset)

Supply Current (Standby) Supply Current (Automatic

Standby)

Supply Current (Program)

(1)

DD5

Supply Current (Erase)

Supply Current

(1,2)

DD6

DD7

PP1

PP2

PP3

Note: 1. Sampled only, not 100% tested.

(Dual Operations)

Supply Current Program/ Erase

(1)

Suspended (Standby)

Supply Current (Program)

PPF

(1)

Supply Current (Erase)

PPF

Supply Current (Read)

PPF

(1)

Supply Current (Standby) V

PPF

Dual Operation curr ent is the sum of read and program or eras e currents.

2. V

0V ≤ V

≤ V

OUT

= VIL, G = V

DDQ

±1 µA ±1 µA

36mA

4 Word 6 13 mA 8 Word 8 14 mA

Continuous 6 10 mA

4 Word 7 16 mA 8 Word 10 18 mA

Continuous 13 25 mA

= VSS ± 0.2V

= VDD ± 0.2V

= VIL, G = V

= V

PPF

= V

PPF

= V

PPF

= V

PPF

PPH

10 50 µA

815mA

10 20 mA

815mA

10 20 mA

Program/Erase in one

Bank, Asynchron ous

13 26 mA

Read in another Bank Program/Erase in one

Bank, Synchronous

16 30 mA

Read in another Bank

= VDD ± 0.2V

= V

PPF

= V

PPF

= V

PPF

= V

PPF

= V

PPF

≤ V

PPF

≤ V

PPF

PPH

10 50 µA

25mA

0.2 5 µA 25mA

0.2 5 µA

100 400 µA

0.2 5 µA

43/92

Page 44

M36WT864TF, M36WT864BF

Table 19. Flash DC Characteristics - Voltages

Symbol Parameter Test Condition Min Typ Max Unit

V V V

PPLK

Input Low Voltage –0.5 0.4 V

Input High Voltage

Output Low Voltage

Output High Voltage

PP1

PPH

PPF

Program Voltage-Logic

Program Voltage Factory

= 100µA

= –100µA V

Program, Erase 1 1.8 1.95 V Program, Erase 11.4 12 12.6 V

–0.4 V

DDQ

–0.1

DDQ

Program or Erase Lockout 0.9 V VDD Lock Voltage

LKO

RP pin Extended High Voltage 3.3 V

RPH

+ 0.4

DDQ

0.1 V

Table 20. SRAM DC Characteristics

Symbol Parameter Test Condition Min Typ Max Unit

DD1

DD2

= 3.3V, f = 1/t

(1,2)

Operating Supply Current

(3)

Operating Supply Current

Standby Supply Current CMOS

DDS

E1 ≥ V

= 0mA

OUT

= 3.3V, f = 1MHz,

DDS

= 0mA

OUT

= 3.3V, f = 0,

DDS

–0.2V or E2 ≤ 0.2V or

DDS

LB=UB ≥ V Input Leakage Current Output Leakage Current

Input High Voltage 2.2

0V ≤ V

≤ V

OUT

AVAV

DDS

≤ V

70ns 35 mA

120µA

–0.2V

DDS

(4)

–1 1 µA –1 1 µA

4mA

DDS

0.3

Note: 1. Ave rage AC current, cycl i ng at t

Input Low Voltage –0.3 0.6 V

Output High Voltage

Output Low Voltage

2. E1

= VILAND E2 = V

3. E1

≤ 0.2V AND E2 ≥ V

4. Output disabled.

LB OR/AND UB = VIL, VIN = VIL OR VIH.

IH,

–0.2V, LB OR/AND UB ≤ 0.2V, VIN≤ 0.2V OR VIN≥ V

DDS

44/92

AVAV

minimum.

= –1.0mA

= 2.1mA

2.4 V

–0.2V.

DDS

0.4 V

Page 45

M36WT864TF, M36WT864BF

Figure 11. Flash Asynchronous Random Access Read AC Waveforms

VALID

tEHTZ

tGHQZ

tEHQZ

tEHQX

tAXQX

tGHQX

AI06275

Standby

VALID

Data Valid

VALID

A0-A21

tAVAV

tAVLH tLHAX

tLLLH

tLLQV

tLHGL

tELLH

tELQV

tELQX

tGLQV

tGLQX

tELTV

Hi-Z

WAITF

tAVQV

Valid Address Latch Outputs Enabled

Hi-Z

DQ0-DQ15

Note. Write Enable, WF, is High, WAIT is active Low.

45/92

Page 46

M36WT864TF, M36WT864BF

Figure 12. Flash Asynchronous Page Read AC Waveforms

VALID ADDRESSVALID ADDRESSVALID ADDRESS

AI06276

Standby

VALID ADDRESS

tAVAV

tLHAX

tAVLH

tLLLH

tLLQV

tLHGL

tELLH

tELQV

tELQX

tELTV

tGLQV

tAVQV1tGLQX

Valid Data

VALID DATAVALID DATA VALID DATA VALID DATA

Outputs

Valid Address Latch

Enabled

46/92

A2-A21

A0-A1

Hi-Z

(1)

WAITF

DQ0-DQ15

Note 1. WAIT is active Low.

Page 47

Table 21. Flash Asynchronous Read AC Characteristics

Symbol A lt Para meter

AVAV

AVQV

AVQV1

(1)

AXQX

ELTV

(2)

ELQV

(1)

ELQX

EHTZ

Read Timings

Latch Timings

Note: 1. Sampled only, not 100% tested.

2. G

3. To be characterized.

(1)

EHQX

(1)

EHQZ

(2)

GLQV

(1)

GLQX

(1)

GHQX

(1)

GHQZ

AVLH

ELLH

LHAX

LLLH

LLQV

LHGL

may be delayed by up to t

ACC

PAGE

OLZ

AV ADVH

ELADVH

ADVHAX

ADVLADVH

ADVLQV

ADVHGL

Address Valid to Next Address Valid Min Address Valid to Output Valid (Random) Max Address Valid to Output Valid (Page) Max Address Transition to Output Transition Min 0 0 0 ns Chip Enable Low to Wait Valid Max Chip Enable Low to Output Valid Max Chip Enable Low to Output Transition Min 0 0 0 ns Chip Enable High to Wait Hi-Z Max Chip Enable High to Output Transition Min 0 0 0 ns Chip Enable High to Output Hi-Z Max Output Enable Low to Output Valid Max 20 25 25 ns Output Enable Low to Output Transition Min 0 0 0 ns Output Enable High to Output Transition Min 0 0 0 ns Output Enable High to Output Hi-Z Max Address Valid to Latch Enable High Min 10 10 10 ns

Chip Enable Low to Latch Enable High Min 10 10 10 ns Latch Enable High to Address Transition Min 10 10 10 ns Latch Enable Pulse Width Min 10 10 10 ns Latch Enable Low to Output Valid (Random) Max Latch Enable High to Output Enable Low Min 0 0 0 ns

- t

ELQV

after the fal ling edge of E without increasing t

GLQV

M36WT864TF, M36WT864BF

M36WT864 TF/BF

70 85 10 0

(3)

ELQV

85 100 ns 85 100 ns 25 25 ns

18 18 ns 85 100 ns

20 20 ns

85 100 ns

Unit

47/92

Page 48

M36WT864TF, M36WT864BF

Figure 13. Flash Synchronous Burst Read AC Waveforms

VALID

tKHQX

tKHQV

NOT VALID

VALID

tKHQX

VALID

tEHQX

tKHQXtKHQV

tEHQZ

tEHEL

tGHQZ

tGHQX

tKHTX

tKHTX tKHTV

tEHTZ

Note 2 Note 2

Standby

Valid

Data

Boundary

Crossing

AI06277

VALID

Hi-Z

DQ0-DQ15

tKHQV

tLLLH

tAVLH

VALID ADDRESS

A0-A21

tLLKH

tAVKH

Note 1

tELKH tKHAX

tGLQX

tKHTV

tELTV

Note 2

Hi-Z

WAITF

X Latency Valid Data Flow

Address

Latch

Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register.

2. The WAIT signal can be configured to be active during wait state or one cycle before. WAIT signal is active Low.

3. Address latched and data output on the rising clock edge.

48/92

Page 49

Figure 14. Flash Single Synchronous Read AC Waveforms

M36WT864TF, M36WT864BF

AI06278

tEHTZ

NOT VALID

VALID

tEHQX

tKHQV

tEHQZ

tEHEL

tGHQX

tGHQZ

tKHTV

Note 3

Hi-Z

DQ0-DQ15

tLLLH

tAVLH

VALID ADDRESS

A0-A21

tLLKH

tAVKH

Note 1

(4)

tELKH tKHAX

tGLQX

tGLQV

tELTV

Hi-Z

(2)

WAITF

Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register.

2. The WAIT signal is configured to be active during wait state. WAIT signal is active Low.

3. WAIT is always asserted when addressed bank is in Read CFI, Read SR or Read electronic signature mode.

WAIT signals valid data if the addressed bank is in Read Array mode.

4. Address latched and data output on the rising clock edge.

49/92

Page 50

M36WT864TF, M36WT864BF

Figure 15. Flash Clock input AC Waveform

tKHKL

tKHKH

tKLKH

Table 22. Flash Synchronous Read AC Characteristics

Symbol Alt P arameter

Synchronous Read Timings

AVKH

ELKH

ELTV

EHEL

EHTZ

KHAX

KHQV

KHTV

AVCLKH

ELCLKH

CLKHAX

CLKHQV

Address Valid to Clock High Min 9 9 9 ns Chip Enable Low to Clock High Min 9 9 9 ns

Chip Enable Low to Wait Valid Max

Chip Enable Pulse Width (subsequent synchronous reads)

Chip Enable High to Wait Hi-Z Max

Clock High to Address Transition Min 10 10 10 ns Clock High to Output Valid

Clock High to WAIT Valid

Min

Max

M36WT864TF/B F

70 85 1 00

(3)

18 18 ns

14 14 ns

20 20 ns

18 18 ns

AI06981

Unit

KHQX

KHTX

LLKH

CLKHQX

ADVLCLKH

Clock High to Output Transition Clock High to WAIT Transition

Latch Enable Low to Clock High Min 9 9 9 ns Clock Period (f=40MHz) Min 25 25 ns

KHKH

CLK

Clock Period (f=54MHz) Min 18.5 ns

KHKL

KLKH

Clock Specifications

Note: 1. Sampled only, not 100% tested.

2. For other ti mings plea se refer to Tab l e 21, Asynchronous Rea d AC Characteristics.

3. To be characterized.

Clock High to Clock Low Clock Low to Clock High

Clock Fall or Rise Time Max 3 3 3 ns

50/92

Min 4 4 4 ns

Min 4.5 5 5 ns

Page 51

Figure 16. Flash Write AC Waveforms, Write Enable Contro lled

M36WT864TF, M36WT864BF

AI06279

VALID ADDRESS

PROGRAM OR ERASE

tWHAV

tWHAX

tAVAV

VALID ADDRESSA0-A21

tAVWH

tWHGL

tELQV

tWHQV

tWHEL

tQVWPL

STATUS REGISTER

tWHWPL

tQVVPL

READ

1st POLLING

STATUS REGISTER

tWHVPL

tELKV

OR DATA INPUT

tLHAX

tLLLH

BANK ADDRESS

tAVLH

tWHLL

tELLH

tELWL tWHEH

tWHWL

tGHWL

tWHDX

tWLWH

tDVWH

tWPHWH

DQ0-DQ15 COMMAND CMD or DATA

WPF

tVPHWH

PPF

SET-UP COMMAND CONFIRM COMMAND

51/92

Page 52

M36WT864TF, M36WT864BF

Table 23. Flash Write AC Characteristics, Write Enable Controlled

Symbol Alt Parame ter

AVAV

AVLH

AVWH

DVWH

(4)

Address Valid to Next Address Valid Min

Address Valid to Latch Enable High Min 10 10 10 ns

Address Valid to Write Enable High Min

Data Valid to Write Enable High Min

M36WT864T F/BF

70 85 100

45 45

(3)

85 100 ns

50 50 ns 50 50 ns

Unit

Write Enable Controlled Timings

ELLH

ELWL

ELQV

ELKV

GHWL

LHAX

LLLH

WHAV

WHAX

WHDX

WHEH

WHEL

WHGL

WHLL

WHWL

WHQV

WLWH

(2)

(4)

Chip Enable Low to Latch Enable High Min 10 10 10 ns

Chip Enable Low to Write Enable Low Min 0 0 0 ns

Chip Enable Low to Output Valid Min

(3)

85 100 ns

Chip Enable High to Clock Valid Min 9 9 9 ns Output Enable High to Write Enable Low Min 20 20 20 ns

Latch Enable High to Address Transition Min 10 10 10 ns Latch Enable Pulse Width Min 10 10 10 ns Write Enable High to Address Valid Min 0 0 0 ns

Write Enable High to Address Transition Min 0 0 0 ns

Write Enable High to Input Transition Min 0 0 0 ns

Write Enable High to Chip Enable High Min 0 0 0 ns

Write Enable High to Chip Enable Low Min

(3)

25 25 ns

Write Enable High to Output Enable Low Min 0 0 0 ns Write Enable High to Latch Enable Low Min 0 0 0 ns

Write Enable High to Write Enable Low Min 25 25 25 ns

WPH

Write Enable High to Output Valid Min

Write Enable Low to Write Enable High Min

95 45

(3)

110 125 ns

(3)

50 50 ns

QVVPL

QVWPL

VPHWH

WHVPL

WHWPL

Protection Timings

WPHWH

Note: 1. Sampled only, not 100% tested.

2. t

3. To be characterized.

4. Meaningful only if LF

has the values show n when reading in the targete d bank. Sys tem desig ners should take this into acc ount and may insert a

WHEL

software No-Op instruction to delay the first read in the same ba nk after issuing a command. If it is a Read Ar ray operation in a different bank t

Output (Status Register) Valid to V Output (Status Register) Valid to Write Protect

Low

VPSVPPF

High to Write Enable High Write Enable High to V Write Enable High to Write Protect Low Min 200 200 200 ns Write Protect High to Write Enable High Min 200 200 200 ns

is 0ns.

WHEL

is always kept low.

52/92

PPF

Low

PPF

Low

Min 0 0 0 ns

Min 200 200 200 ns Min 200 200 200 ns

Page 53

Figure 17. Flash Write AC Waveforms, Chip Enable Controlled

M36WT864TF, M36WT864BF

AI06280

VALID ADDRESS

PROGRAM OR ERASE

tEHAX

tAVAV

VALID ADDRESSA0-A21

tAVEH

tEHGL

tELQV

tWHQV

tWHEL

tQVWPL

STATUS REGISTER

tEHWPL

tQVVPL

READ

1st POLLING

STATUS REGISTER

tEHVPL

tELKV

OR DATA INPUT

tLHAX

tLLLH

BANK ADDRESS

tAVLH

tEHWH

tELLH

tWLEL

tEHEL

tGHEL

tEHDX

tELEH

tDVEH

tWPHEH

DQ0-DQ15 COMMAND CMD or DATA

WPF

tVPHEH

PPF

SET-UP COMMAND CONFIRM COMMAND

53/92

Page 54

M36WT864TF, M36WT864BF

Table 24. Flash Write AC Characteristics, Chip Enable Controlled

Symbol Alt Parameter

AVAV

AVEH

AVLH

DVEH

Address Valid to Next Address Valid Min

Address Valid to Chip Enable High Min

Address Valid to Latch Enable High Min 10 10 10 ns

Data Valid to Write Enable High Min

M36WT864TF/ BF

70 85 100

70 45

(3)

85 100 ns 50 50 ns

50 50 ns

Unit

EHAX

EHDX

EHEL

EHGL

EHWH

ELKV

ELEH

ELLH

ELQV

Chip Enable Controlled Timings

GHEL

LHAX

LLLH

WHEL

WHQV

WLEL

EHVPL

EHWPL

QVVPL

QVWPL

VPHEHtVPSVPPF

Protection Timings

WPHEH

Note: 1. Sampled only, not 100% tested.

2. t

WHEL

software No-Op instruction to delay the first read in the same ba nk after issuing a command. If it is a Read Ar ray operation in a different bank t

3. To be characterized.

Chip Enable High to Address Transition Min 0 0 0 ns

Chip Enable High to Input Transition Min 0 0 0 ns

Chip Enable High to Chip Enable Low Min 25 25 25 ns

WPH

Chip Enable High to Output Enable Low Min 0 0 0 ns

Chip Enable High to Write Enable High Min 0 0 0 ns

Chip Enable Low to Clock Valid Min 9 9 9 ns

Chip Enable Low to Chip Enable High Min

Chip Enable Low to Latch Enable High Min 10 10 10 ns Chip Enable Low to Output Valid Min Output Enable High to Chip Enable Low Min 20 20 20 ns Latch Enable High to Address Transition Min 10 10 10 ns Latch Enable Pulse Width Min 10 10 10 ns

(2)

Write Enable High to Chip Enable Low Min Write Enable High to Output Valid Min 95 110 125 ns

Write Enable Low to Chip Enable Low Min 0 0 0 ns

Chip Enable High to V Chip Enable High to Write Protect Low Min 200 200 200 ns Output (Status Register) Valid to V Output (Status Register) Valid to Write Protect

Low

High to Chip Enable High

Write Protect High to Chip Enable High Min 200 200 200 ns

has the values show n when reading in the targete d bank. Sys tem desig ners should take this into acc ount and may insert a

is 0ns.

WHEL

PPF

Low

PPF

Low

(3)

50 50 ns

85 100 ns

25 25 ns

Min 200 200 200 ns

Min 0 0 0 ns

Min 200 200 200 ns

54/92

Page 55

Figure 18. Flash Reset and Power-up AC Waveforms

M36WT864TF, M36WT864BF

WF, EF, GF, LF

VDD, VDDQ

tPHWL

tPHEL tPHGL

tPHLL

tVDHPH tPLPH

Power-Up Reset

tPLWL

tPLEL tPLGL

tPLLL

Table 25. Flash Reset and Power-up AC Characteristics

Symbol Parameter Test Condition 70 85 100 Unit

PLWL

PLEL

PLGL

PLLL

PHWL

PHEL

PHGL

PHLL

PLPH

VDHPH

Note: 1. The device Res et is possible but not guara nteed if t

2. Sampled only, not 100% tested.

3. It is important to assert R P

Reset Low to Write Enable Low, Chip Enable Low, Output Enable Low, Latch Enable Low

Reset High to Write Enable Low Chip Enable Low Output Enable Low Latch Enable Low

(1,2)

RP Pulse Width Min 50 50 50 ns Supply Voltages High to Reset

(3)

High

in order to allow proper CPU initialization during Power-Up or Reset.

During Program Min 10 10 10 µs During Erase Min 20 20 20 µs

Other Conditions Min 80 80 80 ns

Min 30 30 30 ns

Min 50 50 50 µs

< 50ns.

PLPH

AI06281

55/92

Page 56

M36WT864TF, M36WT864BF

Figure 19. SRAM Address Controlled, Read AC Waveforms

tAVAV

A0-A18

tAVQV tAXQX

DQ0-DQ7 and/or DQ8-DQ15

Note: E1S = Low, E2S = High, GS = Low, WS = High, UBS = Low and/or LBS = Low.

VALID

DATA VALID

Figure 20. SRAM Chip Enable or Output Enable Controlled, Read AC Waveforms

tAVAV

A0-A18

tAVQV tAXQX

tELQV

E1S

E2S

tELQX

tGLQV

VALID

tGHQZ

AI05839

tEHQZ

DQ0-DQ15

UBS, LBS

Note: Write Enable (WF) = High

tGLQX

tBLQV

tBLQX

VALID

tBHQZ

AI06282

56/92

Page 57

M36WT864TF, M36WT864BF

Figure 21. SRAM Chip Enable or UBS/LBS Controlled, Standby AC Waveforms

E1S, UBS, LBS

E2S

tPU

50%

Table 26. SRAM Read and Standby AC Characteristics

Symbol Parameter

AVAV

AVQV

AXQX

(2,3,4)

BHQZ

BLQV

BLQX

(2,3,4)

EHQZ

ELQV

ELQX

(2,3,4)

GHQZ

GLQV

GLQX

(4)

Note: 1. Test condi tions assum e transition t i m i ng r e f erence l evel = 0. 3V

2. At any given tem perature and voltage condition, t any given de vice.

3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage lev el s.

4. Tested init i al l y and after any design or process changes that may affect these parameters.

Read Cycle Time Min 70 ns Address Valid to Output Valid Max 70 ns

(1)

Data hold from address change Min 5 ns Upper/Lower Byte Enable High to Output Hi-Z Max 25 ns

Upper/Lower Byte Enable Low to Output Valid Max 70 ns

(1)

Upper/Lower Byte Enable Low to Output Transition Min 5 ns Chip Enable High to Output Hi-Z Max 25 ns

Chip Enable Low to Output Valid Max 70 ns

(1)

Chip Enable Low to Output Transition Min 5 ns Output Enable High to Output Hi-Z Max 25 ns

Output Enable Low to Output Valid Max 35 ns

(1)

Output Enable Low to Output Transition Min 5 ns Chip Enable or UB/LB High to Power Down Max 0 ns Chip Enable or UB/LB Low to Power Up Min 70 ns

is less than t

GHQZ

DDS

or 0.7V

GLQX

, t

DDS BHQZ

is less than t

M36WT864 TF/BF

and t

BLQX

EHQZ

tPD

AI06283

is less than t

Unit

ELQX

for

57/92

Page 58

M36WT864TF, M36WT864BF

Figure 22. SRAM Write AC Waveforms, Write Enable Controlled

tAVAV

A0-A18

tAVEL

E1S

E2S

tAVWL

tWLQZ

DQ0-DQ15

UBS, LBS

Note: 1. Dur i ng this period DQ0-DQ15 are in output s tate and input signals shoul d not be appli ed.

VALID

tAVWH

tELWH

tWLWH

tWHDX

DATA INPUT

tDVWH

tBLBH

tWHAX

tWHQX

AI06284

58/92

Page 59

Figure 23. SRAM Write AC Waveforms, Chip Enable Controlled

tAVAV

M36WT864TF, M36WT864BF

A0-A18

tAVEL

E1S

E2S

tAVWL

DQ0-DQ15

UBS, LBS

Figure 24. SRAM Write AC Waveforms, UB

VALID

tAVEH

tELEH

tWLEH

tBLBH

/LB Controlled

tEHAX

tEHDX

DATA INPUT

tDVEH

AI06285

tAVAV

A0-A18

E1S

E2S

tAVWL

tWLQZ tBHDX

(1)

DQ0-DQ15

UBS, LBS

Note: 1. Dur i ng this period DQ0-DQ15 are in output s tate and input signals shoul d not be appli ed.

DATA

tAVBL

VALID

tAVBH

tWLBH

DATA INPUT

tDVBH

tBLBH

tBHAX

AI06286

59/92

Page 60

M36WT864TF, M36WT864BF

Table 27. SRAM Write AC Characteristics

Symbol Parameter

AVAV

AVBH

AVBL

AVEH

AVEL

AVWH

AVWL

BHAX

BHDX

BLBH

BLEH

BLWH

DVBH

DVEH

DVWH

EHAX

EHDX

ELBH

ELEH

ELWH

WHAX

WHDX

WHQX

WLBH

WLEH

(1,2,3)

WLQZ

WLWH

Note: 1. At any gi ven temperature and v ol tage condit i on, t

2. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage lev el s.

3. Tested init i al l y and after any design or process changes that may affect these parameters.

Write Cycle Time Min 70 ns Address Valid to LBS, UBS High Min 60 ns Address Valid to LBS, UBS Low Min 0 ns Address Valid to Chip Enable High Min 60 ns Address valid to Chip Enable Low Min 0 ns Address Valid to Write Enable High Min 60 ns Address Valid to Write Enable Low Min 0 ns LBS, UBS High to Address Transition Min 0 ns LBS, UBS High to Input Transition Min 0 ns LBS, UBS Low to LBS, UBS High Min 60 ns LBS, UBS Low to Chip Enable High Min 60 ns LBS, UBS Low to Write Enable High Min 60 ns Input Valid to LBS, UBS High Min 30 ns Input Valid to Chip Enable High Min 30 ns Input Valid to Write Enable High Min 30 ns Chip Enable High to Address Transition Min 0 ns Chip enable High to Input Transition Min 0 ns Chip Enable Low to LBS, UBS High Min 60 ns Chip Enable Low to Chip Enable High Min 60 ns Chip Enable Low to Write Enable High Min 60 ns Write Enable High to Address Transition Min 0 ns Write Enable High to Input Transition Min 0 ns

(1)

Write Enable High to Output Transition Min 5 ns Write Enable Low to LBS, UBS High Min 60 ns Write Enable Low to Chip Enable High Min 60 ns Write Enable Low to Output Hi-Z Max 20 ns Write Enable Low to Write Enable High Min 50 ns

is less than t

WLQZ

for any given device.

WHQX

M36WT864T F/BF

Unit

60/92

Page 61

M36WT864TF, M36WT864BF

Figure 25. SRAM Low VDD Data Retention AC Waveforms, E1S Contr ol led

3.3V

2.7V

DDS

VDR> 1.5V

E1S or UBS/LBS

Figure 26. SRAM Low V

3.3V

2.7V

DDS

VDR> 1.5V

E2S

DATA RETENTION MODE

tCDR

E1S≥ VDR– 0.2V or UBS = LBS ≥ VDR– 0.2V

Data Retention AC Waveforms, E2S Controlled

DATA RETENTION MODE

tCDR

E2S ≥ 0.2V

AI06287

AI06288

Table 28. SRAM Low V

Data Retention Characteristics

Symbol Parameter Test Condition M in Typ M ax Unit

(1)

VDD= 1.5V, E1S ≥ V

DDDR

CDR

Note: 1. All other Inputs at VIH≥ V

Supply Current (Data Retention)

UBS

Chip Deselected to Data

(1,2)

Retention Time

(2)

Operation Recovery Time

(1)

Supply Voltage (Data Retention)

–0.2V or VIL≤ 0.2V.

2. Tested init i al l y and after any design or process that may affect these parameters.

3. No input may exceed V

DDS

+0.2V.

E1S

UBS = LBS ≥ V

E2S ≤ 0.2V or

= LBS ≥ V

≥ V

–0.2V or E2S ≤ 0.2V or

DDS

–0.2V or

DDS

–0.2V, f = 0

AVAV

1.5 V

is Read cycl e time.

AVAV

510µA

0ns

61/92

Page 62

M36WT864TF, M36WT864BF

PACKAGE MECHANICAL

Figure 27. Stacked LFBGA96 - 8x14mm, 8x10ball array, 0.8mm pitch, Bottom View Package Outline

BALL "A1"

Note: Drawing is not to scale.

FE1

ddd

BGA-Z31

Table 29. Stacked LFBGA96 - 8x14mm, 8x10 ball array, 0.8mm pitch, Packag e Mec hanica l Data

Symbol

Typ Min Max Typ Min Max

A 1.400 0.0551 A1 0.300 0.0118 A2 0.960 0.0378

b 0.400 0.350 0.45 0 0.01 57 0.0138 0.0177

D 8 .000 7.900 8.100 0.3150 0.3110 0.3189

D1 5 .600 – – 0.2205 – –

ddd 0.10 0 0.0039

E 1 4.000 13.900 14.1 00 0.5512 0.5472 0.5551 E1 7.200 – – 0.2835 – – E2 10.400 – – 0.40 94 – –

e 0.800 – – 0.0315 – – FD 1.200 – – 0.0472 – – FE 3 .400 – – 0.1339 – –

FE1 1.800 – – 0.0709 – –

SD 0.400 – – 0.0157 – – SE 0.400 – – 0.0157 – –

millimeters inches

62/92

Page 63

M36WT864TF, M36WT864BF

PART NUMBERING

Table 30. Ordering Information Scheme

Example: M36WT864TF 70 ZA 6 T

Device Type

M36 = MMP (Flash + SRAM)

Architecture

W = Multiple Bank, Burst mode

Operating Voltage

T = V

SRAM Chip Size & Organization

8 = 8 Mbit (512K x16-bit)

Device Function

64T = 64 Mbit (x16), Multiple Bank, Top Boot 64B = 64 Mbit (x16), Multiple Bank, Bottom Boot B = SRAM Asynchronous 70ns

= 1.65V to 2.2V; V

DDF

DDS

= V

= 2.7V to 3.3V

DDQF

Speed

70 = 70ns 85 = 85ns 10 = 100ns

Package

ZA = LFBGA96 - 8x14mm, 8x10 ball array, 0.8mm pitch

Temperature Rang e

6 = –40 to 85°C

Option

T = Tape & Reel packing

Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc...) or for further information on any aspec t of this de vice, please contact the STMicroelectronics Sales Office neare st to you.

63/92

Page 64

M36WT864TF, M36WT864BF

REVISION HIST ORY

Table 31. Document Revision History

Date Version Revision Details

10-Jul-2002 1.0 First Issue

64/92

Page 65

APPENDIX A. FLASH BLOCK ADDRESS TABLES

M36WT864TF, M36WT864BF

Table 32. Flash Top Boot Block Addresses

Bank #

Parameter Bank

Bank 0

Bank 1

Bank 2

10 32 3E0000-3E7FFF 11 32 3D8000-3DFFFF 12 32 3D0000-3D7FFF 13 32 3C8000-3CFFFF 14 32 3C0000-3C7FFF 15 32 3B8000-3BFFFF 16 32 3B0000-3B7FFF 17 32 3A8000-3AFFFF 18 32 3A0000-3A7FFF 19 32 398000-39FFFF 20 32 390000-397FFF 21 32 388000-38FFFF 22 32 380000-387FFF 23 32 378000-37FFFF 24 32 370000-377FFF 25 32 368000-36FFFF 26 32 360000-367FFF 27 32 358000-35FFFF 28 32 350000-357FFF 29 32 348000-34FFFF 30 32 340000-347FFF 31 32 338000-33FFFF 32 32 330000-337FFF 33 32 328000-32FFFF 34 32 320000-327FFF 35 32 318000-31FFFF 36 32 310000-317FFF 37 32 308000-30FFFF 38 32 300000-307FFF

Size

(KWord)

0 4 3FF000-3FFFFF 1 4 3FE000-3FEFFF 2 4 3FD000-3FDFFF 3 4 3FC000-3FCFFF 4 4 3FB000-3FBFFF 5 4 3FA000-3FAFFF 6 4 3F9000-3F9FFF 7 4 3F8000-3F8FFF 8 32 3F0000-3F7FFF 9 32 3E8000-3EFFFF

Address Range

39 32 2F8000-2FFFFF 40 32 2F0000-2F7FFF 41 32 2E8000-2EFFFF 42 32 2E0000-2E7FFF 43 32 2D8000-2DFFFF

Bank 3

44 32 2D0000-2D7FFF 45 32 2C8000-2CFFFF 46 32 2C0000-2C7FFF 47 32 2B8000-2BFFFF 48 32 2B0000-2B7FFF 49 32 2A8000-2AFFFF 50 32 2A0000-2A7FFF 51 32 298000-29FFFF

Bank 4

52 32 290000-297FFF 53 32 288000-28FFFF 54 32 280000-287FFF 55 32 278000-27FFFF 56 32 270000-277FFF 57 32 268000-26FFFF 58 32 260000-267FFF 59 32 258000-25FFFF

Bank 5

60 32 250000-257FFF 61 32 248000-24FFFF 62 32 240000-247FFF 63 32 238000-23FFFF 64 32 230000-237FFF 65 32 228000-22FFFF 66 32 220000-227FFF 67 32 218000-21FFFF

Bank 6

68 32 210000-217FFF 69 32 208000-20FFFF 70 32 200000-207FFF 71 32 1F8000-1FFFFF 72 32 1F0000-1F7FFF 73 32 1E8000-1EFFFF 74 32 1E0000-1E7FFF 75 32 1D8000-1DFFFF

Bank 7

76 32 1D0000-1D7FFF 77 32 1C8000-1CFFFF 78 32 1C0000-1C7FFF

65/92

Page 66

M36WT864TF, M36WT864BF

79 32 1B8000-1BFFFF 80 32 1B0000-1B7FFF 81 32 1A8000-1AFFFF 82 32 1A0000-1A7FFF 83 32 198000-19FFFF

Bank 8

84 32 190000-197FFF 85 32 188000-18FFFF 86 32 180000-187FFF 87 32 178000-17FFFF 88 32 170000-177FFF 89 32 168000-16FFFF 90 32 160000-167FFF 91 32 158000-15FFFF

Bank 9

92 32 150000-157FFF 93 32 148000-14FFFF 94 32 140000-147FFF 95 32 138000-13FFFF 96 32 130000-137FFF 97 32 128000-12FFFF 98 32 120000-127FFF 99 32 118000-11FFFF

Bank 10

100 32 110000-117FFF 101 32 108000-10FFFF 102 32 100000-107FFF 103 32 0F8000-0FFFFF 104 32 0F0000-0F7FFF 105 32 0E8000-0EFFFF 106 32 0E0000-0E7FFF 107 32 0D8000-0DFFFF

Bank 11

108 32 0D0000-0D7FFF 109 32 0C8000-0CFFFF 110 32 0C0000-0C7FFF

111 32 0B8000-0BFFFF 112 32 0B0000-0B7FFF 113 32 0A8000-0AFFFF 114 32 0A0000-0A7FFF 115 32 098000-09FFFF

Bank 12

116 32 090000-097FFF 117 32 088000-08FFFF 118 32 080000-087FFF

119 32 078000-07FFFF 120 32 070000-077FFF 121 32 068000-06FFFF 122 32 060000-067FFF 123 32 058000-05FFFF

Bank 13

124 32 050000-057FFF 125 32 048000-04FFFF 126 32 040000-047FFF 127 32 038000-03FFFF 128 32 030000-037FFF 129 32 028000-02FFFF 130 32 020000-027FFF 131 32 018000-01FFFF

Bank 14

132 32 010000-017FFF 133 32 008000-00FFFF 134 32 000000-007FFF

Note: There are two Bank Regions, Region 1 contains all the banks

that are made up of main blocks only, Region 2 contains the banks that are made up of the parame ter and main blocks.

66/92

Page 67

M36WT864TF, M36WT864BF

Table 33. Flash Bottom Boot Block Addresses

Bank #

134 32 3F8000-3FFFFF 133 32 3F0000-3F7FFF 132 32 3E8000-3EFFFF 131 32 3E0000-3E7FFF 130 32 3D8000-3DFFFF

Bank 14

129 32 3D0000-3D7FFF 128 32 3C8000-3CFFFF 127 32 3C0000-3C7FFF 126 32 3B8000-3BFFFF 125 32 3B0000-3B7FFF 124 32 3A8000-3AFFFF 123 32 3A0000-3A7FFF 122 32 398000-39FFFF

Bank 13

121 32 390000-397FFF 120 32 388000-38FFFF 119 32 380000-387FFF 118 32 378000-37FFFF 117 32 370000-377FFF 116 32 368000-36FFFF 115 32 360000-367FFF 114 32 358000-35FFFF

Bank 12

113 32 350000-357FFF 112 32 348000-34FFFF 111 32 340000-347FFF 110 32 338000-33FFFF 109 32 330000-337FFF 108 32 328000-32FFFF 107 32 320000-327FFF 106 32 318000-31FFFF

Bank 11

105 32 310000-317FFF 104 32 308000-30FFFF 103 32 300000-307FFF 102 32 2F8000-2FFFFF 101 32 2F0000-2F7FFF 100 32 2E8000-2EFFFF

Bank 10

99 32 2E0000-2E7FFF 98 32 2D8000-2DFFFF 97 32 2D0000-2D7FFF 96 32 2C8000-2CFFFF 95 32 2C0000-2C7FFF

Size

(KWord)

Address Range

94 32 2B8000-2BFFFF 93 32 2B0000-2B7FFF 92 32 2A8000-2AFFFF 91 32 2A0000-2A7FFF 90 32 298000-29FFFF

Bank 9

89 32 290000-297FFF 88 32 288000-28FFFF 87 32 280000-287FFF 86 32 278000-27FFFF 85 32 270000-277FFF 84 32 268000-26FFFF 83 32 260000-267FFF 82 32 258000-25FFFF

Bank 8

81 32 250000-257FFF 80 32 248000-24FFFF 79 32 240000-247FFF 78 32 238000-23FFFF 77 32 230000-237FFF 76 32 228000-22FFFF 75 32 220000-227FFF 74 32 218000-21FFFF

Bank 7

73 32 210000-217FFF 72 32 208000-20FFFF 71 32 200000-207FFF 70 32 1F8000-1FFFFF 69 32 1F0000-1F7FFF 68 32 1E8000-1EFFFF 67 32 1E0000-1E7FFF 66 32 1D8000-1DFFFF

Bank 6

65 32 1D0000-1D7FFF 64 32 1C8000-1CFFFF 63 32 1C0000-1C7FFF 62 32 1B8000-1BFFFF 61 32 1B0000-1B7FFF 60 32 1A8000-1AFFFF 59 32 1A0000-1A7FFF 58 32 198000-19FFFF

Bank 5

57 32 190000-197FFF 56 32 188000-18FFFF 55 32 180000-187FFF

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Page 68

M36WT864TF, M36WT864BF

54 32 178000-17FFFF 53 32 170000-177FFF 52 32 168000-16FFFF 51 32 160000-167FFF 50 32 158000-15FFFF

Bank 4

49 32 150000-157FFF 48 32 148000-14FFFF 47 32 140000-147FFF 46 32 138000-13FFFF 45 32 130000-137FFF 44 32 128000-12FFFF 43 32 120000-127FFF 42 32 118000-11FFFF

Bank 3

41 32 110000-117FFF 40 32 108000-10FFFF 39 32 100000-107FFF 38 32 0F8000-0FFFFF 37 32 0F0000-0F7FFF 36 32 0E8000-0EFFFF 35 32 0E0000-0E7FFF 34 32 0D8000-0DFFFF

Bank 2

33 32 0D0000-0D7FFF 32 32 0C8000-0CFFFF 31 32 0C0000-0C7FFF 30 32 0B8000-0BFFFF 29 32 0B0000-0B7FFF 28 32 0A8000-0AFFFF 27 32 0A0000-0A7FFF 26 32 098000-09FFFF

Bank 1

25 32 090000-097FFF 24 32 088000-08FFFF 23 32 080000-087FFF

22 32 078000-07FFFF 21 32 070000-077FFF 20 32 068000-06FFFF 19 32 060000-067FFF 18 32 058000-05FFFF

Bank 0

17 32 050000-057FFF 16 32 048000-04FFFF 15 32 040000-047FFF 14 32 038000-03FFFF 13 32 030000-037FFF 12 32 028000-02FFFF

11 32 020000-027FFF

10 32 018000-01FFFF

9 32 010000-017FFF 8 32 008000-00FFFF 7 4 007000-007FFF 6 4 006000-006FFF 5 4 005000-005FFF

Parameter Bank

4 4 004000-004FFF 3 4 003000-003FFF 2 4 002000-002FFF 1 4 001000-001FFF 0 4 000000-000FFF

Note: There are two Bank Regions, Region 1 contains all the banks

that are made up of main blocks only, Region 2 contains the banks that are made up of the parame ter and main blocks.

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APPENDIX B. FLASH COMMON FLASH INTERFACE

The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to det ermine various electrical and t iming parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary.

When the Read CFI Query Command is issued the device enters CFI Query mode and the data structure is read from the memory. Tables 34, 35,

Table 34. Query Structure Overview

Offset Sub-section Name Description

00h Reserved Reserved for algorithm-specific information 10h CFI Query Identification String Command set ID and algorithm data offset 1Bh System Interface Information Device timing & voltage information 27h Device Geometry Definition Flash device layout

P Primary Algorithm-specific Extended Query table

A Alternate Algorithm-specific Extended Query table

80h Security Code Area

Note: T he Flas h m emory di splay the CFI data structure when C F I Query command i s issued . In this table are liste d the mai n sub-sect i ons

detailed in Tables 35, 36, 37, 38, 40 and 1. Query data is always presented on the lowest or der data outputs.

36, 37, 38, 40 and 1 show th e addresses used to retrieve the data. The Query data is always presented on the lowest order data outputs (DQ0DQ7), the other outputs (DQ8-DQ15) are set to 0.

The CFI data structure also contains a security area where a 64 bit unique security number is written (see Table 1, Security Code area). This area can be accessed only in Read mode by the final user. It is impossible to change the security num ber after it has been written by ST. Issue a Read Array command to return to Read mode.

Additional information specific to the Primary Algorithm (optional)

Additional information specific to the Alternate Algorithm (optional)

Lock Protection Register Unique device Number and User Programmable OTP

Table 35. CFI Query Identification String

Offset Sub-section Name Description Value

00h 0020h Manufacturer Code ST 01h 02h reserved Reserved

03h reserved Reserved

04h-0Fh reserved Reserved

10h 0051h 11h 0052h "R" 12h 0059h "Y" 13h 0003h 14h 0000h 15h offset = P = 0039h 16h 0000h 17h 0000h 18h 0000h 19h value = A = 0000h

1Ah 0000h

8810h

8811h

Device Code

Query Unique ASCII String "QRY"

Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm

Address for Primary Algorithm extended Query table (see Table 37) p = 39h

Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported

Address for Alternate Algorithm extended Query table NA

Top

Bottom

"Q"

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Table 36. CFI Query System Interface Information

Offset Data Description Value

Logic Supply Minimum Program/Erase or Write voltage

1Bh 0017h

1Ch 0022h

1Dh 0017h

1Eh 00C0h

1Fh 0004h 20h 0003h 21h 000Ah 22h 0000h 23h 0003h 24h 0004h 25h 0002h

bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts

Logic Supply Maximum Program/Erase or Write voltage

bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts

[Programming] Supply Minimum Program/Erase voltage

PPF

bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts

[Programming] Supply Maximum Program/Erase voltage

PPF

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 millivolts Typical time-out per single byte/word program = 2 Typical time-out for quadruple word program = 2 Typical time-out per individual block erase = 2 Typical time-out for full chip erase = 2 Maximum time-out for word program = 2

times typical Maximum time-out for quadruple word = 2 Maximum time-out per individual block erase = 2

µs

times typical

µs

1.7V

2.2V

1.7V

12V

16µs

8µs

NA 128µs 128µs

26h 0000h

Maximum time-out for chip erase = 2n times typical

Table 37. Device Geometry Definition

Offset Word

Mode

27h 0017h 28h

29h

2Ah 2Bh

2Ch 0002h Number of identical sized erase block regions within the device

2Dh 2Eh

2Fh 30h

31h 32h

33h

M36WT864TF

34h 35h

38h

Data Description Value

in number of bytes

0001h 0000h

0003h 0000h

Device Size = 2

Flash Device Interface Code description

Maximum number of bytes in multi-byte program or page = 2

bit 7 to 0 = x = number of Erase Block Regions

007Eh

0000h 0000h

0001h 0007h

0000h 0020h

0000h

Region 1 Information Number of identical-size erase blocks = 007Eh+1

Region 1 Information Block size in Region 1 = 0100h * 256 byte

Region 2 Information Number of identical-size erase blocks = 0007h+1

Region 2 Information Block size in Region 2 = 0020h * 256 byte

0000h Reserved for future erase block region information NA

8 MByte

x16

Async.

8 Byte

127

64 KByte

8 KByte

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Offset Word

Mode

2Dh 2Eh

2Fh 30h

31h 32h

33h

M36WT864B F

34h 35h

38h

Data Description Value

0007h 0000h

0020h 0000h

007Eh

0000h 0000h

0001h

0000h Reserved for future erase block region information NA

Region 1 Information Number of identical-size erase block = 0007h+1

Region 1 Information Block size in Region 1 = 0020h * 256 byte

Region 2 Information Number of identical-size erase block = 007Eh+1

Region 2 Information Block size in Region 2 = 0100h * 256 byte

8 KByte

64 KByte

Table 38. Primary Algorithm-Specific Extended Qu ery Ta bl e

Offset Data Description Value

(P)h = 39h 0050h

0052h "R"

0049h "I" (P+3)h = 3Ch 0031h Major version number, ASCII "1" (P+4)h = 3Dh 0030h Minor version number, ASCII "0" (P+5)h = 3Eh 00E6h Extended Query table contents for Primary Algorithm. Address (P+5)h

0003h

(P+7)h = 40h 0000h (P+8)h = 41h 0000h

(P+9)h = 42h 0001h Supported Functions after Suspend

(P+A)h = 43h 0003h Block Protect Status (P+B)h = 44h 0000h

Primary Algorithm extended Query table unique ASCII string “PRI”

contains less significant byte.

bit 0 Chip Erase supported (1 = Yes, 0 = No) bit 1 Erase Suspend supported (1 = Yes, 0 = No) bit 2 Program Suspend supported (1 = Yes, 0 = No) bit 3 Legacy Lock/Unlock supported (1 = Yes, 0 = No) bit 4 Queued Erase supported (1 = Yes, 0 = No) bit 5 Instant individual block locking supported (1 = Yes, 0 = No) bit 6 Protection bits supported (1 = Yes, 0 = No) bit 7 Page mode read supported (1 = Yes, 0 = No) bit 8 Synchronous read supported (1 = Yes, 0 = No) bit 9 Simultaneous operation supported (1 = Yes, 0 = No) bit 10 to 31 Reserved; undefined bits are ‘0’. If bit 31 is ’1’ then another 31

bit field of optional features follows at the end of the bit-30 field.

Read Array, Read Status Register and CFI Query

bit 0 Program supported after Erase Suspend (1 = Yes, 0 = No) bit 7 to 1 Reserved; undefined bits are ‘0’

Defines which bits in the Block Status Register section of the Query are implemented.

127

"P"

No Yes Yes

No Yes Yes Yes Yes Yes

Yes

bit 0 Block protect Status Register Lock/Unlock

bit active (1 = Yes, 0 = No) bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No) bit 15 to 2 Reserved for future use; undefined bits are ‘0’

Yes Yes

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Offset Data Description Value

Logic Supply Optimum Program/Erase voltage (highest performance)

(P+C)h = 45h 0018h

bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100 mV

Supply Optimum Program/Erase voltage

PPF

(P+D)h = 46h 00C0h

bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100 mV

Table 39. Protection Register Information

Offset Data Description Value

(P+E)h = 47h 0001h

(P+F)h = 48h 0080h (P+10)h = 49h 0000h (P+11)h = 4Ah 0003h 8 Bytes

(P+12)h= 4Bh 0004h 16 Bytes

Number of protection register fields in JEDEC ID space. 0000h indicates that 256 fields are available.

Protection Field 1: Protection Description Bits 0-7 Lower byte of protection register address Bits 8-15 Upper byte of protection register address

Bits 16-23 2 Bits 24-31 2

bytes in factory pre-programmed region

bytes in user programmable region

1.8V

12V

0080h

Table 40. Burst Read Information

Offset

(P+13)h = 4Ch 0003h Page-mode read capability

(P+14)h = 4Dh 0003h Number of synchronous mode read configuration fields that follow. 3

(P+15)h = 4Eh 0001h Synchronous mode read capability configuration 1

(P+16)h = 4Fh 0002h Synchronous mode read capability configuration 2 8

(P+17)h = 50h 0007h Synchronous mode read capability configuration 3 Cont.

Data Description Value

8 Bytes

bits 0-7 ’n’ such that 2

HEX value represents the number of readpage bytes. See offset 28h for device word width to determine page-mode data output width.

bit 3-7 Reserved

n+1

bit 0-2 ’n’ such that 2

HEX value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. A value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device’s burstable address space. This field’s 3-bit value can be written directly to the read configuration register bit 0-2 if the device is configured for its maximum word width. See offset 28h for word width to determine the burst data output width.

Table 41. Bank and Erase Block Region Information

M36WT864TF (top) M36WT864BF (bottom)

Offset Data Offset Data

Description

(P+18)h =51h 02h (P+18)h =51h 02h Number of Bank Regions within the device

Note: 1. The variable P i s a pointer whi ch is defined at CFI offset 15h.

2. Bank Regions. There are tw o B ank Regi ons, 1 contains all the ban ks that are m ade up of main block s only, 2 contains t he banks that are made up of the para m eter and main blocks.

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Table 42. Bank and Erase Block Region 1 Information

M36WT864TF (top) M36WT864BF (bottom)

Offset Data Offset Data

(P+19)h =52h 0Fh (P+19)h =52h 01h (P+1A)h =53h 00h (P+1A)h =53h 00h

Number of identical banks within Bank Region 1

M36WT864TF, M36WT864BF

Description

(P+1B)h =54h 11h (P+1B)h =54h 11h

(P+1C)h =55h 00h (P+1C)h =55h 00h

(P+1D)h =56h 00h (P+1D)h =56h 00h

(P+1E)h =57h 01h (P+1E)h =57h 02h

(P+1F)h =58h 07h (P+1F)h =58h 07h (P+20)h =59h 00h (P+20)h =59h 00h (P+21)h =5Ah 00h (P+21)h =5Ah 20h (P+22)h =5Bh 01h (P+22)h =5Bh 00h (P+23)h =5Ch 64h (P+23)h =5Ch 64h (P+24)h =5Dh 00h (P+24)h =5Dh 00h

(P+25)h =5Eh 01h (P+25)h =5Eh 01h

(P+26)h =5Fh 03h (P+26)h =5Fh 03h

Number of program or erase operations allowed in region 1: Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations

Number of program or erase operations allowed in other banks while a bank in same region is programming Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations

Number of program or erase operations allowed in other banks while a bank in this region is erasing Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations

Types of erase block regions in region 1 n = number of erase block regions with contiguous same-size erase blocks.

Symmetrically blocked banks have one blocking region.

Bank Region 1 Erase Block Type 1 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: n×256 = number of bytes in erase block region

Bank Region 1 (Erase Block Type 1) Minimum block erase cycles × 1000

Bank Region 1 (Erase Block Type 1): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used” BIts 5-7: reserved 5Eh 01 5Eh 01

Bank Region 1 (Erase Block Type 1): Page mode and synchronous mode capabilities Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved

(2)

(P+27)h =60h 06h (P+28)h =61h 00h (P+29)h =62h 00h (P+2A)h =63h 01h (P+2B)h =64h 64h (P+2C)h =65h 00h

Bank Region 1 Erase Block Type 2 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: n×256 = number of bytes in erase block region

Bank Region 1 (Erase Block Type 2) Minimum block erase cycles × 1000

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Description

Offset Data Offset Data

Bank Regions 1 (Erase Block Type 2): BIts per cell, internal ECC

(P+2D)h =66h 01h

Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used” BIts 5-7: reserved

Bank Region 1 (Erase Block Type 2): Page mode and synchronous mode capabilities

(P+2E)h =67h 03h

Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved

Note: 1. The variable P i s a pointer whi ch is defined at CFI offset 15h.

2. Bank Regions. There are tw o B ank Regi ons, 1 contains all the ban ks that are m ade up of main block s only, 2 contains t he banks that are made up of the para m eter and main blocks.

Table 43. Bank and Erase Block Region 2 Information

M36WT864TF (top) M36WT864BF (bottom)

Offset Data Offset Data

(P+27)h =60h 01h (P+2F)h =68h 0Fh (P+28)h =61h 00h (P+30)h =69h 00h

(P+29)h =62h 11h (P+31)h =6Ah 11h

(P+2A)h =63h 00h (P+32)h =6Bh 00h

(P+2B)h =64h 00h (P+33)h =6Ch 00h

(P+2C)h =65h 02h (P+34)h =6Dh 01h

(P+2D)h =66h 06h (P+35)h =6Eh 07h (P+2E)h =67h 00h (P+36)h =6Fh 00h (P+2F)h =68h 00h (P+37)h =70h 00h (P+30)h =69h 01h (P+38)h =71h 01h

Number of identical banks within bank region 2

Number of program or erase operations allowed in bank region 2: Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations

Number of program or erase operations allowed in other banks while a bank in this region is programming Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations

Types of erase block regions in region 2 n = number of erase block regions with contiguous same-size erase blocks.

Symmetrically blocked banks have one blocking region.

Bank Region 2 Erase Block Type 1 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: n×256 = number of bytes in erase block region

Description

(2)

(P+31)h =6Ah 64h (P+39)h =72h 64h (P+32)h =6Bh 00h (P+3A)h =73h 00h

(P+33)h =6Ch 01h (P+3B)h =74h 01h

74/92

Bank Region 2 (Erase Block Type 1) Minimum block erase cycles × 1000

Bank Region 2 (Erase Block Type 1): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used” BIts 5-7: reserved

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M36WT864TF (top) M36WT864BF (bottom)

Offset Data Offset Data

(P+34)h =6Dh 03h (P+3C)h =75h 03h

(P+35)h =6Eh 07h (P+36)h =6Fh 00h (P+37)h =70h 02h (P+38)h =71h 00h (P+39)h =72h 64h (P+3A)h =73h 00h

(P+3B)h =74h 01h

(P+3C)h =75h 03h

Description

Bank Region 2 (Erase Block Type 1): Page mode and synchronous mode capabilities (defined in table 10) Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved

Bank Region 2 Erase Block Type 2 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: n×256 = number of bytes in erase block region

Bank Region 2 (Erase Block Type 2) Minimum block erase cycles × 1000

Bank Region 2 (Erase Block Type 2): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used” BIts 5-7: reserved

Bank Region 2 (Erase Block Type 2): Page mode and synchronous mode capabilities (defined in table 10) Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted

Bits 3-7: reserved (P+3D)h =76h (P+3D)h =76h Feature Space definitions (P+3E)h =77h (P+3E)h =77h Reserved

Note: 1. The variable P i s a pointer whi ch is defined at CFI offset 15h.

2. Bank Regions. There are t wo B ank Regions, Region 1 contains all the banks that are made up of main bloc ks only, Region 2 contains the banks that are made up of the pa ram eter and mai n bl ocks.

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APPENDIX C. FLASH FLOWCHARTS AND PSEUDO CODES

Figure 28. Program Flow c hart and Pseudo Code

Start

Write 40h or 10h

Write Address

& Data

Read Status

SR7 = 1

YES

SR3 = 0

YES

SR4 = 0

YES

SR1 = 0

YES

End

VPP Invalid

Error (1, 2)

Program to Protected

Block Error (1, 2)

Program

program_command (addressToProgram, dataToProgram) {: writeToFlash (bank_address, 0x40) ; /*or writeToFlash (bank_address, 0x10) ; */

writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/

do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/

} while (status_register.SR7== 0) ;

if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ;

if (status_register.SR4==1) /*program error */ error_handler ( ) ;

if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ;

}

Note: 1. Status check of SR1 (Protected Block), SR3 (V

ation or after a sequence.

2. If an error is f ound, the Status Register must be clea red before fu rther Program/Erase Controller operations.

) Invalid) and SR4 (Pro gram Error) can be made after each program oper-

PP (VPPF

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Figure 29. Doubl e W or d Pr og ram Fl owchart and Pseudo code

Start

M36WT864TF, M36WT864BF

Write 30h

Write Address 1

& Data 1 (3)

Write Address 2

& Data 2 (3)

Read Status

SR7 = 1

YES

SR3 = 0

YES

SR4 = 0

VPP Invalid

Error (1, 2)

Program

Error (1, 2)

double_word_program_command (addressToProgram1, dataToProgram1, addressToProgram2, dataToProgram2) { writeToFlash (bank_address, 0x30) ; writeToFlash (addressToProgram1, dataToProgram1) ; /*see note (3) */ writeToFlash (addressToProgram2, dataToProgram2) ; /*see note (3) */ /*Memory enters read status state after the Program command*/

do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/

} while (status_register.b7== 0) ;

if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ;

if (status_register.SR4==1) /*program error */ error_handler ( ) ;

YES

SR1 = 0

YES

End

Note: 1. Stat us ch ec k of b1 (Pr ot ecte d Bloc k), b3 (V

or after a sequence.

2. If an error is f ound, the Status Register must be clea red before fu rt her Program/Erase operations.

3. Address 1 an d Address 2 mus t be consecut i ve addresse s differing only for bit A0.

Program to Protected

Block Error (1, 2)

if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ;

}

) Inval id ) and b4 (Pr ogram Erro r) can be made after eac h progr am op era tion

PP (VPPF

AI06171

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Figure 30. Quadr upl e W o rd P rogram Flowchart and Pseudo Code

Start

Write 56h

Write Address 1

& Data 1 (3)

Write Address 2

& Data 2 (3)

Write Address 3

& Data 3 (3)

Write Address 4

& Data 4 (3)

Read Status

SR7 = 1

YES

quadruple_word_program_command (addressToProgram1, dataToProgram1, addressToProgram2, dataToProgram2, addressToProgram3, dataToProgram3, addressToProgram4, dataToProgram4) { writeToFlash (bank_address, 0x56) ;

writeToFlash (addressToProgram1, dataToProgram1) ; /*see note (3) */

writeToFlash (addressToProgram2, dataToProgram2) ; /*see note (3) */

writeToFlash (addressToProgram3, dataToProgram3) ; /*see note (3) */

writeToFlash (addressToProgram4, dataToProgram4) ; /*see note (3) */

/*Memory enters read status state after the Program command*/

do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/

} while (status_register.b7== 0) ;

SR3 = 0

SR4 = 0

SR1 = 0

End

Note: 1. Status check of SR1 (Protected Block), SR3 (V

ation or after a sequence.

2. If an error is f ound, the Status Register must be clea red before fu rther Program/Erase operation s.

3. Address 1 to Address 4 mus t be consecut i ve addresse s differing only for bits A0 an d A1.

YES

VPP Invalid

Error (1, 2)

Program

Error (1, 2)

Program to Protected

Block Error (1, 2)

if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ;

if (status_register.SR4==1) /*program error */ error_handler ( ) ;

if (status_register.SR==1) /*program to protect block error */ error_handler ( ) ;

}

) Invalid) and SR4 (Pro gram Error) can be made after each program oper-

PP (VPPF

AI06977

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Figure 31. Program Suspend & Resume Flowchart and Pseudo Code

Start

program_suspend_command ( ) {

Write B0h

Write 70h

Read Status

writeToFlash (any_address, 0xB0) ; writeToFlash (bank_address, 0x70) ;

/* read status register to check if program has already completed */

do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/

SR7 = 1

YES

SR2 = 1

YES

Write FFh

Read data from

another address

Write D0h

Program Continues

Program Complete

Write FFh

Read Data

} while (status_register.SR7== 0) ;

if (status_register.SR2==0) /*program completed */ { writeToFlash (bank_address, 0xFF) ; read_data ( ) ; /*read data from another block*/ /*The device returns to Read Array (as if program/erase suspend was not issued).*/

} else { writeToFlash (bank_address, 0xFF) ; read_data ( ); /*read data from another address*/ writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume program*/ } }

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Figure 32. Block Erase Flowchart and Pseudo Code

Start

Write 20h

Write Block

Address & D0h

erase_command ( blockToErase ) { writeToFlash (bank_address, 0x20) ;

writeToFlash (blockToErase, 0xD0) ; /* only A12-A20 are significannt */

/* Memory enters read status state after

the Erase Command */

Read Status

YES

VPP Invalid

Error (1)

Command

Sequence Error (1)

Erase to Protected

Block Error (1)

SR7 = 1

SR3 = 0

SR4, SR5 = 1

SR5 = 0 Erase Error (1)

SR1 = 0

End

do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/

} while (status_register.SR7== 0) ;

if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ;

if ( (status_register.SR4==1) && (status_register.SR5==1) ) /* command sequence error */ error_handler ( ) ;

if ( (status_register.SR5==1) ) /* erase error */ error_handler ( ) ;

if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ;

}

Note: If an error is found, the Status Register must be cleared before further Program/Erase operations.

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Figure 33. Erase Suspend & Resume Flowchart and Pseudo Code

Start

M36WT864TF, M36WT864BF

Write B0h

Write 70h

Read Status

SR7 = 1

SR6 = 1

Write FFh

Read data from

another block

Program/Protection Program

Block Protect/Unprotect/Lock

or or

Write D0h

Erase Continues

YES

Erase Complete

Write FFh

Read Data

erase_suspend_command ( ) { writeToFlash (bank_address, 0xB0) ;

writeToFlash (bank_address, 0x70) ; /* read status register to check if erase has already completed */

do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/

} while (status_register.SR7== 0) ;

if (status_register.SR6==0) /*erase completed */ { writeToFlash (bank_address, 0xFF) ;

read_data ( ) ; /*read data from another block*/ /*The device returns to Read Array (as if program/erase suspend was not issued).*/

} else { writeToFlash (bank_address, 0xFF) ; read_program_data ( ); /*read or program data from another address*/ writeToFlash (bank_address, 0xD0) ; /*write 0xD0 to resume erase*/ } }

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Figure 34. Lo ck i ng Ope rations Flowchart an d Pseudo Cod e

Start

Write 60h

Write

01h, D0h or 2Fh

Write 90h

Read Block

Lock States

Locking change

confirmed?

YES

Write FFh

End

locking_operation_command (address, lock_operation) { writeToFlash (bank_address, 0x60) ; /*configuration setup*/

if (lock_operation==LOCK) /*to protect the block*/ writeToFlash (address, 0x01) ; else if (lock_operation==UNLOCK) /*to unprotect the block*/ writeToFlash (address, 0xD0) ; else if (lock_operation==LOCK-DOWN) /*to lock the block*/ writeToFlash (address, 0x2F) ;

writeToFlash (bank_address, 0x90) ;

if (readFlash (address) ! = locking_state_expected) error_handler () ; /*Check the locking state (see Read Block Signature table )*/

writeToFlash (bank_address, 0xFF) ; /*Reset to Read Array mode*/ }

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Figure 35. Protection Register Program Flowchart and Pseudo Code

Start

Write C0h

Write Address

& Data

Read Status

SR7 = 1

YES

SR3 = 0

YES

SR4 = 0

YES

SR1 = 0

YES

End

VPP Invalid

Error (1, 2)

Program to Protected

Block Error (1, 2)

Program

protection_register_program_command (addressToProgram, dataToProgram) {: writeToFlash (bank_address, 0xC0) ;

writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/

do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/

} while (status_register.SR7== 0) ;

if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ;

if (status_register.SR4==1) /*program error */ error_handler ( ) ;

if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ;

}

Note: 1. Status check of SR1 (Protected Block), SR3 (V

ation or after a sequence.

2. If an error is f ound, the Status Register must be clea red before fu rther Program/Erase Controller operations.

) Invalid) and SR4 (Pro gram Error) can be made after each program oper-

PP (VPPF

AI06177

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Figure 36. Enhanced Factory Program Flowchart

SETUP PHASE VERIFY PHASE

Start

Write 30h

Address WA1

Write D0h

Address WA1

Write PD1

Address WA1

Read Status

(

Read Status

(

Check SR4, SR3

and SR1 for program,

VPP and Lock Errors

PROGRAM PHASE

Exit

SR7 = 0?

YES

SR0 = 0?

YES

Write PD1

Address WA1

Read Status

SR0 = 0?

YES

Write PD2

Address WA2

Read Status

SR0 = 0?

YES

Write PDn

Address WAn

YES

Write PD2

Address WA2

(

Read Status

SR0 = 0?

YES

Write PDn

Address WAn

(

Read Status

SR0 = 0?

YES

Write FFFFh

Address Block WA1

Note 1. Address can remain Starting Address WA1 or be incremented.

Read Status

SR0 = 0?

YES

Write FFFFh

Address Block WA1

Read Status

SR7 = 1?

YES

Check Status

End

EXIT PHASE

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Enhanced Factory Program Pseudo Code

efp_command(addressFlow,dataFlow,n) /* n is the number of data to be programmed */ {

/* setup phase */ writeToFlash(addressFlow[0],0x30); writeToFlash(addressFlow[0],0xD0); status_register=readFlash(any_address); if (status_register.b7==1){

/*EFP aborted for an error*/ if (status_register.b4==1) /*program error*/

error_handler();

if (status_register. b3==1) /*VPP invalid error*/

error_handler();

if (status_register.b1==1) /*program to protect block error*/

error_handler(); } else{

/*Program Phase*/ do{

status_register=readFlash(any_address);

/* E or G must be toggled*/

} while (status_register.b0 ==1) /*Ready for first data*/ for (i=0; i++; i< n){

writeToFlash(addressFlow[i],dataFlow[i]);

/* status register polling*/

do{

status_register=readFlash(any_address);

/* E or G must be toggled*/ } while (status_register.b0==1); /* Ready for a new data */

} writeToFlash(another_block_address,FFFFh);

M36WT864TF, M36WT864BF

/* Verify Phase */ for (i=0; i++; i< n){

} writeToFlash(another_block_address,FFFFh); /* exit program phase */

/* Exit Phase */ /* status register polling */ do{

} while (status_register.b7 ==0); if (status_register.b4==1) /*program failure error*/

if (status_register. b3==1) /*VPP invalid error*/

if (status_register.b1==1) /*program to protect block error*/

}

writeToFlash(addressFlow[i],dataFlow[i]); /* status register polling*/ do{

status_register=readFlash(any_address);

/* E or G must be toggled*/ } while (status_register.b0==1); /* Ready for a new data */

status_register=readFlash(any_address); /* E or G must be toggled */

error_handler();

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Figure 37. Quadruple Enhanced Factory Program Flowchart

SETUP PHASE

FIRST

LOAD PHASE

Check SR4, SR3

and SR1 for program,

VPP and Lock Errors

Exit

Start

Write 75h

Address WA1

Write PD1

Address WA1

Read Status

SR7 = 0?

YES

Write PD1

Address WA1

Read Status

SR0 = 0?

YES

Write PD2

Address WA2

Read Status

SR0 = 0?

YES

Write PD3

Address WA3

LOAD PHASE

(

Read Status

SR0 = 0?

YES

PROGRAM AND

VERIFY PHASE

Write PD4

Address WA4

Read Status

SR0 = 0?

(

Write FFFFh

Address Block WA1

Check Status

YES

Last Page?

YES

Note 1. Address can remain Starting Address WA1 (in which case the next Page is programmed) or can be any address in the same block.

2.The address is only checked for the first Word of each Page as the order to program the Words is fixed so subsequent Words in each Page can be written to any address.

End

EXIT PHASE

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Quadruple Enhanced Factory Program Pseudo Code

quad_efp_command(addressFlow,dataFlow,n) /* n is the number of pages to be programmed.*/

{

/* Setup phase */ writeToFlash(add ressFlow[0],0x75); for (i=0; i++; i< n){

/*Data Load Phase*/

/*First Data*/ writeToFlash(addressFlow[i],dataFlow[i,0]); /*at the first data of the first page, Quad-EFP may be aborted*/ if (First_Page) {

status_register=readFlash(any_address); if (status_register.b7==1){

/*EFP aborted for an error*/

if (status_register.b4==1) /*program error*/

error_handler();

if (status_register. b3==1) /*VPP invalid error*/

error_handler();

if (status_r egister.b1==1) /*progra m to protect block error*/

error_handler();

} } /*2nd data*/

do{

status_register=readFlash(any_address);

/* E or G must be toggled*/ }while (status_register.b0==1)

writeToFlash(addressFlow[i],dataFlow[i,1]);

M36WT864TF, M36WT864BF

/*3rd data*/

do{

}while (status_register.b0==1)

writeToFlash(addressFlow[i],dataFlow[i,2]);

/*4th data*/

do{

}while (status_register.b0==1)

writeToFlash(addressFlow[i],dataFlow[i,3]);

/* Program&Verify Phase */

do{

}while (status_register.b0==1) } /* Exit Phase */ writeToFlash(another_block_address,FFFFh); /* status register polling */ do{

status_register=readFlash(any_address);

/* E or G must be toggled */ } while (status_register.b7==0); if (status_register.b1==1) /*program to protected block error*/

error_handler(); if (status_register.b3==1) /*VPP invalid error*/

error_handler(); if (status_register.b4==1) /*program failure error*/

error_handler();

}

status_register=readFlash(any_address); /* E or G must be toggled*/

status_register=readFlash(any_address);

/* E or G must be toggled*/

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APPENDIX D. FLASH COMMAND INTERFACE STATE TABLES

Table 44. Command Interface States - Modify Table, Next State

Next CI State After Command Input

Erase

Block

Erase,

Bank Erase

Setup

(3,4)

EFP

Setup

Erase Setup EFP Setup

Quad-

Setup

Quad-EFP

Current CI State

Ready

Read

Array

Ready

(2)

Program

setup

(3,4)

Program

Setup

Program

DWP, QWP

Setup

(3,4)

Program

Setup

Lock/CR Setup Ready (Lock Error) Ready Ready (Lock Error)

OTP

Setup

Busy

OTP Busy

Setup Program Busy

Program

Busy Program Busy

Suspend Program Suspended

Setup Ready (error) Erase Busy Ready (error)

Busy Erase Busy

Erase

Program

Suspend

Setup

Busy

Suspended

Erase

Program in

Erase

Suspend

Erase Suspended

Program in Erase Suspend Busy

in Erase

Suspend

Lock/CR Setup

in Erase Suspend

Program in Erase Suspend Suspended

Erase Suspend (Lock Error)

Setup Ready (error) EFP Busy Ready (error)

EFP

Quad

EFP

Busy Verify Setup

Busy

EFP Busy

EFP V erify Quad EFP Busy Quad EFP Busy

Note: 1. CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple Enhanced Fac-

tory Program, DWP = Double Word Program, QWP = Quadruple Word Program, P/E. C. = Program/Erase Controller.

2. At Power-Up, all banks are in Read Array mode. A Read Array command issued to a busy bank, results in undetermined data output.

3. The two cycle command s hould be issued to the same bank address.

4. If the P/E.C. i s ac tive, both cy cl es are ignored.

5. The Clear Status Register command clears the Status Regist er error bits except when the P/E.C. is busy or suspended.

6. EFP and Quad E FP are all owed o nly w hen S tatu s Regi st er bit S R0 is se t to ‘0’ .E FP and Q uad EFP ar e bu sy if Bl ock Add res s is first EFP Address. Any other comma nds are treated as data.

Confirm

P/E

EFP

Resume,

Block

Unlock

Program/

Erase

Suspend

confirm,

EFP

Confirm

Setup

Program

Suspended

Program

Busy

Erase

Suspended

Erase Busy Erase Suspended

Program in

Erase

Suspend

Suspended

Program in

Erase

Suspend

Program in Erase Suspend Suspended

Busy

Erase

Suspend

(6) (6)

Read

Status

Clear

status

(5)

Ready

Program Busy

Program Suspended

Erase Busy

Program in Eras e Suspend Busy

Erase Suspend (Lock Error)

Read Electronic signature,

Read CFI

Query

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Table 45. Command Interface States - Modify Table, Next Output

Next Output State After Command Input (6)

Erase

Program

Current CI State

Prog ram Setup

Erase Setup

OTP Setup

Program in

Erase Suspend

EFP Setup

EFP B usy

EFP Verify

Quad EFP Setup

Quad EFP Busy

Lock/CR Setu p Lock/CR Setu p

in Erase

Suspend

OTP Busy Array Status Register Output Un changed

Ready

Program Busy

Erase Busy

Program/Erase

Program in

Erase Suspend

Busy

Program in

Erase Suspend

Suspended

Note: 1. CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple Enhanced Fac-

tory Program, DWP = Double Word Program, QWP = Quadruple Word Program, P/E. C. = Program/Erase Controller.

2. At Power-Up, all banks are in Read Array mode. A Read Array command issued to a busy bank, results in undetermined data output.

3. The two cycle command s hould be issued to the same bank address.

4. If the P/E.C. i s ac tive, both cy cl es are ignored.

5. The Clear Status Register command clears the Status Regist er error bits except when the P/E.C. is busy or suspended.

6. The output st ate sh ows th e type of data that appea rs at the outpu ts i f the bank addr ess is t he same as the com ma nd addre ss. A bank can be pl aced in Read Array, Read Status Register, Read Electroni c Signatu re or Read CF I Query mode , depending on the command issued. Each bank remains in its last output state until a new command is issued. The next state does not depend on the bank’s output state.

Read

Array

Array Status Register Output Unchanged

DWP, QWP

(2)

Setup

(3,4)

Block

Erase,

Bank Erase Setup

(3,4)

EFP

Setup

Quad-

EFP

Setup

Confirm

P/E

Resume,

Block

Unlock

confirm,

EFP

Confirm

Status Register

Program/

Erase

Suspend

Read

Status

Clear status

(5)

Output

Unchang ed

Output

Unchang ed

Read Electronic signature,

Read CFI

Query

Status

Electronic

Signature/

CFI

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M36WT864TF, M36WT864BF

Table 46. Command Interface States - Lock Table, Next State

Next CI State After Comman d Inp ut

Current CI State

Ready

Lock/CR

(4)

Setup

Lock/CR

Setup

OTP Setup

(4)

Block Lock

Confirm

OTP Setup Ready N/A

Block

Lock-Down

Confirm

Set CR

Confirm

Lock/CR Setup Ready (Lock error) Ready Ready (Loc k error) N/A

OTP

Setup

Busy Ready

OTP Busy

Setup Program B u sy N/A

Program

Busy Program Busy Ready

Suspend Program Suspended N/A

Setup Ready (error) N/A

Busy Eras e Busy Ready

Erase

Suspend

Lock/CR

Setup in

Erase

Eras e Suspen d ed N/A

Suspend

Setup Program in Erase Suspend Busy N/A

Program in

Erase

Busy Program in Erase Suspend Busy

Suspend

Suspend Program in Era se Suspend Suspended N/A

Lock/CR Setup

in Erase Suspe n d

Erase Suspend (Lock error) Erase Suspend

Setup Ready (error) N/A

EFP

QuadEFP

Busy Verify Setup

Busy

EFP Busy

EFP Veri fy

Quad EFP Busy

(2)

Quad EFP Busy

(2)

Note: 1. CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple Enhanced Fac-

tory Program, P/E. C. = Program/Erase Controller.

2. EFP and Quad EFP are allow ed onl y when Stat us Reg ister bit SR0 i s set to ‘0’. EFP and Quad E FP are bus y if Bloc k Addr ess is first EFP Address. Any other comma nds are treated as data.

3. EFP and Quad EFP exit when Block Address is different from first Block Address and data is FFFFh.

4. If the P/E.C. i s ac tive, both cy cl es are ignored.

5. Illegal com m ands are those not defined in the comma nd set.

EFP Exit,

Quad EFP

(3)

Exit

Illegal

Command

(5)

Erase S uspend (Lock

error)

EFP Verify

Ready

EFP Busy EFP Verify

Quad EFP

Busy

(2)

Completed

Suspended

(2)

P/E. C.

Operation

N/A

Erase

N/A

Ready

N/A

Ready

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Table 47. Command Interface States - Lock Table, Next Output

Next Output State After Command Input

Current CI State

Program Setup

Erase Setup

OTP Setup

Program in Erase

Suspend

EFP Setup

EFP B usy

EFP Verify

Quad EFP Setup

Quad EFP Busy

Lock/CR Setup

Lock/CR Setup in

Erase Suspend

OTP Busy Status Reg i st er Output Unchanged Array

Ready

Program Busy

EraseBusy

Program/Erase

Program in Erase

Suspend Busy

Program in Erase

Suspend

Suspended

Note: 1. CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple Enhanced Fac-

tory Program, P/E. C. = Program/Erase Controller.

2. EFP and Quad EFP exit when Block Address is different from first Block Address and data is FFFFh.

3. If the P/E.C. i s ac tive, both cy cl es are ignored.

4. Illegal com m ands are those not defined in the comma nd set.

Lock/CR

Setup

Status Register Out put Unchang ed Arr ay

(3)

OTP Setup

(3)

Block Lock

Confirm

Status Register Array Status Register

Block

Lock-Down

Confirm

Status Regis ter

Set CR

Confirm

EFP Exit,

Quad EFP

(2)

Exit

Illegal

Command

(4)

Output

Unchanged

Output

Unchanged

P/E. C.

Operation

Completed

Output

Unchanged

Output

Unchanged

Output

Unchanged

Output

Unchanged

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M36WT864TF, M36WT864BF

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implic ation or otherwise under any patent or patent rights of STMi croelectr onics. Specifications mentioned in thi s publicati on are sub j ect to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as cri tical comp onents in life support dev i ces or systems wi t hout express written ap proval of STMi croelect ronics.

The ST log o i s registered trademark of STMicroelectronics

All other nam es are the pro perty of their respective owners

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92/92

Datasheet M36WT864TF, M36WT864BF Datasheet (SGS Thomson Microelectronics)

Specifications and Main Features

Frequently Asked Questions

User Manual