Datasheet M36W832TE, M36W832BE Datasheet (SGS Thomson Microelectronics)

32 Mbit (2Mb x16, Boot Block) Flash Memory

and 8 Mbit (512Kb x16) SRAM, Multiple Memory Product

FEATURES SUMMARY

■ SUPPLY VOLTAGE

–V
–V
–V

■ ACCESS TIMES: 70ns and 85ns

■ LOW POWER CONSUMPTION

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h
– Top Device Code, M36W832TE: 88BAh
– Bottom Device Code, M36W832BE: 88BBh

FLASH MEMORY

■ 32 Mbit (2Mb x16) BOOT BLOCK

– 8 x 4 KWord Parameter Blocks (Top or

■ PROGRAMMING TIME

– 10µ s typical
– Double Word Programming Option
– Quadruple Word Programming Option

■ BLOCK LOCKING

– All blocks locked at Power up
– Any combination of blocks can be locked
–WPF

■ AUTOMATIC STANDBY MODE

■ PROGRAM and ERASE SUSPEND

■ 100,000 PROGRAM/ERASE CYCLES per

BLOCK

■ COMMON FLASH INTERFACE

■ SECURITY

– 128 bit user programmable OTP cells
– 64 bit unique device identifier

= 2.7V to 3.3V

DDF

= V

DDS

= 12V for Fast Program (optional)

PPF

= 2.7V to 3.3V

DDQF

Bottom Location)

for Block Lock-Down

M36W832TE

M36W832B E

Figure 1. Packages

FBGA

Stacked LFBGA66 (ZA)

12 x 8mm

SRAM

■ 8 Mbit (512Kb x 16)

■ ACCESS TIME: 70ns

■ LOW V

■ POWER DOWN FEATURES USING TWO

CHIP ENABLE INPUTS

DATA RETENTION: 1.5V

DDS

1/64May 2003

M36W832TE, M36W832BE

TABLE OF CONTENTS

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. LFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Address Inputs (A0-A18). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Address Inputs (A19-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Data Input/Output (DQ0-DQ15).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Flash Chip Enable (EF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Flash Output Enable (GF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Flash Write Enable (WF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Flash Write Protect (WPF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Flash Reset (RPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SRAM Chip Enable (E1S, E2S).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SRAM Write Enable (WS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

SRAM Output Enable (GS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

SRAM Upper Byte Enable (UBS).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SRAM Lower Byte Enable (LBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

V

Supply Voltage (2.7V to 3.3V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

DDF

V

and V

DDQF

Program Supply Voltage.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

V

PPF

V

and V

SSF

Supply Voltage (2.7V to 3.3V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

DDS

Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SSS

FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 2. Main Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0

Flash Memory Componen t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 5. Flash Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 6. Flash Security Block and Protection Register Memory Map . . . . . . . . . . . . . . . . . . . 12

SRAM Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 7. SRAM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4

Flash Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Read.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Write.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Automatic Standby.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Flash Command Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5

Table 3. Flash Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Read Memory Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2/64

M36W832TE, M36W832BE

Read Electronic Signature Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Read CFI Query Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Double Word Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Quadruple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Program/Erase Suspend Comma nd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Protection Register Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Block Lock Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Table 4. Flash Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Table 5. Flash Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 6. Flash Read Block Lock Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 7. Flash Read Protection Register and Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 8. Flash Program, Erase Times and Program/Erase Endurance Cycles . . . . . . . . . . . . 20

Flash Block Locking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Reading a Block’s Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Locked State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Unlocked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1

Lock-Down State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 9. Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 10. Protection Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Flash Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Erase Status (Bit 5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Program Status (Bit 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

V

Status (Bit 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

PPF

Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Block Protection Status (Bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Reserved (Bit 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 11. Flash Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

SRAM Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Standby/Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 12. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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M36W832TE, M36W832BE

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7

Table 13. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 8. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 9. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 14. Device Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 15. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 10. Flash Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 16. Flash Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 11. Flash Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 17. Flash Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 12. Flash Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 18. Flash Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 13. Flash Power-Up and Reset AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 19. Flash Power-Up and Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 14. SRAM Read Mode AC Waveforms, Address Controlled with UBS = LBS = V

Figure 15. SRAM Read AC Waveforms, GS Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 16. SRAM Standby AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 17. SRAM Write AC Waveforms, E1S or E2S Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 20. SRAM Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 18. SRAM Write AC Waveforms, WS Controlled, GS High during Write . . . . . . . . . . . . . . . 38

Figure 19. SRAM Write AC Waveforms, WS Controlled with GS Low . . . . . . . . . . . . . . . . . . . . . . 38

Figure 20. SRAM Write Cycle Waveform, UBS and LBS Controlled GS Low, . . . . . . . . . . . . . . . . 39

Table 21. SRAM Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 21. SRAM Low V
Figure 22. SRAM Low V
Table 22. SRAM Low V

Data Retention AC Waveforms, E1S Controlled . . . . . . . . . . . . . . . . 41

DDS

Data Retention AC Waveforms, E2S Controlled . . . . . . . . . . . . . . . . 41

DDS

Data Retention Characteristic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

DDS

. . . . . . 36

IL

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 23. Stacked LFBGA66 12x8mm, 8x8 array, 0.8mm pitch, Bottom View Package Outline . . 42
Table 23. Stacked LFBGA66, 12x8mm, 8x8 ball array, 0.8mm pitch, Pa ckage Mechani ca l Data . 42
Figure 24. Stacked LFBGA66 Daisy Chain - Package Connections (Top view through package) . 43
Figure 25. Stacked LFBGA66 Daisy Chain - PCB Connections proposal (Top view through package)44

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 24. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 25. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

APPENDIX A. FLASH MEMORY BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 26. Top Boot Block Addresses, M36W832TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 27. Bottom Boot Block Addresses, M36W832BE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 28. Query Structure Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Table 29. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Table 30. CFI Query System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

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Table 31. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Table 32. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 33. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

APPENDIX C. FLASH MEMORY FLOWCHARTS and PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . 53

Figure 26. Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 27. Double Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 28. Quadruple Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 29. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 56

Figure 30. Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 31. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 32. Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 33. Protection Register Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 60

APPENDIX D. FLASH MEMORY COMMAND INTERFACE and PROGRAM/ERASE CONTROLLER

STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 34. Write State Machine Current/Next, sheet 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 35. Write State Machine Current/Next, sheet 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 36. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

5/64

M36W832TE, M36W832BE

SUMMARY DESCRIPTION

The M36W832TE is a low voltage Multiple Memo­ry Product which combines two me mory devices;
a 32 Mbit boot block Flash memory and an 8 M bit
SRAM. Recommended operating conditions do
not allow both the F lash and the S RAM t o be ac­tive at the same time.

The memory is offered in a Stacked LFBGA66
(12x8mm, 0.8 mm pitch) package and is s upplied

with all the bits erased (set to ‘1’).

Figure 2. Logic Diagram

V

V

DDF

DDQF

V

PPF

V

DDS

Table 1. Signal Names

A0-A18

A19-A20 Address Inputs for Flash Chip only
DQ0-DQ15 Data Input/Output
V

DDF

V

DDQF

V

PPF

V

SSF

V

DDS

Address Inputs common to the Flash
and SRAM chips

Flash Power Supply
Flash Power Supply for I/O Buffers
Flash Optional Supply V oltage for Fast

Program & Erase
Flash Ground
SRAM Power Supply

A0-A20

EF

GF

WF

RPF

WPF

E1S
E2S

GS

WS

UBS

LBS

21

M36W832TE
M36W832BE

V

SSF

V

SSS

16

DQ0-DQ15

AI90161b

V

SSS

NC Not Connected Internally

Flash control functions

EF
GF
WF
RPF
WPF

SRAM control functions

, E2S Chip Enable inputs

E1S
GS
WS
UBS
LBS

SRAM Ground

Chip Enable input
Output Enable input
Write Enable input
Reset input
Write Protect input

Output Enable input
Write Enable input
Upper Byte Enable input
Lower Byte Enable input

6/64

Figure 3. LFBGA Connections (Top view through package)

M36W832TE, M36W832BE

1211109

87654321

NCNC

DDQF

V

SSF

V

A12

A13A11A20NCNC

A15 A14

DQ7

DQ14

WS

DQ15A9A16

DQ5

DQ4

DQ6DQ13NCWF

DDF

V

DDS

V

E2SDQ12V

DQ3DQ2

DQ10

DQ11A19WPF

DQ1DQ0

DQ8DQ9GSLBS

E1SA1

A2A3A6A7A18

NC

NCNCGF

SSF

EFA0A4NCNC

AI90162b

A8 A10

A

B

C

RPF

SSS

D

PPF

V

E

UBS

F

A17

G

A5

NC V

H

7/64

M36W832TE, M36W832BE

Signal Descriptions

See Figure 2 Logic Diagram and Table 1,Signal
Names, for a brief overview of the signals connect­ed to this device.

Address Inputs (A0-A18). Addresses A0-A18 are common inputs for the Flash an d the SRAM components. The Address Inputs select the cells in the memory array to access during Bu s Read operations. During Bus Write operations they con­trol the commands sent to the Command Interface of the internal state machine. The Flash memory is accessed through the Chip Enable ( Enable (WF

) signals, while the SRAM is accessed
through two Chip Enable signals (E1S
and the Write Enable signal (WS

EF) and Write

and E2S)

).

Address Inputs (A19-A20). Addresses A19-A20 are inputs for the Flash component only. The Flash memory is acc essed through the Chip E n­able (EF

) and Write Enable (WF) signals

Data Input/Output (DQ0-DQ15). The Data I/O outputs the data stored at the selected address during a Bus Read operation or inputs a command or the data to be programmed durin g a Write Bus operation.

Flash Chip Enable (EF

). The Chip Enable input

activates the Flash memory control logic, input
buffers, decoders and sense amplifiers. When
Chip Enable is at V
is in active mode. When Chip Enable is at V

and Reset is at VIH the device

IL

IH

the
memory is deselected, the outputs are high imped­ance and the power consumption is reduced to the
standby level.

Flash Output Enable (GF

). The Output Enable

controls the data outputs during the Bus Read op­eration of the Flash memory.

Flash Write Enable (

WF). The Write Enable

controls the Bus Write operation of the Flash

memory’s Command I nterface. The data and ad­dress inputs are latched on the rising edge of Chip
Enable, EF

, or Write Enable, WF, whichever oc-

curs first.

Flash Write Protect (WPF

). Write Protect is an

input that gives an additional hardware protection
for each block. When Write Protect is at V

IL

, the
Lock-Down is enabled and the protection status of
the block cannot be changed. When Write Protect
is at V

, the Lock-Down is disabled and the block

IH

can be locked or unlocked. (refer to T able 6, Read
Protection Register and Protection Register Lock).

Flash Reset (RPF

). The Reset input provides a

hardware reset of the Flash memory. When Reset
is at V

, the memory is in reset mode: the outputs

IL

are high impedance and the current consumption
is minimized. After Reset all blocks are in the
Locked state. When Reset is at V

, the device is

IH

in normal operation. Exiting reset mode the device
enters read array mode, but a negative trans ition

of Chip Enable or a change of the address is re­quired to ensure valid data outputs.

SRAM Chip Enable (E1S

, E2S). The Chip En-

able inputs activate the SRAM memory control
logic, input buffers and decoders. E1S
E2S at V

deselects the memory and reduces the

IL

power consumption to the standby level. E1S

at VIH or

and
E2S can also be used to control writing to the
SRAM memory array, while WS
is not allowed to set EF
at V

at the same time.

IH

SRAM Write Enable (WS

at V

E1S at VIL and E2S

IL,

). The Write Enable in-

remains at V

IL.

It

put controls writing to the SRAM memory array.

is active low.

WS

SRAM Output Enable (GS)

. The Output Enable

gates the outputs through the data buffers during
a read operation of t he SRAM memory. GS

is ac-

tive lo w .

SRAM Upper Byte Enable (UBS)

. The Upper

Byte Enable enables the upper bytes for SRAM
(DQ8-DQ15). UBS

SRAM Lower Byte Enable (LBS

is active low.

). The Lower
Byte Enable enables the lower bytes for SRAM
(DQ0-DQ7). LBS

Supply Voltage (2.7V to 3.3V). V

V

DDF

is active low.

DDF

pro­vides the power supply to the internal core of the
Flash Memory device. It is the main power s upply
for all operations (Read, Program and Erase).

and V

V

DDQF

provides the power supply for the Flash

V

DDQF

memory I/O pins and V
supply for

Supply Voltage (2.7V to 3.3V).

DDS

provides the power

DDS

the SRAM control pi ns. This allows all
Outputs to be powered independently of the Flash
core power supply, V
V

DDS

V

Program Su pp ly V ol t age. V

PPF

DDF

. V

can be tied to

DDQF

PPF

is both a
control input and a power suppl y pin for t he F lash
memory. The two functions are selected by the
voltage range applied to the pin. The S uppl y Volt­age V

and the Program Supply Vol tage V

DDF

PPF

can be applied in any order.
If V

V
age lower than V
against program or erase, while V

is kept in a low voltage range (0V to 3.6V)

PPF

is seen as a control input. In this case a volt-

PPF

gives an absolute protection

PPLK

PPF

> V

PP1

en­ables these functions (see Table 15, DC Charac­teristics for the relevant values). V

PPF

is only
sampled at the beginning of a program or erase; a
change in its value after the operation has started
does not have any effect on Program or Erase,
however for Double or Q uadruple Word Program
the results are uncertain.

If V
power supply pin. In this con dition V

is in the range 11.4V to 12.6V it acts as a

PPF

PPF

must be
stable until the Program/Erase algorit hm is com­pleted (see Table 17 and 18).

8/64

M36W832TE, M36W832BE

V

SSF

and V

Ground. V

SSS

SSF

and V

SSS

are the
ground reference for all voltage measurements in
the Flash and SRAM chips, respectively.

Note: Each device in a system should have V

DF

, V

DDQF

and V

decoupled with a 0.1µF ca-

PPF

D-

FUNCTIONAL DESCRIPTION

The Flash and SRAM components have separate
power supplies and grounds and are distinguished
by three chip enable inputs: EF
ory and, E1S

and E2S for the SRAM.

for the Flash mem-

Recommended operating conditions do not allow
both the Flash and the SRAM to be in active mode
at the same time. The most common example is

Figure 4. Funct i on a l Bl ock D i agram

V

DDF

EF
GF

WF

RPF

WPF

Flash Memory

32 Mbit (x16)

pacitor close to the pin. See Figure 9, AC
Measurement Load Circuit. The PCB trace
widths should be sufficient to carry the re­quired V

program and erase currents.

PPF

simultaneous read operations on the Flash and
the SRAM which would resul t in a data bus con­tention. Therefore it is recommended to put the
SRAM in the h igh impedance state whe n reading
the Flash and vice versa (see Table 2 Main Oper­ation Modes for details).

V

DDQF

V

PPF

A19-A20

A0-A18

E1S
E2S

GS

WS

UBS

LBS

V

DDS

SRAM

8 Mbit (x16)

V

SSS

V

SSF

DQ0-DQ15

AI90163

9/64

M36W832TE, M36W832BE

Table 2. Main Operation Modes

Operation

Mode

Read

Write

Block
Locking

Standby

Flash Memory

Reset X X X
Output

Disable

Read Flash must be disabled

Write Flash must be disabled

Standby/

SRAM

Power
Down

Data
Retention

Output
Disable

Note: X = VIL or VIH, V

EF

GF WF RPF WPF

V

ILVILVIHVIH

V

ILVIHVILVIH

V

XX

IL

V

XX

IH

V

ILVIHVIHVIH

V

IH

V

IH

V

IL

Any Flash mode is allowable

Any Flash mode is allowable

Any Flash mode is allowable

= 12V ± 5%.

PPFH

V

E1S E2S WS GS UBS LBS DQ15-D Q8 DQ7-DQ0

PPF

X Don’t care SRAM must be disabled Data Output

V

or

DDF

X

V

PPFH

V

Don’t care SRAM must be disabled X

IL

SRAM must be disabled Data Input

X Don’t care Any SRAM mode is allowed Hi-Z
X Don’t care Any SRAM mode is allowed Hi-Z

X Don’t care Any SRAM mode is allowed Hi-Z

XXV

V

ILVIHVIHVILVIHVIL

V

ILVIHVIHVILVILVIH

V

ILVIHVIL

V

ILVIHVIL

V

ILVIHVIL

V

IH

X

V

IH

X

V

ILVIHVIHVIH

IHVILVIL

X
X
X

X X X X X Hi-Z

V

XX

IL

X X X X X Hi-Z

V

X X X X Hi-Z

IL

V

IL

Data out

Hi-Z Data out

Data out Hi-Z

V

IL

V

IHVIL

V

ILVIH

V

IHVIH

V

IL

Data in

Hi-Z Data in

Data in Hi-Z

Hi-Z

X X Hi-Z

10/64

M36W832TE, M36W832BE

Flash Memory Componen t

The Flash Memory is a 32 Mbit (2 Mbit x 16) device
that can be erased electrically at block level and
programmed in-system on a Word-by-Word basis.
These operations can be performed using a single
low voltage (2.7 to 3.6V) supply. V

DDQF

allows to
drive the I/O pin down to 1.65V. An optional 12V
V

power supply is provided to speed up cus-

PPF

tomer programming.
The device features an asymmetrical blocked ar-

chitecture with an array of 71 blocks: 8 Parameter
Blocks of 4 KWords and 63 Main Blocks of 32
KWords. The M36W832TE has the Parameter
Blocks at the top of the memory address space
while the M36W832BE locates the Parameter
Blocks starting from the bottom. The memory
maps are shown in Figure 5, Block Addresses.

The Flash Memory features an instant, individual
block locking scheme that allo ws any block to be
locked or unlocked with no latency, enabling in­stant code and data protection. All blocks have
three levels of protection. They can be locked and
locked-down individually preventing any acciden­tal programming or erasure. There is an additional
hardware protection against program and erase.
When V

PPF

≤ V

all blocks are protected

PPLK

against program or erase. All blocks are locked at
Power Up.

Each block can be erased separately. Erase can
be suspended in order to perform either read or
program in any other block and then resumed.
Program can be s uspended to read data in any
other block and then resumed. Each block can be
programmed and erased over 100,000 cycles.

The device includes a Protection Register to in­crease the pro tection of a syste m design. The Pro­tection Register is divided into two segments, t he
first is a 64 bit area which contains a unique device
number written by ST, while the second is a 128 bit
area, one-time-programmable by the user. The
user programmable segment can be permanent ly
protected. Figure 6, shows the Flash Security
Block and Protection Register Memory Map.

Program and Erase command s are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller takes care of the tim­ings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.

Figure 5. Flash Block Addresses

Top Boot Block Addresses

1FFFFF

1FF000

1F8FFF

1F8000

1F7FFF

1F0000

00FFFF

008000

007FFF

000000

4 KWords

4 KWords

32 KWords

32 KWords

32 KWords

Total of 8

4 KWord Blocks

Total of 63

32 KWord Blocks

Bottom Boot Block Addresses

1FFFFF

1F8000

1F7FFF

1F0000

00FFFF

008000

007FFF

007000

000FFF

000000

32 KWords

32 KWords

32 KWords

4 KWords

4 KWords

Total of 63

32 KWord Blocks

Total of 8

4 KWord Blocks

Note: Also see Appendix A, Tab l es 26 and 27 for a ful l l is t i ng of the Flash B l ock Address es.

AI90164

11/64

M36W832TE, M36W832BE

Figure 6. Flash Security Block and Protection Registe r Memory Ma p

PROTECTION REGISTER

8Ch

User Programmable OTP

85h
84h

81h
80h

Note: 1. Bit 2 of the Protection Registe r Lock must no t be program m ed to 0.

Unique device number

Protection Register Lock 2

(1)

10

AI90165b

12/64

M36W832TE, M36W832BE

SRAM C o m pone nt

The SRAM is an 8 Mbit asynchronous random ac­cess memory which features a super lo w voltage
operation and low current consumption with an ac-

Figure 7. SRAM Block Diagram

DATA IN DRIVERS

A0-A10

ROW DECODER

512Kb x 16
RAM Array

2048 x 4096

COLUMN DECODER

A11-A18

cess time of 70ns in all conditions. The memory
operations can be performed using a single low
voltage supply, 2.7V to 3.3V, which is the same as
the Flash voltage supply.

DQ0-DQ7

SENSE AMPS

DQ8-DQ15

UBS
WS

GS

LBS

E2S
E1S

POWER-DOWN

CIRCUIT

UBS
LBS

E2S
E1S

AI07964

13/64

M36W832TE, M36W832BE

OPERATING MODES
Flash Bus Operations

There are six standard bus operations that control
the device. These are Bus Read, Bus Wri te, Out­put Disable, Standby, Automatic Standby and Re­set. See Table 2, Main Operation Modes, for a
summary.

Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.

Read. Read Bus operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the Common Flash Interface. Both Chip Enable and Output En­able must be at VIL in order to perform a read op­eration. The Chip Enable in put should be us ed to enable the device. Out put E nable shoul d be used to gate data onto the output. The data read de­pends on the previous command written to the memory (see Command Interface section). See Figure 10, Flash Read Mode AC Waveforms, and Table 16, Flash Read AC Cha racteristics, for de­tails of when the output becomes valid.

Read mode is the default state of the device when
exiting Reset or after power-up.

Write. Bus Write operations write Commands to the memory or latch Input Data to be programmed. A write operation is initiated when Chip Enable and Write Enable are at V V

. Commands, Input Data and Addresses are

IH

latched on the rising edge of Write Enable or Chip
Enable, whichever occurs first.

with Output Enable at

IL

See Figures 11 and 12, Flash Write AC Wave­forms, and Tables 17 and 18, Write AC Character­istics, for details of the timing requirements.

Output Disa bl e . The data outputs are high im­pedance when the Output Enable is at V

.

IH

Standby. Stan dby disables most of the inte rnal circuitry allowing a substantial reduction of the cur­rent consumption. The memory is in stand-by when Chip Enable is at V

and the device is in

IH

read mode. The power consumption is reduced to
the stand-by level and the o utputs are set to high
impedance, independently from the Output Enable
or Write Enable inputs. If Chip Enable switches to
V

during a program or erase operation, t he de-

IH

vice enters Standby mode when finished. Automatic Standby. Automatic Standby pro-

vides a low power consumption state during Read
mode. Following a read operation, the device en­ters Automatic Standby after 150ns of bus inactiv­ity even if Chip Enable is Low, V
current is reduced to I

. The data I nputs/Out-

DD1

, and the supply

IL

puts will still output data if a bus Read operation is
in progress.

Reset. During Reset mode when Output Enable is Low, V

, the memory is deselected and the out-

IL

puts are high impedance. The memory is in Reset
mode when Reset is at V

. The power consump-

IL

tion is reduced to the Standby level, independently
from the Chip Enable, Output Enable or Write En­able inputs. If Reset is pulled t o V

during a Pro-

SSF

gram or Erase, this operation is aborted and the
memory content is no longer valid.

14/64

Flash Command Interface

All Bus Write operations t o the me mory are in ter­preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper­ations. An internal Program/Erase Controller han­dles all timings and verifies the correct execution
of the Program and Erase commands. The Pro­gram/Erase Controller provides a S tatus Register
whose output may be read at any time during, to
monitor the progress of the operation, or the P ro­gram/Erase states. See Table 4, Command
Codes, for a summary o f the c ommands and see
Appendix 31, Table 34, Write State Machine Cur­rent/Next, for a summa ry of the Command Inter­face.

The Command Interface is reset to Read mode
when power is first applied, when exiting from Re­set or whenever V

is lower than V

DDF

LKO

. Com­mand sequences must be followed exactly. Any
invalid combination of commands will reset the de­vice to Read mode . Refe r to Table 3, Flas h Com ­mand Codes, in conjunction with the following text
descriptions.

Table 3. Flash Command Codes

Hex Code Command

01h

10h Program
20h Erase

2Fh

30h
40h Program

50h Clear Status Register
55h Reserved
56h

60h

70h Read Status Register
90h Read Electronic Signature
98h Read CFI Query
B0h Program/Erase Suspend
C0h Protection Register Program

D0h

FFh Read Memory Array

Block Lock confirm

Block Lock-Down confirm
Double Word Program

Quadruple Word Program
Block Lock, Block Unlock, Block Lock-

Down

Program/Erase Resume, Block Unlock
confirm

M36W832TE, M36W832BE

Read Memory Array Command. The Read

command returns the memory to its Read mode.
One Bus Write cycle is required to issue the Read
Memory Array command and return the memory to
Read mode. Subsequent read operations will read
the addressed location and output the data. When
a device Reset occurs, the memory defaults to
Read mode.

Read Status Register Command. The Status
Register indicates when a program or erase oper­ation is complete and the success or failure of the
operation itself. Issue a Read Status Register

command to read the Status Register’s cont ents.
Subsequent Bus Read operations read the Status
Register at any address, until another command is
issued. See Table 11, Status Register Bits, for de­tails on the definitions of the bits.

The Read Status Register comm and may be is­sued at any time, even during a Program/Erase
operation. Any Read attempt during a Program/
Erase operation will automatically output the con­tent of the Status Register.

Read Electronic Signature Command. The
Read Electronic Signature command reads the
Manufacturer and Device Codes and the Block
Locking Status, or the Protection Register.

The Read Electronic Signature command consists
of one write cycle, a subsequent read will output
the Manufacturer Code, the Device Code, the
Block Lock and Lock-Down Status, or the Protec­tion and Lock Register. See Tables 5, 6 and 7 for
the valid address.

Read CFI Query Command. The Read Query
Command is used to read data from the Common
Flash Interface (CFI) Memory Area, allowing pro­gramming equipment or applications to automati­cally match their interface to the characteristics of
the device. One Bus Write cycle is required to is­sue the Read Query Command. Once the com­mand is issued subsequ ent Bus Read operations
read from the Common Flash Interface Memory
Area. See Appendix B, Common Flash Interface,
Tables 28, 29, 30, 31, 32 and 33 for details on the
information contained in the Common Flash Inter­face memory area.

Block Erase Command. The Block Erase com­mand can be used to erase a bloc k. It set s all t he
bits within the selected block to ’1’. All previous
data in the block is lost. If the block is protected
then the Erase operation will abort, the data in the
block will not be changed and the S tatus Regi ster
will output the e rr o r.

Two Bus Write cycles are required to issue the
command.

■ The first bus cycle sets up the Erase command.

15/64

M36W832TE, M36W832BE

■ The second latches the block address in the

internal state machine and starts the Program/
Erase Controller.

If the second bus cycle is not Write Erase Confirm
(D0h), Status Register bits b4 and b5 a re s et and
the command aborts.

Erase aborts if Reset turns to V

. As data integrity

IL

cannot be guaranteed when the Erase operation is
aborted, the block must be erased again.

During Erase operations the memory will accept
the Read Status Re gister com mand and the P ro­gram/Erase Suspend command, all other com­mands will be ignored. Typical Erase times are
given in Table 8, Flash Program, Erase Times and
Program/Erase Endurance Cycles.

See Appendix C, Figure 30 , Erase Flowchart and
Pseudo Code, for a suggested flowchart for using
the Erase command.

Program Command. T he memory array can be
programmed word-by-word. Two bus write cycles
are required to issue the Program Command.

■ The first bus cycle sets up the Program

command.

■ The second latches the Address and the Data to

be written and starts the Program/Erase
Controller.

During Program operations the memory will ac­cept the Read Status Register command and the
Program/Erase Suspend command. Typical Pro­gram times are given in Table 8, Flash Program,
Erase Times and Program/Erase Endurance Cy­cles .

Programming aborts if Reset goe s to V

. As data

IL

integrity cannot be guaranteed when the program
operation is aborted, the block containing the
memory location must be erased and repro­grammed.

See Appendix C, Figure 26, Program Flowchart
and Pseudo Code, for the f lowchart for using the
Program command.

Doubl e Word Program Comm a nd. This feature
is offered to improve the programming throughput,
writing a page of two adjacent words in paral­lel.The two words mus t di ffer on ly f or the address
A0. Programming should n ot be attempted when
V

is not at V

PPF

PPH

.

Three bus write cycles are necessary to issue the
Double Word Program command.

■ The first bus cycle sets up the Double Word

Program Command.

■ The second bus cycle latches the Address and

the Data of the first word to be written.

■ The third bus cycle latches the Address and the

Data of the second word to be written and starts
the Program/Erase Controller.

Read operations output the Status Register con­tent after the programming has s tarted. Program­ming aborts if Reset goes to V

. As data integrity

IL

cannot be guaranteed when the program opera­tion is aborted, the block containing the memory
location must be erased and reprogrammed.

See Appendix C, Figure 27, Double Word Pro­gram Flowchart and Pseudo Code, for the flow­chart for using the Double Word Program
command.

Quadruple Word Program Command. This
feature is offered to improve the programming
throughput, writing a page of four adjacent words
in parallel.The four words must differ only for the
addresses A0 and A1. Programming should not be
attempted when

is not at V

PPF

PPH

.

V

Five bus write cycles are necessary to issue the
Quadruple Word Program command.

■ The first bus cycle sets up the Quadruple Word

Program Command.

■ The second bus cycle latches the Address and

the Data of the first word to be written.

■ The third bus cycle latches the Address and the

Data of the second word to be written.

■ The fourth bus cycle latches the Address and

the Data of the third word to be written.

■ The fifth bus cycl e latches the Addres s and th e

Data of the fourth word to be written and starts
the Program/Erase Controller.

Read operations output the Status Register con­tent after the programming has s tarted. Program­ming aborts if Reset goes to V

. As data integrity

IL

cannot be guaranteed when the program opera­tion is aborted, the block containing the memory
location must be erased and reprogrammed.

See Appendix C, Figure 28, Quadruple Word Pro­gram Flowchart and Pseudo Code, for the flow­chart for using the Quadruple Word Program
command.

Clear Status Register Command. The Clear
Status Register command can be used to reset

bits 1, 3, 4 and 5 in the Status Register to ‘0’. One
bus write cycle is required to issue the Clear Sta­tus Register command.

The bits in the Status Register do not automatical­ly return to ‘0’ when a new Program or Erase com­mand is issued. The error bits in the Status
Register should be cleared before attempting a
new Program or Erase command.

Program/Erase Suspend Command. The Pro­gram/Erase Suspend comm and is used to pause
a Program or Erase operation. One bus write cycle
is required to issue the Program/Erase c ommand
and pause the Program/Erase controller.

During Program/Erase Suspend the Command In­terface will accept the Program/Erase Resume,

16/64

M36W832TE, M36W832BE

Read Array, Read Status Register, Read Electron­ic Signature and Read CFI Query commands. Ad­ditionally, if the suspend operation was Erase then
the Program, Double Word Program, Quadruple
Word Program, Block Lock, Block Lock -Down or
Protection Program commands will also be ac­cepted. The block being erased may be protected
by issuing the Block Protect, Block Lock or Protec­tion Program commands. When the Program/
Erase Resume com mand is issued the operation
will complete. Only the blocks not being erased
may be read or programmed correctly.

During a Program/Erase Suspend, the device can
be placed in a pseudo-standby mode by taking
Chip Ena ble to V
Reset turns to V

. Program/Erase is aborted if

IH

.

IL

See Appendix C, Figure 2 9, Program or Doub le
Word Program Suspend & Resume Flowchart and
Pseudo Code, an d Figure 31, Erase Sus pend &
Resume Flowchart and Pseudo Code for flow­charts for using the Program/Erase Suspend com­mand.

Program/Erase Resume Command. The Pro­gram/Erase Resume command can be used to re­start the Program/Erase Controller after a
Program/Erase Suspend operat ion h as paused it.
One Bus Write cycle is required to issue the com­mand. Once the command is issued subsequent
Bus Read operations read the Status Register.

See Appendix C, Figure 2 9, Program or Doub le
Word Program Suspend & Resume Flowchart and
Pseudo Code, an d Figure 31, Erase Sus pend &
Resume Flowchart and Pseudo Code for flow­charts for using the Program/Erase Resume com­mand.

Protection Regist er Program Command. The
Protection Register Program c omm and is used to
Program the 128 bit user One-Time-Programma­ble (OTP) segment of the Protection Register. The
segment is programmed 16 bits at a time. When

shipped all bits in the segment are set to ‘1’. The
user can only program the bits to ‘0’.

Two write cycles are required to issue the Protec­tion Register Program command.

■ The first bus cycle sets up the Protection

Register Program command.

■ The second latches the Address and the Data to

be written to the Protection Register and starts
the Program/Erase Controller.

Read operations output the Status Register con­tent after the programming has started.

The segment can be protected by programming bit
1 of the Protection Lock Register (see Figure 6,
Flash Security Block and Protection Register
Memory Map). Attempting to program a previously
protected Protection Register will result in a Status

Register error. The protection of the Protection
Register is not reversible.

The Protection Register Program cannot be sus­pended.

Block Lock Command. The Block Lock com­mand is used to lock a block and prevent Program
or Erase operations from changing the data i n it.
All blocks are locked at power-up or reset.

Two Bus Write cycles are required to issue the
Block Lock command.

■ The first bus cycle sets up the Block Lock

command.

■ The second Bus Write cycle latc hes the block

address.

The lock status can be monitored for each block
using the Read Electronic Signature command.
Table. 10 shows the protection status after issuing
a Block Lock command.

The Block Lock bits are vo latile, once set they re­main set until a hardware reset or power-down/
power-up. They are cleared by a Blocks Unlock
command. Refer to the section, Block Locking, for
a detailed explanation.

Block Unlock Command. The Blocks Unlock
command is used to unlock a block, allowing the
block to be programmed or erased. Two Bus Write
cycles are required to issue the Blocks Unlock
command.

■ The first bus cycle sets up the Block Unlock

command.

■ The second Bus Write cycle latc hes the block

address.

The lock status can be monitored for each block
using the Read Electronic Signature command.
Table. 10 shows the protection status after issuing
a Block Unlock command. Refer to the “Flash
Block Locking” section, for a detailed explanation.

Block Lock-Down Command. A locked block
cannot be Programmed or Erased, or have its pro­tection status changed when WPF
When WPF

is high, V

the Lock-Down function is

IH,

is low, VIL.

disabled and the locked blocks can be individually
unlocked by the Block Unlock command.

Two Bus Write cycles are required to issue the
Block Lock-Down command.

■ The first bus cycle sets up the Block Lock

command.

■ The second Bus Write cycle latc hes the block

address.

The lock status can be monitored for each block
using the Read Electronic Signature command.
Locked-Down blocks revert to the locked (and not
locked-down) state when the device is reset on
power-down. Table. 10 sho ws the protection sta­tus after issuing a Block Lock-Down command.

17/64

M36W832TE, M36W832BE

Refer to the “Flash Block Locking” section for a de­tailed explanation.

Table 4. Flash Commands

Bus Write Operations

Commands

Read Memory
Array

Read Status
Register

Read Electronic
Signature

Read CFI Query 1+ Write X 98h Read QA QD
Erase 2 Write X 20h Write BA D0h

Program 2 Write X

Double Word
Program

Quadruple Word
Program

Clear Status
Register

Program/Erase
Suspend

Program/Erase
Resume

Block Loc k 2 Write X 60h Write
Block Unlock 2 Write X 60h Write
Block Loc k-Down 2 Write X 60h Write
Protection

Register Program

Note: X = Don’t Care.

(3)

(4)

1. The signature a ddresses are l i st ed in Tables 5, 6 and 7.

2. Addr 1 and Addr 2 must be consecu tive Addresses differi ng only for A0.

3. Program Addres ses 1 and 2 must be consecutive Addresses differing onl y for A0.

4. Program Addres ses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1.

5. 55h is reserved.

6. To be characterized.

1+ Write X FFh

1+ Write X 70h Read X SRD

1+ Write X 90h Read

1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle

Cycles

Op. Add Data Op. Add Data Op. Add Data Op. Add Data Op. Add Data

RA RD

Read

(2)

IDh

SA

40h

or

Write PA PD

10h

3 Write X 30h Write PA1 PD1 Write PA2 PD2

5Write X

1 Write X 50h

1Write X B0h

1Write X D0h

(6)

Write PA1 PD1 Write PA2 PD2 Write PA3 PD3 Write PA4 PD4

56h

BA 01h

D0h

BA
BA 2Fh

2 Write X C0h Write

PRA

PRD

18/64

M36W832TE, M36W832BE

Table 5. Flash Read Electronic Signature

Code Device EF GF WF A0 A1 A2-A7 A8-A11 A12-A20 DQ0-DQ7 DQ8-DQ15

Manufacture
Code

Device
Code

Note: RPF = VIH.

M36W832TE
M36W832BE

Table 6. Flash Read Block Lock Signature

Block Status EF GF WF A0 A1 A2-A7 A8-A20 A12-A20 DQ0 DQ1 DQ2-DQ15

Locked Block
Unlocked Block
Locked-Down

Block

Note: 1. A Locked Block can be protected "DQ0 = 1" or unprotected "DQ0 = 0" ; see Block Locking section.

Table 7. Flash Read Protection Register and Lock Register

Word EF

Lock

Unique ID 0
Unique ID 1
Unique ID 2
Unique ID 3
OTP 0
OTP 1
OTP 2
OTP 3

GF WF A0-A7 A8-A20 DQ0 DQ1 DQ2 DQ3-DQ7 DQ8-DQ15

V

ILVILVIH

V

ILVILVIH

V

ILVILVIH

V

ILVILVIH

V

ILVILVIH

V

ILVILVIH

V

ILVILVIH

V

ILVILVIH

V

ILVILVIH

V

ILVILVIHVILVIL

V

ILVILVIHVIHVIL

V

ILVILVIHVIHVIL

V

ILVILVIHVILVIH

V

ILVILVIHVILVIH

V

ILVILVIHVILVIH

80h Don’t Care Don’t Care

81h Don’t Care ID data ID data ID data ID data ID data
82h Don’t Care ID data ID data ID data ID data ID data
83h Don’t Care ID data ID data ID data ID data ID data
84h Don’t Care ID data ID data ID data ID data ID data
85h Don’t Care OTP data OTP data OTP data OTP data OTP data
86h Don’t Care OTP data OTP data OTP data OTP data OTP data
87h Don’t Care OTP data OTP data OTP data OTP data OTP data
88h Don’t Care OTP data OTP data OTP data OTP data OTP data

0 Don’t Care 20h 00h

0 Don’t Care BAh 88h
0 Don’t Care BBh 88h

0 Don’t Care Block Address 1 0 00h
0 Don’t Care Block Address 0 0 00h

0 Don’t Care Block Address

OTP Prot.

data

Don’t Care

See note (1)

X

(1)

1 00h

Don’t
Care

Don’t Care

V

IL

V

IL

V

IL

19/64

M36W832TE, M36W832BE

Table 8. Flash Program, Erase Times and Program /Era se Endu ranc e Cycles

Parameter Test Conditions

Min Typ Max

V

Word Program

Double Word Program
Quadruple Word Program

Main Block Program

Parameter Block Program

Main Block Erase

Parameter Block Erase

= V

PPF

V

= 12V ±5%

PPF

V

= 12V ±5%

PPF

V

= 12V ±5%

PPF

= V

V

PPF

= 12V ±5%

V

PPF

= V

V

PPF

= 12V ±5%

V

PPF

= VDDV

V

PPF

V

= 12V ±5%

PPF

V

= V

PPF

DDF

DDF

DDF

DDF

DDF

Program/Erase Cycles (per Block) 100,000 cycles

Note: 1. Typical time to program a Main or Parameter Block using the Double Word Program and the Quadruple Word Program commands

respectively.

Flash Device

10 200 µs
10 200 µs
10 200 µs

0.16/0.08

(1)

5s

0.32 5 s

0.02/0.01

(1)

4s

0.04 4 s
110s
110s

0.4 10 s

0.4 10 s

Unit

20/64

M36W832TE, M36W832BE

Flash Block Locking

The Flash Memory features an instant, individual
block locking scheme that allo ws any block to be
locked or unlocked with no latency. This locking
scheme has three levels of protection.

■ Lock/Unlock - this first level allows software-

only control of block locking.

■ Lock-Down - this second level requires

hardware interaction before locking can be
changed.

■ V

PPF

≤ V

- the third level offers a complete

PPLK

hardware protection against program and erase
on all blocks.

The protection status of each block can be set to
Locked, Unlocked, and Lock-Down. Table 10, de­fines all of the possible protection states (WPF
DQ1, DQ0), and Appendi x C, Figure 32, shows a
flowchart for the locking operations.

Reading a Block’s Lock Status. The lock status
of every block can be read in the Read Electronic
Signature mode of the device. To ent er this m ode
write 90h to the device. S ubsequent reads at the
address specified in Table 6, will output the protec­tion status of that block. The lock status is repre­sented by DQ0 and DQ1. DQ0 indicates the Block
Lock/Unlock status and is set by the Lock com­mand and cleared by the Unlo ck command. It is
also automatically set when entering Lo ck-Down.
DQ1 indicates the Lock-Down status and is set by
the Lock-Down command. It cannot be cleared by
software, only by a hardware reset or power-down.

The following sections explain the operation of the
locking system.

Locked State. The default status of all blocks on
power-up or after a hardware reset is Locked
(states (0,0,1) or (1,0,1)). Locked blocks are fully
protected from any program or erase. Any pro­gram or erase operations attempted on a locked
block will return an error in the Status Register.
The Status of a Loc ked block can be chan ged to
Unlocked or Lock-Down using the appropriate
software commands. An Unlocked block can be
Locked by issuing the Lock command.

Unlocked State. Unlocked blocks (states (0 ,0 ,0),
(1,0,0) (1,1,0)), can be programmed or erased. All
unlocked blocks return to the Locked state after a
hardware reset or when the device is powered­down. The status of an unlocked block can be
changed to Locked or Locked-Down using the ap-

propriate software commands. A locked block can
be unlocked by issuing the Unlock command.

Lock-Down State. Blocks that are Locked-Down
(state (0,1,x))are protected from program and
erase operations (as for Locked blocks) but their
protection status cannot be changed using soft­ware commands alone. A Locked or Unlocked
block can be L ocked-Down by issuing the Lo ck­Down command. Locked-Down blocks revert to
the Locked state when the device is reset or pow­ered-down.

The Lock-Down function is dependent on the WPF
input pin. When WPF=0 (VIL), the blocks in the
Lock-Down state (0,1,x) are protected from pro­gram, erase and protection status changes. When
WPF

=1 (VIH) the Lock-Down function is disabled
(1,1,1) and Locked-Down blocks can be ind ividu­ally unlocked to the (1,1,0) state by issuing the

,

software command, where they can be erased and
programmed. These blocks can then be relocked
(1,1,1) and unlocked (1,1,0) as desired while WPF
remains high. When WPF is low , blocks that were
previously Locked-Down return to the Lock-Down
state (0,1,x) regardless of any changes made
while WP F

was high. Device reset or power-down
resets all blocks , including those in Lock-Down, to
the Locked state.

Locking Operations During Erase Suspend.

Changes to block lock status can be performed
during an erase suspend by using the standard
locking command sequences to unlock, lock or
lock-down a block. This is useful in the case when
another block needs to be updated while an erase
operation is in progress.

To change block locking during an erase opera­tion, first write the Erase Suspend command, then
check the status register until it indicates that the
erase operation has been suspended. Next write
the desired Lock com mand sequence to a block
and the lock status will be changed. After complet­ing any desired lock, read, or program operations,
resume the erase operation with the Erase Re­sume command.

If a block is locked or locked-down during an erase
suspend of the same block, the locking status bits
will be changed immediately, b ut when the erase
is resumed, the erase operation will complete.

Locking operations cannot be performed du ring a
program suspend. Refer to Appendix D, Com­mand Interface and Program/Erase Controller
State, for detailed information on which com­mands are valid during erase suspend.

21/64

M36W832TE, M36W832BE

Table 9. Block Lock Status

Item Address Data

Block Lock Configuration

LOCK

Block is Unlocked DQ0=0

xx002

Block is Locked DQ0=1

Block is Locked-Down DQ1=1

Table 10. Protection Status

Lock Status

(WPF, DQ1, DQ0)

Current State

Current

Program/Erase

(1)

Allowed

After

Block Lock

Command

Next Lock Status

(WPF, DQ1, DQ0)

After

Block Unlock

Command

1,0,0 yes 1,0,1 1,0,0 1,1,1 0,0,0

1,0,1

(2)

no 1,0,1 1,0,0 1,1,1 0,0,1

1,1,0 yes 1,1,1 1,1,0 1,1,1 0,1,1
1,1,1 no 1,1,1 1,1,0 1,1,1 0,1,1
0,0,0 yes 0,0,1 0,0,0 0,1,1 1,0,0

0,0,1

(2)

no 0,0,1 0,0,0 0,1,1 1,0,1

0,1,1 no 0,1,1 0,1,1 0,1,1

Note: 1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block) as read

in the Read El ectronic Si gnature command with A1 = V

2. All blocks are loc ked at power-up, so the defa ul t configura tion is 001 or 101 according to WPF

3. A WPF

transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.

and A0 = VIL.

IH

(1)

After Block
Lock-Down

Command

status.

After

transition

WPF

1,1,1 or 1,1,0

(3)

22/64

M36W832TE, M36W832BE

Flash Status Register

The Status Register provides information on the
current or previous Program or Erase operation.
The various bits convey information and errors on
the operation. To read the Status register the
Read Status Register command can be issued, re­fer to Read Status Register Command section. To
output the contents, the Status Register is latched
on the falling edge of the Chip Enable or Output
Enable signals, and can be read until Chip Enable
or Output Enable returns to V

. Either Chip En-

IH

able or Output Enable must be toggled to updat e
the latched data.

Bus Read operations from any address always
read the Status Register during Program and
Erase operations.

The bits in the Status Register are summarized in
Table 11, Status Register Bits. Refer to Table 11
in conjunction with the following text descriptions.

Program/Erase Controller Status (Bit 7). The Pro­gra m/Erase Controller Status bit indicates whether
the Program/Erase Controller is active or inactive.
When the Program/Erase Controller Status bit is

Low (set to ‘0’), the Program/Erase Controller is
active; when the bit is High (set to ‘1’), the Pro­gram/Erase Controller is inactive, and the device
is ready to process a new command.

The Program/Erase Controller Status is Low im­mediately after a Program/Erase Suspend com­mand is issued until the Program/Erase Controller
pauses. After the Program/Erase Controller paus­es the bit is High .

During Program, Erase, o perations the Program/
Erase Controller Status bit can be polled to find the
end of the operation. Other bits in the Status Reg­ister should not be tested until the Program/Erase
Controller completes the operation and the bit is
High.

After the Program/Erase Cont roller completes its
operation the Erase Status, Program Status, V

PPF

Status and Block Lock Status bits should be tested
for errors.

Erase Suspend Status (Bit 6). The Erase Sus­pend Status bit indicates that an Erase o peration
has been suspended or is going to be suspended.
When the Erase Suspend Status bit is High (set to
‘1’), a Program/Erase Suspend command has
been issued and the memory is waiting for a Pro­gram/Erase Resume command.

The Erase Suspend Status should only be consid­ered valid when the Program/Erase Controller Sta­tus bit is High (Program/Erase Controller inactive).
Bit 7 is set within 30µs of the Program/Erase Sus­pend command being issued therefore the memo­ry may still complete the operation rather than
entering the Suspend mode.

When a Program/Erase Re sume command is is­sued the Erase Suspend Status bit returns Low.

Erase Status (Bit 5). The Erase Status bit can be
used to identify if the memory has failed to verify
that the block has erased correctly. When the
Erase Status bit is High (set to ‘1’), the Program/
Erase Controller has applied the m aximum num­ber of pulses to the block and still failed to verify
that the block has erased correctly. The Erase Sta­tus bit should be read once the Program/Erase
Controller Status bit is High (Program/Erase Con­troller inactive).

Once set High, the Erase Status bit can only be re­set Low by a Clear Status Register command or a
hardware reset. If set High it should be reset be­fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.

Program Status (Bit 4). The Program Status bit
is used to identify a Program failure. When the
Program Status bit is High (set to ‘1’), the Pro­gram/Erase Controller has applied the maximum
number of pulses to the byte and still failed to ver­ify that it has programmed correctly. The Program
Status bit should be read once the Program/Erase
Controller Status bit is High (Program/Erase Con­troller inactive).

Once set High, the Program Status bit can only be
reset Low by a Clear Status Register command or
a hardware reset. If set High it should be reset be­fore a new command is issued, otherwise the new
command will appear to fail.

Status (Bit 3). Th e V

V

PPF

used to identify an invalid voltage on the V
during Program and Erase operations. The V

Status bit can be

PPF

PPF

pin

PPF

pin is only sampled at the beginning of a Program
or Erase operation. Indeterminate results can oc­cur if V

When the V
voltage on the V
voltage; when the V
‘1’), the V
V

PPF

becomes invalid during an operation.

PPF

Status bit is Low (set to ‘0’), the

PPF

pin has a voltage that is below the

PPF

Lockout Voltage, V

pin was sampled at a valid

PPF

Status bit is High (set to

PPF

, the memory is pro-

PPLK

tected and Program and Erase operations cannot
be performed.

Once set High, the V

Status bit c an only be re-

PPF

set Low by a Clear Status Register command or a
hardware reset. If set High it should be reset be­fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.

Program Suspend Status (Bit 2). The Program
Suspend Status bit indicates that a Program oper­ation has been suspended. When the Program
Suspend Status bit is High (set to ‘1’), a Program/
Erase Suspend command has been issued and
the memory is waiting for a Program/Erase Re­sume command. The Program Suspend Status
should only be considered valid when the Pro-

23/64

M36W832TE, M36W832BE

gram/Erase Controller Status bit is High (Program/

Erase Controller inactive). Bit 2 is set wi thin 5µs of
the Program/Erase Suspend comm and being is­sued therefore the memory may still complete t he
operation rather than entering the Suspend mode.

When a Program/Erase Re sume command is is­sued the Program Suspend Status bit returns Low.

Block Protection Status (Bit 1). The Block Pro­tection Status bit can be used to identify if a Pro­gram or Erase operation has tried to modify the
contents of a locked block.

When the Block Protection Status bit is High (set
to ‘1’), a Program or Erase operation has been at­tempted on a locked block.

Once set High, the Block Protection Status bit can
only be reset Low by a Clear Status Register com­mand or a hardware reset. If set High it should be
reset before a new command is issued, otherwise
the new command will appear to fail.

Reserved (Bit 0). Bit 0 of the Status Register is
reserved. Its value must be masked.

Note: Refer to Appendix C, Flowcharts and
Pseudo Codes, for using the Status Register.

Table 11. Flash Status Register Bits

Bit Name Logic Level Definition

7 P/E.C. Status

6 Erase Suspend Status

5 Erase Status

4 Program Status

’1’ Ready
’0’ Busy
’1’ Suspended
’0’ In progress or Completed
’1’ Erase Error
’0’ Erase Success
’1’ Program Error
’0’ Program Success

V

3

2 Program Suspend Status

1 Block Protection Status

0 Reserved

Note: Logic level ’1’ is High, ’0’ is Low.

PPF

Status

V

’1’
’0’
’1’ Suspended

’0’ In Progress or Completed
’1’ Program/Erase on protected Block, Abort
’0’ No operation to protected blocks

Invalid, Abort

PPF

V

OK

PPF

24/64

M36W832TE, M36W832BE

SRAM Operations

There are five standard operations that control the
SRAM component. These are Bus Read, Bus
Write, Standby/Power-down, Data Retention and
Output Disable. A summary is shown in Table 2,
Main Operation Modes

Read. Read operations are used to output the
contents of the SRAM Array.

The SRAM is in Byte Read mode wh enev er Write
Enable, WS
Chip Enable, E1S
at V

IH

, is at VIH, Output Enable, GS, is a t VIL,

, is at VIL, Chip Enable, E2S, is

, and UBS or LBS is at VIL.

The SRAM is in Word Read mode whenever Write
Enable, WS
Byte Enable inputs UBS

, is at VIH, Output Enable, GS, is a t VIL,

and LBS are both at V

and the two Chip Enable inputs, E1S, and E2S are

Don’t Care.
Valid data will be available on the output pins after

a time of t

after the last stable address. If the

AVQV

Chip Enable or Output Enable access times are
not met, data access will be measured from the
limiting parameter (t

E1LQV

, t

E2HQV

, or t

GLQV

) rath­er than the address. Dat a out may be inde termi­nate at t

E1LQX

, t

will always be valid at t

E2HQX

and t

(see Table 20, Figures

AVQV

, but data lines

GLQX

14 and 15).
Write. Write operations are used to write da ta to

the SRAM. The SRAM is in Write mode whenever

and E1S are at VIL, and E2S is at VIH. Either

WS
the Chip Enable inputs, E1S
Enable input, WS

, must be deas serted during ad-

and E2S, or the Write

dress transitions for subsequent write cycles.

A Write operation is initiated when E1S
E2S is at V
o the falling edge of E1S
the falling edge of WS

and WS is at VIL. The data is latched

IH

, the rising edge of E2S or

, whichever occurs last. The
Write cycle is terminated on the rising edge of
E1S

, the rising edge of WS or the falling edge of

E2S, whichever occurs first.
If the Output is enabled ( E1S

=VIL), then WS will return the outputs to high

GS
impedance within t

WLQZ

=VIL, E2S=VIH and

of its falling edge. Care
must be taken to avoid bus content ion in this type
of operation. The Data input mu st be valid for t

before the rising edge of Write Enable, for

VWH

t

before the rising edge of E1S or for t

DVE1H

before the fallin g edge of E2S, whi chever occurs

IL

first, and remain valid for t

WHDX

, t

E1HAX

(see Table 21, Figure 17, 18, 19 and 20).
Standby/Power-Down . The SRAM component

has a chip enabled power-down feature wh ich in­vokes an automatic standby m ode (see Table 20
and Figure 16). The SRAM is in Standby mode
whenever either Chip Enable is deasserted, E1S
at VIH or E2S at VIL.

Data Retention. The SRAM data retention per­formance as V

goes down to VDR are de-

DDS

scribed in Table 22, Figures 21 and 22, SRAM
Low V
Controlled and SRAM Low V

Data Retention AC Waveforms, E1S

DDS

Data Retention

DDS

AC Waveforms, E2S Controlled, respectively.
Output Disable. The data outputs are high im-

pedance when the Output Enable, GS
with Write Enable, WS, at VIH.

is at VIL,

DVE2L

or t

E2LAX

, is at V

D-

IH

25/64

M36W832TE, M36W832BE

MAXIMUM RATIN G

Stressing the device ab ove the rating listed in the
Absolute Maximum Ratings table m ay cause per­manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions ab ove those i ndicated in t he
Operating sections of this specificat ion is not im-

Table 12. Absolute Maximum Ratings

Symbol Parameter

T

A

T

BIAS

T

STG

V

IO

V

, V

DDF

DDQF

V

PPF

V

DDS

Note: 1. Depends on range.

Ambient Operating Temperature

Temperature Under Bias –40 125 °C
Storage Te mperat ure –55 150 °C
Input or Output Voltage –0.5
Flash Supply Voltage –0.6 4.1 V
Program Voltage –0.6 13 V
SRAM Supply Voltage –0.5 3.6 V

(1)

plied. Exposure to Absolute Maximum Rating con­ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and ot her relevant quality docu­ments.

Value

Min Max

–40 85 °C

V

+0.5

DDQF

Unit

V

26/64

DC AND AC PARAMETERS

This section summarizes the operat ing and mea­surement conditions, and the DC and AC charac­teristics of the device. The parameters in t he DC
and AC characteristics Tables that follow, are de­rived from tests performed under the Measure­ment Conditions summarized in Table 13,
Operating and AC Measurem ent Conditions. De­signers should check that the operating conditions

in their circuit match the measurement conditions
when relying on the quoted parameters.

The operating and A C measurement parame ters
given below (see Table 13, Operating and AC
Measurement Conditions) a re those of t he stand­alone Flash and SRAM devices and some differ
from those of the stacked product.

Table 13. Operating and AC Measurement Conditions

M36W832TE, M36W832BE

SRAM Flash Memory

Parameter

Min Max Min Max

V

Supply Voltage

DDF

Supply Voltage

V

DDQF

Supply Voltage

V

DDS

– – 2.7 3.6 V
– – 2.7 3.6 V

2.7 3.3 – – V
Ambient Operating Temperature – 40 85 – 40 85 °C
Load Capacitance (C

)

L

50 50 pF
Input Rise and Fall Times 3.3 5 ns
Input Pulse Voltages
Input and Output Timing Ref. Voltages

Figure 8. AC Measurement I/O Waveform

V

DDQ

V

0V

AI90166

DDQ

0 to V

DDQF

V

/2 V

DDQF

Figure 9. AC Me asurement Load Circuit

/2

V

DDQF

V

DDF

0 to V

DDQF

DDQF

/2

V

DDQF

25kΩ

Units70 70 / 85

V
V

Note: V

DDQ

means V

DDQF

= V

DDS

0.1µF

0.1µF

DEVICE
UNDER

TEST

CL includes JIG capacitance

Table 14. Device Capacitance

Symbol Parameter Test Condition Max Unit

V

C

IN

C

OUT

Note: Sampled only, not 100% tested.

Input Capacitance
Output Capacitance

= 0V, f=1 MHz

IN

V

= 0V, f=1 MHz

OUT

12 pF
16 pF

CL

25kΩ

AI90167

27/64

M36W832TE, M36W832BE

Table 15. DC Characteristics

Symbol Parameter Device Test Condition Min Typ Max Unit

I

LI

I

LO

I

DDS

I

DDD

I

DD

Input Leakage Current

Flash &

SRAM

Flash

Output Leakage Current

SRAM

Flash

V

Standby Current

DD

SRAM

Supply Current
(Reset)

Flash

Supply Current SRAM

0V ≤ V

0V

≤

0V

≤

SRAM Outputs Hi-Z

EF

= V

V

DDQF

E1S

or E2S ≤ 0.3V

V

V

≥

IN

DDS

f = f

(Address and Data

max

inputs only)

f = 0 (GS

, WS, UBS and LBS)

E1S

or E2S ≤ 0.3V

V

≥

V

IN

DDS

f = 0, V

RPF

V

f = f

= 1/t

max

V

DDS

I

= 0 mA, f = 1MHz, CMOS

OUT

V

≤

IN

DDQF

VOUT ≤ VDDQF,

VOUT ≤ VDDQF,

± 0.2V

DDQF

= V

≥ V

– 0.3V or V

≥ V

– 0.3V or V

DDS

= V

OUT

AVAV

= V

max

DDF

– 0.3V

DDS

IN

– 0.3V

DDS

IN

= V

max

DDS

± 0.2V

SSF

= 0mA

, CMOS levels

max

DDS

Levels

≤

≤

0.3V

0.3V

±2 µA

±10 µA

±1 µA

15 50 µA

825µA

825µA

15 50 µA

715mA

12mA

I

DDR

I

DDW

I

DDE

I

DDES

I

PP

I

PP1

I

PP2

I

PPW

Supply Current
(Read)

Supply Current

(Program)

Supply Current
(Erase)

Supply Current
(Program/Erase
Suspend)

Program Current
(Read or Standby)

Program Current
(Reset)

Program Current
(Program)

Flash

Flash

Flash

Flash

Flash

Flash

Flash

EF

= VIL, GF

=

Program in progress

= 12V ± 5%

V

PPF

Program in progress

= V

V

PPF

Erase in progress

= 12V ± 5%

V

PPF

Erase in progress

= V

V

PPF

E

F = V

DDQF

Erase suspended

> V

V

PPF

V

≤ V

PPF

F = V

RP

Program in progress

= 12V ± 5%

V

PPF

Program in progress

= V

V

PPF

V

SSF

f = 5 MHz

IH,

DDF

DDF

± 0.2V,

DDF

DDF

± 0.2V

DDF

918mA

510mA

10 20 mA

520mA

10 20 mA

15 50 µA

400 µA

15µA

15µA

110mA

15µA

28/64

M36W832TE, M36W832BE

Symbol Parameter Device Test Condition Min Typ Max Unit

I

PPE

V

IL

V

IH

V

OL

V

OH

V

PPL

V

PPH

V

PPLK

Program Current
(Erase)

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

Program Voltage
(Program or Erase
operations)

Program Voltage
(Program or Erase
operations)

Program Voltage
(Program and Erase
lock-out)

Erase in progress

= 12V ± 5%

V

Flash

PPF

Erase in progress

= V

V

PPF

DDF

Flash &

SRAM

Flash &

SRAM

Flash &

SRAM

Flash &

SRAM

V

DDQF

V

DDQF

V

DDQF

V

DDQF

= V

= V

= V
I

OL

= V

I

= –100µA

OH

DDS

= 100µA

DDS

DDS

DDS

= V

= V

≥

≥

2.7V

2.7V

DD

DD

min

min

–0.3 0.8 V

0.7V

QF

2.4 V

Flash 1.65 3.6 V

Flash 11.4 12.6 V

Flash 1 V

310mA

15µA

DD

V

DDQF

+0.4

0.1 V

V

V

Supply Voltage

V

LKO

DDF

(Program and Erase

Flash 2 V

lock-out)

29/64

M36W832TE, M36W832BE

Figure 10. Flash Read Mode AC Waveforms

A0-A20

tAVAV
VALID

tAVQV

EF

tELQV

tELQX

GF

tGLQX

DQ0-DQ15

ADDR. VALID

CHIP ENABLE

Table 16. Flash Read AC Characteristics

OUTPUTS

ENABLED

Symbol Alt Parameter

t

AVAV

t

AVQV

t

AXQX

t

EHQX

t

EHQZ

t

ELQV

t

ELQX

t

GHQX

t

GHQZ

t

GLQV

t

GLQX

Note: 1. Sampled only, not 100% tested.

2. GF

t

Address Valid to Next Address Valid Min 70 85 ns

RC

t

Address Valid to Output Valid Max 70 85 ns

ACC

(1)

t

Address Transition to Output Transition Min 0 0 ns

OH

(1)

t

(1)

(2)

(1)

(1)

(1)

(2)

(1)

may be delayed by up to t

Chip Enable High to Output Transition Min 0 0 ns

OH

t

Chip Enable High to Output Hi-Z Max 20 20 ns

HZ

t

Chip Enable Low to Output Valid Max 70 85 ns

CE

t

Chip Enable Low to Output Transition Min 0 0 ns

LZ

t

Output Enable High to Output Transition Min 0 0 ns

OH

t

Output Enable High to Output Hi-Z Max 20 20 ns

DF

t

Output Enable Low to Output Valid Max 20 20 ns

OE

t

Output Enable Low to Output Transition Min 0 0 ns

OLZ

ELQV

- t

after the fal l in g edge of EF without increasing t

GLQV

tGLQV

tEHQX

tEHQZ

tGHQX

tGHQZ

VALID

DATA VALID STANDBY

Flash Device

70 85

.

ELQV

tAXQX

AI90168b

Unit

30/64

Figure 11. Flash Write AC Waveforms, Write Enable Controlled

M36W832TE, M36W832BE

AI90169b

tWHAX

PROGRAM OR ERASE

tAVAV

VALID

tAVWH

tWHGL

tELQV

tWHEL

tQVWPL

tQVVPL

READ

1st POLLING

STATUS REGISTER

OR DATA INPUT

A0-A20

EF

tELWL tWHEH

GF

tWHWL

WF

tWLWH

tWHDX

COMMAND CMD or DATA STATUS REGISTER

tDVWH

DQ0-DQ15

tWPHWH

WPF

tVPHWH

PPF

V

SET-UP COMMAND CONFIRM COMMAND

31/64

M36W832TE, M36W832BE

Table 17. Flash Write AC Characteristics, Write Enable Controlled

Symbol Alt Parameter

Flash Device

Unit

70 85

t

AVAV

t

AVWH

t

DVWH

t

ELWL

t

ELQV

(1,2)

t

QVVPL

t

QVWPL

t

VPHWH

t

WHAX

t

WHDX

t

WHEH

t

WHEL

t

WHGL

t

WHWL

t

WLWH

t

WPHWH

Note: 1. Sampled only, not 100% tested.

2. Applicable if V

(1)

t

Write Cycle Time Min 70 85 ns

WC

t

Address Valid to Write Enable High Min 45 45 ns

AS

t

Data Valid to Write Enable High Min 45 45 ns

DS

t

Chip Enable Low to Write Enable Low Min 0 0 ns

CS

Chip Enable Low to Output Valid Min 70 85 ns
Output Valid to V
Output Valid to Write Protect Low Min 0 0 ns

t

VPSVPPF

t

AH

t

DH

t

CH

High to Write Enable High

Write Enable High to Address Transition Min 0 0 ns
Write Enable High to Data Transition Min 0 0 ns
Write Enable High to Chip Enable High Min 0 0 ns
Write Enable High to Chip Enable Low Min 25 25 ns
Write Enable High to Output Enable Low Min 20 20 ns

t

Write Enable High to Write Enable Low Min 25 25 ns

WPH

t

Write Enable Low to Write Enable High Min 45 45 ns

WP

Write Protect High to Write Enable High Min 45 45 ns

is seen as a logic input (V

PPF

PPF

Low

PPF

Min 0 0 ns

Min 200 200 ns

< 3.6V).

32/64

Figure 12. Flash Write AC Waveforms, Chip Enable Controlled

M36W832TE, M36W832BE

AI90170b

tEHAX

PROGRAM OR ERASE

tAVAV

VALID

tAVEH

tEHGL

tELQV

tQVWPL

CMD or DATA STATUS REGISTER

tQVVPL

READ

1st POLLING

STATUS REGISTER

OR DATA INPUT

CONFIRM COMMAND

A0-A20

WF

tWLEL tEHWH

GF

tEHEL

EF

tELEH

tEHDX

tDVEH

DQ0-DQ15

tWPHEH

COMMAND

WPF

tVPHEH

PPF

V

POWER-UP AND

SET-UP COMMAND

33/64

M36W832TE, M36W832BE

Table 18. Flash Write AC Characteristics, Chip Enable Controlled

Symbol Alt Parameter

Flash Device

Unit

70 85

t

AVAV

t

AVEH

t

DVEH

t

EHAX

t

EHDX

t

EHEL

t

EHGL

t

EHWH

t

ELEH

t

ELQV

(1,2)

t

QVVPL

t

QVWPL

t

VPHEH

t

WLEL

t

WPHEH

Note: 1. Sampled only, not 100% tested.

2. Applicable if V

(1)

t

Write Cycle Time Min 70 85 ns

WC

t

Address Valid to Chip Enable High Min 45 45 ns

AS

t

Data Valid to Chip Enable High Min 45 45 ns

DS

t

Chip Enable High to Address Transition Min 0 0 ns

AH

t

Chip Enable High to Data Transition Min 0 0 ns

DH

t

Chip Enable High to Chip Enable Low Min 25 25 ns

CPH

Chip Enable High to Output Enable Low Min 25 25 ns

t

Chip Enable High to Write Enable High Min 0 0 ns

WH

t

Chip Enable Low to Chip Enable High Min 45 45 ns

CP

Chip Enable Low to Output Valid Min 70 85 ns
Output Valid to V
Data Valid to Write Protect Low Min 0 0 ns

t

VPSVPPF

t

CS

High to Chip Enable High

Write Enable Low to Chip Enable Low Min 0 0 ns
Write Protect High to Chip Enable High Min 45 45 ns

is seen as a logic input (V

PPF

PPF

Low

PPF

Min 0 0 ns

Min 200 200 ns

< 3.6V).

34/64

Figure 13. Flash Power-Up and Reset AC Waveforms

EF,GF

WF,

RPF

tPHWL

tPHEL

tPHGL

M36W832TE, M36W832BE

tPHWL

tPHEL

tPHGL

tVDHPH

VDDF, VDDQF

Power-Up Reset

Table 19. Flash Power-Up and Reset AC Characteristics

Symbol Parameter Test Condition

t

PHWL

t

PHEL

t

PHGL

t

PLPH

t

VDHPH

Note: 1. The de vice Reset is possible but not guarant eed if t

2. Sampled only, not 100% tested.

3. It is important to ass ert RPF

Reset High to Write Enable Low, Chip Enable Low,
Output Enable Low

(1,2)

Reset Low to Reset High Min 100 100 ns

(3)

Supply Voltages High to Reset High Min 50 50 µs

in order to all ow proper CP U i ni tializat i on during power up or reset .

PLPH

< 100ns.

During

Program and

Erase

others Min 30 30 ns

tPLPH

AI90171

Flash Device

Unit

70 85

Min 50 50 µs

35/64

M36W832TE, M36W832BE

Figure 14. SRAM Read Mode AC Waveforms, Address Controlled with UBS = LBS = V

tAVAV

A0-A18

tAVQV

tAXQX

DQ0-DQ15

Note: E1S = Low, E2 S = High, GS = Low, WS = High.

VALID

DATA VALIDDATA VALID

AI90180

Figure 15. SRAM Read AC Waveforms, GS Controlled

tAVAV

A0-A18

tE1LQV tE1HQZ

E1S

tE1LQX

tE2HQV

E2S

VALID

IL

tE2LQZ

tE2HQX

tGLQV

GS

tGLQX

DQ0-DQ15

tPU

V

DDS

Note: Write Enable (WS) = High. Address Valid prior to or at the same time as E1S goes Low and E2S goes High.

50% 50%

DATA VALID

tGHQZ

tPD

Figure 16. SRAM Standby AC Waveforms

E1S

E2S

I

DD

I

DDS

tPU

50%

AI07965

tPD

AI07985

36/64

Table 20. SRAM Read AC Characteristics

Symbol Alt Parameter

M36W832TE, M36W832BE

SRAM

Unit

Min M ax

t

AVAV

t

AVQV

t

AXQX

t

E1HQZ

t

E2LQZ

t

E1LQV

t

E2HQV

t

E1LQX

t

E2HQX

t

GHQZ

t

GLQV

t

GLQX

(1)

t

PD

(1)

t

PU

Note: 1. Sampled on l y. Not 100% test ed.

t

RC

t

ACC

t

OH

t

CHZ1

t

ACS1

t

CLZ1

t

OHZ

t

OE

t

OLZ

Read Cycle Time 70 ns
Address Valid to Output Valid 70 ns
Address Transition to Output Transition 10 ns

Chip Enable 1 High to Output Hi-Z 25 ns

Chip Enable 1 Low or Chip Enable 2 High to Output Valid 70 ns

Chip Enable 1 Low to Output Transition 10 ns

Output Enable High to Output Hi-Z 25 ns
Output Enable Low to Output Valid 35 ns
Output Enable Low to Output Transition 5 ns
Chip Enable 1 High or Chip Enable 2 Low to Power Down 70 ns

Chip Enable 1 Low or Chip Enable 2 High to Power Up 0 ns

Figure 17. SRAM Write AC Waveforms, E1S or E2S Controlled

tAVAV

tAVE1L

ADDRESS VALID

tAVE1H

tAVE2L

tE1LE1H

A0-A18

tE1HAX

E1S

E2S

WS

DQ0-DQ15

Note: 1. DQ0-DQ1 5 ar e hi gh impedanc e if GS = VIH.

2. If E1S

or E2S an d WS are deasse rted at the same time, DQ0-DQ15 rema in hi gh impedanc e.

tWLE1H

tWLE2L

tDVE1H

tDVE2L

tE2HE2L

tE1HDZ

tE2LDZ

INPUT VALID

tAVE2H tE2LAX

AI07966

37/64

M36W832TE, M36W832BE

Figure 18. SRAM Write AC Waveforms, WS Controlled, GS High during Write

tAVAV

A0-A18

E1S

E2S

WS

GS

DQ0-DQ15

tAVWL

tGHQZ tWHDZ

Note 2

VALID

tAVWH

tE1LWH

tE2HWH

tWLWH

tDVWH

INPUT VALID

tWHAX

Note: 1. DQ0-DQ1 5 ar e hi gh impedanc e if GS = VIH.

or E2s an d WS are deasserted at the same tim e, DQ0-DQ15 rem ai n high impe dance.

2. If E1S

Figure 19. SRAM Write AC Waveforms, WS Controlled with GS Low

tAVAV

A0-A18

E1S

E2S

WS

DQ0-DQ15

tWLQZ

Note 3

VALID

tAVWH

tE1LWH
tE2HWH

tWLWHtAVWL

tDVWH

INPUT VALID

AI07967

tWHAX

tWHQX

tWHDZ

Note: 1. If E1S, E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance.

2. The minimum writ e cycle time (t

3. During this per i od, the I/O pins are i n output mode and input signals should not be applie d.

) is the sum of t

AVAV

WLQZ

and t

DVWH

.

38/64

AI07968

M36W832TE, M36W832BE

Figure 20. SRAM Write Cycle Waveform, UBS and LBS Controlled GS Low,

tAVAV

A0-A18

E1S

E2S

UBS, LBS

tAVWL

WS

tWLQZ

DQ0-DQ15

Note: 1. During this period, the I/O pins are in output mode and input signals should not be applied.

Note 1

VALID

tAVBH

tBLBH

tDVBH

INPUT VALID

tBHAX

tBHQX

tBHDZ

AI07969

39/64

M36W832TE, M36W832BE

Table 21. SRAM Write AC Characteristics

Symbol Alt Parameter

SRAM

Unit

Min Max

t

AVAV

t

AVE1L

t

AVE2H

t

AVWL,

t

AVE1H

t

AVE2L

t

AVBH

t

AVWH

t

BLBH

t

DVE1H

t

DVE2L

t

DVWH

t

DVBH

t

E1HAX

t

E2LAX

t

WHAX

t

BHAX

t

E1HDZ

t

E2LDZ

t

WHDZ

t

BHDZ

t

E1LE1H,

t

E1LWH

t

E2HE2L,

t

E2HWH

t

GHQZ

t

WHQX

t

BHQX

t

WLQZ

t

WLWH

t

WLE1H

t

WLE2L

t

WC

Write Cycle Time 70 ns

,

,

,

t

t

t

t

AS

AW

AW

BW

Address Valid to Beginning of Write 0 ns

Address Valid to Chip Enable 1 Low or Chip Enable 2
High

60 ns

Address Valid to Write Enable High 60 ns
UBS, LBS Low to UBS, LBS High 60 ns

,

,

t

DW

Input Valid to End of Write 30 ns

,

,

t

WR

End of Write to Address Change 0 ns

,

,

t

t

CW1

t

CW2

t

GHZ

t

t

WHZ

t

HD

DH

WP

Address Transition to End of Write 0 ns

Chip Enable 1 Low to End of Write 60 ns

Chip Enable 2 High to End of Write 60 ns

Output Enable High to Output Hi-Z 25 ns

Write Enable High to Input Transition 10 ns

Write Enable Low to Output Hi-Z 20 ns

Write Enable Pulse Width 50 ns

40/64

M36W832TE, M36W832BE

Figure 21. SRAM Low V

V

DDS

E1S

Figure 22. SRAM Low V

V

DDS

E2S

Data Retention AC Waveforms, E1S Controlled

DDS

DATA RETENTION MODE

V

DDS (min)

tCDR

E1S > V

Data Retention AC Waveforms, E2S Controlled

DDS

V

DDS (min)

tCDR

VDR > 1.5V

- 0.3V and E2S < 0.3V

DDS

or E2S > V

DATA RETENTION MODE

VDR > 1.5V

E2S < 0.3V

DDS

- 0.3V

V

DDS (min)

tR

AI07970

V

DDS (min)

tR

AI07982

Table 22. SRAM Low V

Data Retention Characteristic

DDS

Symbol Parameter Test Condition Min Typ Max Unit

V

I

DDDR

V

t

CDR

Note: 1. Sampled only. Not 100% tested.

Supply Current (Data Retention)

Supply Voltage (Data Retention) 1.5 3.3 V

DR

Chip Disable to Power Down 0 ns

t

Operation Recovery Time

R

= 1.5V, E1S ≥ V

DDS

V

IN

≥ V

– 0.3V or V

DDS

No input may exceed V

DDS

IN

DDS

– 0.3V,

0.3V

≤

+ 0.3V

420µA

70

ns

41/64

M36W832TE, M36W832BE

PACKAGE MECHANICAL

Figure 23. Stacked LFBGA66 12x8mm, 8x8 array, 0.8mm pitch, Bottom View Package Outline

D
D2
D1

E

E1

BALL "A1"

Note: Drawing is not to scale.

SE

A

FDFE

SD

e

b

e

ddd

A2

A1

BGA-Z12

Table 23. Stacked LFBGA66, 12x8m m, 8x8 ball arra y, 0.8mm pitch, Package Mechan ica l Data

Symbol

A 1.400 0.0551
A1 0.300 0.0118
A2 1.100 0.0433

b 0 .400 0.300 0.500 0.0157 0.0118 0.0197

D 12.000 – – 0.4724 – –

D1 5.600 – – 0.2205 – –
D2 8.800 – – 0.3465 – –

ddd 0.100 0.0039

E 8.000 – – 0.3150 – –

E1 5.600 – – 0.2205 – –

e 0 .800 – – 0.0315 – –
FD 1.600 – – 0.0630 – –
FE 1.200 – – 0.0472 – –

SD 0.400 – – 0.0157 – –

SE 0.400 – – 0.0157 – –

Typ Min Ma x Typ Min Max

millimeters inches

42/64

M36W832TE, M36W832BE

Figure 24. Stacked LFBGA66 Daisy Chain - Package Connections (Top view through package )

1211

10983

7

6

5412

AI90172b

A

B

C

D

E

F

G

H

43/64

M36W832TE, M36W832BE

Figure 25. Stacked LFBGA66 Daisy Chain - PCB Connections proposal (Top view through package)

END

POINT

1211

109837

6

542

AI90173b

44/64

POINT

START

1

A

B

C

D

E

F

G

H

M36W832TE, M36W832BE

PART NUMBERING

Table 24. Ordering Information Scheme

Example: M36 W 8 32T E 70 ZA 6 T

Device Type

M36 = MMP (Flash + SRAM)

Operating Voltage

W = V

SRAM Chip Size & Organization

8 = 8 Mbit (512Kb x 16 bit)

Flash Chip Size & Organization

32T = 32 Mbit (x16), Boot Block, Top configuration
32B = 32 Mbit (x16), Boot Block, Bottom configuration

SRAM Component

E = 8Mb, 0.16µm, 70ns, 3.0V

Speed

70 = 70ns
85 = 85ns

= 2.7V to 3.3V, V

DDF

DDS

= V

= 2.7V to 3.3V

DDQF

Package

ZA = LFBGA66: 12x8mm, 0.8mm pitch

Temperature Range

1 = 0 to 70°C
6 = –40 to 85°C

Option

T = Tape & Reel packing
S = Special Tape

Devices are shipped from the factory with the memory content bits erased to ’1’.

Table 25. Daisy Chain Ordering Scheme

Example: M36W832TE -ZA T

Device Type

M36W832TE

Daisy Chain

-ZA = LFBGA66: 12x8mm, 0.8mm pitch

Option

T = Tape & Reel Packing

For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,
please contact the STMicroelectronics Sales Office nearest to you.

45/64

M36W832TE, M36W832BE

APPENDIX A. FLASH MEMORY BLOCK ADDRESS TABLES

Table 26. Top Boot Block Addresses, M36W832TE

#

0 4 1FF000-1FFFFF
1 4 1FE000-1FEFFF
2 4 1FD000-1FDFFF
3 4 1FC000-1FCFFF
4 4 1FB000-1FBFFF
5 4 1FA000-1FAFFF
6 4 1F9000-1F9FFF
7 4 1F8000-1F8FFF
8 32 1F0000-1F7FFF

9 32 1E8000-1EFFFF
10 32 1E0000-1E7FFF
11 32 1D8000-1DFFFF
12 32 1D0000-1D7FFF
13 32 1C8000-1CFFFF
14 32 1C0000-1C7FFF
15 32 1B8000-1BFFFF
16 32 1B0000-1B7FFF
17 32 1A8000-1AFFFF
18 32 1A0000-1A7FFF
19 32 198000-19FFFF
20 32 190000-197FFF
21 32 188000-18FFFF
22 32 180000-187FFF
23 32 178000-17FFFF
24 32 170000-177FFF
25 32 168000-16FFFF
26 32 160000-167FFF
27 32 158000-15FFFF
28 32 150000-157FFF
29 32 148000-14FFFF
30 32 140000-147FFF
31 32 138000-13FFFF
32 32 130000-137FFF
33 32 128000-12FFFF

Size

(KWord)

Address Range

34 32 120000-127FFF
35 32 118000-11FFFF
36 32 110000-117FFF
37 32 108000-10FFFF
38 32 100000-107FFF
39 32 0F8000-0FFFFF
40 32 0F00000-F7FFF
41 32 0E8000-0EFFFF
42 32 0E0000-0E7FFF
43 32 0D8000-0DFFFF
44 32 0D0000-0D7FFF
45 32 0C8000-0CFFFF
46 32 0C0000-0C7FFF
47 32 0B8000-0BFFFF
48 32 0B0000-0B7FFF
49 32 0A8000-0AFFFF
50 32 0A0000-0A7FFF
51 32 098000-09FFFF
52 32 090000-097FFF
53 32 088000-08FFFF
54 32 080000-087FFF
55 32 078000-07FFFF
56 32 070000-077FFF
57 32 068000-06FFFF
58 32 060000-067FFF
59 32 058000-05FFFF
60 32 050000-057FFF
61 32 048000-04FFFF
62 32 040000-047FFF
63 32 038000-03FFFF
64 32 030000-037FFF
65 32 028000-02FFFF
66 32 020000-027FFF
67 32 018000-01FFFF
68 32 010000-017FFF
69 32 008000-00FFFF
70 32 000000-007FFF

46/64

M36W832TE, M36W832BE

Table 27. Bottom Boot Block Addresses, M36W832BE

#

70 32 1F8000-1FFFFF
69 32 1F0000-1F7FFF
68 32 1E8000-1EFFFF
67 32 1E0000-1E7FFF
66 32 1D8000-1DFFFF
65 32 1D0000-1D7FFF
64 32 1C8000-1CFFFF
63 32 1C0000-1C7FFF
62 32 1B8000-1BFFFF
61 32 1B0000-1B7FFF
60 32 1A8000-1AFFFF
59 32 1A0000-1A7FFF
58 32 198000-19FFFF
57 32 190000-197FFF
56 32 188000-18FFFF
55 32 180000-187FFF
54 32 178000-17FFFF
53 32 170000-177FFF
52 32 168000-16FFFF
51 32 160000-167FFF
50 32 158000-15FFFF
49 32 150000-157FFF
48 32 148000-14FFFF
47 32 140000-147FFF
46 32 138000-13FFFF
45 32 130000-137FFF
44 32 128000-12FFFF
43 32 120000-127FFF
42 32 118000-11FFFF
41 32 110000-117FFF
40 32 108000-10FFFF
39 32 100000-107FFF
38 32 0F8000-0FFFFF
37 32 0F0000-0F7FFF

Size

(KWord)

Address Range

36 32 0E8000-0EFFFF
35 32 0E0000-0E7FFF
34 32 0D8000-0DFFFF
33 32 0D0000-0D7FFF
32 32 0C8000-0CFFFF
31 32 0C0000-0C7FFF
30 32 0B8000-0BFFFF
29 32 0B0000-0B7FFF
28 32 0A8000-0AFFFF
27 32 0A0000-0A7FFF
26 32 098000-09FFFF
25 32 090000-097FFF
24 32 088000-08FFFF
23 32 080000-087FFF
22 32 078000-07FFFF
21 32 070000-077FFF
20 32 068000-06FFFF
19 32 060000-067FFF
18 32 058000-05FFFF
17 32 050000-057FFF
16 32 048000-04FFFF
15 32 040000-047FFF
14 32 038000-03FFFF
13 32 030000-037FFF
12 32 028000-02FFFF
11 32 020000-027FFF
10 32 018000-01FFFF

9 32 010000-017FFF
8 32 008000-00FFFF
7 4 007000-007FFF
6 4 006000-006FFF
5 4 005000-005FFF
4 4 004000-004FFF
3 4 003000-003FFF
2 4 002000-002FFF
1 4 001000-001FFF
0 4 000000-000FFF

47/64

M36W832TE, M36W832BE

APPENDIX B. COMMON FLASH INTERFACE (CFI)

The Common Flash Interface is a JEDEC ap­proved, standardized data structure that can be
read from the Flash memory device. It allows a
system software to query the device to det ermine
various electrical and t iming parameters, density
information and functions supported by the mem­ory. The system can interface easily with the de­vice, enabling the software to upgrade itself when
necessary.

When the CFI Query Co mmand (RCFI) is issued
the device enters CFI Query mode and the data

Table 28. Query Structure Overvi ew

Offset Sub-section Name Description

00h Reserved Reserved for algorithm-specific information
10h CFI Query Identification String Command set ID and algorithm data offset
1Bh System Interface Information Device timing & voltage information
27h Device Geometry Definition Flash device layout

P Primary Algorithm-specific Extended Query table

A Alternate Algorithm-specific Extended Query table

Note: Query data are always presented on the lowest order data outputs.

structure is read from the memory. Tables 28 , 29,
30, 31, 32 and 33 show the addresses used to re­trieve the data.

The CFI data structure also contains a security
area where a 64 bit unique security number is writ­ten (see Table 33, Security Code area). This area
can be accessed only in Read mode by the final
user. It is impossible to change t he secu rity num­ber after it has been written by ST. Issue a Read
command to return to Read mode.

Additional information specific to the Primary
Algorithm (optional)

Additional information specific to the Alternate
Algorithm (optional)

Table 29. CFI Query Identification String

Offset Data Description Value

00h 0020h Manufacturer Code ST

01h

02h-0Fh reserved Reserved

10h 0051h "Q"
11h 0052h Query Unique ASCII String "QRY" "R"
12h 0059h "Y"
13h 0003h
14h 0000h
15h 0035h
16h 0000h
17h 0000h
18h 0000h
19h 0000h
1Ah 0000h

Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

88BAh
88BBh

Device Code

Primary Algorithm Command Set and Control Interface ID code 16 bit ID code
defining a specific algorithm

Address for Primary Algorithm extended Query table (see Table 31) P = 35h

Alternate Vendor Command Set and Control Interface ID Code second vendor ­specified algorithm supported (0000h means none exists)

Address for Alternate Algorithm extended Query table
(0000h means none exists)

compatible

Top

Bottom

Intel

NA

NA

48/64

M36W832TE, M36W832BE

Table 30. CFI Query System Interface Information

Offset Data Description Value

V

Logic Supply Minimum Program/Erase or Write voltage

1Bh 0027h

1Ch 0036h

1Dh 00B4h

1Eh 00C6h

1Fh 0004h

20h 0004h
21h 000Ah
22h 0000h
23h 0005h
24h 0005h
25h 0003h
26h 0000h

DDF

bit 7 to 4 BCD value in volts
bit 3 to 0 BCD value in 100 mV

Logic Supply Maximum Program/Erase or Write voltage

V

DDF

bit 7 to 4 BCD value in volts
bit 3 to 0 BCD value in 100 mV

V

[Programming] Supply Minimum Program/Erase voltage

PPF

bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV

[Programming] Supply Maximum Program/Erase voltage

V

PPF

bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV

n

ms

n

times typical

n

µs

n

n

ms

Typical time-out per single word program = 2

Typical time-out for Double/ Quadruple Word Program = 2
Typical time-out per individual block erase = 2
Typical time-out for full chip erase = 2
Maximum time-out for word program = 2
Maximum time-out for Double/ Quadruple Word Program = 2
Maximum time-out per individual block erase = 2
Maximum time-out for chip erase = 2

n

times typical

n

times typical

µs

n

times typical

2.7V

3.6V

11.4V

12.6V

16µs
16µs

1s

NA
512µs
512µs

8s

NA

49/64

M36W832TE, M36W832BE

Table 31. Device Geometry Definition

Offset Word

Mode

27h 0016h
28h

29h
2Ah

2Bh

2Ch 0002h

Data Description Value

Device Size = 2

0001h
0000h

0003h
0000h

Flash Device Interface Code description

Maximum number of bytes in multi-byte program or page = 2
Number of Erase Block Regions within the device.

It specifies the number of regions within the device containing contiguous
Erase Blocks of the same size.

n

in number of bytes

4 MByte

x16

Async.

n

8

2

2Dh
2Eh

2Fh

30h
31h

32h

M28W320ECT

33h
34h

2Dh
2Eh

2Fh

30h
31h

32h

M28W320ECB

33h
34h

003Eh

0000h
0000h

0001h
0007h

0000h
0020h

0000h
0007h

0000h
0020h

0000h

003Eh

0000h
0000h

0001h

Region 1 Information
Number of identical-size erase block = 003Eh+1

Region 1 Information
Block size in Region 1 = 0100h * 256 byte

Region 2 Information
Number of identical-size erase block = 0007h+1

Region 2 Information
Block size in Region 2 = 0020h * 256 byte

Region 1 Information
Number of identical-size erase block = 0007h+1

Region 1 Information
Block size in Region 1 = 0020h * 256 byte

Region 2 Information
Number of identical-size erase block = 003Eh=1

Region 2 Information
Block size in Region 2 = 0100h * 256 byte

63

64 KByte

8

8 KByte

8

8 KByte

63

64 KByte

50/64

Table 32. Primary Algorithm-Sp ecific Extend ed Qu ery Ta ble

Offset

P = 35h

(1)

Data Description Value

M36W832TE, M36W832BE

(P+0)h = 35h 0050h

(P+1)h = 36h 0052h "R"

Primary Algorithm extended Query table unique ASCII string “PRI”

"P"

(P+2)h = 37h 0049h "I"
(P+3)h = 38h 0031h Major version number, ASCII "1"

(P+4)h = 39h 0030h Minor version number, ASCII "0"
(P+5)h = 3Ah 0066h Extended Query table contents for Primary Algorithm. Address (P+5)h
(P+6)h = 3Bh 0000h

(P+7)h = 3Ch 0000h
(P+8)h = 3Dh 0000h

contains less significant byte.

bit 0 Chip Erase supported (1 = Yes, 0 = No)
bit 1 Suspend Erase supported (1 = Yes, 0 = No)
bit 2 Suspend Program supported (1 = Yes, 0 = No)
bit 3 Legacy Lock/Unlock supported (1 = Yes, 0 = No)
bit 4 Queued Erase supported (1 = Yes, 0 = No)
bit 5 Instant individual block locking supported (1 = Yes, 0 = No)
bit 6 Protection bits supported (1 = Yes, 0 = No)
bit 7 Page mode read supported (1 = Yes, 0 = No)
bit 8 Synchronous read supported (1 = Yes, 0 = No)
bit 31 to 9 Reserved; undefined bits are ‘0’

No
Yes
Yes

No

No
Yes
Yes

No

No

(P+9)h = 3Eh 0001h Supported Functions after Suspend

Read Array, Read Status Register and CFI Query are always supported
during Erase or Program operation

bit 0 Program supported after Erase Suspend (1 = Yes, 0 = No)
bit 7 to 1 Reserved; undefined bits are ‘0’ Yes

(P+A)h = 3Fh 0003h Block Lock Status

(P+B)h = 40h 0000h

Defines which bits in the Block Status Register section of the Query are
implemented.
Address (P+A)h contains less significant byte

bit 0 Block Lock Status Register Lock/Unlock bit active(1 = Yes, 0 = No)
bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No)

Yes
Yes

bit 15 to 2 Reserved for future use; undefined bits are ‘0’

(P+C)h = 41h 0030h V

Logic Supply Optimum Program/Erase voltage (highest performance)

DDF

3V

bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV

(P+D)h = 42h 00C0h V

Supply Optimum Program/Erase voltage

PPF

12V
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV

(P+E)h = 43h 0001h Number of Protection register fields in JEDEC ID space.

01

"00h," indicates that 256 protection bytes are available

(P+F)h = 44h 0080h Protection Field 1: Protection Description
(P+10)h = 45h 0000h 00h
(P+11)h = 46h 0003h 8 Byte
(P+12)h = 47h 0003h 8 Byte

This field describes user-available. One Time Programmable (OTP)
Protection register bytes. Some are pre-programmed with device unique
serial numbers. Others are user programmable. Bits 0–15 point to the
Protection register Lock byte, the section’s first byte.
The following bytes are factory pre-programmed and user-programmable.

80h

bit 0 to 7 Lock/bytes JEDEC-plane physical low address
bit 8 to 15 Lock/bytes JEDEC-plane physical high address
bit 16 to 23 "n" such that 2n = factory pre-programmed bytes

n

bit 24 to 31 "n" such that 2

= user programmable bytes

(P+13)h = 48h Reserved

Note: 1. See Table 29, offset 15 for P poin ter definiti on.

51/64

M36W832TE, M36W832BE

Table 33. Security Code Area

Offset Data Description

80h 00XX Protection Register Lock
81h XXXX
82h XXXX
83h XXXX
84h XXXX
85h XXXX
86h XXXX
87h XXXX
88h XXXX

89h XXXX
8Ah XXXX
8Bh XXXX
8Ch XXXX

64 bits: unique device number

128 bits: User Programmable OTP

52/64

APPENDIX C. FLASH MEMORY FLOWCHARTS AND PSEUDO CODES

Figure 26. Program Flow c hart and Pseud o C ode

Start

M36W832TE, M36W832BE

Write 40h or 10h

Write Address

& Data

Read Status

Register

b7 = 1

YES

b3 = 0

YES

b4 = 0

YES

b1 = 0

YES

End

NO

NO

NO

NO

V

Error (1, 2)

Error (1, 2)

Program to Protected

Block Error (1, 2)

Invalid

PPF

Program

program_command (addressToProgram, dataToProgram) {:
writeToFlash (any_address, 0x40) ;
/*or writeToFlash (any_address, 0x10) ; */

writeToFlash (addressToProgram, dataToProgram) ;
/*Memory enters read status state after
the Program Command*/

do {
status_register=readFlash (any_address) ;
/* EF or GF must be toggled*/

} while (status_register.b7== 0) ;

if (status_register.b3==1) /*V
error_handler ( ) ;

if (status_register.b4==1) /*program error */
error_handler ( ) ;

if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;

}

invalid error */

PPF

Note: 1. Status check of b1 (Protected Block), b3 (V

a sequence.

2. If an error is foun d, the Status Register m ust be cleared before furt her Program / Erase Con troller ope rations.

Invalid) and b4 (Program Error) can be made after each program operation or after

PPF

AI90174b

53/64

M36W832TE, M36W832BE

Figure 27. Dou bl e W or d Pr ogram Flowc hart and Pseudo Code

Start

Write 30h

Write Address 1

& Data 1 (3)

Write Address 2

& Data 2 (3)

Read Status

Register

b7 = 1

YES

b3 = 0

YES

b4 = 0

NO

NO

NO

V

Invalid

PPF

Error (1, 2)

Program

Error (1, 2)

double_word_program_command (addressToProgram1, dataToProgram1,
addressToProgram2, dataToProgram2)
{
writeToFlash (any_address, 0x30) ;

writeToFlash (addressToProgram1, dataToProgram1) ;
/*see note (3) */
writeToFlash (addressToProgram2, dataToProgram2) ;
/*see note (3) */
/*Memory enters read status state after
the Program command*/

do {
status_register=readFlash (any_address) ;
/* EF or GF must be toggled*/

} while (status_register.b7== 0) ;

if (status_register.b3==1) /*V
error_handler ( ) ;

if (status_register.b4==1) /*program error */
error_handler ( ) ;

invalid error */

PPF

YES

NO

b1 = 0

YES

End

Note: 1. Status check of b1 (Protected Block), b3 (V

a sequence.

2. If an error is foun d, the Status Register m ust be cleared before furt her Program / Erase operations.

3. Address 1 and Address 2 must be consecuti ve addresses differing only for bit A0.

Program to Protected

Block Error (1, 2)

PPF

if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;

}

Invalid) and b4 (Program Error) can be made after each program operation or after

54/64

AI90175b

Figure 28. Quadruple W o rd P rogram Flowc hart and Pseudo Code

Start

M36W832TE, M36W832BE

Write 56h

Write Address 1

& Data 1 (3)

Write Address 2

& Data 2 (3)

Write Address 3

& Data 3 (3)

Write Address 4

& Data 4 (3)

Read Status

Register

b7 = 1

YES

quadruple_word_program_command (addressToProgram1, dataToProgram1,
addressToProgram2, dataToProgram2,
addressToProgram3, dataToProgram3,
addressToProgram4, dataToProgram4)
{
writeToFlash (any_address, 0x56) ;

writeToFlash (addressToProgram1, dataToProgram1) ;
/*see note (3) */

writeToFlash (addressToProgram2, dataToProgram2) ;
/*see note (3) */

writeToFlash (addressToProgram3, dataToProgram3) ;
/*see note (3) */

writeToFlash (addressToProgram4, dataToProgram4) ;
/*see note (3) */

/*Memory enters read status state after
the Program command*/

do {
status_register=readFlash (any_address) ;
/* EF or GF must be toggled*/

NO

} while (status_register.b7== 0) ;

b3 = 0

b4 = 0

b1 = 0

End

Note: 1. Status check of b1 (Protected Block), b3 (V

a sequence.

2. If an error is foun d, the Status Register m ust be cleared before furt her Program / Erase operations.

3. Address 1 to Addr ess 4 must be consecutive addresses differing only for bits A0 and A1.

NO

YES

NO

YES

NO

YES

V

Invalid

PPF

Error (1, 2)

Program

Error (1, 2)

Program to Protected

Block Error (1, 2)

PPF

if (status_register.b3==1) /*V
error_handler ( ) ;

if (status_register.b4==1) /*program error */
error_handler ( ) ;

if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;

}

Invalid) and b4 (Program Error) can be made after each program operation or after

PPF

invalid error */

AI07950

55/64

M36W832TE, M36W832BE

Figure 29. Program Suspend & Resume Flowchart and Pseudo Code

Start

program_suspend_command ( ) {

Write B0h

Write 70h

Read Status

Register

writeToFlash (any_address, 0xB0) ;
writeToFlash (any_address, 0x70) ;

/* read status register to check if
program has already completed */

do {
status_register=readFlash (any_address) ;
/* EF or GF must be toggled*/

b7 = 1

YES

b2 = 1

YES

Write FFh

Read data from

another address

Write D0h

Program Continues

NO

NO

Program Complete

Write FFh

Read Data

} while (status_register.b7== 0) ;

if (status_register.b2==0) /*program completed */
{ writeToFlash (any_address, 0xFF) ;
read_data ( ) ; /*read data from another block*/
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/

}
else
{ writeToFlash (any_address, 0xFF) ;
read_data ( ); /*read data from another address*/
writeToFlash (any_address, 0xD0) ;
/*write 0xD0 to resume program*/
}
}

AI90176b

56/64

Figure 30. Erase Flowchart and Pseudo Code

Start

Write 20h

Write Block

Address & D0h

M36W832TE, M36W832BE

erase_command ( blockToErase ) {
writeToFlash (any_address, 0x20) ;

writeToFlash (blockToErase, 0xD0) ;
/* only A12-A20 are significannt */
/* Memory enters read status state after

the Erase Command */

Read Status

Register

YES

YES

NO

YES

YES

NO

NO

YES

NO

NO

V

PPF

Error (1)

Command

Sequence Error (1)

Erase to Protected

Block Error (1)

b7 = 1

b3 = 0

b4, b5 = 1

b5 = 0 Erase Error (1)

b1 = 0

End

Invalid

do {
status_register=readFlash (any_address) ;
/* EF or GF must be toggled*/

} while (status_register.b7== 0) ;

if (status_register.b3==1) /*V
error_handler ( ) ;

if ( (status_register.b4==1) && (status_register.b5==1) )
/* command sequence error */
error_handler ( ) ;

if ( (status_register.b5==1) )
/* erase error */
error_handler ( ) ;

if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;

}

invalid error */

PPF

AI90177b

Note: If an error is found, the Status Register must be cleared before further Progr am/Erase o perations.

57/64

M36W832TE, M36W832BE

Figure 31. Erase Suspend & Resume Flowchart and Pseudo Code

Start

Write B0h

Write 70h

Read Status

Register

b7 = 1

b6 = 1

Write FFh

Read data from

another block

Program/Protection Program

Block Protect/Unprotect/Lock

or
or

Write D0h

Erase Continues

NO

YES

NO

YES

Erase Complete

Write FFh

Read Data

erase_suspend_command ( ) {
writeToFlash (any_address, 0xB0) ;

writeToFlash (any_address, 0x70) ;
/* read status register to check if
erase has already completed */

do {
status_register=readFlash (any_address) ;
/* EF or GF must be toggled*/

} while (status_register.b7== 0) ;

if (status_register.b6==0) /*erase completed */
{ writeToFlash (any_address, 0xFF) ;

read_data ( ) ;
/*read data from another block*/
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/

}
else
{ writeToFlash (any_address, 0xFF) ;
read_program_data ( );
/*read or program data from another address*/
writeToFlash (any_address, 0xD0) ;
/*write 0xD0 to resume erase*/
}
}

58/64

AI90178b

Figure 32. Lo ck i ng Ope rations Flowchart and Pseudo Cod e

Start

M36W832TE, M36W832BE

Write 60h

Write

01h, D0h or 2Fh

Write 90h

Read Status

Register

Locking
change

confirmed?

YES

Write FFh

End

NO

locking_operation_command (address, lock_operation) {
writeToFlash (any_address, 0x60) ; /*configuration setup*/

if (lock_operation==PROTECT) /*to protect the block*/
writeToFlash (address, 0x01) ;
else if (lock_operation==UNPROTECT) /*to unprotect the block*/
writeToFlash (address, 0xD0) ;
else if (lock_operation==LOCK) /*to lock the block*/
writeToFlash (address, 0x2F) ;

writeToFlash (any_address, 0x90) ;

if (readFlash (address) ! = locking_state_expected)
error_handler () ;
/*Check the locking state (see Read Block Signature table )*/

writeToFlash (any_address, 0xFF) ; /*Reset to Read Array mode*/
}

AI90179

59/64

M36W832TE, M36W832BE

Figure 33. Protection Register Program Flowchart and Pseudo Code

Start

Write C0h

Write Address

& Data

Read Status

Register

b7 = 1

YES

b3 = 0

YES

b4 = 0

YES

b1 = 0

YES

End

NO

NO

NO

NO

V

Error (1, 2)

Error (1, 2)

Program to Protected

Block Error (1, 2)

Invalid

PPF

Program

protection_register_program_command (addressToProgram, dataToProgram) {:
writeToFlash (any_address, 0xC0) ;

writeToFlash (addressToProgram, dataToProgram) ;
/*Memory enters read status state after
the Program Command*/

do {
status_register=readFlash (any_address) ;
/* EF or GF must be toggled*/

} while (status_register.b7== 0) ;

if (status_register.b3==1) /*V
error_handler ( ) ;

if (status_register.b4==1) /*program error */
error_handler ( ) ;

if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;

}

invalid error */

PPF

AI07951

Note: 1. Status check of b1 (Protected Block), b3 (V

a sequence.

2. If an error is foun d, the Status Register m ust be cleared before furt her Program / Erase Con troller ope rations.

Invalid) and b4 (Program Error) can be made after each program operation or after

PPF

60/64

M36W832TE, M36W832BE

APPENDIX D. FLASH MEMORY COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE

Table 34. Write State Machine Current/Next, sheet 1 of 2

Current

State

Read A rray “1” Ar ray Read Array Prog. Setup Ers. Setup Read A rray Read S t s. Read Array

Read

Status

Read

Elect.Sg.

Read CFI

Query

Lock Setup “1” Status Lock Command Error

Lock Cmd

Error
Lock

(complete)
Prot. Prog.

Setup

Prot. Prog.

(continue)

Prot. Prog.
(complete)

Prog. Setup “1” Status Program

Program

(continue)
Prog. Sus

Status

Prog. Sus

Read A rray

Prog. Sus

Read

Elect.Sg.

Prog. Sus

Read CFI

Program

(complete)

Erase
Setup

Erase

Cmd.Error

Erase

(continue)

Erase Sus

Read Sts

Erase Sus

Read A rray

Erase Sus

Read

Elect.Sg.

Erase Sus

Read CFI

Erase

(complete)

Note: Cmd = Command, Elect.Sg. = Electronic Signature, Ers = Er ase, Prog. = Program, Prot = Protec tion, Sus = Suspend.

SR

bit 7

Data

When

Read

“1” Status Read Array

Electronic

“1”

Signature

“1” CFI Read Array

“1” Status Read Array

“1” Status Read Array

“1” Status Protecti on Register P rogram

“0” Status Protectio n Register P rogram conti nue

“1” Status Read Array

“0” Status Program (continue )

“1” Status

“1” Array

Electronic

“1”

Signature

“1” CFI

“1” Status Read Array

“1” Status Erase Command Error

“1” Status Read Array

“0” Status Erase (cont i nue)

“1” Status

“1” Array

Electronic

“1”

Signature

“1” CFI

“1” Status Read Array

Read
Array
(FFh)

Read Array

Prog. Sus

Read Array

Prog. Sus

Read Array

Prog. Sus

Read Array

Prog. Sus

Read Array

Erase Sus

Read Array

Erase Sus

Read Array

Erase Sus

Read Array

Erase Sus

Read Array

Program

Setup

(10/40h)

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Program Suspend to

Read Array

Program Suspend to

Read Array

Program Suspend to

Read Array

Program Suspend to

Read Array

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Command Input (and Next State)

Erase
Setup

(20h)

Erase

Setup

Erase

Setup

Erase

Setup

Erase

Setup

Erase

Setup

Erase

Setup

Erase

Setup

Erase

Setup

Erase Sus

Read Array

Erase Sus

Read Array

Erase Sus

Read Array

Erase Sus

Read Array

Erase
Setup

Erase

Confirm

(D0h)

Lock

(complete)

Program

(continue)

Program

(continue)

Program

(continue)

Program

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

Prog/Ers
Suspend

(B0h)

Read Array

Read Array

Read Array

Lock Cmd

Error

Read Array

Read Array

Read Array

Prog. Sus

Read Sts

Prog. Sus

Read Array

Prog. Sus

Read Array

Prog. Sus

Read Array

Prog. Sus

Read Array
Read Array

Erase

CmdError

Read Array

Erase Sus

Read Sts

Erase Sus

Read Array

Erase Sus

Read Array

Erase Sus

Read Array

Erase Sus

Read Array
Read Array

Prog/Ers

Resume

(D0h)

Lock

(complete)

Program

(continu e)

Program

(continu e)

Program

(continu e)

Program

(continu e)

Erase

(continue)

Erase

(continu e)

Erase

(continu e)

Erase

(continu e)

Erase

(continu e)

Read

Status

(70h)

Read

Status

Read

Status

Read

Status

Lock Command Error

Read

Status

Read

Status

Read

Status

Program (c ontinue)

Prog. Sus

Read Sts

Prog. Sus

Read Sts

Prog. Sus

Read Sts

Prog. Sus

Read Sts

Read

Status

Erase Command Error

Read

Status

Erase (con tinue)

Eras e Sus

Read Sts

Eras e Sus

Read Sts

Eras e Sus

Read Sts

Eras e Sus

Read Sts

Read

Status

Clear

Status

(50h)

Read Array

Read Array

Read Array

Read Array

Read Array

Read Array

Prog. Sus

Read Array

Prog. Sus

Read Array

Prog. Sus

Read Array

Prog. Sus

Read Array
Read Array

Read Array

Eras e Sus

Read Array

Eras e Sus

Read Array

Eras e Sus

Read Array

Eras e Sus

Read Array
Read Array

61/64

M36W832TE, M36W832BE

Table 35. Write State Machine Current/Next, sheet 2 of 2

Command Input (and Next State)

Current State

Read Array Read Elect.Sg. Read CFI Query Lock Setup

Read Status Read Elect.Sg. Read CFI Query Lock Set up

Read Ele ct .Sg. Read Elect.Sg. Read CFI Query Lock Se t up

Read CFI Query Read Elect.Sg. Read CFI Query Lock Setup

Lock S etup Lock Command Error Lock (com plete)

Lock Cmd Error Read Elect.Sg. Read CFI Query Lock Setup

Lock (complete) Re ad Elect.Sg. Read CFI Query Lock Setup

Prot. Prog.

Setup

Prot. Prog.

(continue)

Prot. Prog.
(complete)

Prog. Setup Program

Program

(continu e)

Prog. Suspend

Read Status

Prog. Suspend

Read Array

Prog. Suspend
Read El ect.Sg.

Prog. Suspend

Read CFI

Program

(complete)

Erase Setup Erase Command Error

Erase

Cmd.Error

Erase (con tinue) Erase (continue)

Erase Suspend

Read Ststus

Erase Suspend

Read Array

Erase Suspend

Read El ect.Sg.

Erase Suspend

Read CFI Query

Erase

(complete)

Note: Cmd = Command, Elect.Sg. = Electronic Signature, Prog. = Program, Pro t = P rot ection.

Read Elect.Sg.

(90h)

Read Elec t. S g. Read CFI Query Lock Setup

Prog. Suspend
Read Elec t.Sg.

Prog. Suspend
Read Elec t.Sg.

Prog. Suspend
Read Elec t.Sg.

Prog. Suspend
Read Elec t.Sg.

Read Elect.Sg. Read CFIQuery Lock Setup

Read Elec t. S g. Read CFI Query Lock Setup

Erase Suspend
Read Elec t.Sg.

Erase Suspend
Read Elec t.Sg.

Erase Suspend
Read Elec t.Sg.

Erase Suspend
Read Elec t.Sg.

Read Elec t.Sg. R ead CFI Query Lock Setup

Read CFI

Query

(98h)

Prog. Suspend

Read CFI Query

Prog. Suspend

Read CFI Query

Prog. Suspend

Read CFI Query

Prog. Suspend

Read CFI Query

Erase Suspend

Read CFI Query

Erase Suspend

Read CFI Query

Erase Suspend

Read CFI Query

Erase Suspend

Read CFI Query

Lock Setup

(60h)

Protectio n Register Program

Protection Register Program (continue)

Lock Setup Erase Suspend Read Array

Lock Setup Erase Suspend Read Array

Lock Setup Erase Suspend Read Array

Lock Setup Erase Suspend Read Array

Prot. Prog.

Setup (C0h)

Prot. Prog.

Setup

Prot. Prog.

Setup

Prot. Prog.

Setup

Prot. Prog.

Setup

Prot. Prog.

Setup

Prot. Prog.

Setup

Prot. Prog.

Setup

Program (c ontinue)

Program Suspend Read Array

Program Suspend Read Array

Program Suspend Read Array

Program Suspend Read Array

Prot. Prog.

Setup

Prot. Prog.

Setup

Prot. Prog.

Setup

Lock Confirm

(01h)

Confirm (2Fh)

Lock Down

Read Array

Read Array

Read Array

Read Array

Read Array

Read Array

Read Array

Read Array

Read Array

Read Array

Unlock

Confirm

(D0h)

Program

(continue)

Program

(continue)

Program

(continue)

Program

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

62/64

REVISION HIST ORY

Table 36. Document Revision History

Date Version Revision Details

16-Jul-2002 1.0 First Issue

Revision History moved to end of document. Flash and SRAM components updated.
Table 2, Main Operation Modes, modified.

Flash Device: “Quadruple Word Program Command” added, “Double Word Program
Command” clarified, V
Program, Erase Times and Program/Erase Endurance Cycles, Table 15, DC

29-Nov-2002 2.0

24-Mar-2003 3.0

26-May-2003 3.1 Special tape option added to ordering information scheme

Characteristicss Table and to CFI Tables 30 and 31. Security block removed.
Command Codes Table added, DQ0, DQ2, DQ3-DQ7 and DQ8-DQ15 parameters
modified for Lock in Table 7, Flash Read Protection Register and Lock Register.
70ns Speed Class added. 100ns Speed Class removed.
SRAM device: “Data Retention” on Page 25 and SRAM read and write AC
characteristics (Figures 14, 15, 16, 17, 18, 19, 20, 21 and 22) modified. Figure 7,
SRAM Block Diagram, added.

Document promoted to full Datasheet status. Minor corrections to SRAM Block
Diagram. Input Rise and Fall Time for 70ns speed class modified in Operating and AC
Measurement Conditions Table. LFBGA Connections and Daisy Chain pin numbers
modified.

Maximum changed to 3.6V, Corrections to Table 8, Flash

DDQF

M36W832TE, M36W832BE

63/64

M36W832TE, M36W832BE

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by implic ation or otherwise u nder any pat ent or pat ent rights of STMicroelectronics. Spec i fications mentioned in this publicatio n are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
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64/64