Datasheet M36W432TG, M36W432BG Datasheet (SGS Thomson Microelectronics)

32 Mbit (2Mb x16, Boot Block) Flash Memory

and 4 Mbit (256Kb x16) SRAM, Multiple Memory Product

FEATURES SUMMARY

■ MULTIPLE MEMORY PRODUCT

– 32 Mbit (2Mb x 16), Boot Block, Flash Memory
– 4 Mbit (256Kb x 16) SRAM Memory

■ SUPPLY VOLTAGE

–V
–V
–V

■ ACCESS TIME: 70ns, 85ns

■ LOW POWER CONSUMPTION

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h
– Top Device Code, M36W432TG: 88BAh
– Bottom Device Code, M36W432BG: 88BBh

FLASH MEMORY

■ MEMORY BLOCKS

– Parameter Blocks (Top or Bottom Location)
– Main Blocks

■ PROGRAMMING TIME

– 10µs typical
– Double Word Programming Option
– Quadruple Word Programming Option

■ BLOCK LOCKING

– All blocks locked at Power up
– Any combination of blocks can be locked
–WP

■ AUTOMATIC STANDBY MODE

■ PROGRAM and ERASE SUSPEND

■ 100,000 PROGRAM/ERASE CYCLES per

BLOCK

■ COMMON FLASH INTERFACE

■ SECURITY

– 128 bit user programmable OTP cells
– 64 bit unique device identifier

= 2.7V to 3.3V

DDF

= V

DDS

= 12V for Fast Program (optional)

PPF

for Block Lock-Down

F

= 2.7V to 3.3V

DDQF

M36W432TG

M36W432BG

PRELIMINARY DATA

SRAM

■ 4 Mbit (256Kb x 16)

■ ACCESS TIME: 70ns

■ LOW V

■ POWER DOWN FEATURES USING TWO

CHIP ENABLE INPUTS

Figure 1. Package

DATA RETENTION: 1.5V

DDS

FBGA

Stacked LFBGA66 (ZA)

12 x 8 mm

November 2002

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

1/66

M36W432TG, M36W432BG

TABLE OF CONTENTS

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. LFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Address Inputs (A0-A17). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Address Inputs (A18-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Flash Chip Enable (EF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Flash Output Enable (GF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Flash Write Enable (WF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Flash Write Protect (WPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Flash Reset (RPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SRAM Chip Enable (E1S, E2S). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SRAM Write Enable (WS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SRAM Output Enable (GS).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SRAM Upper Byte Enable (UBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SRAM Lower Byte Enable (LBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

V

Supply Voltage (2.7V to 3.3V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

DDF

and V

V

DDQF

V

Program Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

PPF

V

and V

SSF

Supply Voltage (2.7V to 3.3V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

DDS

Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SSS

FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0

Table 2. Main Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 3. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 4. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 6. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Table 5. Device Capaci ta n ce. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 6. DC Character i stics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6

Figure 7. Stacked LFBGA66 12x8mm , 8x8 ball array, 0.8mm pitch, Bottom View Package Out line16
Table 7. Stacked LFBGA66 12x8mm, 8x8 ball array, 0.8mm pitch, Package Mecha nical Dat a . . . 16
Figure 8. Stacked LFBGA66 Daisy Chain - Package Connections (Top view through package) . . 17
Figure 9. Stac k ed LFBGA6 6 Daisy C hain - PC B Connect ions proposal (Top view through package).18

2/66

M36W432TG, M36W432BG

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 8. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 9. Daisy Chain Orde r ing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

FLASH DEVICE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0

FLASH SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 10. Flash Block Ad d re sse s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 11. Protect ion Regi ster Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

FLASH BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Read.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Write.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Output Disable.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Automatic Standby.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2

FLASH COMMAND INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Read Memory Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Read Electronic Signature Comma nd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Double Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Clear Status Regist e r Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Program/Erase Suspend Comm and . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Program/Eras e Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Protection Regi ste r Pr o g ra m Comman d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Block Lock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Block Lock-Down Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 10. Flash Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 12. Flash Read Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 13. Flash Read Block Lock Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 14. Flash Read Protection Register and Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 15. Flash Program, Erase Times and Program/Erase Endurance Cycles . . . . . . . . . . . 28

FLASH BLOCK LOCKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Reading a Block’s Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Unlocked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9

Lock-Down State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Locking Operatio n s Durin g Erase Su sp e nd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 16. Flash Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 17. Flash Protection Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3/66

M36W432TG, M36W432BG

FLASH STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Erase Status (Bit 5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1

Program Status (Bit 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

V

Status (Bit 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1

PPF

Program Suspend Status (Bit 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Block Protection Status (Bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Reserved (Bit 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2

Table 18. Flash Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 12. Flash Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 19. Flash Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 13. Flash Write AC Wavefo r ms, Write Enable Control l e d . . . . . . . . . . . . . . . . . . . . . . . 34

Table 20. Flash Write AC Chara cte ristics, Write En a ble Controlled. . . . . . . . . . . . . . . . . . . . . 35

Figure 14. Flash Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 21. Flash Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . 37

Figu r e 1 5 . Flash Power -Up an d R e set AC W a veforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 22. Flash Power-Up and Reset AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

SRAM DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

SRAM SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 16. SRAM Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

SRAM OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 0

Standby/Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 17. SRAM Read Mode AC Waveforms, Address Controlled. . . . . . . . . . . . . . . . . . . . . 41

Figure 18. SRAM Read AC Waveforms, GS Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 19. SRAM Standby AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 23. SRAM Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Figure 20. SRAM Write AC Waveforms, WS Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figu r e 2 1 . SRAM Write A C Wav e forms, E1S Con trolle d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 22. SRAM Write AC Waveforms, WS Controlled with GS Low . . . . . . . . . . . . . . . . . . . 45

Figure 23. SRAM Write Cycle Waveform, UBS and LBS Controlled, GS Low . . . . . . . . . . . . . 45

Table 24. SRAM Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 24. SRAM Low V
Table 25. SRAM Low V

Data Retention AC Waveforms, E1S or UBS / LBS Controlled . . 47

DDS

Data Retention Characte r i stic. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

DDS

APPENDIX A. FLASH BLOCK ADDRESS TABLES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 26. Top Boot Block Addresses, M36W432TG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 27. Botto m Boo t Bl oc k Addre sse s, M36W432BG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4/66

M36W432TG, M36W432BG

APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 28. Query Stru cture Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Table 29. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Table 30. CFI Query System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 31. Device Geome try Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Table 32. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 33. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

APPENDIX C. FLASH FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 25. Flash Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 26. Double Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 28. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 58

Figure 29. Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 30. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 31. Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

APPENDIX D. FLASH COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE. 63

Table 34. Write State Machine Current/Next, sheet 1 of 2.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 35. Write State Machine Current/Next, sheet 2 of 2.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 36. Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

5/66

M36W432TG, M36W432BG

SUMMARY DESCRIPTION

The M36W432TG is a low voltage Multiple Memo­ry Product which combines two me mory devices;
a 32 Mbit boot block F lash memory and a 4 Mbit
SRAM. Recommended operating conditions do
not allow both the Flash an d S RA M d ev ices to be
active at the same time.

The memory is offered in a Stacked LFBGA66
(12x8mm, 8x8 active ball array, 0.8 mm pitch)
package and is supplied with all the bits erased
(set to ‘1’).

Table 1. Signal Names

A0-A17

A18-A20 Address Inputs for Flash Chip only
DQ0-DQ15 Data Input/Output
V

DDF

V

DDQF

Address Inputs common to the Flash
and SRAM chips

Flash Power Supply
Flash Power Supply for I/O Buffers

Figure 2. Logi c D iagram

V

DDQF

V

M36W432TG
M36W432BG

A0-A20

E
G

W

RP

WP

E1
E2

G

W

UB

LB

V

DDF

21

F
F
F
F
F

S
S
S
S
S
S

PPF

V

DDS

16

DQ0-DQ15

V

V
V
V

PPF

SSF

DDS

SSS

Flash Optional Supply V oltage for Fast
Program & Erase

Flash Ground
SRAM Power Supply
SRAM Ground

NC Not Connected Internally

Flash control functions

E

F

G
W
RP
WP

F

F

F

F

Chip Enable input
Output Enable input
Write Enable input
Reset input
Write Protect input

SRAM control functions

E1
G
W

, E2

S

S

S

S

Chip Enable inputs
Output Enable input
Write Enable input

6/66

V

SSF

V

SSS

AI07925

UB
LB

S

S

Upper Byte Enable input
Lower Byte Enable input

Figure 3. LFBGA Connections (Top view through package)

#4#387

NCNC

M36W432TG, M36W432BG

AI90162

NC

NCNCGF

654321#2#1

DDQF

V

SSF

V

A12

A13A11A20NCNC

A15 A14

DQ7

DQ14

WS

DQ15A9A16

A8 A10

DQ5

DQ4

DQ6DQ13NCWF

DDF

V

DDS

V

E2SDQ12V

RPF

SSS

DQ3DQ2

DQ10

DQ11A19WPF

PPF

V

DQ1DQ0

DQ8DQ9GSLBS

UBS

E1SA1

A2A3A6A7A18

A17

SSF

EFA0A4NCNC

A5

NC V

A

B

C

D

E

F

G

H

7/66

M36W432TG, M36W432BG

SIGNAL DESCRIPTION

See Figure 2 Logic Diagram and T able 1,Signal
Names, for a brief overview of the signals connect­ed to this de vice.

Address Inputs (A0-A17). Addresses A0-A17
are common inputs for the Flash an d the SRAM
components. The Address Inputs select the cells
in the memory array to access during Bu s Read
operations. During Bus Write operations they con­trol the commands sent to the Command Interface
of the internal state machine. The Flash memory is
accessed through the Chip Enable (
Enable (W

) signals, while the SRAM is accessed

F

through two Chip Enable signals (E1
and the Write Enable signal (W

Address Inputs (A18-A20). Addresses A18-A20
are inputs for the Flash component only. The
Flash memory is acc essed through the Chip E n­able (E

) and Write Enable (WF) signals

F

Data Input/Output (DQ0-DQ15). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation or inputs a command
or the data to be programmed durin g a Write Bus
operation.

Flash Chip Enable (E

). The Chip Enable input

F

activates the memory control logic, input buffers,
decoders and sense amplifiers. When Chip En­able is at V

andReset is at VIH the device is in ac-

IL

tive mode. When Chip Enable is at V
memory is deselected, the outputs are high imped­ance and the power consumption is reduced to the
stand-b y l e v el.

Flash Output Enable (G

). The Output Enable

F

controls data outputs during the Bus Read opera­ti on of the memo ry.

W

Flash Write Enable (

). The Write Enable

F

controls the Bus Write operation of the Flash
memory’s Command Inte rface. The data and ad­dress inputs are latched on the rising edge of Chip
Enable, E

, or Write Enable, WF, whichever oc-

F

curs first.

Flash Write Protect (WP

). Write Protect is an

F

input that gives an additional hardware protection
for each block. When Write Protect is at V
Lock-Down is enabled and the protection status of
the block cannot be changed. When Write Protect
is at V

, the Lock-Down is disabled and the block

IH

can be locked or unlocked. (refer to T able 6, Read
Protection Register and Protection Register Lock).

Flash Reset (RP

). The Reset input provides a

F

hardware reset of the Flash memory. When Reset
is at V

, the memory is in reset mode: the outputs

IL

are high impedance and the current c onsumption
is minimized. After Reset all blocks are in the
Locked state. When Reset is at V
in normal operation. Exiting reset mode the device
enters read array mode, but a negative t ransition

E

) and Write

F

S

).

S

, the device is

IH

and E2S)

the

IH

, the

IL

of Chip Enable or a change of the address is re­quired to ensure valid data outputs.

SRAM Chip Enable (E1

, E2S). The Chip En-

S

able inputs activate the SRAM memory control
logic, input buffers and decoders. E1
E2

at VIL deselects the memory and reduces the

S

power consumption to t he standby level. E 1

can also be used to control writing to the

E2

S

SRAM memory array, while W
is not allowed to set E
at V

at the same time.

IH

SRAM Write Enable (W

at V

F

S

rema in s at V

S

E1S at VIL and E2

IL,

). The Write Enable in-

at VIH or

S

and

S

IL.

It

put controls writing to the SRA M memory array.

is active low .

W

S

SRAM Output E nable (G

). The Output Enable

S

gates the outputs through the data buffers during
a read operation of the SRAM m emory. G

is ac-

S

tive low.

SRAM Upper Byte Enable (UB

). The Upper

S

Byte Enable enables the upper bytes for SRAM
(DQ8-DQ15). UB

SRAM Lower Byte Enable (LB

is acti v e low.

S

). The Lower

S

Byte Enable enables the lower bytes for SRAM
(DQ0-DQ7). LB

Supply Voltage (2.7V to 3.3V). V

V

DDF

is active low.

S

DDF

pro­vides the power supply to the internal core of the
Flash Memory device. It is the main power s upply
for all operations (Read, Program and Erase).

and V

V

DDQF

provides the power supply for the Flash

V

DDQF

memory I/O pins and V

Supply Voltage (2.7V to 3.3V).

DDS

provides the power

DDS

supply for the SRAM control pins . This allows all
Outputs to be powered independently of the Flash
core power supply, V

.

V

DDS

Program Supp ly Vol tage. V

V

PPF

DDF

. V

can be tied to

DDQF

PPF

is both a
control input and a power suppl y pin for t he F lash
memory. The two functions are selected by the
voltage range applied to the pin. The Supply Volt­age V

and the Program Supply Vol tage V

DDF

PPF

can be applied in any order.
If V

V
age lower than V
against program or erase, while V

is kept in a low voltage range (0V t o 3.6V)

PPF

is seen as a control input. In this case a volt-

PPF

gives an absolute protection

PPLK

PPF

> V

PP1

en­ables these functions (see Table 6, DC Character­istics for the relevant values). V

is only

PPF

sampled at the beginning of a program or erase; a
change in its value after the operation has started
does not have any effect on Program or Erase,
however for Double or Q uadruple Word Program
the results are uncertain.

If V
power supply pin. In this condition V

is in the range 11.4V to 12.6V it acts as a

PPF

PPF

must be

S

8/66

M36W432TG, M36W432BG

stable until the Program/Erase algorithm i s com­pleted (see Table 20 and 21).

V

SSF

and V

Ground. V

SSS

SSF

and V

SSS

are the
ground references for all voltage measurements in
the Flash and SRAM chips, respectively.

Note: Each device in a system should have V

DF

, V

DDQF

and V

decoupled with a 0.1µF ca-

PPF

D-

pacitor close to the pin. See Figure 9, AC
Measurement Load Circuit. The PCB trace
widths should be sufficient to carry the re­quired V

program and erase currents.

PPF

9/66

M36W432TG, M36W432BG

FUNCTIONAL DESCRIPTION

The Flash and SRAM components have separate
power supplies and grounds and are distinguished
by three chip enable inputs: E
ory and, E1

and E2S for the SRAM.

S

Recommended operating conditions do not allow
both the Flash and the SRAM to be in active mode
at the same time. The most common example is

Figure 4. Func ti onal Block Di a gram

for the Flash mem-

F

simultaneous read operations on the Flash and
the SRAM which would resul t in a data bus con­tention. Therefore it is recommended to put the
SRAM in the h igh impedance state whe n reading
the Flash and vice versa (see Table 2 Main Oper­ation Modes for details).

E

G

W

RP

WP

A18-A20

A0-A17

E1
E2

G

W

UB

LB

V

DDF

F
F
F
F
F

V

DDS

S
S
S
S
S
S

V

DDQF

Flash Memory

32 Mbit (x16)

SRAM

4 Mbit (x16)

V

V

PPF

SSF

DQ0-DQ15

10/66

V

SSS

AI07926

Table 2. Main Operation Modes

Operation

Mode

Read

Write

Block
Locking

Standby

Flash Memory

Reset X X X
Output

Disable

E

FGFWF

V

ILVILVIHVIH

V

ILVIHVILVIH

V

XX

IL

V

XX

IH

V

ILVIHVIHVIH

Read Flash must be disabled
Read Flash must be disabled
Read Flash must be disabled
Write Flash must be disabled
Write Flash must be disabled
Write Flash must be disabled
Standby/

Power
Down

SRAM

Data
Retention

Output
Disable

Output
Disable

Output
Disable

Note: 1. X = Don’t Care = VIL or VIH, V

2. If UBS

and LBS are tied t ogether the bus is at 16 bit. Fo r an 8 bit bus conf i guration use UBS and LBS separately.

Any Flash mode is allowable

Any Flash mode is allowable

Any Flash mode is allowable

Any Flash mode is allowable

Any Flash mode is allowable

RPFWP

V

IH

V

IH

V

IL

PPFH

M36W432TG, M36W432BG

V

F

X Don’t care SRAM must be disabled Data Output

V

X

V

DDF

V

PPFH

Don’t care SRAM must be disabled X

IL

X Don’t care Any SRAM mode is allowed Hi-Z
X Don’t care Any SRAM mode is allowed Hi-Z

X Don’t care Any SRAM mode is allowed Hi-Z

= 12V ± 5%.

E1SE2SGSWSUBSLB

PPF

or

SRAM must be disabled Data Input

V

ILVIHVILVIHVIL

V

ILVIHVILVIHVIL

V

ILVIHVILVIHVIH

V

ILVIH

V

ILVIH

V

ILVIH

V

IHVIL

X
X
X
X X X X Hi-Z

XXXX

V

IHVIL

X X X X Hi-Z

XXXX

V

ILVIHVIHVIHVIL

V

ILVIHVIHVIHVIL

V

ILVIHVIHVIHVIH

V

ILVIL

V

ILVIH

V

ILVIL

V

IH

V

IH

DQ15-DQ8 DQ7-DQ0

S

V

Data out Word Read

IL

V

Data out Hi-Z

IH

V

IL

V

IL

V

IL

V

IH

V

IH

V

IH

V

IL

V

IH

V

IL

Hi-Z Data out

Data in Word Write

Data in Hi-Z

Hi-Z Data in

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

11/66

M36W432TG, M36W432BG

MAXIMUM RATIN G

Stressing the device above the rating l isted in the
Absolute Maximum Ratings table m ay cause per­manent damage to the device. These are stress
ratings only and operation of the device at t hese or
any other conditions ab ove those i ndicated in t he
Operating sections of this specificat ion is not im-

Table 3. Absolute Maximum Ratings

Symbol Parameter

T

A

T

BIAS

T

STG

V

IO

V

, V

DDF

DDQF

V

PPF

V

DDS

Note: 1. Depends on range.

Ambient Operating Temperature
Temperature Under Bias –40 125 °C
Storage Temperature –55 150 °C
Input or Output Voltage –0.5
Flash Supply Voltage –0.6 3.8 V
Program Voltage –0.6 13 V
SRAM Supply Voltage –0.5 3.8 V

(1)

plied. Exposure to Absolute Maximum Rating con­ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu­ments.

Value

Min Max

–40 85 °C

V

+0.3

DDQF

Unit

V

12/66

DC AND AC PARAMETERS

This section summarizes the operat ing and mea­surement conditions, and the DC and AC charac­teristics of the device. The parameters in the DC
and AC characteristics Tables that follow, are de­rived from tests performed under the Measure-

Table 4. Operating and AC Measurement Conditions

M36W432TG, M36W432BG

ment Conditions summarized in Table 4,
Operating and AC Measurem ent Conditions. De­signers should check that the operating conditions
in their circuit match the measurement conditions
when relying on the quoted parameters.

SRAM Flash Memory

Parameter

Min Max Min Max

V

Supply Voltage

DDF

V

DDQF = VDDS

Supply Voltage

– – 2.7 3.3 V

2.7 3.3 2.7 3.3 V
Ambient Operating Temperature – 40 85 – 40 85 °C
Load Capacitance (C

)

L

30 50 pF
Input Rise and Fall Times 1V/ns 5ns
Input Pulse Voltages
Input and Output Timing Ref. Voltages

Figure 5. AC Measurement I/O Waveform

V

DDQ

V

0V

AI90166

Note: V

DDQ

means V

DDQF

= V

DDS

DDQ

0 to V

DDQF

V

/2 V

DDQF

Figure 6. AC Me asureme nt Load Circuit

/2

V

DDQF

V

DDF

0 to V

DDQF

DEVICE

UNDER

TEST

DDQF

/2

V

DDQF

25kΩ

Units70 70/85

V
V

0.1µF

0.1µF

CL includes JIG capacitance

C

Table 5. Device Capacitance

Symbol Parameter Test Condition Typ Max Unit

V

C

IN

C

OUT

Note: Sampled o nl y, not 100% test ed.

Input Capacitance
Output Capacitance

= 0V, f=1 MHz

IN

V

= 0V, f=1 MHz

OUT

12 12 pF
20 15 pF

L

25kΩ

AI90167

13/66

M36W432TG, M36W432BG

Table 6. DC Characteristics

Symbol Parameter Device Test Condition Min Typ Max Unit

I

I

DDS

I

Input Leakage Current

LI

Output Leakage Current

LO

VDDStandby Current

Flash &

SRAM

Flash

SRAM

Flash

SRAM

0V≤ V

0V ≤V
0V≤V

SRAM Outputs Hi-Z

E

= V

F

RP

= V

F

E1

S

V

V

≥

IN

DDS

f = fmax (A0-A17 and DQ0-

DQ15 only)

f = 0 (G

V

IN

, WS, UBS and LBS)

S

E1

S

V

≥

DDS

V

≤

IN

DDQF

V

≤

OUT

V

≤

OUT

± 0.2V

DDQF

± 0.2V

DDQF

V

≥

– 0.2V

DDS

– 0.2V or V

V

≥

– 0.2V

DDS

– 0.2V or V

f = 0

DDQF

DDQF,

IN

IN

≤

≤

0.2V

0.2V,

±1 µA

±10 µA

±1 µA

15 50 µA

715µA

715µA

I

DDD

I

DD

I

DDR

I

DDW

I

DDE

I

DDWES

I

PPS

I

PPR

I

PPW

I

PPE

Supply Current (Reset) Flash

Supply Current SRAM

Supply Current (Read) Flash

Supply Current (Program)

Flash

Supply Current (Erase) Flash

Supply Current

(Program/Erase Suspend)

Program Current

(Read or Standby)

Flash

Flash

Program Current (Reset) Flash

Program Current
(Program)

Flash

Program Current (Erase) Flash

RP

= V

F

SSF

f = fmax = 1/

0.2V, I

V

≤

IN

f = 1MHz,

0.2V, I

≤

V

IN

E

= VIL, G

F

=

F

Program in progress

= 12V ± 5%

V

PPF

Program in progress

= V

V

PPF

Erase in progress

= 12V ± 5%

V

PPF

Erase in progress

= V

V

PPF

EF = V

DDQF

Erase suspended

≤

V

PPF

V

> V

PPF

RP

= V

F

SSF

Program in progress

= 12V ± 5%

V

PPF

Program in progress

= V

V

PPF

Erase in progress
V

= 12V ± 5%

PPF

Erase in progress

= V

V

PPF

± 0.2V

OUT

OUT

V

IH,

DDF

DDF

± 0.2V,

V

DDF

DDF

± 0.2V

DDF

DDF

,

AVAV

= 0 mA

= 0 mA

f = 5MHz

15 50 µA

5.5 12 mA

1.5 3 mA

918mA

510mA

10 20 mA

520mA

10 20 mA

15 50 µA

15µA

400 µA

15µA

110mA

15µA

310mA

15µA

14/66

M36W432TG, M36W432BG

Symbol Parameter Device Test Condition Min Typ Max Unit

V

V

V

V

V

V

V

IL

V

IH

OL

OH

PPL

PPH

PPLK

LKO

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

Program Voltage
(Program or Erase
operations)

Program Voltage
(Program or Erase
operations)

Program Voltage
(Program and Erase lock­out)

V

Supply Voltage

DDF

(Program and Erase lock­out)

Flash &

SRAM

Flash &

SRAM

Flash and

SRAM

Flash &

SRAM

V

DDQF

V

DDQF

V

DDQF

V

DDQF

= V

I

= V

I

OH

= V

= V

OL

DDS

= 100µA

DDS

= –100µA

Flash 1.65 3.6 V

Flash 11.4 12.6 V

Flash 1 V

Flash 2 V

≥

DDS

≥

DDS

= VDDmin

= VDDmin

2.7V

2.7V

–0.3 0.8 V

V

0.7

DDQF

V

DDQF

+0.3

0.1 V

V

DDQF

–0.1

V

V

15/66

M36W432TG, M36W432BG

PACKAGE MECHANICAL

Figure 7. Stacked LFBGA66 12x8mm, 8x8 ball array, 0.8mm pitch, Bottom View Package Outline

D
D2
D1

E

E1

BALL "A1"

Note: Drawing is not to scale.

SE

A

FDFE

SD

e

b

e

ddd

A2

A1

BGA-Z12

Table 7. Stacked LFBGA66 12x8mm , 8x8 ball array, 0.8mm pitch, Package M echan ical Data

Symbol

A 1.400 0.0551
A1 0.300 0.0118
A2 1.100 0.0433

b 0.400 0.300 0.500 0.0157 0.0118 0.0197

D 12.000 – – 0.47 24 – –

D1 5.600 – – 0.2205 – –
D2 8.800 – – 0.3465 – –

ddd 0.100 0.0039

E 8.000 – – 0.3150 – –

E1 5.600 – – 0.2205 – –

e 0.800 – – 0.0315 – –

FD 1.600 – – 0.0630 – –
FE 1.200 – – 0.0472 – –

SD 0.400 – – 0.0157 – –

SE 0.400 – – 0.0157 – –

Typ Min Ma x Typ Min Max

millimeters inches

16/66

M36W432TG, M36W432BG

Figure 8. Stacked LFBGA66 Daisy Chain - Package Connections (Top view through package)

AI90172

#4#3

8761

5

4

32#1 #2

A

B

C

D

E

F

G

H

17/66

M36W432TG, M36W432BG

Figure 9. Stacked LFBGA66 Daisy Chain - PCB Connections proposal (Top view through package)

#4#3

AI90173

END

POINT

POINT

START

87615

4

32#2

18/66

#1

A

B

C

D

E

F

G

H

M36W432TG, M36W432BG

PART NUMBERING
Table 8. Ordering Information Scheme

Example: M36 W 4 32T G 70 ZA 6 T

Device Type

M36 = MMP (Flash + SRAM)

Operating Voltage

W = V

SRAM Chip Size & Organization

4 = 4 Mbit (256Kb x 16)

Flash Device Size & Organization

32 = 32 Mbit (x16), Boot Block, Flash memory

Array Matrix

T = Top Boot
B = Bottom Boot

SRAM Device

G = 4Mb, 0.16µm, 70ns, 3V

= 2.7V to 3.3V, V

DDF

DDS

= V

= 2.7V to 3.3V

DDQF

Speed

70 = 70ns
85 = 85ns

Package

ZA = LFBGA66: 12 x 8mm, 0.8mm pitch

Temperature Range

1 = 0 to 70°C
6 = –40 to 85°C

Option

T = Tape & Reel packing

Devices are shipped from the factory with the memory content bits erased to ’1’.

Table 9. Daisy Chain Ordering Scheme

Example: M36W432TG -ZA T

Device Type

M36W432TG

Daisy Chain

-ZA = LFBGA66: 12 x 8mm, 0.8mm pitch

Option

T = Tape & Reel Packing

For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,
please contact the STMicroelectronics Sales Office nearest to you.

19/66

M36W432TG, M36W432BG

FLASH DEVICE

The M36W432TG contains one 32 Mbit Flash
memory. This section describes how to use the

FLASH SUMMARY DESCRIPTION

The Flash Memory is a 32 Mbit (2 Mbit x 16) device
that can be erased electrically at block level and
programmed in-system on a Word-by-Word basis.
These operations can be performed using a single
low voltage (2.7 to 3.6V) supply. V
drive the I/O pin down to 1.65V. An optional 12V

power supply is provided to speed up cus-

V

PPF

tomer programming.
The device features an asymmetrical blocked ar-

chitecture with an array of 71 blocks: 8 Parameter
Blocks of 4 KWords and 63 Main Blocks of 32
KWords. The M36W432TG has the Parameter
Blocks at the top of the memory address space
while the M36W432BG locates the Parameter
Blocks starting from the bottom. The memory
maps are shown in Figure 10, Block Addresses.

The Flash Memory features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency, enabling in­stant code and data protection. All blocks have
three levels of protection. They can be locked and
locked-down individually preventing any acciden­tal programming or erasure. There is an additional
hardware protection against program and erase.
When V

PPF

≤ V

all blocks are protected

PPLK

DDQF

allows to

Flash device and all signals refer to the Flash de­vice .

against program or erase. All blocks are locked at
Power Up.

Each block can be erased separately. Erase can
be suspended in order to perform either read or
program in any other block and then resumed.
Program can be suspended to read data in any
other block and then resumed. Each block can be
programmed and erased over 100,000 cycles.

The device includes a Protection Register to in­crease the p rotecti on of a syst em desi gn. The Pro­tection Register is divided into t wo se gments, the
first is a 64 bit area which contains a unique device
number written by ST, while the second is a 128 bit
area, one-time-programmable by the user. The
user programmable segment can be permanent ly
protected. Figure 11, shows the Protection Regis­ter Memo ry Map.

Program and Erase command s are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller takes care of the tim­ings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.

20/66

Figure 10. Flash Block Addresses

M36W432TG, M36W432BG

Top Boot Block Addresses

1FFFFF

1FF000

1F8FFF

1F8000

1F7FFF

1F0000

00FFFF

008000

007FFF

000000

Note: Also see Appendix A, Tables 26 and 27 f or a full listing of the Flash Bl ock Addresses.

4 KWords

Total of 8

4 KWord Blocks

4 KWords

32 KWords

Total of 63

32 KWord Blocks

32 KWords

32 KWords

Bottom Boot Block Addresses

1FFFFF

1F8000

1F7FFF

1F0000

00FFFF

008000

007FFF

007000

000FFF

000000

32 KWords

32 KWords

Total of 63

32 KWord Blocks

32 KWords

4 KWords

Total of 8

4 KWord Blocks

4 KWords

AI90164

Figure 11. Protection Register Memory Map

PROTECTION REGISTER

8Ch

User Programmable OTP

85h
84h

81h
80h

Note: 1. Bit 2 of the Protectio n Register Lock must not be program m ed t o 0.

Unique device number

Protection Register Lock 2

(1)

10

AI07927

21/66

M36W432TG, M36W432BG

FLASH BUS OPERATIONS

There are six standard bus operations that control
the device. These are Bus Read, Bus Wri te, Out­put Disable, Standby, Automatic Standby and Re­set. See Table 2, Main Operation Modes, for a
summary.

Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.

Read. Read Bus operations are used to output
the contents of the Memory Array, the Electronic
Signature, the Status Register and the Common
Flash Interface. Both Chip Enable and Output En­able must be at V
eration. The Chip Enable input should be used t o
enable the device. Out put E nable shoul d be used
to gate data onto th e output. The data read de­pends on the previous command written to the
memory (see Command Interface section). See
Figure 12, Flash Read Mode AC W av eforms , and
Table 19, Flash Read AC Chara cteristics, for de­tails of when the output becomes valid.

Read mode is the default state of the device when
exiting Reset or after power-up.

Write. Bus Write operations write Comm ands to
the memory or latch Input Data to be programmed.
A write operation is initiated when Chip Enable
and Write Enable are at V
V

. Commands, Input Data and Addresses are

IH

latched on the rising edge of Write Enable or Chip
Enable, whichever occurs first.

in order to perform a read op-

IL

with Output Enable at

IL

See Figures 13 and 14, Flash Write AC Wave­forms, and Tables 20 and 21, Write AC Character­istics, for details of the timing requirements.

Output Disa bl e . The data outputs are high im­pedance when the Output Enable is at V

.

IH

Standby. Stan dby disables most of the inte rnal
circuitry allowing a substantial reduction of the cur­rent consumption. The memory is in stand-by
when Chip Enable is at V

and the device is in

IH

read mode. The power consumption is reduced to
the stand-by level and the o utputs are set to high
impedance, independently from the Output Enable
or Write Enable inputs. If Chip Enable switches to
V

during a program or erase operation, t he de-

IH

vice enters Standby mode when finished.
Automatic Standby. Automatic Standby pro-

vides a low power consumption state during Read
mode. Following a read operation, the device en­ters Automatic Standby after 150ns of bus inactiv­ity even if Chip Enable is Low, V
current is reduced to I

. The data I nputs/Out-

DD1

, and the supply

IL

puts will still output data if a bus Read operation is
in progress.

Reset. During Reset mode when Output Enable
is Low, V

, the memory is deselected and the out-

IL

puts are high impedance. The memory is in Reset
mode when Reset is at V

. The power consump-

IL

tion is reduced to the Standby level, independently
from the Chip Enable, Output Enable or Write En­able inputs. If Reset is pulled t o V

during a Pro-

SSF

gram or Erase, this operation is aborted and the
memory content is no longer valid.

22/66

FLASH COMMAND INTERFACE

All Bus Write operations t o the me mory are in ter­preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper­ations. An internal Program/Erase Controller han­dles all timings and verifies the correct execution
of the Program and Erase commands. The Pro­gram/Erase Controller provides a Status Regi ster
whose output may be read at any time during, to
monitor the progress of the operat ion, or the Pro­gram/Erase states. See Table 10, Command
Codes, for a summary o f the c ommands and see
Appendix 30, Table 34, Write State Machine Cur­rent/Next, for a summary of the Command Inter­face.

The Command Interface is reset to Read mode
when power is first applied, when exiting from Re­set or whenever V

is lower than V

DDF

LKO

. Com­mand sequences must be followed exactly. Any
invalid combination of commands will reset the de­vice to Read mode. Refer to Table 11, Com­mands, in conjunction with the text descriptions
below.

Read Memory Array Command

The Read command returns the memory to its
Read mode. One Bus Write cycle is required to is­sue the Read Memory Array command and return
the memory to Read mode. Subsequ ent read op­erations will read the addressed location and out­put the data. When a device Reset occurs, the
memory defaults to Read mode.

Read Status Register Command

The Status Register indicates when a program or
erase operation is complete and the success or
failure of the operation itself. Issue a Read Status
Register command to rea d the Status Register’s
contents. Subsequent Bus Read op erations read
the Status Register at any address, u ntil another
command is issued. See Table 18, Status Register
Bits, for details on the definitions of the bits.

The Read Status Register command m ay be is­sued at any time, even during a Program/Erase
operation. Any Read attempt during a Program/
Erase operation will automatically output the con­tent of the Status Register.

Read Electronic Signature Command

The Read Electronic Signature command reads
the Manufacturer and Device Codes and the Block
Locking Status, or the Protection Register.

The Read Electronic Signature command consists
of one write cycle, a subsequent read will ou tput
the Manufacturer Code, the Device Code, the
Block Lock and Lock-Down Status, or the Protec­tion and Lock Register. See Tables 12, 13 and 14
for the valid address.

M36W432TG, M36W432BG

Table 10. Fla sh C om m and Codes

Hex Code Command

01h Block Lock confirm

10h Program
20h Erase

2Fh Block Lock-Down confirm

30h
40h Program

50h Clear Status Register
55h Reserved

56h

60h

70h Read Status Register
90h Read Electronic Signature
98h Read CFI Query
B0h Program/Erase Suspend
C0h Protection Register Program

D0h

FFh Read Memory Array

Read CFI Query Command

The Read Query Command is used to read dat a
from the Common Flash Interface (CFI) Me mory
Area, allowing programming equi pment or appli­cations to automatically match their interface to
the characteristics of the device. One Bus Write
cycle is required to issue the Read Query Com­mand. Once the command is issued subsequent
Bus Read operations read from the Common
Flash Interface Memory Area. See Appendix B,
Common Flash Inte rface, Tables 28, 29, 30, 31,
32 and 33 for details on the information contained
in the Common Flash Interface memory area.

Block Erase Command

The Block Erase com mand can be used to erase
a block. It sets all the bits within the selected block
to ’1’. A ll previous data in t he block is lost. If the
block is protected then the Erase operation will
abort, the data in the block will not be changed and
the Status Register will output the error.

Two Bus Write cycles are required to issue the
command.

■ The first bus cycle sets up the Erase command.

Double Word Program

Quadruple Word Program
Block Lock, Block Unlock, Block Lock-

Down

Program/Erase Resume, Block Unlock
confirm

23/66

M36W432TG, M36W432BG

■ The second latches the block address in the

internal state machine and starts the Program/
Erase Controller.

If the second bus cycle is not Write Erase Confirm
(D0h), Status Register bits b4 and b5 are set and
the command aborts.

Erase aborts if Reset turns to V

. As data integrity

IL

cannot be guaranteed when the Erase operation is
aborted, the block must be erased again.

During Erase operations the memory will accept
the Read Status Re gister com mand and the P ro­gram/Erase Suspend command, all other com­mands will be ignored. Typical Erase times are
given in Table 15, Program, Erase Times and Pro­gram/Erase Endurance Cycles.

See Appendix C, Figure 29 , Erase Flowchart and
Pseudo Code, for a suggested flowchart for using
the Erase command.

Program Command

The memory array can be programmed word-by­word. Two bus write cycles are required to issue
the Program Command.

■ The first bus cycle sets up the Program

command.

■ The second latches the Address and the Data to

be written and starts the Program/Erase
Controller.

During Program operations the memory will ac­cept the Read Status Register command and the
Program/Erase Suspend command. Typical Pro­gram times are given in Table 15, Program, Erase
Times and Program/Erase Endurance Cycles.

Programming aborts if Reset goe s to V

. As data

IL

integrity cannot be guaranteed when the program
operation is aborted, the block containing the
memory location must be erased and repro­grammed.

See Appendix C, Figure 25, Program Flowchart
and Pseudo Code, for the f lowchart for using the
Program command.

Double Word Program Command

This feature is offered to improve the programming
throughput, writing a page of two adjacent words
in parallel.The two words m ust differ only for the
address A0. Programm ing s hould not b e at t emp t­ed when V

is not at V

PPF

PPH

.

Three bus write cycles are necessary to issue the
Double Word Program command.

■ The first bus cycle sets up the Double Word

Program Command.

■ The second bus cycle latches the Address and

the Data of the first word to be written.

■ The third bus cycle latches the Address and the

Data of the second word to be written and starts
the Program/Erase Controller.

Read operations output the Status Register con­tent after the programming has s tarted. Program­ming aborts if Reset goes to V

. As data integrity

IL

cannot be guaranteed when the program opera­tion is aborted, the block containing the memory
location must be erased and reprogrammed.

See Appendix C, Figure 26, Double Word Pro­gram Flowchart and Pseudo Code, for the flow­chart for using the Double Word Program
command.

Quadruple Word Program Command

This feature is offered to improve the programming
throughput, writing a page of four adjacent words
in parallel.The four words must differ only for the
addresses A0 and A1. Programming should not be
attempted when

is not at V

PPF

PPH

.

V

Five bus write cycles are necessary to issue the
Quadruple Word Program command.

■ The first bus cycle sets up the Quadruple Word

Program Command.

■ The second bus cycle latches the Address and

the Data of the first word to be written.

■ The third bus cycle latches the Address and the

Data of the second word to be written.

■ The fourth bus cycle latches the Address and

the Data of the third word to be written.

■ The fifth bus cycle latches the Ad dr es s and th e

Data of the fourth word to be written and starts
the Program/Erase Controller.

Read operations output the Status Register con­tent after the programming has s tarted. Program­ming aborts if Reset goes to V

. As data integrity

IL

cannot be guaranteed when the program opera­tion is aborted, the block containing the memory
location must be erased and reprogrammed.

See Appendix C, Figure 27, Quadruple Word Pro­gram Flowchart and Pseudo Code, for the flow­chart for using the Quadruple Word Program
command.

Clear Status Register Command

The Clear Status Register comm and can be used
to reset bits 1, 3, 4 and 5 in the Status Register to
‘0’. One bus write cycle is required to issue the
Clear Status Register command.

The bits in the Status Register do not automatical­ly return to ‘0’ when a new Program or Erase com­mand is issued. The error bits in the Status
Register should be cleared before attempting a
new Program or Erase command.

Program/Erase Suspend Command

The Program/Erase Suspend command is used to
pause a Program or Erase operation. One bus
write cycle is required to issue the Program/Erase
command and pau se the Prog ram/Erase control­ler.

24/66

M36W432TG, M36W432BG

During Program/Erase Suspend the Command In­terface will accept the Program/Erase Resume,
Read Array, Read Status Register, Read Electron­ic Signature and Read CFI Query commands. Ad­ditionally, if the suspend operation was Erase then
the Program, Double Word Program, Quadruple
Word Program, Block Lo ck, Block Lock-Down or
Protection Program commands will also be ac­cepted. The block being erased may be protected
by issuing the Block Protect, Block Lock or Protec­tion Program commands. When the Program/
Erase Resume comm and is issued the operation
will complete. Only the blocks not being erased
may be read or programmed correctly.

During a Program/Erase Suspend, the device can
be placed in a pseudo-standby mode by taking
Chip Ena ble to V
Reset turns to V

. Program/Erase is aborted if

IH

.

IL

See Appendix C, Figure 2 8, Program or Double
Word Program Suspend & Resume Flowchart and
Pseudo Code, an d Figure 30, Erase Sus pend &
Resume Flowchart and Pseudo Code for flow­charts for using the Program/Erase Suspend com­mand.

Program/Erase Resume Command

The Program/Erase Resume command can be
used to restart the Program/Erase Controller after
a Program/Erase Suspend o peration has paused
it. One Bus Write cycle is required to issue the
command. Once the command is issued subse­quent Bus Read operations read the Status Reg­ister.

See Appendix C, Figure 2 8, Program or Double
Word Program Suspend & Resume Flowchart and
Pseudo Code, an d Figure 30, Erase Sus pend &
Resume Flowchart and Pseudo Code for flow­charts for using the Program/Erase Resume com­mand.

Prot e ction R e gister P rogram C om m and

The Protection Register Program command is
used to Program the 128 bit user O ne-Time-Pro­grammable (OTP) segment of the Protection Reg­ister. The segment is programmed 16 bits at a
time. When shipped all bits in the segment are set
to ‘1’. The user can only program the bits to ‘0’.

Two write cycles are required to issue the Protec­tion Register Program command.

■ The first bus cycle sets up the Protection

Register Program command.

■ The second latches the Address and the Data to

be written to the Protection Register and starts
the Program/Erase Controller.

Read operations output the Status Register con­tent after the programming has started.

The segment can be protected by programming bit
1 of the Protection Lock Register (see Figure 11,

Protection Register Memory Map). Attempting to
program a previously prot ected Protection Regis­ter will result in a Status Register error. The pro­tection of the Protection Register is not reversible.

The Protection Register Program cannot be sus­pended.

Block Lock Command

The Block Lock command is used to lock a block
and prevent Program or Erase operations from
changing the data in it. All blocks are locked at
power-up or reset.

Two Bus Write cycles are required to issue the
Block Lock command.

■ The first bus cycle sets up the Block Lock

command.

■ The second Bus Write cycle latc hes the blo ck

address.

The lock status can be monitored for each block
using the Read Electronic Signature command.
Table. 17 shows the protection status after issuing
a Block Lock command.

The Block Lock bits are volatile, once set they re­main set until a hardware reset or power-down/
power-up. They are cleared by a Blocks Unlock
command. Refer to the section, Block Locking, for
a detailed explanation.

Block Unlock Command

The Blocks Unlock command i s used to unlock a
block, allowing the block to be programmed or
erased. Two Bus Write cycles are requ ired to is­sue the Blocks Unlock command.

■ The first bus cycle sets up the Block Unlock

command.

■ The second Bus Write cycle latc hes the blo ck

address.

The lock status can be monitored for each block
using the Read Electronic Signature command.
Table. 17 shows the protection status after issuing
a Block Unlock command. Refer to the section,
Block Locking, for a detailed explanation.

Block Lock-Down Command

A locked block cannot be Programmed or Erased,
or have its protection status changed when WP
low, V

. Whe n WPF is high, V

IL

the Lock-Down

IH,

is

F

function is disabled and the lock ed blocks can be
individually unlocked by the Block Unlock com­mand.

Two Bus Write cycles are required to issue the
Block Lock-Down command.

■ The first bus cycle sets up the Block Lock

command.

■ The second Bus Write cycle latc hes the blo ck

address.

25/66

M36W432TG, M36W432BG

The lock status can be monitored for each block
using the Read Electronic Signature command.
Locked-Down blocks revert to the locked (and not
locked-down) state when the device is reset on

power-down. Table. 17 sho ws the protection sta­tus after issuing a Block Lock-Down command.
Refer to the section, Block Locking, for a detailed
explanation.

Table 11. Flash Commands

Bus Write Operations

Commands

Read Memory
Array

Read Status
Register

Read Electronic
Signature

Read CFI Query 1+ Write X 98h Read QA QD
Erase 2 Write X 20h Write BA D0h

Program 2 Write X

Double Word
Program

Quadruple Word
Program

Clear Status
Register

Program/Erase
Suspend

Program/Erase
Resume

Block Loc k 2 Write X 60h Write
Block Unlock 2 Write X 60h Write
Block Loc k-Down 2 Writ e X 60h Write
Protectio n

Register Program

Note: 1. X = Don’t C are, RA=Rea d Addre ss, RD =Read D ata, SRD =Stat us Regis ter Da ta, ID =Identif ier (Ma nufact ure and Devic e Code),

(3)

(4)

QA=Query Address, QD=Query Data, BA=Block Address, PA=Program Address, PD=Program Data, PRA=Protection Register Ad­dress, PRD=Protection Regis ter Data.

2. The s i gnature addresses are l i st ed in Tables 12, 13 and 14.

3. Program Addres ses 1 and 2 must b e consecutive Addresses differing only for A0.

4. Program Addres ses 1,2,3 and 4 m ust be consecutive Addresses differing only for A0 and A1.

5. 55h is reserved.

6. To be c haracteriz e d.

1+ Write X FFh

1+ Write X 70h Read X SRD

1+ Write X 90h Read

1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle

Cycles

Op. Add Data Op. Add Data Op. Add Data Op. Add Data Op. Add Data

RA RD

Read

(2)

IDh

SA

40h

or

Write PA PD

10h

3 Write X 30h Write PA1 PD1 Write PA2 PD2

5Write X

1 Write X 50h

1Write X B0h

1Write X D0h

(6)

Write PA1 PD1 Write PA2 PD2 Write PA3 PD3 Write PA4 PD4

56h

BA 01h
BA D0h

2Fh

BA

2 Write X C0h Write

PRA PRD

26/66

M36W432TG, M36W432BG

Table 12. Flash Read Electronic Signature

E

Code Device

Manufacture.
Code

M36W432TG

Device Code

M36W432BG

Note: RP = VIH.

Table 13. Flash Read Block Lock Signature

E

Block Status

Locked Block
Unlocked Block
Locked-Down

Block

Note: 1. A Locked -Down Block can be locked "DQ0 = 1" or unlock ed "DQ0 = 0"; see B l ock Locking sec tion.

GFW

F

V

ILVILVIHVILVIH

V

ILVILVIHVILVIH

V

ILVILVIHVILVIH

Table 14. Flash Read Protection Register and Lock Register

E

Word

Lock

Unique ID 0
Unique ID 1
Unique ID 2
Unique ID 3
OTP 0
OTP 1
OTP 2
OTP 3
OTP 4
OTP 5
OTP 6
OTP 7

Note: 1. DQ2 in the Protection Lock Register must not be programmed to 0.

GFW

F

V

ILVILVIH

V

ILVILVIH

V

ILVILVIH

V

ILVILVIH

V

ILVILVIH

V

ILVILVIH

V

ILVILVIH

V

ILVILVIH

V

ILVILVIH

V

ILVILVIH

V

ILVILVIH

V

ILVILVIH

V

ILVILVIH

A0-A7 A8-A20 DQ0 DQ1 DQ2 DQ3-DQ7 DQ8-DQ15

F

GFW

F

VILV

V

IL

V

VILV

IL

V

VILV

IL

A0 A1 A2-A7 A8-A11 A12-A20 DQ0 DQ1 DQ2-DQ15

F

A0 A1 A2-A7 A8-A20 DQ0-DQ7 DQ8-DQ15

F

V

IH

IHVIH

IHVIH

V

IL

V
V

0 Don’t Care 20h 00h

IL

0 Don’t Care BAh 88h

IL

0 Don’t Care BBh 88h

IL

0 Don’t Care Block Address 1 0 00h
0 Don’t Care Block Address 0 0 00h

0 Don’t Care Block Address

80h Don’t Care Don’t Care

OTP Prot.

data

Don’t Care

See note (1)
81h Don’t Care ID data ID data ID data ID data ID data
82h Don’t Care ID data ID data ID data ID data ID data
83h Don’t Care ID data ID data ID data ID data ID data
84h Don’t Care ID data ID data ID data ID data ID data
85h Don’t Care OTP data OTP data OTP data OTP data OTP data
86h Don’t Care OTP data OTP data OTP data OTP data OTP data
87h Don’t Care OTP data OTP data OTP data OTP data OTP data
88h Don’t Care OTP data OTP data OTP data OTP data OTP data
89h Don’t Care OTP data OTP data OTP data OTP data OTP data
8Ah Don’t Care OTP data OTP data OTP data OTP data OTP data
8Bh Don’t Care OTP data OTP data OTP data OTP data OTP data
8Ch Don’t Care OTP data OTP data OTP data OTP data OTP data

(1)

X

1 00h

Don’t
Care

Don’t Care

27/66

M36W432TG, M36W432BG

Table 15. Flash Program, Erase Times and Program/Erase Endurance Cycles

Parameter Test Conditions

Min Typ Max

V

Word Program
Double Word Program
Quadruple Word Program

Main Block Program

Parameter Block Program

Main Block Erase

Parameter Block Erase

= V

PPF

V

= 12V ±5%

PPF

V

= 12V ±5%

PPF

V

= 12V ±5%

PPF

= V

V

PPF

V

= 12V ±5%

PPF

= V

V

PPF

= 12V ±5%

V

PPF

= VDDV

V

PPF

V

= 12V ±5%

PPF

V

= V

PPF

DDF

DDF

DDF

DDF

DDF

Program/Erase Cycles (per Block) 100,000 cycles

Note: 1. Typical time to program a Main or Parameter Block using the Double Word Program and the Quadruple Word Program commands

respectively.

Flash Device

10 200 µs
10 200 µs
10 200 µs

0.16/0.08

(1)

5s

0.32 5 s

0.02/0.01

(1)

4s

0.04 4 s
110s
110s

0.4 10 s

0.4 10 s

Unit

28/66

FLASH BLOCK LOCKING

The M36W432TG features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency. This locking
scheme has three levels of protection.

■ Lock/Unlock - this first level allows software-

only control of block locking.

■ Lock-Down - this second level requires

hardware interaction before locking can be
changed.

■ V

PPF

≤ V

- the third leve l offers a compl e te

PPLK

hardware protection against program and erase
on all blocks.

The protection status of each block can be set to
Locked, Unlocked, and Lock-Down. Table 17, de­fines all of the possible protection states (WP

F

DQ1, DQ0), and Appendi x C, Figure 31, shows a
flowchart for the locking operations.

Reading a Block’s Lock Status

The lock status of every block can be read in the
Read Electronic Signature mode of the device. To
enter this mode write 90h t o the device. Subse­quent reads at the a ddress s pecified in Table 13,
will output the p rotectio n status of that block. The
lock status is represented by DQ0 and DQ1. DQ 0
indicates the Block Lock/Unlock s tatus and is set
by the Lock comm and and cleared by the Unlock
command. It is also autom atically set when en ter­ing Lock-Down. DQ1 indicates the Lock-Down sta­tus and is set by the Lock-Down command. It
cannot be cleared by software, only by a hardware
reset or power-down.

The following sections explain the operation of the
locking system.

Locked State

The default status of all blocks on power-up or af­ter a hardware reset is Locked (states (0,0,1) or
(1,0,1)). Locked blocks are fully protected from
any program or erase. Any program or erase oper­ations attempted on a locked block will return an
error in the Status Register. The Status of a
Locked block can be changed to Unlocked or
Lock-Down using the appropriate software com­mands. An Unlocked block can be Locked by issu­ing the Lock command.

Unlocked State

Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)),
can be programmed or erased. All unlocked
blocks return to the Locked state a ft er a hardware
reset or when the device is powered-down. The
status of an unlocked block can be changed to
Locked or Locked-Down using the appropriate

M36W432TG, M36W432BG

software commands. A locked block can be un­locked by issuing the Unlock command.

Lock-Down State

Blocks that are Locked-Down (state (0,1,x))are
protected from program and erase operations (as
for Locked blocks) but their protection status can­not be changed using software comma nds alone.
A Locked or Unlocked block can be Locked-Down
by issuing the Lock-Down command. Locked­Down blocks revert to the Locked state when the
device is reset or powered-down.

The Lock-Down function is dependent on the WP
input pin. When WPF=0 (VIL), the blocks in the
Lock-Down state (0,1,x) are protected from pro­gram, erase and protection status changes. When
WP

=1 (VIH) the Lock-Down function is disabled

,

F

(1,1,1) and Locked-Down blocks can be ind ividu­ally unlocked to the (1,1,0) state by issuing the
software command, where they can be erased and
programmed. These blocks can then be relocked
(1,1,1) and unlocked (1,1,0) as desired while WP
remains high. When WPF is low , blocks that were
previously Locked-Down return to the Lock-Down
state (0,1,x) regardless of any changes made
while WP

was high. Device reset or power-down

F

resets all blocks , including those in Lock-Down, to
the Locked state.

Locking Operations During Erase Suspend

Changes to block lock status can be performed
during an erase suspend by using the standard
locking command sequences to unlock, lock or
lock-down a block. This is useful in the case when
another block needs to be updated while an erase
operation is in progress.

To change block locking during an erase opera­tion, first write the Erase Suspend command, then
check the status register until it indicates that the
erase operation has been suspended. Next write
the desired Lock com mand sequence to a block
and the lock status will be changed. After complet­ing any desired lock, read, or program operations,
resume the erase operation with the Erase Re­sume command.

If a block is locked or locked-down during an erase
suspend of the same block, the locking status bits
will be changed immediately , but when the eras e
is resumed, the erase operation will complete.

Locking operations cannot be performed du ring a
program suspend. Refer to Appendix D, Com­mand Interface and Program/Erase Controller
State, for detailed information on which com­mands are valid during erase suspend.

F

F

29/66

M36W432TG, M36W432BG

Table 16. Flash Block Lock Status

Item Address Data

Block Lock Configuration

LOCK

Block is Unlocked DQ0=0

xx002

Block is Locked DQ0=1

Block is Locked-Down DQ1=1

Table 17. Flash Protection Status

Protection Status

(WPF, DQ1, DQ0)

Current State

Current

Program/Erase

(1)

Allowed

After

Block Lock

Command

Next Protection Status

(WPF, DQ1, DQ0)

After

Block Unlock

Command

1,0,0 yes 1,0,1 1,0,0 1,1,1 0,0,0

1,0,1

(2)

no 1,0,1 1,0,0 1,1,1 0,0,1

1,1,0 yes 1,1,1 1,1,0 1,1,1 0,1,1
1,1,1 no 1,1,1 1,1,0 1,1,1 0,1,1
0,0,0 yes 0,0,1 0,0,0 0,1,1 1,0,0

0,0,1

(2)

no 0,0,1 0,0,0 0,1,1 1,0,1

0,1,1 no 0,1,1 0,1,1 0,1,1

Note: 1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block) as read

in the Read El ectronic Si gnature comm and with A1 = V

2. All blocks are loc ked at power-up, so the default config uration is 00 1 or 101 accor di ng to WP

3. A WP

transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.

F

and A0 = VIL.

IH

(1)

After Block
Lock-Down

Command

status.

F

After

transition

WP

F

1,1,1 or 1,1,0

(3)

30/66

FLASH STATUS REGISTER

The Status Register provides information on t he
current or previous Program or Erase operation.
The various bits convey information and errors on
the operation. To read the Status register the
Read Status Register command can be issued, re­fer to Read Status Register Command section. To
output the contents, the Status Register is latched
on the falling edge of the Chip Enable or Output
Enable signals, and can be read until Chip Enable
or Output Enable returns to V

. Either Chip En-

IH

able or Output Enable must be toggled to update
the latched data.

Bus Read operations from any address always
read the Status Register during Program and
Erase operations.

The bits in the Status Register are summarized in
Table 18, Status Register Bits. Refer to Table 18
in conjunction with the following text descriptions.

Program/Erase Controller Status (Bit 7). The Pro­gra m/Erase Controller Status bit indicates whether
the Program/Erase Controller is active or inactive.
When the Program/Erase Controller Status bit is
Low (set to ‘0’), the Program/Erase Controller is
active; when the bit is High (set to ‘1’), the Pro­gram/Erase Controller is inactive, and the device
is ready to process a new command.

The Program/Erase Controller Status is Low im­mediately after a Program/Erase Suspend com­mand is issued until the Program/Erase Controller
pauses. After the Program/Erase Controller paus­es the bit is High .

During Program, Erase, operations the Program/
Erase Controller Status bit can be polled to find the
end of the operation. Other bits in the Status Reg­ister should not be tested until the Program/Erase
Controller completes the operation and the bit is
High.

After the Program/Erase Cont roller completes its
operation the Erase Status, Program Status, V

PPF

Status and Block Lock Status bits should be tested
for errors.

Erase Suspend Status (Bit 6). The Erase Sus­pend Status bit indicates that an Erase o peration
has been suspended or is going to be suspended.
When the Erase Suspend Status bit is High (set to
‘1’), a Program/Erase Suspend command has
been issued and the memory is waiting for a Pro­gram/Erase Resume command.

The Erase Suspend Status should only be consid­ered valid when the Program/Erase Controller Sta­tus bit is High (Program/Erase Controller inactive).
Bit 7 is set within 30µs of the Program/Erase Sus­pend command being issued therefore the memo­ry may still complete the operation rather than
entering the Suspend mode.

M36W432TG, M36W432BG

When a Program/Erase Re sume command is is­sued the Erase Suspend Status bit returns Low.

Erase Status (Bit 5). The Erase Status bit can be
used to identify if the memory has failed to verify
that the block has erased correctly. When the
Erase Status bit is High (set t o ‘1’), the Program/
Erase Controller has applied the max imum num­ber of pulses to the block and still failed to verify
that the block has erased correctly. The Erase Sta­tus bit should be read once the Program/Erase
Controller Status bit is High (Program/Erase Con­troller inactive).

Once set High, the Erase Status bit can only be re­set Low by a Clear Status Register command or a
hardware reset. If set High it should be reset be­fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.

Program Status (Bit 4). The Program Status bit
is used to identify a Program failure. When the
Program Status bit is High (set to ‘1’), the Pro­gram/Erase Controller has applied the maximum
number of pulses to the byte and still failed to ver­ify that it has programmed correctly. The Program
Status bit should be read once the Program/Erase
Controller Status bit is High (Program/Erase Con­troller inactive).

Once set High, the Program Status bit can only be
reset Low by a Clear Status Register command or
a hardware reset. If set High it should be reset be­fore a new command is issued, otherwise the new
command will appear to fail.

Status (Bit 3). Th e V

V

PPF

used to identify an invalid voltage on the V
during Program and Erase operations. The V
pin is only sampled at the beginning of a Program
or Erase operation. Indeterminate results can oc­cur if V

When the V
voltage on the V
voltage; when the V
‘1’), the V
V

PPF

becomes invalid during an operation.

PPF

Status bit is Low (set to ‘0’), the

PPF

pin has a voltage that is be low the

PPF

pin was sampled at a val id

PPF

Status bit is High (set to

PPF

Lockout Voltage, V
tected and Program and Erase operations cannot
be performed.

Once set High, the V

PPF

set Low by a Clear Status Register command or a
hardware reset. If set High it should be reset be­fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.

Program Suspend Status (Bit 2). The Program
Suspend Status bit indicates that a Program oper­ation has been suspended. When the Program
Suspend Status bit is High (set to ‘1’), a Program/
Erase Suspend command has been issued and
the memory is waiting for a Program/Erase Re­sume command. The Program Suspend Status

Status bit can be

PPF

, the memory is pro-

PPLK

PPF

pin

PPF

Status bit c an only be re-

31/66

M36W432TG, M36W432BG

should only be considered valid when the Pro­gram/Erase Controller Status bit is High (Program/
Erase Controller inactive). Bit 2 is set wi thin 5µs of
the Program/Erase Suspend comm and being is­sued therefore the memory may still complete t he
operation rather than entering the Suspend mode.

When a Program/Erase Re sume command is is­sued the Program Suspend Status bit returns Low.

Block Protection Status (Bit 1). The Block Pro­tection Status bit can be used to identify if a Pro­gram or Erase operation has tried to modify the
contents of a locked block.

When the Block Protection Status bit is High (set
to ‘1’), a Program or Erase operation has been at­tempted on a locked block.

Once set High, the Block Protection Status bit can
only be reset Low by a Clear Status Register com­mand or a hardware reset. If set High it should be
reset before a new command is issued, otherwise
the new command will appear to fail.

Reserved (Bit 0). Bit 0 of the Status Register is
reserved. Its value must be masked.

Note: Refer to Appendix C, Flowcharts and
Pseudo Codes, for using the Status Register.

Table 18. Flash Status Register Bits

Bit Name Logic Level Definition

7 P/E.C. Status

6 Erase Suspend Status

5 Erase Status

4 Program Status

’1’ Ready
’0’ Busy
’1’ Suspended
’0’ In progress or Completed
’1’ Erase Error
’0’ Erase Success
’1’ Program Error
’0’ Program Success

V

3

2 Program Suspend Status

1 Block Protection Status

0 Reserved

Note: Logic level ’1’ is High, ’0’ is Low.

PPF

Status

V

’1’
’0’
’1’ Suspended

’0’ In Progress or Completed
’1’ Program/Erase on protected Block, Abort
’0’ No operation to protected blocks

Invalid, Abort

PPF

V

OK

PPF

32/66

Figure 12. Flash Read Mode AC Waveforms

M36W432TG, M36W432BG

tAVAV

A0-A20

tAVQV

E

F

tELQV

tELQX

G

F

tGLQX

DQ0-DQ15

ADDR. VALID

CHIP ENABLE

Table 19. Flash Read AC Characteristics

Symbol Alt Parameter

t

AVAV

t

AVQV

(1)

t

AXQX

(1)

t

EHQX

(1)

t

EHQZ

(2)

t

ELQV

(1)

t

ELQX

(1)

t

GHQX

(1)

t

GHQZ

(2)

t

GLQV

(1)

t

GLQX

Note: 1. Sampled only, not 100% tested.

2. G

t

Address Valid to Next Address Valid Min 70 85 ns

RC

t

Address Valid to Output Valid Max 70 85 ns

ACC

t

Address Transition to Output Transition Min 0 0 ns

OH

t

Chip Enable High to Output Transition Min 0 0 ns

OH

t

Chip Enable High to Output Hi-Z Max 20 20 ns

HZ

t

Chip Enable Low to Output Valid Max 70 85 ns

CE

t

Chip Enable Low to Output Transition Min 0 0 ns

LZ

t

Output Enable High to Output Transition Min 0 0 ns

OH

t

Output Enable High to Output Hi-Z Max 20 20 ns

DF

t

Output Enable Low to Output Valid Max 20 20 ns

OE

t

Output Enable Low to Output Transition Min 0 0 ns

OLZ

may be delayed by up to t

F

ELQV

- t

after the falling edge of EF without increasing t

GLQV

tGLQV

OUTPUTS
ENABLED

VALID

tEHQX

tEHQZ

tGHQX

tGHQZ

VALID

DATA VALID STANDBY

Flash

70 85

.

ELQV

tAXQX

AI07928

Unit

33/66

M36W432TG, M36W432BG

Figure 13. Flash Write AC Waveforms, Write Enable Contro lled

AI07929

tWHAX

PROGRAM OR ERASE

tAVAV

VALIDA0-A20

tAVWH

tWHGL

tELQV

tWHEL

tQVWPL

STATUS REGISTER

tQVVPL

READ

1st POLLING

STATUS REGISTER

OR DATA INPUT

E

F

tELWL tWHEH

tVPHWH

tWHWL

tWPHWH

tWHDXtDVWH

tWLWH

SET-UP COMMAND CONFIRM COMMAND

F

G

F

W

DQ0-DQ15 COMMAND CMD or DATA

F

WP

V

PPF

34/66

Table 20. Flash Write AC Characteristics, Write Enable Controlled

Symbol Alt Parameter

M36W432TG, M36W432BG

Flash

Unit

70 85

t

AVAV

t

AVWH

t

DVWH

t

ELWL

t

ELQV

(1,2)

t

QVVPL

t

QVWPL

t

Note: 1. Sampled only, not 100% tested.

(1)

VPHWH

t

WHAX

t

WHDX

t

WHEH

t

WHEL

t

WHGL

t

WHWL

t

WLWH

t

WPHWH

2. Appl i cable if V

t

Write Cycle Time Min 70 85 ns

WC

t

Address Valid to Write Enable High Min 45 45 ns

AS

t

Data Valid to Write Enable High Min 45 45 ns

DS

t

Chip Enable Low to Write Enable Low Min 0 0 ns

CS

Chip Enable Low to Output Valid Min 70 85 ns
Output Valid to V
Output Valid to Write Protect Low Min 0 0 ns

t

VPSVPPF

t

AH

t

DH

t

CH

High to Write Enable High

Write Enable High to Address Transition Min 0 0 ns
Write Enable High to Data Transition Min 0 0 ns
Write Enable High to Chip Enable High Min 0 0 ns
Write Enable High to Chip Enable Low Min 25 25 ns
Write Enable High to Output Enable Low Min 20 20 ns

t

Write Enable High to Write Enable Low Min 25 25 ns

WPH

t

Write Enable Low to Write Enable High Min 45 45 ns

WP

Write Protect High to Write Enable High Min 45 45 ns

is seen as a logic input (V

PPF

PPF

Low

PPF

Min 0 0 ns

Min 200 200 ns

< 3.6V).

35/66

M36W432TG, M36W432BG

Figure 14. Flash Write AC Waveforms, Chip Enable Controlled

AI07930

tEHAX

PROGRAM OR ERASE

tAVAV

VALIDA0-A20

tAVEH

tEHGL

tELQV

tQVWPL

CMD or DATA STATUS REGISTER

tQVVPL

READ

1st POLLING

STATUS REGISTER

OR DATA INPUT

CONFIRM COMMAND

W

F

tWLEL tEHWH

tVPHEH

tEHEL

tWPHEH

tEHDX

tELEH

POWER-UP AND

SET-UP COMMAND

tDVEH

F

G

F

E

DQ0-DQ15 COMMAND

F

WP

V

PPF

36/66

Table 21. Flash Write AC Characteristics, Chip Enable Controlled

Symbol Alt Parameter

M36W432TG, M36W432BG

Flash

Unit

70 85

t

AVAV

t

AVEH

t

DVEH

t

EHAX

t

EHDX

t

EHEL

t

EHGL

t

EHWH

t

ELEH

t

ELQV

(1,2)

t

QVVPL

t

QVWPL

(1)

t

VPHEH

t

WLEL

t

WPHEH

Note: 1. Sampled only, not 100% tested.

2. Appl i cable if V

t

Write Cycle Time Min 70 85 ns

WC

t

Address Valid to Chip Enable High Min 45 45 ns

AS

t

Data Valid to Chip Enable High Min 45 45 ns

DS

t

Chip Enable High to Address Transition Min 0 0 ns

AH

t

Chip Enable High to Data Transition Min 0 0 ns

DH

t

Chip Enable High to Chip Enable Low Min 25 25 ns

CPH

Chip Enable High to Output Enable Low Min 25 25 ns

t

Chip Enable High to Write Enable High Min 0 0 ns

WH

t

Chip Enable Low to Chip Enable High Min 45 45 ns

CP

Chip Enable Low to Output Valid Min 70 85 ns
Output Valid to V
Data Valid to Write Protect Low Min 0 0 ns

t

V

VPS

t

CS

High to Chip Enable High

PPF

Write Enable Low to Chip Enable Low Min 0 0 ns
Write Protect High to Chip Enable High Min 45 45 ns

is seen as a logic input (V

PPF

PPF

Low

PPF

Min 0 0 ns

Min 200 200 ns

< 3.6V).

37/66

M36W432TG, M36W432BG

Figure 15. Flash Power-Up and Reset AC Waveforms

EF,G

WF,

RP

V

Table 22. Flash Power-Up and Reset AC Characteristics

Symbol Parameter Test Condition

t

PHWL

t

PHEL

t

PHGL

t

PLPH

t

VDHPH

Note: 1. The devi ce Reset is possible but not guarant eed if t

2. Sampled only, not 100% tested.

3. It is im portant to ass ert RP

DDF

F

F

tVDHPH

, V

DDQF

tPHWL

tPHEL
tPHGL

Power-Up Reset

During

Reset High to Write Enable Low, Chip Enable
Low, Output Enable Low

Program and

Eras e
others Min 30 30 ns

(1,2)

Reset Low to Reset High Min 100 100 ns

(3)

Supply Voltages High to Reset High Min 50 50 µs

< 100ns.

PLPH

in order to allow proper CPU initialization during power up or reset.

F

tPHWL

tPHEL

tPHGL

tPLPH

AI07931

Flash

Unit

70 85

Min 50 50 µs

38/66

SRAM DEV ICE

This section describes how to use the SRAM de­vice and all signals refer to it

SRAM SUMMARY DESCRIPTION

The SRAM is a 4Mbit asynchronous random ac­cess memory which features a super lo w voltage
operation and low current consumption with an ac­cess time of 70 ns under all conditions. The mem-

Figure 16. SRAM Logic Diagram

DATA IN DRIVERS

M36W432TG, M36W432BG

ory operations can be performed using a single
low voltage supply, 2.7V to 3.3V, which is the
same as the Flash voltage supply.

A0-A10

ROW DECODER

COLUMN DECODER

256Kb x 16
RAM Array

2048 x 2048

A11-A17

POWER-DOWN

CIRCUIT

SENSE AMPS

DQ0-DQ7

DQ8-DQ15

UB

S

W

S

G

S

LB

S

UB

S

LB

S

E1
E2

AI

S
S

07939

39/66

M36W432TG, M36W432BG

SRAM OPERATIONS

There are five standard operations that control the
SRAM component. These are Bus Read, Bus
Write, Standby/Power-down, Data Retention and
Output Disable. A summary is shown in Table 2,
Main Operation Modes

Read. Read operations are used to output the
contents of the SRAM Array. The SRAM is in Read
mode whenever Write Enable, W
put Enable, G
V

, Chip En ab le, E2S, is at VIH, and Byte Enable

IL

inputs, UB

, is at VIL, Chip Enable, E1S, is at

S

and LBS are at VIL.

S

Valid data will be available on the output pins after
a time of t

after the last stable address. If the

AVQV

Chip Enable or Output Enable ac cess times are
not met, data access will be measured fro m the
limiting parameter (t

E1LQV

, t
er than the address. Dat a out may be inde termi­nate at t
will alway s be valid a t t

E1LQX

, t

E2HQX

and t

AVQV

23, Figures 17 and 18, SRAM Read AC Character­istics).

Write. Write operations are used to write da ta to
the SRAM. The SRAM is in Write mode whenever

and E1S are at VIL, and E2S is at VIH. Either

W

S

the Chip Enable inputs, E1
Enable input, W

, must be deasserted durin g ad-

S

S

dress transitions for subsequent write cycles.
A Write operation is initiated when E1

is at VIH and WS is at VIL. The data is latched

E2

S

on the falling e dge of E1

, the rising edge of E 2

S

or the falling edg e of WS, whichever occurs last.
The Write cycle is terminated on the ri sing edge of

, the rising edge of WS or the falling e dge of

E1

S

E2

, whichever occurs first.

S

, is a t VIH, Out-

S

, or t

E2HQV

, but data lines

GLQX

GLQV

) rath-

(see Table 23 , Tab le

and E2S, or the Write

is at VIL,

S

If the Output is enabled (E1
G
pedance within t

), then WS will return the outputs to high im-

S=VIL

of its falling edge. Care must

WLQZ

, E2S=VIH and

S=VIL

be taken to avoid bus contention in this type of op­eration. The Data input must be valid for t
fore the rising edge of Write Enable, for t
before the rising edge of E 1S or for t
the falling edge of E2
remain valid for t

, whichever occurs first, and

S

WHDX

, t

E1HAX

or t

E2LAX

24, SRAM Write AC Characteristics, Figures 20,
21, 22 and 23).

Standby/Power-Down . The SRAM component
has a chip enabled power-down feature wh ich in­vokes an automatic standby mode (see Table 23,
SRAM Read AC Characteristics, Figure 19, SRAM
Standby AC Waveforms). The SRAM is in Standby
mode whenever either Chip Enable is deasserted,
E1S at VIH or E2S at VIL. It is also possible when

and LBS are at VIH.

UB

S

Data Retention. The SRAM data retention per­formance as V

goes down to VDR are de-

DDS

scribed in Table 25, SRAM Low V
Retention Characteristic, and Figure 24, SRAM
Low V
UB

S

Data Retention AC Waveforms, E1S or

DDS

/ LBS Controlled. In E1S controlled data reten­tion mode, the minimum standby current mode is
entered when E1
or E2

≥ V

S

– 0 .2V. In E2S controlled data re-

DDS

≥ V

S

– 0.2V and E2S≤ 0.2V

DDS

tention mode, minimum standby c urrent mode is
entered when E2

S

Output Disa bl e . The data outputs are high im-

≤ 0.2V.

S

pedance when the Output Enable, G
with Write Enable, WS, at VIH.

DVWH

DVE1H

before

DVE2L

(see Table

Data

DDS

, is at V

S

be-

IH

40/66

Figure 17. SRAM Read Mode AC Waveforms, Address Controlled

tAVAV

M36W432TG, M36W432BG

A0-A17

VALID

tAVQV

tAXQX

DQ0-DQ15

Note: E1S = Low, E2S = High, GS = Low, UBS and/or LBS = High, WS = High.

Figure 18. SRAM Read AC Waveforms, GS Controlled

tAVAV

A0-A17

E1

S

E2

S

tE1LQV tE1HQZ

tE1LQX

tE2HQV

tE2HQX

tBLQV

VALID

DATA VALIDDATA VALID

AI07942

tE2LQZ

tBHQZ

, LB

UB

S

S

tBLQX

tGLQV

G

S

tGHQZ

tGLQX

DQ0-DQ15

DATA VALID

Note: Write Enable (WS) = High. Address Valid prior to or at the same time as E1S, UBS and LBS going Low.

Figure 19. SRAM Standby AC Waveforms

E1

S

E2

S

I

DD

tPU

50%

AI07943

tPD

AI07913

41/66

M36W432TG, M36W432BG

Table 23. SRAM Read AC Characteristics

Symbol Alt Parameter

SRAM

Unit

Min Max

t

AVAV

t

AVQV

t

AXQX

t

BHQZ

t

BLQV

t

BLQX

t

E1LQV

t

E2HQV

t

E1LQX

t

E2HQX

t

E1HQZ

t

E2LQZ

t

GHQZ

t

GLQV

t

GLQX

(1)

t

PD

(1)

t

PU

Note: 1. Sampl e d only. Not 100% tested.

t

RC

t

ACC

t

OH

t

BHZ

t

AB

t

BLZ

t

ACS1

t

CLZ1

t

HZCE

t

OHZ

t

OE

t

OLZ

Read Cycle Time 70 ns
Address Valid to Output Valid 70 ns
Address Transition to Output Transition 10 ns
UBS, LBS Disable to Hi-Z Output
UBS, LBS Access Time
UBS, LBS Enable to Low-Z Output

Chip Enable 1 Low or Chip Enable 2 High to Output Valid 70 ns

Chip Enable 1 Low or Chip Enable 2 High to Output
Transition

Chip Enable High or Chip Enable 2 Low to Output Hi-Z 25 ns

Output Enable High to Output Hi-Z 25 ns
Output Enable Low to Output Valid 35 ns
Output Enable Low to Output Transition 5 ns
Chip Enable 1 High or Chip Enable 2 Low to Power Down 70 ns

Chip Enable 1 Low or Chip Enable 2 High to Power Up 0 ns

25 ns
70 ns

5ns

10 ns

42/66

Figure 20. SRAM Write AC Waveforms, WS Controlled

tAVAV

M36W432TG, M36W432BG

A0-A17

VALID

tAVWH

E1

E2

tE1LWH

S

S

tWHAX

tE2HWH

tAVWL

W

S

tWLWH

tBLWH

UBS, LB

S

G

S

tDVWH

INPUT VALID

AI07944

DQ0-DQ15

tGHQZ tWHDZ

Note 2

Note: 1. WS, E1S, E2S, UBS and/or LBS must be asserted to initiate a write cycle. Output Enable (GS) = Low (otherwise, DQ0-DQ15 are high

impedance). If E1

2. The I /O pins are in output mode and input signal s must not be applied.

, E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance.

S

43/66

M36W432TG, M36W432BG

Figure 21. SRAM Write AC Waveforms, E1S Controlled

tAVAV

A0-A17

E1

S

E2

S

W

S

UB

, LB

S

S

G

S

DQ0-DQ15

tGHQZ

Note 3

VALID

tAVE1H
tAVE2L

tAVE1L

tAVE2H tE2LAX

tE1LE1H

tE2HE2L

tE1HAX

tWLE1H
tWLE2L

tBLE1H

tBLE2L

tDVE1H
tDVE2L

tE1HDZ

tE2LDZ

INPUT VALID

AI07945

Note: 1. WS, E1S, E2S, UBS and/or LBS must be asserted to initiate a write cycle. Output Enable (GS) = Low (otherwise, DQ0-DQ15 are high

impedance). If E1

, E2S and WS are deasserted at the sa m e time, DQ0-DQ15 remain high impe dance.

2. If E1

S

3. The I /O pins are in output mode and input signal s must not be applied.

, E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance.

S

44/66

Figure 22. SRAM Write AC Waveforms, WS Controlled with GS Low

tAVAV

M36W432TG, M36W432BG

A0-A17

VALID

tAVWH

tE1LWH
tE2HWH

E1

S

E2

S

tBLWH

UB

, LB

S

S

tWLWHtAVWL

W

S

tWLQZ

DQ0-DQ15

tDVWH

INPUT VALID

Note: 1. If E1S, E2S and WS are deasserted at the sa m e time, DQ0-DQ15 remain high impe dance.

tWHAX

tWHQX

tWHDZ

AI07946

Figure 23. SRAM Write Cycle Waveform, UBS and LBS Controlled, GS Low

tAVAV

A0-A17

E1

S

E2

S

tAVBL

, LB

UB

S

S

W

S

DQ0-DQ15

Note: 1. If E1S, E2S and WS are deasserted at the sa m e time, DQ0-DQ15 remain high impe dance.

VALID

tAVBH

tE1LBH
tE2HBH

tWLBH

tBLBH

tDVBH

INPUT VALID

tBHDZ

tBHAX

AI07947

45/66

M36W432TG, M36W432BG

Table 24. SRAM Write AC Characteristics

Symbol Alt Parameter

SRAM

Unit

Min Ma x

t

AVAV

t

AVE1L

t

AVE2H

t

AVWL,

t

AVBL

t

AVE1H

t

AVE2L

t

AVWH

t

BLWH

t

BLE1H

t

BLE2L

t

AVBH

t

BLBH

t

DVE1H

t

DVE2L

t

DVWH

t

DVBH

t

E1HAX

t

E2LAX

t

WHAX

t

BHAX

t

E1HDZ

t

E2LDZ

t

WHDZ

t

BHDZ

t

E1LE1H

t

E1LBH

t

E1LWH

t

E2HE2L,

t

E2HBH,

t

E2HWH

t

GHQZ

t

WHQX

t

WLBH

t

WLQZ

t

WLWH

t

WLE1H

t

WLE2L

t

WC

Write Cycle Time 70 ns

,
,

,

t

t

t

t

t

AS

AW

AW

BW

BW

Address Valid to Beginning of Write 0 ns

Address Valid to Chip Enable 1 Low or Chip Enable 2
High

60 ns

Address Valid to Write Enable High 60 ns

UBS, LBS Valid to End of Write

UBS, LBS Low to UBS, LBS High

60 ns

60 ns

,

,

t

DW

Input Valid to End of Write 30 ns

,

,

t

WR

End of Write to Address Change 0 ns

,

,

t

Address Transition to End of Write 0 ns

HD

,

t

CW1

t

CW2

t

GHZ

t

t

t

WHZ

t

WP

WP

Chip Enable 1 Low to End of Write 60 ns

Chip Enable 2 High to End of Write 60 ns

Output Enable High to Output Hi-Z 25 ns
Write Enable High to Input Transition 5 ns

DH

Write Enable Low to UBS, LBS High

50 ns

Write Enable Low to Output Hi-Z 25 ns

Write Enable Pulse Width 50 ns

46/66

M36W432TG, M36W432BG

Figure 24. SRAM Low V

V

DDS

E1S or
UB

, LB

S

S

Table 25. SRAM Low V

Data Retention AC Waveforms, E1S or UBS / LBS Controlled

DDS

DATA RETENTION MODE

V

DDS (min)

tCDR

Data Retention Characteristic

DDS

V

DDS (min)

tR

AI07918

Symbol Parameter Test Condition Min Typ Max Unit

I

DDDR

V

DR

t

CDR

t

2. Sampled only. Not 100% tested.

Supply Current (Data Retention)

Supply Voltage (Data Retention) 1.5 3.3 V
Chip Disable to Power Down 0 ns
Operation Recovery Time 70 ns

R

V

V

DDS

IN

= 1.5V, E1

V

≥

– 0.2V or V

DDS

V

≥

DDS

– 0.2V,

0.2V

≤

IN

310µA

S

47/66

M36W432TG, M36W432BG

APPENDIX A. FLASH BLOCK ADDRESS TABLES

Table 26. Top Boot Block Addresses,
M36W432TG

#

0 4 1FF000-1FFFFF
1 4 1FE000-1FEFFF
2 4 1FD000-1FDFFF
3 4 1FC000-1FCFFF
4 4 1FB000-1FBFFF
5 4 1FA000-1FAFFF
6 4 1F9000-1F9FFF
7 4 1F8000-1F8FFF
8 32 1F0000-1F7FFF

9 32 1E8000-1EFFFF
10 32 1E0000-1E7FFF
11 32 1D8000-1DFFFF
12 32 1D0000-1D7FFF
13 32 1C8000-1CFFFF
14 32 1C0000-1C7FFF
15 32 1B8000-1BFFFF
16 32 1B0000-1B7FFF
17 32 1A8000-1AFFFF
18 32 1A0000-1A7FFF
19 32 198000-19FFFF
20 32 190000-197FFF
21 32 188000-18FFFF
22 32 180000-187FFF
23 32 178000-17FFFF
24 32 170000-177FFF
25 32 168000-16FFFF
26 32 160000-167FFF
27 32 158000-15FFFF
28 32 150000-157FFF
29 32 148000-14FFFF
30 32 140000-147FFF
31 32 138000-13FFFF
32 32 130000-137FFF
33 32 128000-12FFFF

Size

(KWord)

Address Range

34 32 120000-127FFF
35 32 118000-11FFFF
36 32 110000-117FFF
37 32 108000-10FFFF
38 32 100000-107FFF
39 32 0F8000-0FFFFF
40 32 0F00000-F7FFF
41 32 0E8000-0EFFFF
42 32 0E0000-0E7FFF
43 32 0D8000-0DFFFF
44 32 0D0000-0D7FFF
45 32 0C8000-0CFFFF
46 32 0C0000-0C7FFF
47 32 0B8000-0BFFFF
48 32 0B0000-0B7FFF
49 32 0A8000-0AFFFF
50 32 0A0000-0A7FFF
51 32 098000-09FFFF
52 32 090000-097FFF
53 32 088000-08FFFF
54 32 080000-087FFF
55 32 078000-07FFFF
56 32 070000-077FFF
57 32 068000-06FFFF
58 32 060000-067FFF
59 32 058000-05FFFF
60 32 050000-057FFF
61 32 048000-04FFFF
62 32 040000-047FFF
63 32 038000-03FFFF
64 32 030000-037FFF
65 32 028000-02FFFF
66 32 020000-027FFF
67 32 018000-01FFFF
68 32 010000-017FFF
69 32 008000-00FFFF
70 32 000000-007FFF

48/66

M36W432TG, M36W432BG

Table 27. Bottom Boot Block Addresses,
M36W432BG

#

70 32 1F8000-1FFFFF
69 32 1F0000-1F7FFF
68 32 1E8000-1EFFFF
67 32 1E0000-1E7FFF
66 32 1D8000-1DFFFF
65 32 1D0000-1D7FFF
64 32 1C8000-1CFFFF
63 32 1C0000-1C7FFF
62 32 1B8000-1BFFFF
61 32 1B0000-1B7FFF
60 32 1A8000-1AFFFF
59 32 1A0000-1A7FFF
58 32 198000-19FFFF
57 32 190000-197FFF
56 32 188000-18FFFF
55 32 180000-187FFF
54 32 178000-17FFFF
53 32 170000-177FFF
52 32 168000-16FFFF
51 32 160000-167FFF
50 32 158000-15FFFF
49 32 150000-157FFF
48 32 148000-14FFFF
47 32 140000-147FFF
46 32 138000-13FFFF
45 32 130000-137FFF
44 32 128000-12FFFF
43 32 120000-127FFF
42 32 118000-11FFFF
41 32 110000-117FFF
40 32 108000-10FFFF
39 32 100000-107FFF
38 32 0F8000-0FFFFF
37 32 0F0000-0F7FFF

Size

(KWord)

Address Range

36 32 0E8000-0EFFFF
35 32 0E0000-0E7FFF
34 32 0D8000-0DFFFF
33 32 0D0000-0D7FFF
32 32 0C8000-0CFFFF
31 32 0C0000-0C7FFF
30 32 0B8000-0BFFFF
29 32 0B0000-0B7FFF
28 32 0A8000-0AFFFF
27 32 0A0000-0A7FFF
26 32 098000-09FFFF
25 32 090000-097FFF
24 32 088000-08FFFF
23 32 080000-087FFF
22 32 078000-07FFFF
21 32 070000-077FFF
20 32 068000-06FFFF
19 32 060000-067FFF
18 32 058000-05FFFF
17 32 050000-057FFF
16 32 048000-04FFFF
15 32 040000-047FFF
14 32 038000-03FFFF
13 32 030000-037FFF
12 32 028000-02FFFF
11 32 020000-027FFF
10 32 018000-01FFFF

9 32 010000-017FFF
8 32 008000-00FFFF
7 4 007000-007FFF
6 4 006000-006FFF
5 4 005000-005FFF
4 4 004000-004FFF
3 4 003000-003FFF
2 4 002000-002FFF
1 4 001000-001FFF
0 4 000000-000FFF

49/66

M36W432TG, M36W432BG

APPENDIX B. COMMON FLASH INTERFACE (CFI)

The Common Flash Interface is a JEDEC ap­proved, standardized data structure that can be
read from the Flash memory device. It allows a
system software to query the device to det ermine
various electrical and t iming parameters, density
information and functions supported by the mem­ory. The system can interface easily with the de­vice, enabling the software to upgrade itself when
necessary.

When the CFI Query Co mmand (RCFI) is issued
the device enters CFI Query mode and the data

Table 28. Query Structure Overview

Offset Sub-section Name Description

00h Reserved Reserved for algorithm-specific information
10h CFI Query Identification String Command set ID and algorithm data offset

1Bh System Interface Information Device timing & voltage information

27h Device Geometry Definition Flash device layout

P Primary Algorithm-specific Extended Query table

A Alternate Algorithm-specific Extended Query table

Note: Query data are always presented on the lowest order data outputs.

structure is read from the memory. Tables 28, 29,
30, 31, 32 and 33 show the addresses used to re­trieve the data.

The CFI data structure also contains a security
area where a 64 bit unique security number is writ­ten (see Table 33, Security Code area). This area
can be accessed only in Read mode by the final
user. It is impossible to change the security num ­ber after it has been written by ST. Issue a Read
command to return to Read mode.

Additional information specific to the Primary
Algorithm (optional)

Additional information specific to the Alternate
Algorithm (optional)

Table 29. CFI Query Identification String

Offset Data Description Value

00h 0020h Manufacturer Code ST

01h

02h-0Fh reserved Reserved

10h 0051h "Q"
11h 0052h Query Unique ASCII String "QRY" "R"
12h 0059h "Y"
13h 0003h
14h 0000h
15h 0035h
16h 0000h
17h 0000h
18h 0000h
19h 0000h

1Ah 0000h

Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

88BAh
88BBh

Device Code

Primary Algorithm Command Set and Control Interface ID code 16 bit ID code
defining a specific algorithm

Address for Primary Algorithm extended Query table (see Table 31) P = 35h

Alternate Vendor Command Set and Control Interface ID Code second vendor ­specified algorithm supported (0000h means none exists)

Address for Alternate Algorithm extended Query table
(0000h means none exists)

compatible

Top

Bottom

Intel

NA

NA

50/66

M36W432TG, M36W432BG

Table 30. CFI Query System Interface Information

Offset Data Description Value

V

Logic Supply Minimum Program/Erase or Write voltage

1Bh 0027h

1Ch 0036h

1Dh 00B4h

1Eh 00C6h

1Fh 0004h

20h 0004h
21h 000Ah
22h 0000h
23h 0005h
24h 0005h
25h 0003h
26h 0000h

DDF

bit 7 to 4 BCD value in volts
bit 3 to 0 BCD value in 100 mV

Logic Supply Maximum Program/Erase or Write voltage

V

DDF

bit 7 to 4 BCD value in volts
bit 3 to 0 BCD value in 100 mV

V

[Programming] Supply Minimum Program/Erase voltage

PPF

bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV

V

[Programming] Supply Maximum Program/Erase voltage

PPF

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 mV
Typical time-out per single word program = 2
Typical time-out for Double/ Quadruple Word Program = 2
Typical time-out per individual block erase = 2
Typical time-out for full chip erase = 2
Maximum time-out for word program = 2

n

n

ms

n

times typical

µs

n

n

ms

Maximum time-out for Double/ Quadruple Word Program = 2
Maximum time-out per individual block erase = 2
Maximum time-out for chip erase = 2

n

times typical

n

times typical

µs

n

times typical

2.7V

3.6V

11.4V

12.6V

16µs
16µs

1s

NA
512µs
512µs

8s

NA

51/66

M36W432TG, M36W432BG

Table 31. Device Geometry Definition

Offset Word

Mode

27h 0016h
28h

29h

2Ah
2Bh

2Ch 0002h

Data Description Value

Device Size = 2

0001h
0000h

0003h
0000h

Flash Device Interface Code description

Maximum number of bytes in multi-byte program or page = 2
Number of Erase Block Regions within the device.

It specifies the number of regions within the device containing contiguous
Erase Blocks of the same size.

n

in number of bytes

4 MByte

x16

Async.

n

8

2

M36W432TG

M36W432BG

2Dh
2Eh

2Fh
30h

31h
32h

33h
34h

2Dh
2Eh

2Fh
30h

31h
32h

33h
34h

003Eh
0000h

0000h
0001h

0007h
0000h

0020h
0000h

0007h
0000h

0020h
0000h

003Eh
0000h

0000h
0001h

Region 1 Information
Number of identical-size erase block = 003Eh+1

Region 1 Information
Block size in Region 1 = 0100h * 256 byte

Region 2 Information
Number of identical-size erase block = 0007h+1

Region 2 Information
Block size in Region 2 = 0020h * 256 byte

Region 1 Information
Number of identical-size erase block = 0007h+1

Region 1 Information
Block size in Region 1 = 0020h * 256 byte

Region 2 Information
Number of identical-size erase block = 003Eh=1

Region 2 Information
Block size in Region 2 = 0100h * 256 byte

63

64 KByte

8

8 KByte

8

8 KByte

63

64 KByte

52/66

Table 32. Primary Algorithm-Specific Extended Qu ery Ta bl e

Offset

P = 35h

(1)

Data Description Value

M36W432TG, M36W432BG

(P+0)h = 35h 0050h
(P+1)h = 36h 0052h "R"

Primary Algorithm extended Query table unique ASCII string “PRI”

"P"

(P+2)h = 37h 0049h "I"
(P+3)h = 38h 0031h Major version number, ASCII "1"

(P+4)h = 39h 0030h Minor version number, ASCII "0"
(P+5)h = 3Ah 0066h Extended Query table contents for Primary Algorithm. Address (P+5)h
(P+6)h = 3Bh 0000h
(P+7)h = 3Ch 0000h
(P+8)h = 3Dh 0000h

contains less significant byte.

bit 0 Chip Erase supported (1 = Yes, 0 = No)
bit 1 Suspend Erase supported (1 = Yes, 0 = No)
bit 2 Suspend Program supported (1 = Yes, 0 = No)
bit 3 Legacy Lock/Unlock supported (1 = Yes, 0 = No)
bit 4 Queued Erase supported (1 = Yes, 0 = No)
bit 5 Instant individual block locking supported (1 = Yes, 0 = No)
bit 6 Protection bits supported (1 = Yes, 0 = No)
bit 7 Page mode read supported (1 = Yes, 0 = No)
bit 8 Synchronous read supported (1 = Yes, 0 = No)
bit 31 to 9 Reserved; undefined bits are ‘0’

No
Yes
Yes

No

No
Yes
Yes

No

No

(P+9)h = 3Eh 0001h Supported Functions after Suspend

Read Array, Read Status Register and CFI Query are always supported
during Erase or Program operation

bit 0 Program supported after Erase Suspend (1 = Yes, 0 = No)

bit 7 to 1 Reserved; undefined bits are ‘0’ Yes
(P+A)h = 3Fh 0003h Block Lock Status
(P+B)h = 40h 0000h

Defines which bits in the Block Status Register section of the Query are
implemented.
Address (P+A)h contains less significant byte

bit 0 Block Lock Status Register Lock/Unlock bit active(1 = Yes, 0 = No)

bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No)

Yes
Yes

bit 15 to 2 Reserved for future use; undefined bits are ‘0’
(P+C)h = 41h 0030h V

Logic Supply Optimum Program/Erase voltage (highest performance)

DDF

3V
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV

(P+D)h = 42h 00C0h V

Supply Optimum Program/Erase voltage

PPF

12V
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV

(P+E)h = 43h 0001h Number of Protection register fields in JEDEC ID space.

01

"00h," indicates that 256 protection bytes are available

(P+F)h = 44h 0080h Protection Field 1: Protection Description
(P+10)h = 45h 0000h 00h
(P+11)h = 46h 0003h 8 Byte
(P+12)h = 47h 0003h 8 Byte

This field describes user-available. One Time Programmable (OTP)
Protection register bytes. Some are pre-programmed with device unique
serial numbers. Others are user programmable. Bits 0–15 point to the
Protection register Lock byte, the section’s first byte.
The following bytes are factory pre-programmed and user-programmable.

80h

bit 0 to 7 Lock/bytes JEDEC-plane physical low address
bit 8 to 15 Lock/bytes JEDEC-plane physical high address

n

bit 16 to 23 "n" such that 2
bit 24 to 31 "n" such that 2

= factory pre-programmed bytes

n

= user programmable bytes

(P+13)h = 48h Reserved

Note: 1. See Table 29, offset 15 f or P pointer definition.

53/66

M36W432TG, M36W432BG

Table 33. Security Code Area

Offset Data Description

80h 00XX Protection Register Lock
81h XXXX
82h XXXX
83h XXXX
84h XXXX
85h XXXX
86h XXXX
87h XXXX
88h XXXX

89h XXXX
8Ah XXXX
8Bh XXXX
8Ch XXXX

64 bits: unique device number

128 bits: User Programmable OTP

54/66

APPENDIX C. FLASH FLOWCHARTS AND PSEUDO CODES

Figure 25. Flash Program Flowchart and Pseudo Code

Start

M36W432TG, M36W432BG

Write 40h or 10h

Write Address

& Data

Read Status

Register

b7 = 1

YES

b3 = 0

YES

b4 = 0

YES

b1 = 0

YES

End

NO

NO

NO

NO

V

Error (1, 2)

Error (1, 2)

Program to Protected

Block Error (1, 2)

Invalid

PPF

Program

program_command (addressToProgram, dataToProgram) {:
writeToFlash (any_address, 0x40) ;
/*or writeToFlash (any_address, 0x10) ; */

writeToFlash (addressToProgram, dataToProgram) ;
/*Memory enters read status state after
the Program Command*/

do {
status_register=readFlash (any_address) ;

or GF must be toggled*/

/* E

F

} while (status_register.b7== 0) ;

if (status_register.b3==1) /*V
error_handler ( ) ;

if (status_register.b4==1) /*program error */
error_handler ( ) ;

if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;

}

invalid error */

PPF

AI07932

Note: 1. Status check of b1 (Protected Block), b3 (V

a sequence.

2. If an er ror is found, the Status Register must be cleare d before further Program/ Erase Con troller ope rations.

Invalid) and b4 (Program Error) can be made after each program operation or after

PPF

55/66

M36W432TG, M36W432BG

Figure 26. Doubl e W or d Pr og ram Fl owchart and Pseudo Code

Start

Write 30h

Write Address 1

& Data 1 (3)

Write Address 2

& Data 2 (3)

Read Status

Register

b7 = 1

YES

b3 = 0

YES

b4 = 0

NO

NO

NO

V

Invalid

PPF

Error (1, 2)

Program

Error (1, 2)

double_word_program_command (addressToProgram1, dataToProgram1,
addressToProgram2, dataToProgram2)
{
writeToFlash (any_address, 0x30) ;

writeToFlash (addressToProgram1, dataToProgram1) ;
/*see note (3) */
writeToFlash (addressToProgram2, dataToProgram2) ;
/*see note (3) */
/*Memory enters read status state after
the Program command*/

do {
status_register=readFlash (any_address) ;
/* E

or GF must be toggled*/

F

} while (status_register.b7== 0) ;

if (status_register.b3==1) /*V
error_handler ( ) ;

invalid error */

PPF

if (status_register.b4==1) /*program error */
error_handler ( ) ;

YES

b1 = 0

Program to Protected

Block Error (1, 2)

if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;

NO

YES

End

Note: 1. Status check of b1 (Protected Block), b3 (V

a sequence.

2. If an er ror is found, the Status Register must be cleare d before further Program/ Erase operations.

3. Address 1 and Address 2 must be consecutive addresse s differing only for bit A0.

PPF

}

Invalid) and b4 (Program Error) can be made after each program operation or after

56/66

AI07933

Figure 27. Quadr upl e W o rd P rogram Flowchart and Pseudo Code

Start

M36W432TG, M36W432BG

Write 56h

Write Address 1

& Data 1 (3)

Write Address 2

& Data 2 (3)

Write Address 3

& Data 3 (3)

Write Address 4

& Data 4 (3)

Read Status

Register

b7 = 1

YES

NO

quadruple_word_program_command (addressToProgram1, dataToProgram1,
addressToProgram2, dataToProgram2,
addressToProgram3, dataToProgram3,
addressToProgram4, dataToProgram4)
{
writeToFlash (any_address, 0x56) ;

writeToFlash (addressToProgram1, dataToProgram1) ;
/*see note (3) */

writeToFlash (addressToProgram2, dataToProgram2) ;
/*see note (3) */

writeToFlash (addressToProgram3, dataToProgram3) ;
/*see note (3) */

writeToFlash (addressToProgram4, dataToProgram4) ;
/*see note (3) */

/*Memory enters read status state after
the Program command*/

do {
status_register=readFlash (any_address) ;
/* E

or GF must be toggled*/

F

} while (status_register.b7== 0) ;

b3 = 0

NO

V

Invalid

PPF

Error (1, 2)

if (status_register.b3==1) /*V
error_handler ( ) ;

PPF

YES

b4 = 0

NO

Program

Error (1, 2)

if (status_register.b4==1) /*program error */
error_handler ( ) ;

YES

b1 = 0

Program to Protected

Block Error (1, 2)

if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;

NO

YES

End

Note: 1. Status check of b1 (Protected Block), b3 (V

a sequence.

2. If an er ror is found, the Status Register must be cleare d before further Program/ Erase operations.

3. Address 1 to Address 4 must be consecutive addresse s differing only for bits A0 an d A1.

}

Invalid) and b4 (Program Error) can be made after each program operation or after

PPF

invalid error */

AI07934

57/66

M36W432TG, M36W432BG

Figure 28. Program Suspend & Resume Flowchart and Pseudo Code

Start

program_suspend_command ( ) {

Write B0h

Write 70h

Read Status

Register

writeToFlash (any_address, 0xB0) ;
writeToFlash (any_address, 0x70) ;

/* read status register to check if
program has already completed */

do {
status_register=readFlash (any_address) ;
/* E

or GF must be toggled*/

F

b7 = 1

YES

b2 = 1

YES

Write FFh

Read data from

another address

Write D0h

Program Continues

NO

NO

Program Complete

Write FFh

Read Data

} while (status_register.b7== 0) ;

if (status_register.b2==0) /*program completed */
{ writeToFlash (any_address, 0xFF) ;
read_data ( ) ; /*read data from another block*/
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/

}
else
{ writeToFlash (any_address, 0xFF) ;
read_data ( ); /*read data from another address*/
writeToFlash (any_address, 0xD0) ;
/*write 0xD0 to resume program*/
}
}

AI07935

58/66

Figure 29. Erase Flowchart and Pseudo Code

Start

Write 20h

Write Block

Address & D0h

M36W432TG, M36W432BG

erase_command ( blockToErase ) {
writeToFlash (any_address, 0x20) ;

writeToFlash (blockToErase, 0xD0) ;
/* only A12-A20 are significannt */

/* Memory enters read status state after

the Erase Command */

Read Status

Register

YES

YES

NO

YES

YES

NO

NO

YES

NO

NO

V

PPF

Error (1)

Command

Sequence Error (1)

Erase to Protected

Block Error (1)

b7 = 1

b3 = 0

b4, b5 = 1

b5 = 0 Erase Error (1)

b1 = 0

End

Invalid

do {
status_register=readFlash (any_address) ;

or GF must be toggled*/

/* E

F

} while (status_register.b7== 0) ;

if (status_register.b3==1) /*V
error_handler ( ) ;

if ( (status_register.b4==1) && (status_register.b5==1) )
/* command sequence error */
error_handler ( ) ;

if ( (status_register.b5==1) )
/* erase error */
error_handler ( ) ;

if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;

}

invalid error */

PPF

AI07936

Note: If an error is fo und, the Stat us Register must be cleared before fu rther Program /Erase operations.

59/66

M36W432TG, M36W432BG

Figure 30. Erase Suspend & Resume Flowchart and Pseudo Code

Start

Write B0h

Write 70h

Read Status

Register

b7 = 1

b6 = 1

Write FFh

Read data from

another block
Program/Protection Program
Block Protect/Unprotect/Lock

or
or

Write D0h

Erase Continues

NO

YES

NO

YES

Erase Complete

Write FFh

Read Data

erase_suspend_command ( ) {
writeToFlash (any_address, 0xB0) ;

writeToFlash (any_address, 0x70) ;
/* read status register to check if
erase has already completed */

do {
status_register=readFlash (any_address) ;

or GF must be toggled*/

/* E

F

} while (status_register.b7== 0) ;

if (status_register.b6==0) /*erase completed */
{ writeToFlash (any_address, 0xFF) ;

read_data ( ) ;
/*read data from another block*/
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/

}
else
{ writeToFlash (any_address, 0xFF) ;
read_program_data ( );
/*read or program data from another address*/
writeToFlash (any_address, 0xD0) ;
/*write 0xD0 to resume erase*/
}
}

60/66

AI07937

Figure 31. Lo ck i ng Ope rations Flowchart an d Pseudo Cod e

Start

M36W432TG, M36W432BG

Write 60h

Write

01h, D0h or 2Fh

Write 90h

Read Block
Lock States

Locking

change

confirmed?

YES

Write FFh

End

NO

locking_operation_command (address, lock_operation) {
writeToFlash (any_address, 0x60) ; /*configuration setup*/

if (lock_operation==LOCK) /*to protect the block*/
writeToFlash (address, 0x01) ;
else if (lock_operation==UNLOCK) /*to unprotect the block*/
writeToFlash (address, 0xD0) ;
else if (lock_operation==LOCK-DOWN) /*to lock the block*/
writeToFlash (address, 0x2F) ;

writeToFlash (any_address, 0x90) ;

if (readFlash (address) ! = locking_state_expected)
error_handler () ;
/*Check the locking state (see Read Block Signature table )*/

writeToFlash (any_address, 0xFF) ; /*Reset to Read Array mode*/
}

AI04364

61/66

M36W432TG, M36W432BG

Figure 32. Protection Register Program Flowchart and Pseudo Code

Start

Write C0h

Write Address

& Data

Read Status

Register

b7 = 1

YES

b3 = 0

YES

b4 = 0

YES

b1 = 0

YES

End

NO

NO

NO

NO

V

Error (1, 2)

Error (1, 2)

Program to Protected

Block Error (1, 2)

Invalid

PPF

Program

protection_register_program_command (addressToProgram, dataToProgram) {:
writeToFlash (any_address, 0xC0) ;

writeToFlash (addressToProgram, dataToProgram) ;
/*Memory enters read status state after
the Program Command*/

do {
status_register=readFlash (any_address) ;
/* E

or GF must be toggled*/

F

} while (status_register.b7== 0) ;

if (status_register.b3==1) /*V
error_handler ( ) ;

invalid error */

PPF

if (status_register.b4==1) /*program error */
error_handler ( ) ;

if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;

}

AI07938

Note: 1. Status check of b1 (Protected Block), b3 (V

a sequence.

2. If an er ror is found, the Status Register must be cleare d before further Program/ Erase Con troller ope rations.

Invalid) and b4 (Program Error) can be made after each program operation or after

PPF

62/66

M36W432TG, M36W432BG

APPENDIX D. FLASH COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE

Table 34. Write State Machine Current/Next, sheet 1 of 2.

Current

State

Read Array “1” Array Read Array Prog.Setup Ers. Setup Read Array Read S ts. Read Array

Read

Status

Read

Elect.Sg.

Read CFI

Query

Lock Setup “1” Statu s Lock Com mand Error

Lock Cmd

Error

Lock

(complete)

Prot. Prog.

Setup

Prot. Prog.

(continue)

Prot. Prog.
(complete)

Prog. Setup “1” Status Program

Program

(continue)
Prog. Sus

Status

Prog. Sus

Read Array

Prog. Sus

Read

Elect.Sg.

Prog. Sus

Read CFI

Program

(complete)

Erase
Setup

Erase

Cmd.Error

Erase

(continue)
Erase Sus

Read Sts

Erase Sus

Read Array

Erase Sus

Read

Elect.Sg.

Erase Sus

Read CFI

Erase

(complete)

Note: Cmd = Command, Elect.Sg. = Electronic Signature, Ers = Erase, Prog. = Pro gram , Prot = Protection, Sus = Suspend.

SR

bit 7

“1” Status Read Array

“1”

“1” CFI Read Array

“1” Status Read Array

“1” Status Read Array

“1” Statu s Protec tion Register Program

“0” Statu s Protection Registe r Program cont i nue

“1” Status Read Array

“0” Statu s P rogram (continue)

“1” Status

“1” Array

“1”

“1” CFI

“1” Status Read Array

“1” S tatus Erase C o mman d Error

“1” Status Read Array

“0” Statu s Erase (continue)

“1” Status

“1” Array

“1”

“1” CFI

“1” Status Read Array

Data

When

Read

Electronic

Signature

Electronic

Signature

Electronic

Signature

Read
Array
(FFh)

Read Array

Prog. Sus

Read Array

Prog. Sus

Read Array

Prog. Sus

Read Array

Prog. Sus

Read Array

Erase Sus

Read Array

Erase Sus

Read Array

Erase Sus

Read Array

Erase Sus

Read Array

Program

Setup

(10/40h)

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Program Suspend to

Read Array

Program Suspend to

Read Array

Program Suspend to

Read Array

Program Suspend to

Read Array

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Command Input (and Next State)

Erase

Setup

(20h)

Erase
Setup

Erase
Setup

Erase
Setup

Erase
Setup

Erase
Setup

Erase
Setup

Erase
Setup

Erase
Setup

Erase Sus

Read Array

Erase Sus

Read Array

Erase Sus

Read Array

Erase Sus

Read Array

Erase
Setup

Erase

Confirm

(D0h)

Lock

(complete)

Program

(continue)

Program

(continue)

Program

(continue)

Program

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

Prog/Ers

Suspend

(B0h)

Read Array

Read Array

Read Array

Lock Cmd

Error

Read Array

Read Array

Read Array

Prog. Sus

Read Sts

Prog. Sus

Read Array

Prog. Sus

Read Array

Prog. Sus

Read Array

Prog. Sus

Read Array
Read Array

Erase

CmdErr or

Read Array

Erase Sus

Read Sts

Erase Sus

Read Array

Erase Sus

Read Array

Erase Sus

Read Array

Erase Sus

Read Array
Read Array

Prog/Ers

Resume

(D0h)

Lock

(complete)

Program

(continu e)

Program

(continu e)

Program

(continu e)

Program

(continu e)

Erase

(continu e)

Erase

(continu e)

Erase

(continu e)

Erase

(continu e)

Erase

(continu e)

Read

Status

(70h)

Read

Status

Read

Status

Read

Status

Lock Command Error

Read

Status

Read

Status

Read

Status

Program (continue)

Prog. Sus

Read Sts

Prog. Sus

Read Sts

Prog. Sus

Read Sts

Prog. Sus

Read Sts

Read

Status

Erase Command Error

Read

Status

Erase (con tinue)

Eras e Sus

Read Sts

Eras e Sus

Read Sts

Eras e Sus

Read Sts

Eras e Sus

Read Sts

Read

Status

Clear

Status

(50h)

Read Array

Read Array

Read Array

Read Array

Read Array

Read Array

Prog. Sus

Read Array

Prog. Sus

Read Array

Prog. Sus

Read Array

Prog. Sus

Read Array
Read Array

Read Array

Eras e Sus

Read Array

Eras e Sus

Read Array

Eras e Sus

Read Array

Eras e Sus

Read Array
Read Array

63/66

M36W432TG, M36W432BG

Table 35. Write State Machine Current/Next, sheet 2 of 2.

Command Input (and Next State)

Current State

Read Array Read Elect.Sg. Read CFI Query Lock Setup

Read Status Read Elect.Sg. Read CFI Query Lock Setup

Read Ele ct .Sg. Read Elect.S g. R ead CFI Query Lock Setup

Read CFI Query Read Elect.Sg. Read CFI Query Lock Setup

Lock Setup Lock Comm and Error Loc k (c o m plete)

Lock Cmd Error Read Elect.Sg. Read CFI Query Lock Setup

Lock (comple te) Re ad Elect.Sg. Read CFI Query Lock Setup

Prot. Prog.

Setup

Prot. Prog.

(continue)

Prot. Prog.
(complete)

Prog. Setup Program

Program

(continu e)

Prog. Suspend

Read Status

Prog. S uspend

Read Array

Prog. S uspend
Read El ect.Sg.

Prog. S uspend

Read CFI

Program

(complete)

Erase Setup Erase Command Error

Erase

Cmd.Error

Erase (con tinue) Erase (continu e)

Erase Suspend

Read Ststus

Erase Suspend

Read Array

Erase Suspend

Read El ect.Sg.

Erase Suspend

Read CFI Query

Erase

(complete)

Note: Cmd = Command, Elect.Sg. = Electronic Signature, Pro g. = Program, Pro t = P rot ection.

Read Ele ct.Sg.

(90h)

Read Elec t.Sg. Read CFI Query Lock Setup

Prog. Suspend

Read Elec t.Sg.

Prog. Suspend

Read Elec t.Sg.

Prog. Suspend

Read Elec t.Sg.

Prog. Suspend

Read Elec t.Sg.
Read Elect.Sg. Read CFIQuery Lock Setup

Read Elec t.Sg. Read CFI Query Lock Setup

Erase Suspend
Read Elec t.Sg.

Erase Suspend
Read Elec t.Sg.

Erase Suspend
Read Elec t.Sg.

Erase Suspend
Read Elec t.Sg.

Read Elec t.Sg. Read CFI Query Lock Setup

Read CFI

Query

(98h)

Prog. Suspend

Read CFI Query

Prog. Suspend

Read CFI Query

Prog. Suspend

Read CFI Query

Prog. Suspend

Read CFI Query

Erase Suspend

Read CFI Query

Erase Suspend

Read CFI Query

Erase Suspend

Read CFI Query

Erase Suspend

Read CFI Query

Lock Setup

(60h)

Protectio n Register P rogram

Protection Register Program (continue)

Lock Setup Eras e Suspend R ead Array

Lock Setup Eras e Suspend R ead Array

Lock Setup Eras e Suspend R ead Array

Lock Setup Eras e Suspend R ead Array

Prot. Prog.

Setup (C0h)

Prot. Prog.

Setup

Prot. Prog.

Setup

Prot. Prog.

Setup

Prot. Prog.

Setup

Prot. Prog.

Setup

Prot. Prog.

Setup

Prot. Prog.

Setup

Program (continue)

Program Suspend Read Array

Program Suspend Read Array

Program Suspend Read Array

Program Suspend Read Array

Prot. Prog.

Setup

Prot. Prog.

Setup

Prot. Prog.

Setup

Lock Confirm

(01h)

Confirm (2Fh)

Lock Down

Read Array

Read Array

Read Array

Read Array

Read Array

Read Array

Read Array

Read Array

Read Array

Read Array

Unlock

Confirm

(D0h)

Program

(continue)

Program

(continue)

Program

(continue)

Program

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

64/66

REVISION HIST ORY

Table 36. Document Revision History

Date Version Revision Details

19-Nov-2002 1.0 First Issue

M36W432TG, M36W432BG

65/66

M36W432TG, M36W432BG

Information furnished is believed to be accurate an d rel i able. However, STMicroelectro ni cs assumes no responsibilit y for the cons equences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or otherwise under any patent or patent rights of STMi croelectr onics. Specifications mentioned in th i s publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authoriz ed for use as critical comp onents in lif e support devi ces or systems wi thout exp ress written approval of STM i croelect ronics.

The ST logo i s registered trademark of STMicroel ectronics
All other nam es are the pro perty of their respective owners

© 2002 STMicroelectronics - All Rights Reserved

Australi a - Brazil - Canada - China - F i nland - France - German y - Hong Kong - Indi a - Israel - It al y - Japan - Mal a ysia - Malta -

Morocc o - Singapore - S pai n - Sweden - Swi tzerland - United Kingdom - United States

STMicroelectronics GROUP OF COMPANIES

www.st.com

66/66