Datasheet M36DR432BD, M36DR432AD Datasheet (SGS Thomson Microelectronics)

32 Mbit (2Mb x16, Dual Bank, Page) Flash Memory

and 4 Mbit (256Kb x16) SRAM, Multiple Memory Product

FEATURES SUMMARY

■ Multiple Memory Product

– 1 bank of 32 Mbit (2Mb x16) Flash Memory
– 1 bank of 4 Mbit (256Kb x16) SRAM

■ SUPPLY VOLTAGE

–V
–V

■ ACCESS TIMES: 85ns, 100ns, 120ns

■ LOW POWER CONSUMPTION

■ ELECTRONIC SIGNATURE

= V

DDF

= 12V for Fast Program (optional)

PPF

– Manufacturer Code: 0020h
– Top Device Code, M36DR432AD: 00A0h
– Bottom Device Code, M36DR432BD: 00A1h

=1.65V to 2.2V

DDS

M36DR432AD
M36DR432BD

Figure 1. Package

FBGA

Stacked LFBGA66 (ZA)

12 x8mm

FLASH MEMORY

■ MEMORY BLOCKS

– Dual Bank Memory Array: 4 Mbit, 28 Mbit
– Parameter Blocks (Top or Bott o m location)

■ PROGRAMMING TIME

– 10µs by Word typical
– Double Word Program Option

■ ASYNCHRONOUS PAGE MODE READ

– Page Width: 4 Words
– Page Access: 35ns
– Random Access: 85ns, 100ns, 120ns

■ DUAL BANK OPERATIONS

– Read within one Bank while Program or

Erase within the other

– No delay between Read and Write operations

■ BLOCK LOCKING

– All blocks locked at Power up
– Any combination of blocks can be locked
–WPF

■ COMMON FLASH INTERFACE (CFI)

for Block Lock-Down

– 64 bit Unique Device Identifier
– 64 bit User Programmable OTP Cells

■ ERASE SUSPEND and RESUME MODES

■ 100,000 PROGRAM/ER ASE CYCL ES per

BLOCK

■ 20 YEARS DATA RETENTI ON

– Defectivity below 1ppm/year

SRAM

■ 4 Mbit (256Kb x16)

■ LOW V

■ POWER DOWN FEATURES USING TWO

DATA RETENTION: 1.0V

DDS

CHIP ENABLE INPUTS

1/52February 2003

M36DR432AD, M36DR432B D

TABLE OF CONTENTS

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. TFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Address Inputs (A0-A17). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Address Inputs (A18-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Flash Chip Enable (EF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Flash Output Enable (GF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Flash Write Enable (WF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Flash Write Protect (WPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Flash Write Protect (WPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Flash Reset/Power-Down (RPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

VDDF Supply Voltage (1.65V to 2.2V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

V

Programming Voltage (11.4V to 12.6V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

PPF

V

Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SSF

SRAM Chip Enable (ES). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SRAM Write Enable (WS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SRAM Output Enable (GS).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SRAM Upper Byte Enable (UBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SRAM Lower Byte Enable (LBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

VDDS Supply Voltage (1.65V to 2.2V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 2. Main Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

FLASH MEMORY COMPONENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 3. Flash Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figu r e 5 . Flash Secur i ty Block and Protection Reg i s te r Memo ry Map . . . . . . . . . . . . . . . . . . . . . . 13

Flash Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Flash Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Flash Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Flash Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Flash Standby.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3

Automatic Flash Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3

Flash Power-Down.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Dual Bank Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Flash Command Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Flash Read/Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Flash Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2/52

M36DR432AD, M36DR432BD

Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Set Configuration Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Double Word Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Quadruple Word Program Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Enter Bypass Mode Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Exit Bypass Mode Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Program in Bypass Mode Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Double Word Program in Bypass Mode Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Quadruple Word Program in Bypass Mode Comman d. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Block Lock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5

Block Lock-Down Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5

Block Erase Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Bank Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Erase Suspend Comma nd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6

Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 4. Flash Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 5. Read Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 6. Flash Read Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Table 7. Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 8. Read Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9

Table 9. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 19

Flash Block Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Reading a Block’s Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Unlocked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Lock-Down State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 10. Flash Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Flash Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Polling and Toggle Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 11. Polling and Toggle Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 12. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

SRAM COMPONENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4

SRAM Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3/52

M36DR432AD, M36DR432B D

Standby/Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 13. Absolute Maximum Ratings(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 14. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 6. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 7. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 15. Device Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6

Table 16. Flash DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 17. SRAM DC Characteristics (T

Figure 8. Flash Random Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 9. Flash Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 18. Flash Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 10. Flash Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 19. Flash Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 11. Flash Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 20. Flash Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 12. Flash Reset/Power-Down AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 21. Flash Reset/Power-Down AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 13. Flash Data Polling DQ7 AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 14. Flash Data Toggle DQ6, DQ2 AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 22. Flash Data Polling and Toggle Bits AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 15. Flash Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure 16. Flash Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 17. SRAM Read Mode AC Waveforms, Address Controlled with UBS = LBS = V

Figure 18. SRAM Read AC Waveforms, ES or GS Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Figure 19. SRAM Standby AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 23. SRAM Read AC Characteristics) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 20. SRAM Write AC Waveforms, WS Controlled with GS Low . . . . . . . . . . . . . . . . . . . . . .40

Figure 21. SRAM Write AC Waveforms, WS Controlled with GS High. . . . . . . . . . . . . . . . . . . . . . 40

Figure 22. SRAM Write Cycle Waveform, UBS and LBS Controlled, G Low . . . . . . . . . . . . . . . . .41

Figure 23. SRAM Write AC Waveforms, ES Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Table 24. SRAM Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 24. SRAM Low V
Table 25. SRAM Low V

Data Retention AC Waveforms, ES Controlled . . . . . . . . . . . . . . . . . 42

DDS

Data Retention Characteristics (1, 2) . . . . . . . . . . . . . . . . . . . . . . . . . 43

DDS

= –40 to 85°C; V

A

DDF

= V

= 1.65V to 2.2V) . . . . . . . . 28

DDS

. . . . . . 38

IL

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 25. Stacked LFBGA 12x8mm - 8x8 ball array, 0.8mm pitch, Bottom View Package Outline44
Table 26. Stacked LFBGA 12x8mm - 8x8 ball array, 0.8mm pitch, Package Mechanica l Data . . . 44

4/52

M36DR432AD, M36DR432BD

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 27. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

APPENDIX A. BLOCK ADDRESSES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 28. Bank A, Top Boot Block Addresses M36DR432AD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 29. Bank B, Top Boot Block Addresses M36DR432AD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 30. Bank B, Bottom Boot Block Addresses M36DR432BD . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 31. Bank A, Bottom Boot Block Addresses M36DR432BD . . . . . . . . . . . . . . . . . . . . . . . . . . 47

APPENDIX B. COMMON FLASH INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 32. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Table 33. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Table 34. CFI Query System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 35. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 36. Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

5/52

M36DR432AD, M36DR432B D

SUMMARY DESCRIPTION

The M36DR432AD/BD is a low-voltage Multiple
Memory Product which combines two memory de­vices: a 32 Mbit (2Mbit x16) non-volatile Flash
memory and a 4 Mbit SRAM.

The memory is available in a Stacked LFBGA66
12x8mm - 8x8 active ball array, 0.8mm pitch pack­age and supplied with all the bits erased (set to

‘1’).

Figure 2. Logic Diagram

Table 1. Signal Names

A0-A17 Address Inputs
A18-A20 Address Inputs for Flash Chip only
DQ0-DQ15 Data Input/Outputs, Command Inputs
V

V

DDF

PPF

Flash Power Supply
Flash Optional Supply V oltage for Fast

Program & Erase

A0-A20

WF

EF
GF

RPF

WPF

E1S
E2S

GS

WS

UBS

LBS

21

V

V

DDF

PPF

M36DR432AD
M36DR432BD

V

SSF

V

SSS

V

DDS

16

DQ0-DQ15

AI07309b

V

SSF

V

DDS

V

SSS

NC Not Connected Internally

Flash control functions

EF
GF
WF
RPF
WPF

SRAM control functions

1S Chip Enable

E
E2S Chip Enable
GS
WS
UBS
LBS

Flash Ground
SRAM Power Supply
SRAM Ground

Chip Enable
Output Enable
Write Enable
Reset/Power-Down
Write Protect input

Output Enable
Write Enable
Upper Byte Enable
Lower Byte Enable

6/52

Figure 3. TFBGA Connections (Top view through package)

#4#3

NCNC

M36DR432AD, M36DR432BD

AI90204

NC

NCNCGF

87654321

NC

SSF

V

A12

A13A11A20NCNC

A15 A14

DQ7

DQ14

WS

DQ15A9A16

A8 A10

DQ5

DQ4

DQ6DQ13NCWF

DDF

V

DDS

V

E2SDQ12V

RPF

SSS

DQ3DQ2

DQ10

DQ11A19WPF

PPF

V

DQ1DQ0

DQ8DQ9GSLBS

UBS

E1SA1

A2A3A6A7A18

A17

SSF

EFA0A4NCNC

A5

NC V

#2#1

A

B

C

D

E

F

G

H

7/52

M36DR432AD, M36DR432B D

SIGNAL DESCRIPTIONS

See Figure 2 Logic Diagram and Tabl e 1, Signal
Names, for a brief overview of the signals connect­ed to this device.

Address Inputs (A0-A17). Addresses A0-A17 are common inputs for the Flash an d the SRAM components. The Address Inputs select the cells in the memory array to access during Bu s Read operations. During Bus Write operations they con­trol the commands sent to the Command Interface of the internal state machine. During a write oper­ation, the address inputs for the Flash memory are latched on the falling edge of the Flash Chip E n­able (EF last, whereas for the SRAM array they are latched on the falling edge of the SRAM Chip Enable lines (E1S the datasheet, only the Active Low SRAM Chip Enable line will be di scussed. I t wil l be ref erred to as ES

Address Inputs (A18-A20). Addresses A18-A20 are inputs for the Flash component only. They are latched during a write operation on the falling edge of Flash Chip Enable (EF whichever occurs last.

Data Input/Output (DQ0-DQ15). The Data I/O output the data stored at the selected address dur­ing a Bus Read operation or input a command or the data to be programmed during a Write Bus op­eration.

The input is data to be programmed in the Flash or
SRAM memory array or a command to be written
to the C.I. of the Flash memory. Both are latched
on the rising edge of Flash Write Enable (WF
SRAM Chip Enable lines (ES
(WS
array or SRAM array, the Electronic Signature
Manufacturer or Device codes, the Block Protec­tion status, the Configuration Register status or
the Status Register Data (Polling bit DQ7, Toggle
bits DQ6 and DQ2, Error bit DQ5 or Erase Timer
bit DQ3) depending on the address. Outputs are
valid when Flash Chip Enable (EF
able (GF
Output Enable (GS

The output is high impedance when both the Flash
chip and the SRAM chip are deselected or the out­puts are disabled and when Reset (RPF

Flash Chip Enable (EF

activates the Flash memory control logic, input
buffers, decoders and sense amplifiers. When
Chip Enable is at V
and the power consumption is reduced to the
standby level.

Flash Output Enable (GF

through the data buffers during a read operation.

) or Write Enable (WF), whichever occurs

or E2S) or Write Enable (WS). In the rest of

.

) or Write Enable (WF),

) and,

) or Write Enable

). The output is data from the Flash memory

) and Output En-

) or SRAM Chip Enable lines (ES) and

) are active.

) is at VIL.

). The Chip Enable input

the memory is deselected

IH

). gates the outputs

When Output Enable, GF

, is at VIH the outputs are

High impedance.

Flash Write Enable (

WF). The Write Enable

controls the Bus Write operation of the Flash

memory’s Command Interface.

Flash Write Protect (WPF

). Write Protect is an

input that gives an additional hardware protect ion
for each Flash block. When Write Protect is at V

IL

the locked-down blocks cannot be locked or un­locked. When Write Protect is at V

, the Lock-

IH

Down is disabled and the Locked-Down blocks
can be locked or unlocked. Refer to Table 8, Read
Protection Register.

Flash Reset/Power-Down (RPF

). The Reset/

Power-Down input provides hardwa re res et of the
Flash memory, and/or Power-Down functions, de­pending on the Flash Configuration Register sta­tus. Reset or Power-Down of the memory is
achieved b y pulling RPF

to VIL for at least t

PLPH

.

The Reset/Power-Down function is set in the Con­figuration Register (see Set Configuration Regis­ter Command). If it is set to ‘0’ the Reset function
is enabled, if it is set to ‘1’ the Power-Down func­tion is enabled. After a Reset or Power-Up the
power save function is disabled and all blocks are
locked.

The memory Command Interface is reset on Pow­er Up to Read Array. Either Chip Enabl e or Write
Enable must be tied to V

during Power Up to al-

IH

low maximum security and the possibility to write a
command on the first rising edge of Write Enable.

After a Reset, when the de vice is in Re ad, Eras e
Suspend Read or Standby, valid data will be out­put t

PHQ7V1

after the rising edge of RPF. If the de­vice is in Erase or Program, the operation will be
aborted and the reset recovery will t ake a maxi­mum of t
set/Power-Down t
RPF

. See Tables 18 and 19, and Figure 12.

Supply Voltage (1.65V to 2.2 V). V

V

DDF

. The memory will recover from Re-

PLQ7V

PHQ7V2

after the rising ed ge of

DDF

pro­vides the power supply to the internal core and I/O
pins of the memory device. It is the main power
supply for all operations (read, program and
erase).

Programming Voltage (11.4V to 12.6V).

V

PPF

provides a high voltage power supply for fast

V

PPF

factory programming. V

is required to use the

PPF

Double Word and Quadruple Word Program com­mands.

V

Ground. V

SSF

ground is the reference for

SSF

the core supply. It must be connected to the sys­tem ground.

SRAM Chip Enable (ES

). The Chip Enable in-

puts for SRAM activate the memory con trol logic,
input buffers and decoders. ES

at VIH deselects

,

8/52

M36DR432AD, M36DR432BD

the memory and red uces the power consumption
to the standby level. ES

can also be used to con­trol writing to the SRAM memory array, while WS
remains at VIL. It is not allowed to set EF at VIL and
ES

at VIL at the same time.

SRAM Write Enable (WS

). The Write Enable in-

put controls writing to the SRAM memory array.
WS

is active Low.

SRAM Output E nable (GS

). The Output Enable

gates the outputs through the data buffers during
a read operation of the SRAM c hip. GS

is active

Low.

SRAM Upper Byte Enable (UBS

upper bytes for SRAM (DQ8-DQ15). UBS

). Enables the

is acti ve

Low.

SRAM Lower Byte Enable (LBS

lower bytes for SRAM (DQ0-DQ7). LBS

). Enables the

is active

Low.

V

Supply Voltage (1.65V to 2.2V) . V

DDS

DDS

is the

SRAM power supply for all operations.

Note: Each device in a system should have
V

DDF

and V

decoupled with a 0.1µF capaci-

PPF

tor close to the pin. See Figure 7, AC Measure­ment Load Circuit. The PCB trace widths
should be sufficient to carry the required V

PPF

program and erase currents.

9/52

M36DR432AD, M36DR432B D

FUNCTIONAL DESCRIPTION

The Flash and SRAM components have separate
power supplies and grounds and are distinguished
by three chip enable inputs: EF

Figure 4. Funct i on a l Bl ock D i agram

for the Flash mem-

ory and ES
SRAM .

(E1S and E2S, respectively) f or the

EF

GF

WF

RPF

WPF

A18-A20

A0-A17

E1S
E2S

GS

WS

UBS

LBS

V

DDF

Flash Memory

32 Mbit (2Mb x 16)

V

DDS

SRAM

4 Mbit (256Kb x 16)

V

PPF

V

SSF

DQ0-DQ15

10/52

V

SSS

AI07310b

Table 2. Main Operation Modes

Operation Mode EF GF WF RPF WPF ES GS WS

V

V

Read
Page Read
Write
Standby
Reset/

Flash Memory

Power-Down
Output Disable

IL

V

IL

V

IL

V

IH

XXX

V

IL

V

IL

V

V

IL

V

IH

XX

V

V

IH

Read Flash must be disabled

V

IH

V

IH

V

V

IL

V

V

V

IH

V

IH

IH

IH

IH

IL

IH

IH

V

IH

V

IH

V

IH

V

IH

V

IH

SRAM must be disabled Data Output
SRAM must be disabled Data Output
SRAM must be disabled Data Input

Any SRAM mode is allowed Hi-Z

Any SRAM mode is allowed Hi-Z

Any SRAM mode is allowed Hi-Z

V

VILV

IL

M36DR432AD, M36DR432BD

(1)

DQ15-DQ0

Data out

Word Read

IH

UBS, LBS

V

IL

Write Flash must be disabled

Standby/Power
Down

SRAM

Any Flash mode is allowable

Data Retention Any Flash mode is allowable

Output Disable Any Flash mode is allowable

Note: 1. X = Don’t care (VIL or VIH).

UBS and LBS are tied toge ther the bus is at 16 bit. For an 8 bi t bus configuration use U BS and LBS separately.

2. If

V

V

IL

IHVIL

V

X X X Hi-Z

IH

XXX

V

X X X Hi-Z

IH

XXX

V

V

IL

IHVIH

V

IL

V

IH

V

IH

Data in Word

Write

Hi-Z

Hi-Z

X Hi-Z

11/52

M36DR432AD, M36DR432B D

FLASH MEMORY COMPONENT

The Flash Memory is a 32 Mbit (2Mbit x16) non­volatile Flash memory that may be erased electri­cally at block level and programmed in-s ystem on
a Word-by-Word basis using a 1.65V to 2.2V V
supply for the circuitry and a 1.65V to 2.2V V
supply for the Input/Output pins (in the stacked de­vice , V
tional 12V V

DDF

and V

power supply is provided to speed

PPF

are tied internally). An op-

DDQF

up customer programming.
The Flash device features an asymmetrical block

architecture with an array of 71 bl ocks divided into
two banks, Banks A and B, providing Dual Bank
operations. While programming or erasing in Bank
A, read operations are poss ible in Ban k B or vice
versa. Only one ban k at a t ime is allowed to be in
program or erase mode. The ba nk architectu re is
summarized in Table 3, and the B lock Addresses
are shown in Appendi x A. The Parameter B locks
are located at the top of the memory address
space for the M36DR432AD and, at the bottom for
the M 36DR432BD.

Each block can be erased separately. Erase can
be suspended, in order to perform either read or
program in any other block, and then resumed.
Each block can be programmed and erased over
100,000 cycles.

DDF

DDQF

Program and Erase command s are written to the
Command Interface of the memory. An internal
Program/Erase Controller takes care of the tim­ings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified in the
Status Register. The command set required to
control the memory is consistent with JEDEC stan­dards.

The Flash memory features an instant, individual
block locking scheme that allo ws any block to be
locked or unlocked with no latency, enabling in­stant code and data protection. All blocks have two
levels of protection. They can be individually
locked and locked-down preventing any acciden­tal programming or erasure. All blocks are locked
at Power Up and Reset.

The device includes a 128 b it Protection Register
and a Security Block to increase the protection of

a system’s design. The Prote ction Register is di­vided into two 64 bit segments. The first segment
contains a unique device numb er written by ST,
while the second one is one-time-programmable
by the user. The user programmable segment can
be permanently protected. The Security Block, pa­rameter block 0, can be permanently protected by
the user. Figure 5, shows the Flash Security Block
and Protection Register Memory Map.

Table 3. Flash Bank Architecture

Bank A 4 Mbits 8 blocks of 4 KWords 7 blocks of 32 KWords
Bank B 28 Mbits - 56 blocks of 32 KWords

Bank Size Parameter Blocks Main Blocks

12/52

M36DR432AD, M36DR432BD

Figure 5. Flash Security Block and Protection Register Memo ry Ma p

PROTECTION REGISTER

88h

SECURITY BLOCK

85h
84h

Parameter Block # 0

81h
80h

User Programmable OTP

Unique device number

Protection Register Lock 2 1 0

AI06185

Flash Bus Operations

The following operations can be performed using
the appropriate bus cycles: Flash Read Array
(Random and Page Modes), Flash Write, Flash
Output Disable, Flash Standby and F lash Reset/
Power-Down, see Table 2, Main Operation
Modes.

Flash Read. Flash Read operat ions are used to output the contents of the Memory Array, the Elec­tronic Signature, the Status Register, the CF I, the Block Protection Status or the Configuration Reg­ister status. Read operation of the Flash memory array is performed in asynchronous page mode, that provides fast access time. Data is internally read and stored in a page buffer. The page has a size of 4 words and is addressed by A0-A1 ad­dress inputs. Read operations of the Electronic Signature, the Status Register, the CFI, the Block Protection Status, the Configuration Register sta­tus and the Security Code are performed as single asynchronous read cycles (Random Read). Both Flash Chip Enable EF GF

must be at VIL in order to read the output of the

and Flash Output Enable

memory. Flash Write. Write operations are used to give

commands to the memory or to latch Input Data to
be programmed. A write operation is initiated
when Chip Enable EF

with Output E nable G F at VIH. Addresses are

V

IL

latched on the falling edge of WF

and Write Enable WF are at

or EF whichever
occurs last. Commands and Input Data are
latched on the rising edge of WF

or EF whichever
occurs first. Noise pulses of less than 5ns typical
on EF

, WF and GF signals do not start a write cy-

cle.

Flash Output Disable. The data outputs are high impedance when the Output Enable GF

is at V

IH

with Write Enable WF at VIH. Flash Standby. The memory is in standby when

Chip Enable EF

is at VIH and the P/E.C. is idle.
The power consumption is reduced to the standby
level and the outputs are high imped ance, inde­pendent of the Output Enable GF

inputs.

WF

or Write Enable

Automatic Flash Standby. In Read mode, after 150ns of bus inactivity and when CMOS levels are driving the addresses, the chip automatically en­ters a pseudo-standby mode where consumption is reduced to the CMOS standby value, while out­puts still drive the bus.

Flash Power-Down. The memory is in Power­Down when the Configuration Register is set for/ Power-Down and RPF

is at VIL. The power con­sumption is reduced to the Power-Down level, and
Outputs are high impedance, independent of the
Chip Enable EF
able WF

inputs.

, Output Enable GF or Write En-

Dual Bank Operations. The Dual Bank allows data to be read from on e bank of memory while a program or erase operation is i n progress in the other bank of the memory. Read and Write cycles can be initiated for simultaneous operations in dif­ferent banks without any delay. Status Register during Program or Erase must be monitored using an address within the bank being modified.

Flash Command Interface

All Bus Write operations t o the me mory are in ter­preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper­ations. An internal Program/Erase Controller han-

13/52

M36DR432AD, M36DR432B D

dles all timings and verifies the correct execution
of the Program and Erase commands. Two bus
write cycles are required to unlo ck the Com mand
Interface. They are followed by a setup or confirm
cycle. The increased number of write cycles is to
ensure maximum data security.

The Program/Erase Controller provides a Status
Register whose output may be read at any time to
monitor the progress or the result of the operation.

The Command Interface is reset to Read mode
when power is first applied or exiting from Reset.
Command sequences must be followed exactly.
Any invalid combination of commands will reset
the device to Read mode

Flash Read/Reset Command. The Read/Reset command returns the device to Read mode. One Bus Write cycle is required to issue the Read/Re­set command and return the device to Read mode. Subsequent Read operations will read the ad­dressed location and output the data. The write cy­cle can be preceded by the unlock cycles but it is not mandatory.

Flash Read CFI Query Command. The Read CFI Query command is used to read data from the Common Flash Interface (CFI) and the Electronic Signature (Manufacturer or the Device Code, see Table 5). The Read CFI Query Command consists of one Bus Write cycle. Once the command is is­sued the device enters Read CFI mode. Subse­quent Bus Read operations read the Common Flash Interface or Electronic Signature. Once the device has entered Read CFI mode, only the Read/Reset command should be used and no oth­er. Issuing the Read/Res et command returns t he device to Read mode.

See Appendix B, Common Flash Interface, Tables
33, 34, and 35 for details on the information con­tained in the Common Flash Interface memory ar­ea.

Auto Select Command. The Auto Select com­mand uses the two unlock cycles followed by one write cycle to any bank address to setup the com­mand. Subsequent reads at any address will ou t­put the Block Protection status, Protection Register and Protection Register Lock or the Con­figuration Register status depending on the levels of A0 and A1 (see Tables 6, 7 an d 8). Once the Auto Select command has been issued only the Read/Reset command should be used and no oth­er. Issuing the Read/Res et command returns t he device to Read mode.

Set Conf iguration Regist er Command . The Flash component contains a Configuration Regis­ter, see Table 7, Configuration Register.

It is used to define the status of the Res et/Power­Down functions. The value for the Configuration
Register is always presented on A0-A15, the other

address bits are ignore d. Address input A10 de­fines the status of the Reset/Power-Down func-

tions. If it is set to ‘0’ the Reset function is enabled,
if it is set to ‘1’ the Power-Down function is en­abled. At Power Up the Configuration Register bit
is set to ‘0’.

The Set Configuration Register command is used
to write a new value to the Configuration Register.
The command uses the two unlock cycles followed
by one write cycle to setup the command and a
further write cycle to wri te the data and confirm the
command.

Program Command. The Program command uses the two unlock cycles followed by a write cy­cle to setup the command and a further write cycle to latch the Address and Dat a and start the Pro­gram Erase Controller. Read operations within the same bank output the Status Register after pro­gramming has started.

Note that the Program command cannot change a
bit set at ’0’ bac k to ’1’. One of the E rase Com­mands must be used to set all the bits in a block or
in the whole bank from ’0’ to ’1’. If the Program
command is used to try to set a bi t from ‘0’ to ‘ 1’
Status Register Error bit DQ5 will be set to ‘1’, only

is in the range of 11.4V to 12.6V.

if V

PPF

Double Word Pr ogr a m C omman d. This feature is offered to improve the programming throughput by writing a page of two adjacent words in parallel. The V

supply voltage is required to be from

PPF

11.4V to 12.6V for the Double Word Program com­mand.

The command uses the two unlock cycles followed
by a write cycle to setup the command. A further
two cycles are required t o latch the address and
data of the two Words and start the Program Erase
Controller.

The addresses must be the same except for the
A0. The Double Wo rd Program com mand can be
executed in Bypass mode t o skip the two unlock
cycles.

Note that the Double Word Program command
cannot change a bit set at ’0’ back to ’1’. One of the
Erase Commands must be used to set all the bits
in a block or in the whole bank from ’0’ to ’1’. If the
Double Word Program comm and is used t o try to
set a bit from ‘0’ to ‘1’ Status Register Error bit DQ5
will be set to ‘1 ’.

Quadruple Word Program Command. The Quadruple Word Program command improves the programming throughput by writing a page of four adjacent words in parallel. The four words must differ only for the addresses A0 and A1. The V

PPF

supply voltage is required to be from 11.4V to

12.6V for the Quadruple Word Program com­mand.

14/52

M36DR432AD, M36DR432BD

The command uses the two unlock cycles followed
by a write cycle to setup the command. A further
four cycles are required to latch the address and
data of the four Words and start the Program
Erase Controller.

The Quadruple Word Program command can be
executed in Bypass mode t o skip the two unlock
cycles.

Note that the Quadruple Word Program command

cannot change a bit set to ’0’ back to ’1’. One of the
Erase Commands must be used to set all the bits
in a block or in the whole bank from ’0’ to ’1’. If the
Quadruple Word Program command is used to try
to set a bit from ‘0’ to ‘ 1’ Status Register E rror bit
DQ5 will be set to ‘1’.

Enter Bypas s Mode Comman d. The Bypass mode is used to reduce the overall programming time when large memory array s need to be pro­grammed.

The Enter Bypass Mode command uses the two
unlock cycl e s followed by on e wri te cycle to set u p
the command. Once in Bypass mode, it is impera­tive that only the following commands be issued:
Exit Bypass, Program, Double Word Program or
Quadruple Word Program.

Exit Bypass Mode Command. The Exit Bypas s Mode command uses two write cycles to setup and confirm the command. The unlock cycles are not required. After the Exit Bypass Mode com­mand, the device resets to Read mode.

Program in Bypass Mode Command. The Program in Bypass Mode command can be is­sued when the device is in Bypas s m ode (issue a Enter Bypass Mode command). It uses the same sequence of cycles as the Program command with the exception of the unlock cycles.

Double Word Program in Bypass Mode Com­mand. The Double Word Program in Bypass

Mode command can be issued when the device is
in Bypass mode (issue a Enter Bypass Mode com­mand). It uses the same sequence of cycles as the
Double Word Program comma nd with the excep­tion of the unlock cycles.

Quadruple Word Program in Bypass Mode Command. The Quadruple Word Program in By-

pass Mode command can be issued when the de­vice is in Bypass mode (issue a Enter Bypass
Mode command). I t uses the same sequence of
cycles as the Quadruple Word Program command
with the exception of the unlock cycles.

Block Lock Command. The Block Lock com­mand is used to lock a block and prevent Program
or Erase operations from changing the data i n it.
All blocks are locked at power-up or reset.

Three Bus Write cycles are required to issue the
Block Lock command.

■ The first two bus cycles unlock the Command

Interface.

■ The third bus cycle sets up the Block Lock

command and latches the block address.

The lock status can be monitored for each block
using the Auto Select comma nd. Table 10 shows
the Lock Status a fter issuing a Block Lock com­mand.

The Block Lock bits are vo latile, once set they re­main set until a hardware reset or power-down/
power-up. They are cleared by a Blocks Unlock
command. Refer to the section, Block Locking, for
a detailed explanation.

Block Unlock Command. The Blocks Unlock
command is used to unlock a block, allowing the
block to be programmed or erased.

Three Bus Write cycles are required to issue the
Blocks Unlock command.

■ The first two bus cycles unlock the Command

Interface.

■ The third bus cycle sets up the Block UnLock

command and latches the block address.

The lock status can be monitored for each block
using the Auto Select comma nd. Table 10 shows
the lock status after issuing a Block Unlock com­mand. Refer to the section, Block Locking, for a
detailed explanation.

Block Lock-Down Command. A locked or un­locked block can be locked-down by issuing the
Block Lock-Down command. A locked-down block
cannot be programmed or erased, or have its pro­tection status changed when WPF
When WPF

is High, V

the Lock-Down function is

IH,

is Low, VIL.

disabled and the locked blocks can be individually
unlocked by the Block Unlock command.

Three Bus Write cycles are required to issue the
Block Lock-Down command.

■ The first two bus cycles unlock the Command

Interface.

■ The third bus cycle sets up the Block Lock-

Down command and latches the block address.

The lock status can be monitored for each block
using the Auto Select command. Locked-Down
blocks revert to the locked (and not locked-down)
state when the device is reset on power-down. Ta­ble 10 shows the Lock Status after issuing a Block
Lock-Down command. Refer to the section, Block
Locking, for a detailed explanation.

Block Erase Command. The Block Erase com­mand can be used to erase a bloc k. It set s all t he bits within the selected block to ’1’. All previous data in the block is lost. If the block is protected then the Erase operation will abort, the data in the block will not be changed and the device will return to Read Array mode. It is not necessary to pre-pro-

15/52

M36DR432AD, M36DR432B D

gram the block as the Program/ Erase Controller
does it automatically before erasing.

Six Bus Write cycles are required to issue the
command.

■ The first two write cycles unlock the Command

Interface.

■ The third write cycles sets up the command

■ the fourth and fifth write cycles repeat the unlock

sequence

■ the sixth write cycle latches the block address

and confirms the command.

Additional Block Erase confirm cycles can be is­sued to erase other bloc ks without further unlock
cycles. All blocks must belong to the same bank; if
a new block belonging to the other ban k is given,
the operation is aborted.

The additional Block Erase confirm cycles must be
given within the DQ3 erase timeout period. Each
time a new confirm cycle is issued the timeout pe­riod restarts. The status of the internal timer can
be monitored through the level of DQ3, see Status
Register section for more details.

Once the command is issued the device outputs
the Status Register data when any address within
the bank is read.

After the command has been issued the Flash
Read/Reset command will be accepted during the
DQ3 timeout period, after that only the Erase Sus­pend command will be accepted.

On successfu l compl etio n of t he Bl ock Erase c om­mand, the device returns to Read Array mode.

Bank Erase Command. The Bank Erase com­mand can be used to eras e a bank. It sets all the

bits within the selected bank to ’1’. All previous
data in the bank is lost. The Bank Erase command
will ignore an y pro tec t e d b locks within the bank. If
all blocks in the bank are protected then the Bank
Erase operation will abort and the data in the bank
will not be changed. It is not necessary to pre-pro­gram the bank as the Program/Erase Controller
does it automatically before erasing.

As for the Block Erase command six Bus Write cy­cles are required to issue the command.

■ The first two write cycles unlock the Command

Interface.

■ The third write cycles sets up the command

■ the fourth and fifth write cycles repeat the unlock

sequence

■ the sixth write cycle latches the block address

and confirms the command.

Once the command is issued the device outputs
the Status Register data when any address within
the bank is read.

On successful completion of the Bank Erase com­mand, the device returns to Read Array mode.

Erase Suspend Command. The Erase Suspend command is used to pause a Block Erase opera­tion. In a Dual Bank memory it can be used to read data within the bank where an Erase operation is in progress. It is also possible to program data in blocks not being erased.

One bus write cycle is required to issue the Erase
Suspend command. The Program/Erase Control­ler suspends the Erase operation within 20µs of
the Erase Suspend command being issued and
bits 7, 6 and/ or 2 of the Status Register are set to
‘1’. The device is then automatically set to Read
mode. The command can be addressed to any
bank.

During Erase Suspend the memory will accept the
Erase Resume, Program, Read CFI Query, Auto
Select, Block Lock, Block U nlock and B lo ck Lo ck­Down commands.

Erase Resume Command. The Erase Resume command can be used to restart the Program/ Erase Controller after an Erase Suspend com­mand has paused it. One Bus Write cycle is re­quired to issue the command. The command must be issued to an address within the bank being erased. The unlock cycles are not required.

Protection R egister Progr am C om m and. The
Protection Register Program c omm and is used to
Program the Protection Register (One-Time-Pro­grammable (OTP) segment and Protection Regis­ter Lock). The OTP segment is programmed 16
bits at a time. When shipped all bits in the segment
are set to ‘1’. The user can only program the bits
to ‘0’ .

Four write cycles are required to issue the Protec­tion Register Program command.

■ The first two bus cycles unlock the Command

Interface.

■ The third bus cycle sets up the Protection

Register Program command.

■ The fourth latches the Address and the Data to

be written to the Protection Register and starts
the Program/Erase Controller.

Read operations output the Status Register con­tent after the programming has started.

The OTP segment can be p rotected by program­ming bit 1 of the Protection Register Lock. The
segment can be protected by programming bit 1 of
the Protection Register Lock. Bit 1 of the P rotec­tion Register Lock also protects bit 2 of the Protec­tion Register Lock. Programming bit 2 of the
Protection Register Lock will result in a permanent
protection of Parameter Block #0 (see Figure 5,
Flash Security Block and Protection Register
Memory Map). Attempting to program a previously

16/52

M36DR432AD, M36DR432BD

protected Protection Register will result in a Status
Register error. The protection of the Protection

Register and/or the Security Block is not revers­ible.

Table 4. Flash Commands

Bus Operations

Commands

Read/Reset

CFI Query 1+ 55h 98h Read CFI and Electronic Signature until a Read/Reset command is issued.

Auto Select 3+ 555h AAh 2AAh 55h 555h 90h

Set Configuration
Register

Program 4 555h AAh 2AAh 55h 555h A0h PA PD

Double Word
Program

Quadruple Word
Program

Enter Bypass
Mode

Exit Bypass
Mode

Program in
Bypass Mode

Double Word
Program in
Bypass Mode

Quadruple Word
Program in
Bypass Mode

1+ X F0h Read Memory Array until a new write cycle is initiated.
3+ 555h AAh 2AAh 55h 555h F0h Read Memory Array until a new write cycle is initiated.

4 555h AAh 2AAh 55h 555h 60h CRD 03h

5 555h AAh 2AAh 55h 555h 40h PA1 PD1 PA2 PD2

5 555h AAh 2AAh 55h 555h 50h PA1 PD1 PA2 PD2 PA3 PD3 PA4 PD4

3 555h AAh 2AAh 55h 555h 20h

2 X 90h X 00h

2 X A0h PA PD Read Data Polling or Toggle Bit until Program completes.

3 X 40h PA1 PD1 PA2 PD2

3 X 50h PA1 PD1 PA2 PD2 PA3 PD3 PA4 PD4

1st 2nd 3rd 4th 5th 6th 7th

Add Data Add Data Add Data Add Data Add Data Add Data Add Data

No of Cycles

Read Protection Register, Block Protection or

Configuration Register Status until a Read/Reset

command is issued.

Read Data Polling or Toggle Bit until

Program completes.

Block Lock 4 555h AAh 2AAh 55h 555h 60h BA 01h
Block Unlock 4 555h AAh 2AAh 55h 555h 60h BA D0h
Block Lock-Down 4 555h AAh 2AAh 55h 555h 60h BA 2Fh
Block Erase 6+ 555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h BA 30h
Bank Erase 6 555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h BA 10 h

Erase Suspend 1 X B0h

Erase Resume 1 BA 30h

Protection
Register Program

Note: X = Don’t C ar e, B A = Bl ock Add ress , P A = P rogr am a ddr ess, PD = Pr ogram Da ta , CR D = C on figura tio n Reg ist er Da t a. For C oded

cycles address input s A12-A20 are don’t care.

4 555h AAh 2AAh 55h PA C0h PA PD

Read until Toggle stops, then read all the data needed from any Blocks not being

erased then Resume Erase.

Read Data Polling or Toggle Bits until Erase completes or Erase is suspended

another time

17/52

M36DR432AD, M36DR432B D

Table 5. Read Electronic Signature

Code Device EF GF WF A0 A1 A7-A2 A8-A20 DQ 15-DQ0

Manufacturer Code

M36DR432AD

Device Code

M36DR432BD

Note: X = Don’t care.

Table 6. Flash Read Block Protection

Block Status EF

Locked Block
Unlocked Block
Locked-Down

Block

Note: X = Don’t care.

GF WF A0 A1 A20-A12 A7-A2

V

ILVILVIHVILVIH

V

ILVILVIHVILVIH

V

ILVILVIHVILVIH

Table 7. Configuration Register

Function EF GF WF A0 A1 A7-A2 Other Addresses DQ10

RPF

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IH

V

IH

V

IH

V
V
V

V

IL

IH

IH

IL

V

IL

V

IL

Addresses

0 X 0020h
0 X 00A0h
0 X 00A1h

Other

DQ0 DQ1 DQ15-DQ2

Block Address 0 X 1 0 0000h
Block Address 0 X 0 0 0000h

Block Address 0 X X 1 0000h

DQ9-DQ0

DQ15-DQ11

Reset
Reset/Power-Down

Note: X = Don’t care.

V

V

V

V

IL

IL

IH

V

V

IL

V

IL

IH

V

IH

V

V

IH

0 X 0 Don’t Care

IH

0 X 1 Don’t Care

IH

18/52

M36DR432AD, M36DR432BD

Table 8. Read Protection Register

Word EF GF WF A20-A8 A7-0 DQ15-8 DQ7-3 DQ2 DQ1 DQ0

Lock

Unique ID 0
Unique ID 1
Unique ID 2
Unique ID 3
OTP 0
OTP 1
OTP 2
OTP 3

Note: X= Don’t care.

V

ILVILVIH

V

ILVILVIH

V

ILVILVIH

V

ILVILVIH

V

ILVILVIH

V

ILVILVIH

V

ILVILVIH

V

ILVILVIH

V

ILVILVIH

X 80h XXh 00000b

X 81h ID data ID data ID data ID data ID data
X 82h ID data ID data ID data ID data ID data
X 83h ID data ID data ID data ID data ID data
X 84h ID data ID data ID data ID data ID data
X 85h OTP data OTP data OTP data OTP data OTP data
X 86h OTP data OTP data OTP data OTP data OTP data
X 87h OTP data OTP data OTP data OTP data OTP data
X 88h OTP data OTP data OTP data OTP data OTP data

Security

prot.data

Table 9. Program, Erase Times and Progra m, Erase Endu ran ce Cycle s

M36DR432AD, M36D R432 BD

Parameter

Parameter Block (4 KWord) Erase (Preprogrammed) 2.5 0.3 1 s

Min Max Typ

OTP

prot.data

Typical after

100k W/E Cycles

0

Unit

Main Block (32 KWord) Erase (Preprogrammed) 4 0.8 3 s
Bank Erase (Preprogrammed, Bank A) 3 6 s
Bank Erase (Preprogrammed, Bank B) 20 30 s

Chip Program

(1)

Chip Program (Double Word, V
Word Program

Double Word Program (V
Quadruple Word Program (V

(2)

PPF

= 12V)

PPF

= 12V)

PPF

= 12V)

(1)

100 10 µs

100 8 µs
100 8 µs

20 25 s

8s

Program/Erase Cycles (per Block) 100,000 cycles

Note: 1. Excl udes the time needed to execute the sequence for program command.

2. Sam e tim i ng value if V

Flash Block Locking

The Flash memory features an instant, individual
block locking scheme that allo ws any block to be
locked or unlocked with no latency. This locking
scheme has two levels of protection.

■ Lock/Unlock - this first level allows software-

only control of block locking.

■ Lock-Down - this second level requires

hardware interaction before locking can be
changed.

PPF

= 12V

The protection status of each block can be set to
Locked, Unlocked, and Lock-Down. Table 10, de­fines all of the possible protection states (WPF
DQ1, DQ0).

Reading a Block’s Lock Status

The lock status of every block can be read in the
Auto Select mode of the device. Subsequent
reads at the address specified in Table 6, will out­put the protection status of that block. The lock
status is represented by DQ0 and DQ1. DQ0 indi­cates the Block Lock/Unlock status and is se t by
the Lock command and cleared by the Unlock
command. It is also automatically set when enter-

,

19/52

M36DR432AD, M36DR432B D

ing Lock-Down. DQ1 indicates the Lock-Down sta­tus and is set by the Lock-Down command. It
cannot be cleared by software, only by a hardware
reset or power-down.

The following sections explain the operation of the
locking system.

Locked State

The default status of all blocks on power-up or af­ter a hardware reset is L ocked (states (0,0,1) or
(1,0,1)). Locked blocks are fully protected from
any program or erase. Any program or erase oper­ations attempted on a locked block will reset the
device to Read Array mode. The Status of a
Locked block can be changed to Unlocked or
Lock-Down using the appropriate software com­mands. An Unlocked block can be Locked by issu­ing the Lock command.

Unlocked State

Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)),
can be programmed or erased. All unlocked
blocks return to the Locked state after a hardware
reset or when the device is powered-down. The
status of an unlocked block can be changed to
Locked or Locked-Down using the appropriate
software commands. A locked block can be un­locked by issuing the Unlock command.

Lock-Down State

Blocks that are Locked-Down (state (0,1,x))are
protected from program and erase operations (as
for Locked blocks) but th eir protect ion status can­not be changed using software comma nds alone.
A Locked or Unlocked block can be Locked-Down
by issuing the Lock-Down command. Locked­Down blocks revert to the Locked state when the
device is reset or powered-down.

The Lock-Down function is dependent on the WPF
input pin. When WPF=0 (VIL), the blocks in the
Lock-Down state (0,1,x) are protected from pro­gram, erase and protection status changes. When

=1 (VIH) the Lock-Down function is disabled

WPF
(1,1,1) and Locked-Down blocks can be ind ividu­ally unlocked to the (1,1,0) state by issuing the
software command, where they can be erased and
programmed. These blocks can then be re-locked
(1,1,1) and unlocked (1,1,0) as desired while WPF
remains High. When WPF is Low, blocks that were
previously Locked-Down return to the Lock-Down
state (0,1,x) regardless of any changes made
while WPF

was High. Device reset or power-down
resets all bl ocks, including those in Lock -Do wn, to
the Locked state.

Locking Operations During Erase Suspend

Changes to block lock status can be performed
during an erase suspend by using the standard
locking command sequences to unlock, lock or
lock-down a block. This is useful in the case when
another block needs to be updated while an erase
operation is in progress.

To change block locking during an erase opera­tion, first write the Erase Suspend command, then
check the status register until it indicates that the
erase operation has been suspended. Next write
the desired Lock com mand sequence to a block
and the lock status will be changed. After complet­ing any desired lock, read, or program operations,
resume the erase operation with the Erase Re­sume command.

If a block is locked or locked-down during an erase
suspend of the same block, the locking status bits
will be changed immediately, b ut when the erase
is resumed, the erase operation will complete.

20/52

M36DR432AD, M36DR432BD

Table 10. Flash Lock Status

Current

Protection Status

(WPF, DQ1, DQ0)

Current State

1,0,0 yes 1,0,1 1,0,0 1,1,1 0,0,0

(2)

1,0,1

1,1,0 yes 1,1,1 1,1,0 1,1,1 0,1,1
1,1,1 no 1,1,1 1,1,0 1,1,1 0,1,1
0,0,0 yes 0,0,1 0,0,0 0,1,1 1,0,0

(2)

0,0,1

0,1,1 no 0,1,1 0,1,1 0,1,1

Note: 1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block) as read

in the Auto Select command with A1 = V

2. All blocks are loc ked at power-up, so the defa ul t configura t io n i s 001 or 101 according to WP F

3. A WPF

transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.

(1)

Program/Erase

Allowed

no 1,0,1 1,0,0 1,1,1 0,0,1

no 0,0,1 0,0,0 0,1,1 1,0,1

After

Block Lock

Command

and A0 = VIL.

IH

Next Protection Status

(WPF, DQ1, DQ0)

After

Block Unlock

Command

(1)

After Block
Lock-Down

Command

status.

After

transition

WPF

1,1,1 or 1,1,0

(3)

Flash Status Register

The Status Register provides information on the
current or previous Program or Erase operations.
Bus Read operations from any address within the
bank, always read the Status Register during Pro­gram and Erase operations.

The various bits convey information about the sta­tus and any errors of the operation.

The bits in the Status Register are summarized in
Table 12, Status Register Bits. Refer to Tables 11
and 12 in conjunction with the following text de­scrip tions .

Data Polling Bit (DQ7). When Program opera­tions are in progress, the Data Polling bit outputs the complement of the bit being programmed on DQ7. For a Double Word P rogram operation, it is the complement of DQ7 for the last Word written to the Command Interface.

During an Erase operation, it outputs a ’0’. After
completion of the operation, DQ7 will output the bi t
last programmed or a ’1’ after erasing.

Data Polling is valid and o nly effective during P/
E.C. operation, that is after the fourth WF
programming or after the sixth WF

pulse for

pulse for erase.
It must be performed at the address being pro­grammed or at an address within the block being
erased. See Figure 22 for the D ata Polling f low­chart and Figure 13 for the Data Polling wave­forms.

DQ7 will also flag an Erase Suspend by switching
from ’0’ to ’1’ at the start of the Erase Suspend . In
order to monitor DQ7 in the Erase Suspend mode
an address within a block being erased mus t be

provided. DQ7 will output ’1’ if the read is attempt­ed on a block being erased and the data val ue on
other blocks. During a program operation in Erase
Suspend, DQ7 will have the sam e behavior as in
the normal program.

Toggle Bit (DQ6). When Program or Erase oper­ations are in progress, successive attempts to read DQ6 will output complementary data. DQ6 will toggle following the toggling of either GF

or EF .
The operation is com pleted when t wo success ive
reads give the s ame output data. The n ext read
will output the bit last programmed or a ’1’ after
erasing.

The Toggle Bit DQ6 is valid only during P/ E.C. op­erations, that is after the fourth WF
gramming or after the sixth WF

pulse for pro-

pulse for Erase.
DQ6 will be set to ’1’ if a read operation is attempt­ed on an Erase Suspend block. When erase is
suspended DQ6 will toggle during programming
operations in a block different from the block in
Erase Suspend.

See Figure 16 for Toggle Bit f lowcha rt an d Figure
14 for Toggle Bit waveforms.

Toggle Bit (DQ2). Toggle Bit DQ2, together with DQ6, can be used to det ermine the d evice status during erase operations.

During Erase Suspend a read from a block being
erased will cause DQ2 t o toggle. A read from a
block not being eras ed will o utput data . DQ2 will

be set to '1' during program operation and to ‘0’ in
erase operation. If a read operation is addres sed
to a block where an erase error has occurred, DQ2
will toggle.

21/52

M36DR432AD, M36DR432B D

Error Bit (DQ5). The Error Bit can be used to

identify if an error occurs during a program or
erase operation.

The Error Bit is set to ‘1’ when a program or erase
operation has failed. When it is set to ‘0’ the pro­gram or erase operation was successful.

If any Program command is used to try to set a bit
from ‘0’ to ‘1’ Stat u s Re gis ter Error bit DQ5 w ill be
set to ‘1’, only if V

is in the range of 11.4V to

PP

12.6V. The Error Bit is reset by a Read/Reset command. Erase Timer Bit (DQ3). The Erase Timer bit is

used to indicate the timeout period for an erase
operation.

When the last block Erase command has been en­tered to the Command Interface and it is waiting
for the erase operation to start, the Erase Timer Bit
is set to ‘0’. When the erase timeou t period is fin­ished, DQ3 returns to ‘1’, (80µs to 120µs).

DQ0, DQ1 and DQ4 are reserved for future use
and should be masked.

Table 11. Polling and Toggle Bits

Mode DQ7 DQ6 DQ2

Program DQ7
Erase 0 T oggle N/A
Erase Suspend Read

(in Erase Suspend
block)

Erase Suspend Read
(outside Erase Suspend
block)

Erase Suspend Program DQ7

DQ7 DQ6 DQ2

Toggle 1

1 1 Toggle

Toggle 1

22/52

M36DR432AD, M36DR432BD

Table 12. Status Register Bits

DQ Name Logic Level Definition Note

Erase complete or erase block
in Erase Suspend.

Program complete or data of
non erase block during Erase
Suspend.

Program in progress

(2)

Erase complete or Erase
Suspend on currently addressed
block

Indicates the P/E.C. status, check
during Program or Erase, and on
completion before checking bits DQ5
for Program or Erase success.

complementary data on DQ6 while
Programming or Erase operations are
in progress. DQ6 remains at constant
level when P/E.C. operations are
completed or Erase Suspend is
acknowledged.

Data

7

Polling

6 Toggle Bit

’1’

’0’ Erase in progress

DQ

DQ

’-1-0-1-0-1-0-1-’ Erase or Program in progress Successive reads output

DQ Program complete

’-1-1-1-1-1-1-1-’

5 Error Bit

’1’ Program or Erase Error
’0’ Program or Erase in progress

This bit is set to ’1’ in the case of
Programming or Erase failure.

4 Reserved

P/E.C. Erase operation has started.

’1’ Erase Timeout Period Expired

Only possible command entry is Erase
Suspend

Erase Time

3

Bit

’0’

Erase Timeout Period in
progress

An additional block to be erased in
parallel can be entered to the P/E.C
provided that it belongs to the same
bank

Erase Suspend read in the
Erase Suspended Block.

’-1-0-1-0-1-0-1-’

Erase Error due to the currently
addressed block (when DQ5 =

2 Toggle Bit

1

DQ

’1’).
Program in progress or Erase

complete.
Erase Suspend read on non

Erase Suspend block.

Indicates the erase status and allows
to identify the erased block.

1 Reserved
0 Reserved

Note: 1. Logic lev el ’1’ is Hig h, ’0’ is Low. -0-1-0 -0-0-1-1-1-0- repres ent bit value i n successive read operations.

2. In case of double word program DQ7

refers to the last word input.

23/52

M36DR432AD, M36DR432B D

SRAM C O MPONENT

The SRAM is a 4 Mbit (256Kb x16) low-power con­sumption memory array with low V
tion.

SRAM Operations

The following operations can be performed using
the appropriate bus cycles: Read Array, Write Ar­ray, Output Disable, Power Down (see Table 2).

Read. Read operations are used to output the
contents of the SRAM Array. The SRAM is in Read
mode whenever Write Enable (WS
Output Enable ( GS
UBS

, LBS combinations are asserted.

) at VIL, Chip Enable ES and

Valid data will be available at the output pins within
t

after the last stable address, provided that

AVQV

is Low and ES is Low. If Chip Enable or Output

GS
Enable access times are not met, data access will
be measured from the limiting parameter (t
t

) rather than the address. Data out may be

GLQV

indeterminate at t
will always be valid at t

ELQX

and t

GLQX

(see Table 23, Figures

AVQV

17 and 18).
Write. Write operations are used to write data in

the SRAM. The SRAM is in Write mode whenever
the WS
able input (ES

and ES pins are at VIL. Either t he Chi p En-

) or the Write Enable input (WS)
must be de-asserted during address transitions for
subsequent write cycles. Write begins with the
concurrence of Chip E nab le being active and WS
at VIL. A Write begins at the latest transition

data reten-

DDS

) is at VIH with

or

ELQV

, but d ata lines

among ES

going to VIL and WS going to VIL.
Therefore, address setup time is referenced to
Write Enable and Chip Enable as t

AVWL

and t

AVEL

respectively, and is determined by the latter occur­ring edge. The W rite cycle can be terminated by
the rising edge of ES

or the rising edge of WS,

whichever occurs first.
If the Output is enabled (ES

then WS
within t

will return the outputs to high impedance

of its falling edge. Care must be taken

WLQZ

=VIL and GS=VIL),

to avoid bus c ontention in this type of operation.
Data input must be valid for t
ing edge of Write Enable, or for t
rising edge of ES
main valid for t

, whichever occurs first, and re-

and t

WHDX

EHAX

before the ris-

DVWH

DVEH

before the

(see Table 24, Fig-

ure 20, 22, 24).
Standby/Power-Down. The SRAM chip has a

Chip Enable power-down feature which invokes
an automatic standby mode (see Table 23, Figure

19) whenever either Chip E nable is de-asserted

=VIH).

(ES
Data Retention. The SRAM data retention per-

formances as V
in Table 25 and Figure 24. In E S

go down to VDR are described

DDS

controlled data
retention mode, minimum standby current mode is
entered when ES

≥ V

DDS

–0.2V.

Output Disa bl e . The data outputs are high im­pedance when the Out put Enable (GS

) is at V

IH

with Write Enable (WS) at VIH.

24/52

M36DR432AD, M36DR432BD

MAXIMUM RATIN G

Stressing the device ab ove the rating listed in the
Absolute Maximum Ratings table m ay cause per­manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions ab ove those i ndicated in t he
Operating sections of this specificat ion is not im-

(1)

Table 13. Absolute Maximum Ratings

Symbol Parameter Value Unit

T

A

Ambient Operating Temperature

(3)

plied. Exposure to Absolute Maximum Rating con­ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and ot her relevant quality docu­ments.

–40 to 85 °C

T

BIAS

T

STG

(2)

V

IO

V

DDF

V

DDS

V

PPF

Note: 1. Minimum voltage ma y undershoo t to –2V during tra nsition and for less than 20ns.

2. Depends on range.

3. V

DD

Temperature Under Bias –40 to 125 °C
Storage Temperature –55 to 150 °C

Input or Output Voltage
Supply Voltage –0.5 to 2.7 V

SRAM Chip Supply Voltage –0.5 to 2.4 V
Program Voltage –0.5 to 13 V

= V

= V

DDF

.

DDS

–0.5 to V

DD

(3)

+0.5

V

25/52

M36DR432AD, M36DR432B D

DC AND AC PARAMETERS

This section summarizes t he operating m easure­ment conditions, and the DC and AC characteris­tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement

Table 14. Operating and AC Measurement Conditions

Conditions summarized in Table 14, Operating
and AC Measurement Conditions. Designers
should check that the operating conditions in their
circuit match the operating conditions when rely­ing on the quoted parameters.

SRAM Flash

Parameter

70 85 100, 120

Min Max Min Max Min Max

V

Supply Voltage

DDF

Supply Voltage

V

DDS

Supply Voltage

V

PPF

- - 1.8 2.2 1.65 2.2 V

1.65 2.2 ----V

11.4 12.6 11.4 12.6 V

Ambient Operating Temperature – 40 85 – 40 85 – 40 85 °C

Load Capacitance (C

)

L

30 5 30 30 pF

Input Rise and Fall Times 2 4 4 ns

DDS

= V

(1)

(1)

DDF

Input Pulse Voltages
Input and Output Timing Ref. Voltages

Note: 1. VDD = V

Figure 6. AC Measurement I/O Waveform

V

DD

0V

Note: VDD means V

DDF

= V

DDS

VDD/2

AI90206

0 to V

DD

0 to V

DD

0 to V

VDD/2 VDD/2 VDD/2

Figure 7. AC Me asurement Load Circuit

VDD

DEVICE

UNDER

TEST

0.1µF

CL = 50pF

DD

V

DD

Units

V
V

25kΩ

25kΩ

CL includes JIG capacitance

Note: VDD means V

DDF

= V

DDS

Table 15. Device Capacitance

Symbol Parameter Test Condition Min Max Unit

V

V

IN

OUT

= 0V

= 0V

12 pF
15 pF

C

IN

C

OUT

Note: Sampled only, not 10 0% tested.

Input Capacitance
Output Capacitance

26/52

AI90207

M36DR432AD, M36DR432BD

Table 16. Flash DC Characteristics

Symbol Parameter Test Condition Min Typ Max Unit

I

LI

I

LO

I

CC1

I

CC2

I

CC3

(1)

I

CC4

(1)

I

CC5

I

PPF1

I

PPF2

V

IL

V

IH

V

OL

V

OH

Input Leakage Current

Output Leakage Current
Supply Current

0V ≤ V

0V ≤ V

E

F = VIL, GF = VIH, f =

(Read Mode)
Supply Current

(Power-Down)
Supply Current (Standby)
Supply Current

RP

E

Word Program, Block Erase

(Program or Erase)

Supply Current
(Dual Bank)

V

Supply Current

PPF

(Program or Erase)
V

Supply Current

PPF

(Standby or Read)

Program/Erase in progress

in one Bank, Read in the

V

PPF

V

PPF

Input Low Voltage –0.5 0.4 V
Input High Voltage
Output Low Voltage
Output High Voltage

CMOS

≤ V

IN

DD

≤ V

OUT

DD

6MHz

F = VSS ± 0.2V

F = VDD ± 0.2V

in progress

other Bank

= 12V ± 0.6V

V

≤ V

PPF

DD

= 12V ± 0.6V

V

I

= 100µA

OL

= –100µA VDD –0.1

I

OH

36mA

210µA

10 50 µA

10 20 mA

13 26 mA

25mA

0.2 5 µA

100 400 µA

– 0.4 VDD + 0.4

DD

±1 µA
±5 µA

0.1 V

V

V

PPF

Note: 1. Sampled only, not 100% tested.

(Program or Erase)

may be connected to 12V power supply for a total of less than 100 hrs.

2. V

PPF

3. For s tandard program/erase operation V

V

Supply Voltage

PPF

(2,3)

V

V

–0.4

DD

+ 0.4

Double Word Program 11.4 12.6 V

is don’t ca re.

PPF

V

27/52

M36DR432AD, M36DR432B D

Table 17. SRAM DC Characteristics

(T

= –40 to 85°C; V

A

Symbol Parameter Test Condition Min Typ Max Unit

I

OZ

I

IX

I

DDS

I

DD

V

IL

V

IH

V

OL

V

OH

Note: 1. I

2. V

Output Leakage

Current

Input Load Current

V

DD

Current

Supply Current

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

and I

DDES

and I

= VIL or V

IN

DDWS

If the device is read while in program suspend, current draw is the sum of

DDR.

IH

= V

DDF

Standby

are speci f i ed with device deselected. If device is read while in erase s uspend, current draw is sum of I

= 1.65V to 2.2V)

DDS

0V ≤ V

E

S ≥ V

DDS

= 0 mA, f = f

I

OUT

≤ V

OUT

0V ≤ V

DDS,

IN

– 0.2V, VIN ≥ V

or V

≤

IN

V

DDS

MAX

V

DDS

I

= 0 mA, f = 0Hz

OUT

CMOS levels

V

DDS

V

DDS

V

DDS

I

= 0.1µA

OL

V

DDS

I

= –0.1µA

OH

output disabled

≤ V

DDS

– 0.2V

DDS

0.2V, f=0

= 2.2V

= 1/tRC, CMOS levels

= 2.2V

= 1.65V

= 2.2V

= 1.65V

= 1.65V

-1 +1 +1 µA

-1 ±1 +1 µA

110µA

47mA

15mA

–0.5 0.4 V

1.4

V

DDS

1.4 V

IDDWS

and I

DDR

.

+0.2V

0.2 V

V

DDES

28/52

Figure 8. Flash Random Read AC Waveforms

tEHQZ

tGHQZ

tGHQX

M36DR432AD, M36DR432BD

AI07312

VALID

tAVAV

A0-A20

VALID

tAVQV tAXQX

tELQV

EF

tELQX tEHQX

GF

tGLQV

tGLQX

DQ0-DQ15

Note: Wri te Enable (WF) = High.

29/52

M36DR432AD, M36DR432B D

Figure 9. Flash Page Read AC Waveforms

AI07313

VALID

VALID

VALIDVALID

tGLQV

tGHQZ

tEHQZ

VALID

tGHQX

tEHQX

tAVQV1

VALID VALID VALID

30/52

A2-A20

VALID

A0-A1

tELQV

EF

GF

tAVQV

DQ0-DQ15

Table 18. Flash Read AC Characteristics

Symbol Alt Parameter Test Condition

t

AVAV

t

AVQV

t

AVQV1tPAGE

(1)

t

ELQX

(2)

t

ELQV

(1)

t

GLQX

Address Valid to Next

t

RC

Address Valid
Address Valid to

t

ACC

Output Valid (Random)
Address Valid to

Output Valid (Page)
Chip Enable Low to

t

LZ

Output Transition
Chip Enable Low to

t

CE

Output Valid
Output Enable Low to

t

OLZ

Output Transition

= VIL, GF = V

EF

= VIL, GF = V

EF

= VIL, GF = V

EF

= V

GF

= V

GF

= V

EF

M36DR432AD, M36DR432BD

M36DR432AD, M36DR432BD

Unit85 100 120

Min Max Min Max Min Max

(3)

IL

85

IL

IL

IL

IL

IL

00 0 ns

00 0 ns

100 120 ns

85

30

85

(3)

(3)

(3)

100 120 ns

35 45 ns

100 120 ns

(2)

t

GLQV

t

EHQX

(1)

t

EHQZ

t

GHQX

(1)

t

GHQZ

t

AXQX

Note: 1. Sampled only, not 100% tested.

2. GF

may be delayed by up to t

3. To be c haracteriz ed.

Output Enable Low to

t

OE

Output Valid
Chip Enable High to

t

OH

Output Transition
Chip Enable High to

t

HZ

Output Hi-Z
Output Enable High to

t

OH

Output Transition
Output Enable High to

t

DF

Output Hi-Z
Address Transition to

t

OH

Output Transition

ELQV

= V

EF

IL

= V

GF

IL

= V

GF

IL 20

= V

EF

IL

= V

EF

IL 20

= VIL, GF = V

EF

- t

after the fal l in g edge of EF without increasing t

GLQV

00 0 ns

00 0 ns

00 0 ns

IL

25

(3)

(3)

(3)

25 35 ns

25 35 ns

25 35 ns

.

ELQV

31/52

M36DR432AD, M36DR432B D

Figure 10. Flash Write AC Waveforms, Write Enable Controlled

tAVAV

A0-A20

tAVWL

EF

VALID

tWLAX

tWHEH

tELWL

GF

tWLWHtGHWL

WF

tDVWH

DQ0-DQ15

V

DDF

tVDHEL

Note: Addresses are latched on the falling edge of WF, Data is latched on the ris i ng edge of WF.

VALID

Table 19. Flash Write AC Characteristics, Write Enable Controlled

M36DR432AD, M36DR432BD

Symbol Alt Parameter

Min Max Min Max Min Max

t

AVAV

t

ELWL

t

WLWHtWP

t

DVWH

t

WHDXtDH

t

WHEHtCH

t

WHWLtWPH

t

AVWL

t

WLAX

t

GHWL

t

VDHELtVCSVDD

t

WHGLtOEH

t

PLQ7V

Note: 1. To be characterized .

t

Address Valid to Next Address Valid

WC

t

Chip Enable Low to Write Enable Low 0 0 0 ns

CS

Write Enable Low to Write Enable High

t

Input Valid to Write Enable High

DS

Write Enable High to Input Transition 0 0 0 ns
Write Enable High to Chip Enable High 0 0 0 ns
Write Enable High to Write Enable Low 30 30 30 ns

t

Address Valid to Write Enable Low 0 0 0 ns

AS

t

Write Enable Low to Address Transition 50 50 50 ns

AH

Output Enable High to Write Enable Low 0 0 0 ns

High to Chip Enable Low

Write Enable High to Output Enable Low 30 30 30 ns
RPF Low to Reset Complete During

Program/Erase

85

50
40

(1)

(1)

(1)

100 120 ns

50 50 ns
50 50 ns

50 50 50 µs

15 15 15 µs

tWHGL

tWHWL

tWHDX

AI07314

Unit85 100 120

32/52

Figure 11. Flash Write AC Waveforms, Chip Enable Controlled

tAVAV

A0-A20

tAVEL

WF

VALID

M36DR432AD, M36DR432BD

tELAX

tEHWH

tWLEL

GF

tELEHtGHEL

EF

tDVEH

DQ0-DQ15

V

DDF

tVDHWL

Note: Addresses are latched on the falling edge of EF, Data is latched on the rising edge of EF.

VALID

Table 20. Flash Write AC Characteristics, Chip Enable Controlled

M36DR432AD, M36DR432BD

Symbol Alt Parameter

Min Max Min Max Min Max

t

AVAV

t

Address Valid to Next Address Valid

WC

85

(1)

tEHGL

tEHEL

tEHDX

AI07315

Unit85 100 120

100 120 ns

t

WLEL

t

ELEH

t

DVEH

t

EHDX

t

EHWH

t

EHEL

t

AVEL

t

ELAX

t

GHEL

t

VDHWLtVCSVDD

t

EHGL

t

PLQ7V

Note: 1. To be characterized

t

Write Enable Low to Chip Enable Low 0 0 0 ns

WS

t

Chip Enable Low to Chip Enable High

CP

t

Input Valid to Chip Enable High

DS

t

Chip Enable High to Input Transition 0 0 0 ns

DH

t

Chip Enable High to Write Enable High 0 0 0 ns

WH

t

Chip Enable High to Chip Enable Low 30 30 30 ns

CPH

t

Address Valid to Chip Enable Low 0 0 0 ns

AS

t

Chip Enable Low to Address Transition 50 50 50 ns

AH

Output Enable High Chip Enable Low 0 0 0 ns

t

Chip Enable High to Output Enable Low 30 30 30 ns

OEH

RPF Low to Reset Complete During
Program/Erase

High to Write Enable Low

50
40

(1)

(1)

50 50 ns
50 50 ns

50 50 50 µs

15 15 15 µs

33/52

M36DR432AD, M36DR432B D

Figure 12. Flash Reset/Power-Down AC Waveform

READ

WF

DQ7

RPF

tPHQ7V

VALID

Table 21. Flash Reset/Power-Down AC Characteristics

Symbol Alt Parameter Test Condition

t

PHQ7V1

RPF High to Data Valid
(Read Mode)

PROGRAM / ERASE

DQ7 VALID

tPLPH

tPLQ7V

AI07316

M36DR432AD, M36DR432BD

Unit85 100 120

Min Max Min Max Min Max

150 150 150 ns

t

PHQ7V2

t

PLQ7V

t

PLPHtRP

RPF High to Data Valid
(Reset/Power-Down

50 50 50 µs

enabled)

RPF Low to Reset
Complete

During Program 10 10 10 µs

During Erase 20 20 20 µs

RPF Pulse Width 50 50 50 ns

34/52

Figure 13. Flash Data Polling DQ7 AC Waveforms

M36DR432AD, M36DR432BD

AI07317

ARRAY

READ CYCLE

ADDRESS (WITHIN BLOCKS)

tELQV

tAVQV

tEHQ7V

tGLQV

VALID

DQ7

tWHQ7V

VALID

tQ7VQV

IGNORE

DATA POLLING (LAST) CYCLE MEMORY

A0-A20

EF

GF

WF

DQ7

DQ0-DQ6/

DQ8-DQ15

READ CYCLES

DATA POLLING

PROGRAM

OR ERASE

CYCLE OF

LAST WRITE

INSTRUCTION

35/52

M36DR432AD, M36DR432B D

Figure 14. Flash Data Toggle DQ6, DQ2 AC Waveforms

AI06196

VALID

tEHQV

tAVQV

tELQV

tGLQV

VALID

tWHQV

STOP TOGGLE

VALID

IGNORE

READ CYCLE

MEMORY ARRAY

READ CYCLE

DATA TOGGLE

36/52

A0-A20

EF

GF

WF

DQ6,DQ2

DQ0-DQ1,DQ3-DQ5,

DQ7-DQ15

DATA

TOGGLE

READ CYCLE

OF ERASE

PROGRAM

CYCLE OF

LAST WRITE

INSTRUCTION

Note: Al l ot her timings are as a normal Read cycle.

Table 22. Flash Data Polling and Toggle Bits AC Characteristics

Symbol Parameter

t

WHQ7V

t

EHQ7V

Write Enable High to DQ7 Valid (Program, WF Controlled) 8 100 µs

Write Enable High to DQ7 Valid (Block Erase, WF

Controlled) 0.8 4 s
Chip Enable High to DQ7 Valid (Program, EF Controlled) 8 100 µs
Chip Enable High to DQ7 Valid (Block Erase, EF

Controlled) 0.8 4 s

M36DR432AD, M36DR432BD

M36DR432AD,

M36DR432BD

Min Max

Unit

t

Q7VQV

Q7 Valid to Output Valid (Data Polling) 0 ns
Write Enable High to Output Valid (Program) 8 100 µs

t

WHQV

t

EHQV

Note: All other tim i ngs are defin ed i n Read AC Characteristi cs

Write Enable High to Output Valid (Block Erase) 0.8 4 s
Chip Enable High to Output Valid (Program) 8 100 µs
Chip Enable High to Output Valid (Block Erase) 0.8 4 s

Figure 15. Flash Data Polling Flowchart Figure 16. Flash Data Toggle Flowchart

START

START

READ

READ DQ5 & DQ7

at VALID ADDRESS

DQ7

=

DATA

NO

NO

DQ5

= 1

YES

READ DQ7

YES

DQ5 & DQ6

TOGGLES

NO

READ DQ6

DQ6

=

DQ5

= 1

NO

YES

YES

DQ7

=

DATA

FAIL PASS

YES

NO

AI06197

DQ6

=

TOGGLES

FAIL PASS

NO

YES

AI06198

37/52

M36DR432AD, M36DR432B D

Figure 17. SRAM Read Mode AC Waveforms, Address Controlled with UBS = LBS = V

tAVAV

A0-A17

tAVQV

tAXQX

DQ0-DQ15

Note: ES = Low, GS = Lo w, WS = High.

VALID

DATA VALIDDATA VALID

AI90217

Figure 18. SRAM Read AC Waveforms, ES or GS Controlled

tAVAV

A0-A17

tAVQV tAXQX

tELQV

VALID

tEHQZ

IL

ES

UBS, LBS

GS

DQ0-DQ15

Note: Write Enable (WS) = High.

tELQX

tBLQV

tBLQX

tGLQX

tGLQV

tBHQZ

tGHQZ

DATA VALID

AI07311

38/52

Figure 19. SRAM Standby AC Waveforms

ES

M36DR432AD, M36DR432BD

I

DD

tPU

Table 23. SRAM Read AC Characteristics)

Symbol Alt Parameter

t

AVAV

t

AVQV

t

AXQX

t

BHQZ

t

BLQV

t

BLQX

t

EHQZ

t

ELQV

t

ELQX

t

GHQZ

t

GLQV

t

GLQX

(1)

t

PD

(1)

t

PU

Note: 1. Sampl e d only. Not 100% tested.

t

t

t

t

BHZ

t

t

BLZ

t

t

ACE

t

t

OHZ

t

t

OLZ

Read Cycle Time 70 ns

RC

Address Valid to Output Valid 70 ns

AA

Address Transition to Output Transition 10 ns

OH

UBS, LBS Disable to Hi-Z Output 25 ns
UBS, LBS Access Time 45 ns

BA

UBS, LBS Enable to Low-Z Output 5 ns
Chip Enable High to Output Hi-Z 25 ns

HZ

Chip Enable Low to Output Valid 70 ns
Chip Enable Low to Output Transition 5 ns

LZ

Output Enable High to Output Hi-Z 25 ns
Output Enable Low to Output Valid 35 ns

EO

Output Enable Low to Output Transition 5 ns
Chip Enable High to Power Down 70 ns

Chip Enable Low to Power Up 0 ns

tPD

AI07320

SRAM

Unit70

Min Max

39/52

M36DR432AD, M36DR432B D

Figure 20. SRAM Write AC Waveforms, WS Controlled with GS Low

tAVAV

A0-A17

tAVEL

ES

UBS, LBS

WS

tWLQZ

DQ0-DQ15

Note: Output E nable (GS) = Low.

VALID

tAVWH

tELWH

tBLWH

tWLWHtAVWL

tDVWH

INPUT VALID

Figure 21. SRAM Write AC Waveforms, WS Controlled with GS High

tAVAV

A0-A17

VALID

tWHAX

tWHQX

tWHDX

AI07321

ES

UBS, LBS

WS

GS

DQ0-DQ15

tAVEL

tAVWH

tELWH

tBLWH

tWHAX

tWLWHtAVWL

tDVWH

INPUT VALID

tWHDX

AI07322

40/52

M36DR432AD, M36DR432BD

Figure 22. SRAM Write Cycle Waveform, UBS and LBS Controlled, G Lo w

tAVAV

A0-A17

ES

UBS, LBS

tAVWL

WS

DQ0-DQ15

tWLQZ

Figure 23. SRAM Write AC Waveforms, ES

A0-A17

VALID

tAVWH

tBLWH

tWLEH

Controlled

tAVAV
VALID

tDVWH

INPUT VALID

tEHAX

tWHQX

tWHDX

AI07323

ES

UBS, LBS

WS

DQ0-DQ15

Note: Output E nable (GS) = High.

tAVEL

tELWH

tBLWH

tWLWH

tDVWH

INPUT VALID

tEHAX

tWHDX

AI07324

41/52

M36DR432AD, M36DR432B D

Table 24. SRAM Write AC Characteristics

Symbol Alt Parameter

t

AVAV

t

AVEL

t

AVWH

t

AVWL

t

BLWH

t

DVWH

t

EHAX

t

,

ELWH

t

WHAX

t

WHDX

t

WHQX

t

WLQZ

t

WLWH

Note: 1. tAS is measured from the address valid t o the beginnin g of write.

2. t

WR

3. t

CW

4. A Wri te occu rs dur ing th e over lap ( t
UBS
liest transi t i on when ES

t

WC

t

AS

t

AW

t

AS

t

BW

t

DW

t

WR

t

CW

t

WR

t

DH

t

OW

t

WHZ

t

WP

is measured from the end o r write to the address change. tWR applied in c ase a write ends as ES or WS goes High.
is measured from ES going Low end of write.

or LBS for single byt e operation or sim ultaneously assertin g UBS and LBS for double byte operation. A write ends at the ear-

Write Cycle Time 70 ns

(1)

Address Valid to Chip Enable Low 0 ns
Address Valid to Write Enable High 60 ns

(1)

Address Valid to Write Enable Low 0 ns
UBS, LBS Valid to End of Write 60 ns
Input Valid to Write Enable High 30 ns

(2)

Chip Enable High to Address Transition 0 ns

(3)

Chip Select to End of Write 60 ns

(2)

Write Enable High to Address Transition 0 ns
Write Enable High to Input Transition 0 ns
Write Enable High to Output Transition 10 ns

Write Enable Low to Output Hi-Z 25 ns

(4)

Write Enable Pulse Width 50 ns

) of Low ES and Low WS. A write begins when ES goes Low and WS goes Low w it h as se rti ng

WP

goes High an d WS goes High. The tWP is measured from the beginning o f wr ite to the end of write.

SRAM

Unit70

Min Max

Figure 24. SRAM Low V

V

42/52

DDS

ES

1.65 V

V

DR

≥

1.0 V

Data Retention AC Waveforms, ES Controlled

DDS

tCDR

ES ≥ V

DDS

– 0.2V

tRDATA RETENTION MODE

AI07325

M36DR432AD, M36DR432BD

Table 25. SRAM Low V

Data Retention Characteristics

DDS

(1, 2)

Symbol Parameter Test Condition Min Typical Max Unit

V

I

DDDR

V

t

CDR

Note: 1. All other Inputs VIH ≤ V

Supply Current (Data Retention)

Supply Voltage (Data Retention)

DR

Chip Disable to Data Retention
Time

t

Operation Recovery Time

R

2. Sampled only. Not 100% tested.

– 0.2V or VIL ≤ 0.2V.

DDS

= 1.0V, ES ≥ V

DDS

no input may exceed V

ES

≥ V

DDS

≥ V

ES

DDS

DDS

DDS

– 0.2V

– 0.2V

– 0.2V

+ 2V

0.5 10 µA

1 2.2 V

0ns

t

RC

ns

43/52

M36DR432AD, M36DR432B D

PACKAGE MECHANICAL

Figure 25. Stacked LFBGA 12x8mm - 8x8 ball array, 0.8mm pitch, Bottom View Package Outline

D
D2
D1

E

E1

Note: Drawing is not to scale.

SE

BALL "A1"

A

FDFE

SD

e

b

e

ddd

A2

A1

BGA-Z12

Table 26. Stacked LFBGA 12x8mm - 8x8 ball array, 0.8mm pitch, Packag e Mec han ical Data

Symbol

Typ Min Max Typ Min Max

A 1.400 0.0551
A1 0.250 0.0098
A2 1.100 0.0433

b 0 .400 0.350 0.45 0 0.0157 0.0 138 0.0177

D 12.000 – – 0.4724 – –

D1 5.600 – – 0.2205 – –
D2 8.800 – – 0.3465 – –

ddd 0.100 0.0039

E 8.000 – – 0.3150 – –
E1 5.600 – – 0.2205 – –

e 0 .800 – – 0.0315 – –

FD 1.600 – – 0.0630 – –

FE 1.200 – – 0.0472 – –

SD 0.400 – – 0.0157 – –
SE 0.400 – – 0.0157 – –

millimeters inches

44/52

M36DR432AD, M36DR432BD

PART NUMBERING

Table 27. Ordering Information Scheme

Example: M36 D R 4 32A D 10 ZA 6 T

Device Type

M36 = MMP (Flash + SRAM)

Architecture

D = Dual Bank, Page Mode

Operating Voltage

R = V

SRAM Chip Size & Organization

4 = 4 Mbit (256Kb x 16 bit)

Flash Specification Details

32A = 32 Mbit (x16), Dual Bank: 1/8-7/8 partitioning, Top Configuration
32B = 32 Mbit (x16), Dual Bank: 1/8-7/8 partitioning, Bottom Configuration

SRAM Specification Details

D = Asynchronous SRAM, 0.16µm, 70ns speed

DDF

= V

= 1.65V to 2.2V

DDS

Speed

85 = 85ns (to be characterized)
10 = 100ns
12 = 120ns

Package

ZA = LFBGA66: 0.8mm pitch

Temperature Range

6 = –40 to 85°C

Option

T = Tape & Reel packing

Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available op­tions (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST­Microelectronics Sales Office nearest to you.

45/52

M36DR432AD, M36DR432B D

APPENDIX A. BLOCK ADDRESSES

Table 28. Bank A, Top Boot Block Addresses M36DR432AD

#

14 4 1FF000h-1FFFFFh
13 4 1FE000h-1FEFFFh
12 4 1FD000h-1FDFFFh
11 4 1FC000h-1FCFFFh
10 4 1FB000h-1FBFFFh

9 4 1FA000h-1FAFFFh
8 4 1F9000h-1F9FFFh
7 4 1F8000h-1F8FFFh
6 32 1F0000h-1F7FFFh
5 32 1E8000h-1EFFFFh
4 32 1E0000h-1E7FFFh
3 32 1D8000h-1DFFFFh
2 32 1D0000h-1D7FFFh
1 32 1C8000h-1CFFFFh
0 32 1C0000h-1C7FFFh

Size

(KWord)

Address Range

Table 29. Bank B, Top Boot Block Addresses M36DR432AD

#

55 32 1B8000h-1BFFFFh
54 32 1B0000h-1B7FFFh
53 32 1A8000h-1AFFFFh
52 32 1A0000h-1A7FFFh
51 32 198000h-19FFFFh
50 32 190000h-197FFFh
49 32 188000h-18FFFFh
48 32 180000h-187FFFh
47 32 178000h-17FFFFh
46 32 170000h-177FFFh
45 32 168000h-16FFFFh
44 32 160000h-167FFFh
43 32 158000h-15FFFFh
42 32 150000h-157FFFh
41 32 148000h-14FFFFh
40 32 140000h-147FFFh
39 32 138000h-13FFFFh

Size

(KWord)

Address Range

38 32 130000h-137FFFh
37 32 128000h-12FFFFh
36 32 120000h-127FFFh
35 32 118000h-11FFFFh
34 32 110000h-117FFFh
33 32 108000h-10FFFFh
32 32 100000h-107FFFh
31 32 0F8000h-0FFFFFh
30 32 0F0000h-0F7FFFh
29 32 0E8000h-0EFFFFh
28 32 0E0000h-0E7FFFh
27 32 0D8000h-0DFFFFh
26 32 0D0000h-0D7FFFh
25 32 0C8000h-0CFFFFh
24 32 0C0000h-0C7FFFh
23 32 0B8000h-0BFFFFh
22 32 0B0000h-0B7FFFh
21 32 0A8000h-0AFFFFh
20 32 0A0000h-0A7FFFh
19 32 098000h-09FFFFh
18 32 090000h-097FFFh
17 32 088000h-08FFFFh
16 32 080000h-087FFFh
15 32 078000h-07FFFFh
14 32 070000h-077FFFh
13 32 068000h-06FFFFh
12 32 060000h-067FFFh
11 32 058000h-05FFFFh
10 32 050000h-057FFFh

9 32 048000h-04FFFFh
8 32 040000h-047FFFh
7 32 038000h-03FFFFh
6 32 030000h-037FFFh
5 32 028000h-02FFFFh
4 32 020000h-027FFFh
3 32 018000h-01FFFFh
2 32 010000h-017FFFh
1 32 008000h-00FFFFh
0 32 000000h-007FFFh

46/52

M36DR432AD, M36DR432BD

Table 30. Bank B, Bottom Boot Block Addresses M36DR432BD

#

55 32 1F8000h-1FFFFFh
54 32 1F0000h-1F7FFFh
53 32 1E8000h-1EFFFFh
52 32 1E0000h-1E7FFFh
51 32 1D8000h-1DFFFFh
50 32 1D0000h-1D7FFFh
49 32 1C8000h-1CFFFFh
48 32 1C0000h-1C7FFFh
47 32 1B8000h-1BFFFFh
46 32 1B0000h-1B7FFFh
45 32 1A8000h-1AFFFFh
44 32 1A0000h-1A7FFFh
43 32 198000h-19FFFFh
42 32 190000h-197FFFh
41 32 188000h-18FFFFh
40 32 180000h-187FFFh
39 32 178000h-17FFFFh
38 32 170000h-177FFFh
37 32 168000h-16FFFFh
36 32 160000h-167FFFh
35 32 158000h-15FFFFh
34 32 150000h-157FFFh
33 32 148000h-14FFFFh
32 32 140000h-147FFFh
31 32 138000h-13FFFFh
30 32 130000h-137FFFh
29 32 128000h-12FFFFh
28 32 120000h-127FFFh
27 32 118000h-11FFFFh
26 32 110000h-117FFFh
25 32 108000h-10FFFFh
24 32 100000h-107FFFh
23 32 0F8000h-0FFFFFh
22 32 0F0000h-0F7FFFh
21 32 0E8000h-0EFFFFh
20 32 0E0000h-0E7FFFh
19 32 0D8000h-0DFFFFh

Size

(KWord)

Address Range

18 32 0D0000h-0D7FFFh
17 32 0C8000h-0CFFFFh
16 32 0C0000h-0C7FFFh
15 32 0B8000h-0BFFFFh
14 32 0B0000h-0B7FFFh
13 32 0A8000h-0AFFFFh
12 32 0A0000h-0A7FFFh
11 32 098000h-09FFFFh
10 32 090000h-097FFFh

9 32 088000h-08FFFFh
8 32 080000h-087FFFh
7 32 078000h-07FFFFh
6 32 070000h-077FFFh
5 32 068000h-06FFFFh
4 32 060000h-067FFFh
3 32 058000h-05FFFFh
2 32 050000h-057FFFh
1 32 048000h-04FFFFh
0 32 040000h-047FFFh

Table 31. Bank A, Bottom Boot Block Addresses M36DR432BD

#

14 32 038000h-03FFFFh
13 32 030000h-037FFFh
12 32 028000h-02FFFFh
11 32 020000h-027FFFh
10 32 018000h-01FFFFh

9 32 010000h-017FFFh
8 32 008000h-00FFFFh
7 4 007000h-007FFFh
6 4 006000h-006FFFh
5 4 005000h-005FFFh
4 4 004000h-004FFFh
3 4 003000h-003FFFh
2 4 002000h-002FFFh
1 4 001000h-001FFFh
0 4 000000h-000FFFh

Size

(KWord)

Address Range

47/52

M36DR432AD, M36DR432B D

APPENDIX B. COMMON FLASH INTERFACE

The Common Flash Interface is a JEDEC ap­proved, standardized data structure that can be
read from the Flash memory device. It allows a
system software to query the device to determi ne
various electrical and t iming parameters, density
information and functions supported by the mem­ory. The system can interface easily with the de­vice, enabling the software to upgrade itself when
necessary.

When the Read CFI Query Command is issued
the device enters CFI Query mode and the data

Table 32. Query Structure Overview

Offset Sub-section Name Description

00h Reserved Reserved for algorithm-specific information
10h CFI Query Identification String Command set ID and algorithm data offset
1Bh System Interface Information Device timing & voltage information
27h Device Geometry Definition Flash device layout

P Primary Algorithm-specific Extended Query table

A Alternate Algorithm-specific Extended Query table

structure is read from the memory. Tables 32 , 33,
34 and 35 show the address used to retrieve each
data. The Query data is always presented on the
lowest order data outputs (DQ0-DQ7), the other
outputs (DQ8-DQ15) are set to 0.

The CFI data structure contains also a security
area starting at address 81h. This area can be ac­cessed only in read mode and it is impossible to
change after it has been written by ST. Issue a
Read command to return to Read mode.

Additional information specific to the Primary
Algorithm (optional)

Additional information specific to the Alternate
Algorithm (optional)

Table 33. CFI Query Identification String

Offset Data Description

00h 0020h Manufacturer Code

01h

02h-0Fh reserved Reserved

10h 0051h Query Unique ASCII String "QRY"
11h 0052h Query Unique ASCII String "QRY"
12h 0059h Query Unique ASCII String "QRY"
13h 0002h
14h 0000h
15h offset = P = 0040h
16h 0000h
17h 0000h
18h 0000h
19h value = A = 0000h

1Ah 0000h

00A1h - bottom

00A0h - top

Device Code

Primary Algorithm Command Set and Control Interface ID code 16 bit ID code
defining a specific algorithm

Address for Primary Algorithm extended Query table

Alternate V endor Command Set and Control Interface ID Code second vendor

- specified algorithm supported (note: 0000h means none exists)

Address for Alternate Algorithm extended Query table
note: 0000h means none exists

48/52

Table 34. CFI Query System Interface Information

Offset Data Desc ription

V

Logic Supply Minimum Program/Erase or Write voltage

1Bh 0017h

1Ch 0022h

1Dh 0000h

1Eh 00C0h

1Fh 0004h

20h 0003h

21h 000Ah

22h 0000h

23h 0003h

24h 0004h

25h 0002h

26h 0000h

DDF

bit 7 to 4 BCD value in volts
bit 3 to 0 BCD value in 100 millivolts

V

Logic Supply Maximum Program/Erase or Write voltage

DDF

bit 7 to 4 BCD value in volts
bit 3 to 0 BCD value in 100 millivolts

V

[Programming] Supply Minimum Program/Erase voltage

PPF

bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 millivolts
Note: This value must be 0000h if no V

V

[Programming] Supply Maximum Program/Erase voltage

PPF

bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 millivolts
Note: This value must be 0000h if no V

Typical timeout per single byte/word program (multi-byte program count = 1), 2

(if supported; 0000h = not supported)
Typical timeout for maximum-size multi-byte program or page write, 2

(if supported; 0000h = not supported)

n

Typical timeout per individual block erase, 2

ms

(if supported; 0000h = not supported)

n

Typical timeout for full chip erase, 2

ms

(if supported; 0000h = not supported)

n

Maximum timeout for byte/word program, 2

times typical (offset 1Fh)

(0000h = not supported)
Maximum timeout for multi-byte program or page write, 2

(0000h = not supported)
Maximum timeout per individual block erase, 2

(0000h = not supported)

n

Maximum timeout for chip erase, 2

times typical (offset 22h)

(0000h = not supported)

M36DR432AD, M36DR432BD

pin is present

PPF

pin is present

PPF

n

times typical (offset 20h)

n

times typical (offset 21h)

n

µs

n

µs

49/52

M36DR432AD, M36DR432B D

Table 35. Device Geometry Definition

Offset Word

Mode

27h 00 16h
28h 0001h

29h 0000h
2Ah 0000h
2Bh 0000h
2Ch 0002h Number of Erase Block Regions within device

M36DR432AD M36DR432AD Erase Block Region Information

2Dh 003Eh
2Eh 0000h
2Fh 0000h

30h 0001h

31h 0007h

32h 0000h

33h 0020h

34h 0000h

M36DR432AD M36DR432AD

2Dh 0007h
2Eh 0000h
2Fh 0020h

30h 0000h

31h 003Eh

32h 0000h

33h 0000h

34h 0001h

Data Descr iption

n

Device Size = 2
Flash Device Interface Code description: Asynchronous x16

Maximum number of bytes in multi-byte program or page = 2

bit 7 to 0 = x = number of Erase Block Regions
Note:1. x = 0 means no erase blocking, i.e. the device erases at once in "bulk."

2. x speci fies the numb er of regions w ithin the devi ce containin g one or more
contiguous Era se Bl ocks of th e sam e siz e. For e xample, a 128K B de vice
(1Mb) having blocking of 16KB, 8KB, four 2KB, two 16KB, and one 64KB is
considered to have 5 E rase Bl ock Re gions . Even thou gh two region s both
contain 16 KB block s, the fa ct that t hey are not contig uous me ans they are
separate Erase Block Regions.

3. By definition, symmetrically block devices have only one blocking region.

bit 31 to 16 = z, where the Erase Block(s) within this Region are (z) times 256 bytes
in size. The value z = 0 is used for 128 byte block size.
e.g. for 64KB block size, z = 0100h = 256 => 256 * 256 = 64K

bit 15 to 0 = y , where y+1 = Number of Erase Blocks of identical size within the Erase
Block Region:
e.g. y = D15-D0 = FFFFh => y+1 = 64K blocks [maximum number]

y = 0 means no blocking (# blocks = y+1 = "1 block")

Note: y = 0 value must be used with number of block regions of one as indicated

by (x) = 0

in number of bytes

n

50/52

M36DR432AD, M36DR432BD

REVISION HIST ORY

Table 36. Document Revision History

Date Version Revision Details

15-Jan-2003 1.0 First issue.
15-Jan-2003 1.1 Bottom Device Code corrected on page 1.
25-Feb-2003 2.0 Document promoted from Preliminary Data to full Datasheet status.

signal removed from datasheet. SRAM Input Rise and Fall Times added to,

V

DDQF

28-Feb-2003 2.1

and V
Measurement Conditions. V

DDF

and V

parameters differentiated in Table 14, Operating and AC

DDS

added to the SIGNAL DESCRIPTIONS section.

DDS

51/52

M36DR432AD, M36DR432B D

Information furnished is believed to be ac curate and reliable. Howev er, STMicroelectronics assumes no responsibility for t he consequ ences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or otherwise u nder any patent or pat ent rights of STMicroelectron i cs. Specific ations mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as cri t i cal compone nt s i n l i f e support devi ces or systems wi thout express written approval of STM i croelect ronics.

The ST log o i s registered trademark of STMicroel ectronics
All other nam es are the pro perty of their respective owners

© 2003 STMicroelectronics - All Rights Reserved

STMicroelectron ics group of com panies

India - Israel - Italy - J apan - Malays i a - M al ta - Morocco - Singapore - Spain - Sweden - Switz erl and - United Kingdom - Uni ted States.

Austra lia - Brazil - Can ada - China - Finl and - France - Germany - Hon g Kong -

www.st.com

52/52