Page 1
查询M36D0R6040B0ZAI供应商
64 Mbit (4Mb x16, Multiple Bank, Page) Flash Memory
and 16 Mbit (1Mb x16) PSRAM, Multi-Chip Package
FEATURES SUMMARY
■ MULTI-CHIP PACKAGE
– 1 die of 64 Mbit (4Mb x 16) Flash Memory
– 1 die of 16 Mbit (1Mb x 16) Pseudo SRAM
■ SUPPLY VOLTAGE
DDF
= V
–V
■ LOW POWER CONSUMPTION
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code (Top Flash Configuration),
M36D0R6040T0: 8810h
– Device Code (Bottom Flas h
Configuration), M36D0R6040B0: 8811h
■ PACKAGE
– Compliant with Lead-Free Soldering
Processes
– Lead-Free Versions
FLASH MEMORY
■ PROGRAMMING TIME
– 8µs by Word typical for Fast Factory
Program
– Double/Quadruple Word Program option
– Enhanced Factory Program options
■ MEMORY BLOCKS
– Multiple Bank Memory Array: 4 Mbit
Banks
– Parameter Blocks (Top location)
■ ASYNCHRONOUS READ
– Asynchronous Page Read mode
– Random Access: 70ns
■ DUAL OPERATIONS
– Program Eras e in one Bank wh ile Rea d in
others
– No delay between Read and Write
operations
■ BLOCK LOCKING
– All blocks lock ed at Powe r-up
– Any combination of blocks can be locked
–WP
for Block Lock-Down
F
= 1.7V to 1.95V
DDP
M36D0R6040T0
M36D0R6040B0
Figure 1. Package
FBGA
Stacked TFBGA67 (ZAI)
12 x 8mm
■ SECURITY
– 128-bit user programmable OTP cells
– 64-bit unique device number
■ COMMON FLASH INTERFACE (CFI)
■ 100,000 PROGRAM/ERASE CYCLES per
BLOCK
PSRAM
■ ACCESS TIME: 70ns
■ LOW STANDBY CURRENT: 110µA
■ DEEP POWER DOWN CURRENT: 10µA
1/18December 2004
Page 2
M36D0R6040T0, M36D0R6040B0
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Address Inputs (A0-A19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Address Inputs (A20-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Chip Enable (E
Flash Output Enable (G
Flash Write Enable (W
Flash Write Protect (WP
Flash Reset (RP
PSRAM Chip Enable (E1
PSRAM Chip Enable (E2
PSRAM Output Enable (G
PSRAM Write Enable (W
PSRAM Upper Byte Enable (UB
PSRAM Lower Byte Enable (LB
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
V
DDF
V
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DDP
Program Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
V
PPF
V
Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SS
).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
F
).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
F
).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
F
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
F
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
F
).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
P
).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
P
).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
P
).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
P
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
P
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
P
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Main Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
FLASH MEMORY COMPONENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PSRAM COMPONENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/18
Page 3
M36D0R6040T0, M36D0R6040B0
Table 5. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 6. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 7. Flash Memory DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 8. Flash Memory DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 9. PSRAM DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. Stacked TFBGA67 12x8mm - 8x8 active ball array, 0.8mm pitch, Package Outline . . . 15
Table 10. Stacked TFBGA67 12x8mm - 8x8 ball array, 0.8mm pitch, Package Mechanical Data . 15
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 11. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3/18
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M36D0R6040T0, M36D0R6040B0
SUMMARY DESCRIPTION
The M36D0R6040T0 and M 36D0R6040B0 combine two memory devices in a Multi-Chip Package:
a 64-Mbit, Multiple Bank Flash memory, the
M58WR064FT/B, and a 16-Mbit Pseudo SRAM,
the M69AR024B. Recommended operating conditions do not allow more than one memory to be active at the same time.
The memory is offered in a Stacked TFBGA67
(12 x 8mm, 8x8 ball array, 0.8mm pitch) package.
In addition to the stan dard version, the pac kages
are also available in Lead- free version , in comp liance with JEDEC Std J-STD-020 B, the ST ECOPACK 7191395 Specification, and the RoHS
(Restriction of Hazardous Substances) directive.
All packages are c omp lia nt with Le ad- fr ee so ld er ing processes.
The memory is supplied with all the bits erased
(set to ‘1’).
Figure 2. Logic Diagram
V
PPF
A0-A21
E
G
W
RP
V
DDF
22
F
F
F
F
V
DDP
16
DQ0-DQ15
Table 1. Signal Names
A0-A19 Common Address Inputs
DQ0-DQ15 Common Data Input/Output
V
DDF
V
PPF
V
SS
V
DDP
NC Not Connected Internally
Flash Memory Signals
A21-A20
E
F
G
F
W
F
RP
F
WP
F
PSRAM Signals
E1
P
G
P
W
P
E2
P
UB
P
LB
P
Flash Memory Powe r Sup ply
Common Flash Optional Supply
Voltage for Fast Program & Erase
Ground
PSRAM Power Supply
Address Inputs for the Flash memory
only
Chip Enable input
Output Enable input
Write Enable input
Reset input
Write Protect input
Chip Enable input
Output Enable input
Write Enable input
Power-down input
Upper Byte Enable inp ut
Lower Byte Enable inp ut
4/18
WP
E1
E2
UB
LB
G
W
F
P
P
P
P
P
P
M36D0R6040T
M36D0R6040B
V
SS
AI09200
Page 5
Figure 3. TFBGA Connections (Top view through package)
M36D0R6040T0, M36D0R6040B0
AI09201
1211
109876543
NCNC
NC
SSF
V
A12
A13A11A20NC
A15 A14
DQ7
DQ14
P
W
DQ15A9A16
A8 A10
DQ5
DQ4
DQ6DQ13NCW
A21
DDF
V
DDP
V
P
E2
DQ12V
F
RP
DQ3DQ2
DQ10
DQ11A19WP
PPF
V
DQ1DQ0
DQ8
DQ9G
P
P
UB
P
E1
A1
A2A3A6A7A18
A17
NC
NCG
NC
F
SSF
V
F
E
A0A4NCNC
A5
F
21
NC
A
B
C
SSP
D
F
E
LB
F
P
G
NC
H
5/18
Page 6
M36D0R6040T0, M36D0R6040B0
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram and Table 1., Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A19). Addresses A0-A19
are common inputs for the Flash Memory and
PSRAM components. T he Address Inputs select
the cells in the memory array to access during Bus
Read operations. During Bus Write operations
they control the command s sent to the Comma nd
Interface of the Flash memory internal state machine and they select the cells to access in the
PSRAM.
The Flash memory is acce ssed through the Chip
Enable signal (E
) signal, while the PSRAM is accessed
(W
F
through two Chip Enable signals (E1
and the Write Enable signal (W
Address Inputs (A20-A21). Addresses A20-A21
are inputs for the Fl ash Memo ry compon ent only.
The Flash Memory is acce ssed through the Chip
Enable signals (
(W
) signal.
F
Data Input/Output (DQ0-DQ15). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation or inputs a command
or the data to be progra mmed d uring a Write Bus
operation.
Flash Chip Enable (E
puts activate the memory control logics, input buffers, decoders and sense amplifiers. When Chip
Enable is Low, V
vice is in active mode. When Chip Enable is at V
the Flash memory is deselec ted, the outputs are
high impedance and the power consumption is reduced to the standby level.
Flash Output Enable (G
pins control data outputs during Flash memory
Bus Read operations.
Flash Write Enable (
controls the Bus Write operation of the Flash
memories’ Command Int erface. The data an d address inputs are latched on the rising edge of Chip
Enable or Write Enable whichever occurs first.
Flash Write Protect (WP
input that gives an additio nal hardware protection
for each block. When Write Protect is Low, V
Lock-Down is enabled and the protection status of
the Locked-Down blocks cannot be changed.
When Write Protect is a t High, V
disabled and the Locked-Down blocks can be
locked or unlocked. (Refer to Lock Status Table in
M58WR064F(T/B) datasheet).
Flash Reset (RP
hardware reset of the m emory. When Reset is at
V
, the memory is in Reset mode: the outputs are
IL
) and through the Wr ite Enable
F
and E2P)
P
).
P
E
) and through the Writ e Enable
F
). The Chip Enable in-
F
, and Reset is High, VIH, the de-
IL
). The Output Enable
F
W
). The Write Enable
F
). Write Protect is an
F
, Lock-Down is
IH
). The Reset input provides a
F
IH
IL
high impedance and the current consumption is
reduced to the Reset Supply Current I
Table 7.,Flash Memory DC Characteristics - Currents, for the value of I
. After Reset all b locks
DD2
are in the Locked state and the Configuration Register is reset. When Reset is at V
, the device is in
IH
normal operation. Exiti ng Reset mode the devic e
enters Asynchronous Read mode, but a nega tive
transition of Chip Enable or Latch Enable is required to ensure valid data outputs.
The Reset pin can be interfaced with 3V logic without any additional circui try. It can be tied to V
(refer to Table 8., Flash Memory DC Characteris-
tics - Voltages).
PSRAM Chip Enable (E1
(Low), the Chip Enable, E1
). When asserted
P
, activates the memo-
P
ry state machine, address buffers and decod ers,
allowing Read and Write operations to be performed. When de-asserted (High), all other pins
are ignored, and the device is put, automatically, in
low-power Standby mode.
PSRAM Chip Enable (E2
, puts the device i n Deep Power-down mode
E2
P
). The Chip Enable,
P
when it is driven Low. This is the lowest power
mode.
PSRAM Output Enable (G
able, G
, provides a h igh speed tri-state c ontrol,
P
). The Output En-
P
allowing fast read/write cycles to be achieved with
the common I/O data bus.
PSRAM Write Enable (W
W
, controls the Bus Wri te o per ati on of the mem -
P
). The Write Enable,
P
ory’s Command Interface.
PSRAM Upper Byte Enable (UB
Byte Enable, UB
, gates the data on the Upper
P
). The Upper
P
Byte Data Inputs/Outp uts (DQ8-DQ15) t o or from
the upper part of the selected address during a
Write or Read operation.
PSRAM Lower Byte Enable (LB
Byte Enable, LB
, gates the data on the Lower
P
). The Lower
P
Byte Data Inputs/Outputs (DQ0-DQ7) to or from
the lower part of the selected address during a
Write or Read operation.
V
Supply Voltage. V
DDF
provides the power
DDF
supply to the internal core of the Flash memory
component. It is the main power supplies for all
Flash memory operations (Read, Program and
,
Erase).
V
Supply Voltage. The V
DDP
Supply Volt-
DDP
age supplies the power for all operations (Read or
Write) and for driving the refresh logic, even when
the device is not being accessed.
V
Program Supply Voltage. V
PPF
PPF
Flash Memory control input and a Flash Mem ory
power supply pin. The two functions are selected
by the voltage range applied to the pin.
. Refer to
DD2
is both a
RPH
6/18
Page 7
M36D0R6040T0, M36D0R6040B0
If V
V
age lower than V
tion against Program or Erase, while V
is kept in a low voltage range (0V to V
PPF
is seen as a control input. In this case a volt-
PPF
gives an absolute pro tec-
PPLKF
PPF
> V
DDF
PP1F
enables these functions (see Tables 7 an d 8, DC
Characteristics for the relevant values). V
PPF
is
only sampled at the beginning of a Program or
Erase; a change in its value after the operation has
started does not have any effec t and Program or
Erase operations continue.
If V
supply pin. In th is condition V
is in the range of V
PPF
it acts as a power
PPHF
must be stable
PPF
until the Program/Erase algorithm is completed.
V
)
Ground. VSS is the common ground refer-
SS
ence for all voltage measurements in the Flash
(core and I/O Buffers) and PSRAM chips.
Note: Each Flash memory device in a system
should have its supply voltage (V
program supply voltage V
PPF
DDF
decoupled with a
0.1µF ceramic capacitor close to the pin (high
frequency, inherently low inductance capacitors should be as close as possible to the
package). See Table 5., AC Measurement Load
Circuit. The PCB track widths should be suffi-
cient to carry the requ ired V
program and
PPF
erase currents.
) and the
7/18
Page 8
M36D0R6040T0, M36D0R6040B0
FUNCTIONAL DESCRIPTION
The Flash memory and PSRAM components have
separate power supplies but share the same
grounds. They are distinguished by three Chip Enable inputs: E
for the PSRAM.
E2
P
Recommended operating conditions do not allow
more than one device to be ac tive at a time. The
Figure 4. Functional Block Diagram
for the Flash memory and E1P and
F
most common example is simultaneous read operations on the Flash memory and the PSRAM,
which would result in a data bus contention.
Therefore it is recomme nded to put the ot her devices in the high imp edance state when reading
the selected device.
A20-A21
A0-A19
E
F
G
W
RP
WP
DDF
V
PPF
V
64 Mbit
F
Flash
Memory
F
F
F
V
DDP
DQ0-DQ15
8/18
E1
G
W
E2
UB
LB
P
P
P
P
P
P
16 Mbit
PSRAM
V
SS
AI09204
Page 9
M36D0R6040T0, M36D0R6040B0
Table 2. Main Operating modes
E
Operation
Flash Read
Flash Write
Flash Address
Latch
Flash Output
Disable
Flash Standby
Flash Reset X X X X
GPWPLFRP
F
V
ILVILVIHVIL(2)VIH
V
ILVIHVILVIL(2)VIH
V
V
X
IL
V
ILVIHVIH
V
XX X
IH
V
IH
IL
X
F
V
IH
V
IH
V
IH
V
IL
PSRAM Read
Flash Memory must be disabled
PSRAM Write
Output Disable
PSRAM
Standby
Any Flash mode is allowed.
PSRAM Deep
Power-Down
Note: 1. X = Don't care.
2. L
can be tied to VIH if the valid address has been previous ly latched.
F
3. Depends on G
4. WAIT signal polarity is configured using the Set Conf igurat ion Regist er command. Refer to M58WR064 F(T/B) dat asheet for det ails.
.
F
(4)
WAIT
E1PE2PGPWPUBPLB
F
P
DQ15-DQ0
Flash Data Out
PSRAM must be disab led
Flash Data In
Flash Dat a Out
or Hi-Z
Flash Hi-Z
Hi-Z Flash Hi-Z
Any PSRAM mode is allowed
Hi-Z Flash Hi-Z
V
ILVIHVILVIHVILVIL
V
ILVIHVIHVIL
V
ILVIHVIHVIH
V
IHVIH
X
X X X X PSRAM Hi- Z
V
X X X X PSRAM Hi- Z
IL
VILV
X X PSRA M Hi- Z
PSRAM data
PSRAM data in
IL
(3)
out
9/18
Page 10
M36D0R6040T0, M36D0R6040B0
FLASH MEM O RY CO MP O N EN T
The M36D0R6040T0 and M36D0R6040B0 contain a 64Mbit Flas h memory, the M58WR064F(T/
B). The burst mode of t his device is not avail able
in the M36D0R6040(T/B).
PSRAM COMPONENT
The M36D0R6040T0 and M36D0R6040B0 contain a 16Mbit PSRAM. For detailed information on
how to use it, see the M69AR024B datasheet
For detailed information on how to use the Flash
memory, see the M58WR064F(T/B) datasheet
which is available from your local STMicroelectronics distributor.
which is available from the internet site
www.st.com
distributor.
or from your lo cal ST Micro elect ronics
http://
10/18
Page 11
M36D0R6040T0, M36D0R6040B0
MAXIMUM RATING
Stressing the device above the ra ting l isted in the
Absolute Maximum Ratin gs table ma y cause per manent damage to the device. Thes e are stress
ratings only and operation of the device at these or
any other conditions abo ve those indica ted in the
Operating sections of this specification is not im-
Table 3. Absolute Maximum Ratings
Symbol Parameter
T
A
T
BIAS
T
STG
T
LEAD
V
IO
V
DDF
V
DDP
V
PPF
I
O
t
VPPFH
Note: 1. V
DDF
2. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK
and the European directive on Restr i ctions on Hazardous Substances (RoHS) 2002/95/EU.
Ambient Operating Temperature –30 85 °C
Temperature Under Bias –40 125 °C
Storage Te mp era tu re –65 155 °C
Lead Temperature during Soldering
Input or Output Voltage –0.5
Flash Memory Core Supply Voltage –0.2 2.45 V
PSRAM Supply Voltage –0.2 3.3 V
Flash Memory Program Voltage –0.2 14 V
Output Short Circuit Current 100 mA
= V
Time for V
= VDD.
DDP
PPF
at V
PPFH
plied. Exposu re to Abso lute Max imum Rati ng conditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and o ther relevant quality documents.
Value
Min Max
(1)
(1)
V
+0.6
DD
100 hours
®
7191395 specification,
Unit
°C
V
11/18
Page 12
M36D0R6040T0, M36D0R6040B0
DC AND AC PARAMETERS
This section summ arizes the operating measurement conditions, and th e DC and AC c haracteris tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Table 4. Operating and AC Measurement Conditions
Parameter
Supply Voltage
V
DDF
V
Supply Voltage
DDP
V
Supply Voltage (Factory environment)
PPF
V
Supply Voltage (Application environment)
PPF
Ambient Operating Temperature –40 85 –30 85 °C
Conditions summarized in Table 4., Operating and
AC Measurement Conditions. Designers should
check that the operating conditi ons in their circuit
match the operating conditions when relying on
the quoted parameters.
Flash Memory PSRAM
Min Max Min Max
1.7 1.95 – – V
––1.71.95V
11.4 12.6 – – V
V
–0.4
DDF
+0.4
––V
Unit
Load Capacitance (C
)
L
30 50 pF
Input Rise and Fall Times 5 ns
DDP
(1)
(1)
= VDD.
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Note: 1. V
DDF
= V
Figure 5. AC Measurement I/O Waveform
V
DD
VDD/2
0V
Note: V
DDF
= V
DDP
= VDD.
AI09202
0 to V
DD
0 to V
DD
VDD/2 VDD/2
Table 5. AC Measurement Load Circuit
V
DD
V
DDF
16.7kΩ
DEVICE
UNDER
TEST
0.1µF
Note: V
DDF
includes JIG capacitance
C
L
= V
= VDD.
DDP
CL
16.7kΩ
I09203
V
V
Table 6. Device Capacitance
Symbol Parameter Test Condition Min Max Unit
C
IN
C
OUT
Note: Sampled only, not 100% tested.
Input Capacitance
Output Capacitance
12/18
V
V
OUT
IN
= 0V
= 0V
12 pF
15 pF
Page 13
M36D0R6040T0, M36D0R6040B0
Table 7. Flash Memory DC Characteristics - Currents
Symbol Parameter Test Condition Min Typ Max Unit
I
Input Leakage Current
LI
I
I
DD1
I
DD2
I
DD3
I
DD4
Output Leakage Curr en t
LO
Supply Current
Asynchronous Read (f=6MHz)
Supply Current
(Reset)
Supply Current (Standby)
Supply Current (Automatic
Standby)
Supply Current (Prog ram )
(1)
I
DD5
Supply Current (Erase )
Supply Current
(1,2)
I
DD6
I
DD7
I
PP1
I
PP2
I
PP3
Note: 1. Sampled only, not 100% tested.
(Dual Operations)
Supply Current Progr am / Eras e
(1)
Suspended (Standby)
V
Supply Current (Progr am )
PPF
(1)
Supply Current (Erase )
V
PPF
V
Supply Current (Read ) V
PPF
(1)
V
Supply Current (Standby) V
PPF
2. V
Dual Operation current is the sum of read and program or erase currents.
DDF
0V ≤ V
0V ≤ V
E
F
RP
E
E
F
≤ V
IN
≤ V
OUT
= VIL, GF = V
= V
SSF
DDF
± 0.2V
± 0.2 V
F
= V
F
= VIL, GF = V
V
= V
PPF
PPH
V
= V
PPF
DDF
= V
V
PPF
PPH
V
= V
PPF
DDF
DDF
DDF
IH
IH
Program/Erase in one
Bank, Asynchronous
Read in another Bank
= V
E
F
V
V
V
V
PPF
PPF
PPF
PPF
PPF
PPF
DDF
= V
= V
= V
= V
≤ V
≤ V
± 0.2 V
PPH
DDF
PPH
DDF
DDF
DDF
±1 µA
±1 µA
36mA
10 50 µA
10 50 µA
10 50 µA
815mA
10 20 mA
815mA
10 20 mA
13 26 mA
10 50 µA
25mA
0.2 5 µA
25mA
0.2 5 µA
0.2 5 µA
0.2 5 µA
Table 8. Flash Memory DC Characteristics - Voltages
Symbol Parameter Test Condition Min Typ Max Unit
V
V
V
V
V
V
V
V
V
PPLK
Input Low Voltage –0.5 0.4 V
IL
V
Input High Voltage
IH
Output Low Voltage
OL
Output High Voltage
OH
V
PP1
PPH
PPF
V
PPF
Program Voltage-Logic
Program Voltage Factory
I
= 100µA
OL
I
= –100µA V
OH
Program, Erase 1 1.8 3.3 V
Program, Erase 11.4 12 12.6 V
–0.4 V
DDF
–0.1
DDF
Program or Erase Lockout 0.4 V
V
LKO
RPH
Lock Voltage
DDF
RPF pin Extended High Voltage
1V
+ 0.4
DDF
0.1 V
3.3 V
V
V
13/18
Page 14
M36D0R6040T0, M36D0R6040B0
Table 9. PSRAM DC Characteristics
Symbol Parameter Test Condition Min Max Unit
Read /
t
DDP
DDP
– 0.2V,
AVAV
t
Write =
AVAV
minimum
t
Read /
AVAV
t
Write =
AVAV
maximum
20 mA
3mA
–1 1 µA
–1 1 µA
10 µ A
110 µA
V
+
0.8V
DDP
DDP
– 0.2
DDP
0.2
0.2 V
DDP
by 1.0V for pe r i od s
SS
by 1.0V for
I
CC1
VCC Active Current
I
CC2
I
Input Leakage Current
LI
I
I
I
V
IH
V
IL
V
V
Note: 1. The maximum DC voltage on input and I/O pins is V
Output Leakage Curr en t
LO
Deep Power Down Cur r en t
PD
Standby Supply Current
SB
CMOS
(1)
Input High Voltage
(2)
Input Low Voltage –0.3 0.4 V
Output High Voltage
OH
Output Low Voltage
OL
periods of up to 5ns.
2. The minimum DC voltage on input or I/O pins is –0.3V. During voltage transitions, inputs may undershoot V
of up to 5ns.
E1
P
= 1.95V,
V
DDP
VIN = VIH or VIL,
= VIL and E2P = VIH,
I
= 0mA
OUT
E1P ≥ V
V
≥ V
IN
E1
P
DDP
0V ≤ V
0V
DDP
DDP
= E2P ≥ V
≤ V
IN
≤ V
≤ V
OUT
V
= 1.95V,
DDP
– 0.2V or E1P ≤ VIL,
– 0.2V or VIN ≤ 0.2V
= 1.95V,
V
DDP
DDP
I
= 0mA
OUT
I
= –0.5mA V
OH
I
= 1mA
OL
+0.2V. During voltage transitions, inputs may overshoot V
V
V
14/18
Page 15
M36D0R6040T0, M36D0R6040B0
PACKAGE MECHANICAL
Figure 6. Stacked TFBGA67 12x8mm - 8x8 active ball array, 0.8mm pitch, Package Outline
D
D2
D1
E1
E
FE
Note: Drawing is not to scale.
SE
BALL "A1"
FD1
FD
A
SD
e
b
e
ddd
A2
A1
BGA-Z41
Table 10. Stacked TFBGA67 12x8mm - 8x8 ball array, 0.8mm pitch, Package Mechanical Data
Symbol
Typ Min Max Typ Min Max
Symbol Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.200 0.0079
A2 0.810 0.0319
b 0.400 0.350 0.450 0.0157 0.0138 0.0177
D 12.000 11.900 12.100 0.4724 0.4685 0.4764
D1 5.600 – – 0.2205 – –
D2 8.800 – – 0.3465 – –
ddd 0.100 0.0039
E 8.000 7.900 8.100 0.3150 0.3110 0.3189
E1 5.600 – – 0.2205 – –
e 0.800 – – 0.0315 – –
FD 3.200 – – 0.1260 – –
FD1 1.600 – – 0.0630 – –
FE 1.200 – – 0.0472 – –
SD 0.400 – – 0.0157 – –
SE 0.400 – – 0.0157 – –
millimeters inches
15/18
Page 16
M36D0R6040T0, M36D0R6040B0
PART NUMBERING
Table 11. Ordering Information Scheme
Example: M36 D0 R 6 0 4 0 T 0 ZAI T
Device Type
M36 = Multi-Chip Package (Flash + RAM)
Flash 1 Architecture
D = Multiple Bank, Page mode
Flash 2 Architecture
0 = none present
Operating Voltage
R = V
Flash 1 Density
6 = 64 Mbit
Flash 2 Density
0 = none present
DDF
= V
= 1.7V to 1.95V
DDP
RAM 1 Density
4 = 16 Mbit
RAM 0 Density
0 = none present
Parameter Blocks Location
T = Top Boot Block Flash
B = Bottom Boot Block Flash
Product Version
0 = 0.13µm Flash technology, 70ns;
0.18µm RAM, 70ns speed
Package
ZAI = Stacked TFBGA67 12 x 8mm - 8x8 active ball array, 0.8mm pitch
Option
Blank = Standard Packing
T = Tape & Reel Packing
E = Lead-Free and RoHS Package, Standard Packing
F = Lead-Free and RoHS Package, Tape & Reel Packing
Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
16/18
Page 17
REVISION HISTORY
Table 12. Document Revision History
Date Version Revision Details
26-Nov-2003 1.0 First Issue
Document status promoted from Target Specification to full Datasheet.
07-Dec-2003 2.0
TFBGA67 package fully compliant with the ST ECOPACK specification.
Flash memory and PSRAM data updated to the revision 5.0 of the M58WR064F(T/B)
datasheet and to the revision 6.0 of the M69AR024B datasheet.
M36D0R6040T0, M36D0R6040B0
17/18
Page 18
M36D0R6040T0, M36D0R6040B0
Information furnished is be lieved to be a ccur ate and reli able. Howe ver, STMicroele ctronic s assu mes no r esponsib ilit y for th e consequences
of use of such information nor for any infrin gement of patent s or other rights of third parties which ma y result from it s use. No license is granted
by implication or otherwi se under any patent or patent rights of STMicroelectronics. Specifications mentioned i n this publication are s ubject
to change without not ice. This pub licat ion su persed es and repl aces all in format ion previou sly su pplie d. STMicroele c tronic s prod ucts ar e no t
authorized for use as critical compone nts in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
ECOPACK is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
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18/18
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