Page 1
MITSUBISHI LINEAR IC’s
M35502AFP
FLD CONTROLLER
DESCRIPTION/FEATURES
High-breakdown-voltage output port ......................................... 25
•
• Segment output............................................ 8 to 20
• Digit output................................................... 5 to 16
(Ports P0 to P2 are also used as normal output ports)
• Output breakdown..................................Vcc – 45 V
• Output current ............... –18 mA (at DIG selecting),
–7 mA (at SEG selecting)
• Pull-down resistor .........................................built-in
• Dimmer switch ............................................ 4 levels
A-D converter ................................................... 8-bit ✕ 4 channels
•
• Absolute accuracy....................................... ±3 LSB
PIN CONFIGURATION (TOP VIEW)
FLD0
FLD1
FLD2
FLD3
FLD4
FLD5
Serial I/O ..................................... 3 (CS controller, external clock)
•
• Noise filter.....................................................built-in
(in serial input pin and clock pin, 2 MHz sampling)
• FLD display data ............................................. input
• A-D conversion data ..................................... output
• Command ....................................................... input
Package ......................................................................... 36P2R-G
•
Oscillation circuit ........... CR oscillation cirucit (external capacitor)
•
• Oscillation frequency.....................................2 MHz
Power source voltage.................................................. 4.0 to 5.5 V
•
FLD6
FLD7
FLD8
FLD9
FLD10
FLD11
FLD12
FLD13
FLD14
FLD15
FLD16
VEE
3635343332313029282726252423222120
M35502AFP
1
2
3
4
5
6
7
8
9
101112131415161718
SDATA
SCLK
CS
3
AN
CC
VSS
AN2
AN1
AN0
OSC
V
FLD24/P0
23/P1
FLD
22/P2
FLD
21
FLD
FLD20
FLD19
FLD18
19
FLD17
Fig.1 Pin configuration of M35502AFP
Package type: 36P2R-G
Page 2
FUNCTIONAL BLOCK
/
MITSUBISHI LINEAR IC’s
M35502AFP
FLD CONTROLLER
V
EE
FLD
16
FLD
17
FLD
18
FLD
19
FLD
20
FLD
21
FLD22/P2
23
/P1
FLD
24
/P0
FLD
19
20
18
17
16
15
14
13
12
11
21
FLD15–FLD
25242322
Memory
address
8
Mode
register
Transfer
counter
FLD7–FLD
282726
0
3635343332313029
Display control circuit
Display RAM
DATA
S
CLK
CS
V
CC
V
SS
1
2
3
10
8
S
Fig.2 Functional block diagram
Noise filter
Noise filter
Clock generating
circuit
9
OSC
Command
analytic circuit
Selector
A-D control circuit
4
567
AN3–AN
Byte end
Serial I/O
Trigger
A-D
0
2
Page 3
h
h
MITSUBISHI LINEAR IC’s
M35502AFP
FLD CONTROLLER
PIN DESCRIPTION
Table 1 Pin description
Pin
VCC, VSS
VEE
OSC
____
CS
SCLK
SDAT A
FLD24/P0 –
FLD22/P2
FLD21–
FLD0
Name
Power source
Pull-down
power source
Clock input
Chip select
Serial clock
Serial input/
output
Digit/Port
Segment/Digit
Input
Input
CMOS input
CMOS input
Noise filter
CMOS input
Noise filter
Output
N-channel
open-drain
P-channel
open-drain
P-channel
open-drain
• Apply voltage of 5 V to VCC, and 0 V to VSS.
• Applies voltage supplied to pull-down resistors.
• Connect an external capacitor to this pin.
• Serial transfer is possible by inputting “L” signal.
• Pull-up resistor is built in.
• Clock for serial transfer is input.
•
Read a clock twice with 2 MHz sampling clock and judge if it is a noise or not.
• Serial data is input/output.
•
In input mode, read a clock twice with 2 MHz sampling clock and judge if it is a
noise or not.
• Pin for ordinary output or digit output.
• At reset this port is set to VEE level through a pull-down resistor.
• Pin for digit output or segment output.
• At reset this port is set to VEE level through a pull-down resistor.
Function
PORT BLOCK
(1) Digit/Port pin
(2) Segmen/Digit pin
Segment/Digit data
✽ High-breakdown-voltage P-channel transistor
Note: Dimmer signal is for setting the Toff time.
Data bus
Digit data
Dimmer signal
(Note)
Latc
Dimmer signal
(Note)
Latc
(3) S
DATA
pin
Serial output
✽
V
EE
Serial input
(4) CS pin
Noise filter
CS input
(5) S
CLK
pin
✽
V
EE
Serial clock input
Noise filter
(6) A-D input
A-D conversion input
Fig.3 Port block diagram
3
Page 4
COMMAND STYLE
b0b1b2b3b4b5b6
b7
MITSUBISHI LINEAR IC’s
M35502AFP
FLD CONTROLLER
Display data setting
(Command 0)
Display state setting
(Command 1)
111
a4
1 1 0 M1 M0M2M3M4
a1
a0a2a3
Digit start pin setting
0 0 0 0 : FLD
0 0 0 1 : FLD
0 0 1 0 : FLD
0 0 1 1 : FLD
0 1 0 0 : FLD
0 1 0 1 : FLD
0 1 1 0 : FLD
0 1 1 1 : FLD
1 0 0 0 : FLD
1 0 0 1 : FLD
1 0 1 0 : FLD
Serial data transfer setting
1 : 3-byte transfer
0 : 4-byte transfer
Display ON or OFF setting
1 : ON
0 : OFF
Display duty setting
1 1 : 15/16
1 0 : 6/16
0 1 : 4/16
0 0 : 3/16
18
17
16
15
14
13
12
11
10
9
8
Number of timing
selecting
(Command 2)
Port data setting
(Command 3)
Note:
DIG/PORT switch setting becomes valid when command 3 (port data setting) is accepted. When command 3
is not used, set “11
1 0 T3 T2 T1 T0
1–
100––p2p1p0
2
” to these bits.
DIG/PORT switch setting (Note )
0 0 : P0 output of command 3 valid
0 1 : P0, P1 output of command 3 valid
1 0 : P0, P1, P2 output of command 3
valid
1 1 : All port is set as DIG.
Number of timing setting
0 0 0 0 : T16
0 0 0 1 : T15
0 0 1 0 : T14
0 0 1 1 : T13
0 1 0 0 : T12
0 1 0 1 : T11
0 1 1 0 : T10
0 1 1 1 : T9
1 0 0 0 : T8
1 0 0 1 : T7
1 0 1 0 : T6
1 0 1 1 : T5
P2–P0 output data
Fig.4 Command style
4
Page 5
SERIAL I/O PROTOCOL
Byte protocol
MITSUBISHI LINEAR IC’s
M35502AFP
FLD CONTROLLER
CS
CLK
Command protocol
Display data setting
(Command 0)
Other setting except
display data setting
(Command 1 to 3)
S
DATA
DATA
S
CS
CLK
S
DATA
(input)
(output)
Note: S
(input)
Notes 1: The serial data which is transmitted after executing command
2: Set the CS signal to “H” level after transferring a display data.
b0 b1 b2 b3 b4 b5 b6 b7
b0 b1 b2 b3 b4 b5 b6 b7
DATA
is in high-impedance state during CS signal is “H”.
Command 0 Data 1 Data 2
0 is recognized as a display data.
Data i
Fig.5 Serial I/O protocol
CS
CLK
S
DATA
(input)
Command
5
Page 6
SERIAL COMMUNICATION FORMAT (DISPLAY DATA, A-D OUTPUT)
When using 25 high-breakdown-voltage ports (segment + grid) (4-byte transfer)
CS
CLK
MITSUBISHI LINEAR IC’s
M35502AFP
FLD CONTROLLER
S
DATA
AD0AD1AD2AD
X
AD valid data
Output mode
Co m -
FLD
m and
3
0-7
0
FLD
8-15
Tn
FLD
16-23
FLD
24
Input mode
FLD
16-23
T2
FLD
24
FLD
0-7
The SDATA pin becoms output mode from after the CS pin falling until the 5th byte of serial data.
The S
DATA becomes command input mode from the 6th byte of serial data.
When using 24 high-breakdown-voltage ports (segment + grid) (3-byte transfer)
CS
CLK
S
DATA
AD0AD1AD2AD
X
Output mode
Co m -
FLD
m and
3
0-7
0
FLD
8-15
TnAD valid data
FLD
16-23
FLD
0-7
Tn-1
Input mode
FLD
0-7
The SDATA pin becoms output mode from after the CS pin falling until the 5th byte of serial data.
The S
DATA becomes command input mode from the 6th byte of serial data.
FLD
8-15
T2
FLD
16-23
FLD
8-15
FLD
0-7
T1
FLD
16-23
FLD
8-15
T1
FLD
24
FLD
16-23
When using 16 high-breakdown-voltage ports (segment + grid) or less (3-byte transfer)
CS
CLK
AD0AD1AD2AD
S
DATA
X
Output mode
Transfer dummy data to the third byte of each timing.
The S
DATA pin becoms output mode from after the CS pin falling until the 5th byte of serial data.
The S
DATA becomes command input mode from the 6th byte of serial data.
Fig.6 Serial communication format
6
Com-
FLD
m and
3
0-7
0
FLD
8-15
TnAD valid data
Dum-
my
data
FLD
0-7
Tn-1
FLD
0-7
Input mode
FLD
8-15
T2
Dum-
my
data
FLD
0-7
FLD
8-15
T1
Dum-
my
data
Page 7
FLD DISPLAY TIMING
MITSUBISHI LINEAR IC’s
M35502AFP
FLD CONTROLLER
Gn
Gn-1
G1
Segment
output
Digit
Segment
Fig.7 FLD display timing diagram
Tn Tn-1 T1 Tn Tn-1
Tdisp
Toff
Tdisp
Tscan=0ns
Tdisp = 384 µs (oscillation frequency f(OSC) = 2.0 MHz)
=
Toff 312 µs (3/16 ✕ Tdisp)
288 µs (4/16 ✕ Tdisp)
240 µs (6/16 ✕ Tdisp)
24 µs (15/16 ✕ Tdisp)
SEGMENT/DIGIT SETTING EXAMPLE
PORT FLD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
2324P2
25P1P0
FLD
FLD
FLD
FLD
FLD
FLD
FLD
FLD
FLD
FLD
FLD
FLD
FLD
FLD
FLD
FLD
FLD
FLD
FLD
FLD
FLD
FLD
FLD
FLD
FLD
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Grid: 5
Segm ent:8
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
GRID5
GRID4
GRID3
GRID2
GRID1
Grid: 7
Segm ent:8 Segm ent:8
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
GRID7
GRID6
GRID5
GRID4
GRID3
GRID2
GRID1
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
GRID10
GRID9
GRID8
GRID7
GRID6
GRID5
GRID4
GRID3
GRID2
GRID1
Grid: 7Grid: 10
Segm ent:18
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
GRID7
GRID6
GRID5
GRID4
GRID3
GRID2
GRID1
Fig.8 Segment/Digit setting example
7
Page 8
BIT ALLOCATION FOR DISPLAY RAM
MITSUBISHI LINEAR IC’s
M35502AFP
FLD CONTROLLER
ADDRESS
16
00
01
16
02
16
03
16
04
16
05
16
06
16
07
16
08
16
09
16
0A
16
0B
16
0C
16
0D
16
0E
16
0F
16
10
16
11
16
12
16
13
16
14
16
15
16
16
16
17
16
18
16
19
16
1A
16
1B
16
1C
16
1D
16
1E
16
1F
16
FLD
17
FLD
1
b0
FLD
24
16
8
0
FLD
24
16
8
0
FLD
24
16
8
0
FLD
24
16
8
0
FLD
24
16
8
0
FLD
24
16
8
0
FLD
24
16
8
0
FLD
24
FLD
16
8
FLD
0
b7
FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD
FLD15FLD14FLD13FLD12FLD11FLD10FLD9FLD
FLD7FLD6FLD5FLD4FLD3FLD2FLD1FLD
FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD
FLD
FLD15FLD14FLD
FLD7FLD6FLD5FLD4FLD3FLD2FLD1FLD
FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD
FLD15FLD14FLD13FLD12FLD11FLD10FLD9FLD
FLD7FLD
FLD23FLD22FLD21FLD
FLD15FLD14FLD13FLD
FLD7FLD6FLD
FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD
FLD15FLD14FLD13FLD12FLD11FLD10FLD9FLD
FLD
7
FLD23FLD22FLD21FLD
FLD15FLD
FLD7FLD6FLD5FLD4FLD3FLD2FLD1FLD
FLD23FLD
FLD15FLD14FLD13FLD12FLD11FLD10FLD9FLD
FLD7FLD6FLD5FLD4FLD3FLD2FLD1FLD
FLD23FLD22FLD
FLD15FLD14FLD13FLD12FLD11FLD10FLD9FLD
FLD7FLD
13
FLD5FLD4FLD
6
5
FLD5FLD
FLD
6
FLD13FLD12FLD11FLD10FLD9FLD
14
FLD
21
22
21
FLD
6
5
FLD11FLD10FLD9FLD
12
FLD2FLD1FLD
3
FLD19FLD18FLD17FLD
20
FLD11FLD10FLD9FLD
12
FLD3FLD2FLD1FLD
FLD
4
FLD3FLD2FLD1FLD
4
FLD18FLD17FLD
FLD
19
20
FLD20FLD19FLD18FLD17FLD
FLD20FLD19FLD
FLD
4
18
FLD3FLD
2
T1
T2
T3
T4
T5
T6
T7
T8
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
b7
16
FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD
16
FLD15FLD14FLD13FLD12FLD11FLD10FLD9FLD
16
FLD7FLD6FLD5FLD4FLD3FLD2FLD1FLD
16
16
FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD
16
FLD15FLD14FLD13FLD12FLD11FLD10FLD9FLD
16
FLD7FLD6FLD5FLD4FLD3FLD2FLD1FLD
16
16
FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD
16
FLD15FLD14FLD13FLD12FLD11FLD10FLD9FLD
16
FLD6FLD5FLD4FLD3FLD2FLD1FLD
FLD
16
7
16
FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD
16
FLD15FLD14FLD13FLD12FLD11FLD10FLD
16
FLD7FLD6FLD5FLD4FLD3FLD2FLD
16
16
FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD
16
FLD15FLD14FLD13FLD12FLD11FLD10FLD9FLD
16
FLD7FLD6FLD5FLD4FLD3FLD2FLD1FLD
16
16
FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD
16
FLD15FLD14FLD13FLD12FLD11FLD10FLD9FLD
16
FLD7FLD6FLD5FLD4FLD3FLD2FLD1FLD
16
16
FLD23FLD22FLD21FLD20FLD
16
FLD15FLD14FLD13FLD12FLD11FLD10FLD9FLD
16
FLD7FLD6FLD5FLD4FLD3FLD2FLD1FLD
16
16
FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD
16
FLD15FLD14FLD13FLD12FLD11FLD10FLD9FLD
16
FLD7FLD6FLD5FLD4FLD3FLD2FLD1FLD
16
19
b0
FLD
24
16
8
0
FLD
24
16
8
0
FLD
24
16
8
0
FLD
24
16
FLD
9
8
FLD
0
1
FLD
24
16
8
0
FLD
24
16
8
0
FLD
FLD18FLD17FLD
24
16
8
0
FLD
24
16
8
0
T9
T10
T11
T12
T13
T14
T15
T16
Fig.9 Bit allocation for display RAM
8
Page 9
CLOCK GENERATING CIRCUIT
Oscillating circuit is built up by connecting a capacitor between pins
OSC and VSS.
When supplying a clock externally, input it to the OSC pin.
MITSUBISHI LINEAR IC’s
M35502AFP
FLD CONTROLLER
OSC
OSC
External oscillation circuit
OSC
C
Fig.10 CR generating circuit Fig.11 External clock input circuit
V
CC
V
SS
HANDLING OF UNUSED PINS
Handle unused pins as the follow.
Table 2 Handling of unused pins
Pin
Segment
Digit
Analog input
Open
Open
Connect to VCC or VSS through a resistor.
Handling
POWER-ON RESET
Reset can be performed automatically during power on (power-on reset) by the built-in power-on reset circuit.
Poweron
Fig.12 Power-on reset
VDD
Reset state
Internal reset signal
Reset released
9
Page 10
ABSOLUTE MAXIMUM RATINGS
MITSUBISHI LINEAR IC’s
M35502AFP
FLD CONTROLLER
VCC
VEE
VI
VI
VO
VO
Pd
Topr
Tstg
Power source voltage
Pull-down power source voltage
Input voltage AN0 – AN3
Input voltage__CS, SDATA, SCLK
Output voltage FLD0 – FLD24
Output voltage SDAT A
Power dissipation
Operating temperature
Storage temperature
RECOMMENDED OPERATING CONDITIONS
ParameterSymbol Unit
VCC
VSS
VEE
VIH
VIL
Power source voltage
Power source voltage
Pull-down power source voltage
“H” input voltage__CS, SCLK, SDATA
“L” input voltage__CS, SCLK, SDATA
ConditionsParameterSymbol Unit
• All voltage are based on VSS.
• Output transistors are cut off.
• A waveform: 450 µs or more
frequency and 30 µs or less
pulse width.
• Connect only capacitor load
(CL = 200pF).
• All voltage are based on VSS.
• Output transistors are cut off.
Ta = 25 °C
(VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Min.
4.0
VCC–38
0.75VCC
0
Ratings
–0.3 to 6.5
VCC–45 to VCC+0.3
–0.3 to VCC+0.3
–0.3 to VCC+0.3
VCC–45 to VCC+0.3
VCC–50 to VCC+0.3
–0.3 to VCC+0.3
600
–20 to 85
–40 to 125
Limits
Typ.
5.0
0
Max.
VCC
VCC
0.25VCC
5.5
V
V
V
V
V
V
mW
°C
°C
V
V
V
V
V
RECOMMENDED OPERATING CONDITIONS (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
ParameterSymbol Unit
ΣIOH(peak)
ΣIOH(avg)
IOH(peak)
IOH(peak)
IOL(peak)
IOH(avg)
IOH(avg)
IOL(avg)
f(OSC)
f(SCLK)
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average
2: The peak output current is the peak current flowing in each port.
3: The average output current is an average value measured over 100 ms.
4: When the oscillation frequency has a 50 % duty cycle.
“H” total peak output current FLD0 – FLD24 (Note 1)
“H” total average output current FLD0 – FLD24
“H” peak output current FLD0 – FLD24 (at DIG selecting) (Note 2)
“H” peak output current FLD0 – FLD24 (at SEG selecting) (Note 2)
“L” peak output current SDAT A
“H” peak output current FLD0 – FLD24 (at DIG selecting) (Note 3)
“H” average output current FLD0 – FLD24 (at SEG selecting) (Note 3)
“L” average output current SDAT A
Clock input oscillation frequency (Note 4)
Serial I/O external clock frequency
value measured over 100 ms. The total peak current is the peak value of all the currents.
Min. Typ.
1.4
Limits
2.0
250
Max.
–240
–120
–40
–20
10
–18
–7
5.0
2.6
mA
mA
mA
mA
mA
mA
mA
mA
MHz
kHz
10
Page 11
MITSUBISHI LINEAR IC’s
ELECTRICAL CHARACTERISTICS (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
–500
–4.0
VOH
VOL
VT+—VT–
IIH
IIL
ILOAD
ILEAK
“H” output voltage
“L” output voltage
Hysteresis
“H” input current
“L” input current
Output load current
Output leakage
current
DIG output
SEG output
SDATA
SDATA, SCLK, CS
SDATA, SCLK, CS
SDATA, SCLK
____
CS
OSC
FLD0 – FLD24
FLD0 – FLD24
____
____
Test conditionsParameterSymbol
IOH = –18 mA
IOH = –7 mA
IOL = 5 mA
VCC = 5.0 V
VI = VCC
VI = VSS
VEE = VCC–36 V
VOL = VCC
Output transistors “off”
VEE = VCC–38 V
VOL = VCC–38 V
Output transistors “off”
Min.
VCC–2.0
VCC–2.0
250
M35502AFP
FLD CONTROLLER
Max.
2.0
0.5
5.0
–5.0
500
750
–10
Unit
V
V
V
V
µ
µ
µ
µ
µ
µ
A
A
A
A
A
A
ELECTRICAL CHARACTERISTICS (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
1.5
VRAM
ICC
RAM hold voltage
Power source current
Test conditionsParameterSymbol
When clock is stopped
VCC = 5 V, f(XIN) = 2.0 MHz
Output transistors “off” at
A-D converter operating
Min.
2.0
A-D CONVERTER CHARACTERISTICS (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
0.5
35
—
—
Tconv
VIA
IIA
RLADDER
Resolution
Absolute accuracy (excluding quantization error)
Conversion time
Analog input voltage
Analog port input current
Ladder resistor
Test conditionsParameterSymbol
VCC = 5.12 V
Min.
0
Max.
5.5
2.5
Max.
8
±3
100
VCC
5.0
Unit
V
mA
Unit
Bits
LSB
tc(OSC)
V
µ
A
kΩ
11
Page 12
TIMING REQUIREMENTS (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
)
ParameterSymbol Unit
tc(OSC)
twH(OSC)
twL(OSC)
tc(SCLK)
twH(SCLK)
twL(SCLK)
tsu(S
DA TA-SCLK
th(S
CLK-SDATA
__
tsu(CS)
__
th(CS)
tre(SCLK)
Note: The unit means a number of noise filter sampling clock (tc(OSC)).
Reset input “L” pulse width
Clock input “H” pulse width
Clock input “L” pulse width
Serial clock input cycle time (Note)
Serial clock input “H” pulse width (Note)
Serial clock input “L” pulse width (Note)
Serial input setup time (Note)
)
Serial input hold time (Note)
)
Serial input setup time
Serial input hold time
Serial clock interval time
50 tc(OSC)
50 tc(OSC)
50 tc(OSC)
MITSUBISHI LINEAR IC’s
M35502AFP
FLD CONTROLLER
Limits
Min.
384
120
120
5
2
3
2
3
Typ. Max.
ns
ns
ns
CLKs
CLKs
CLKs
CLKs
CLKs
ns
ns
ns
SWITCHING CHARACTERISTICS (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
ParameterSymbol Unit
td
(S
CLK-SOUT
tv
(S
CLK-SOUT
tr(Pch)
COSC
Note 1: The unit means a number of noise filter sampling clock (tc(OSC)).
)
Serial I/O output delay time (Note 1)
)
Serial I/O output valid time
High-breakdown-voltage P-channel
open-drain output rising time
External capacitor size (Note 2)
2: An external capacitor size varies with a mounted condition.
Test conditions
CL = 100pF
VEE = VCC–36 V
Min.
0
Measuring condition: Ta = 25°C, Vcc = 5.0 V)
Frequency - External capacitor size
3.0
2.5
2.0
1.5
1.0
Limits
Typ.
1.8
18
Max.
3
80
CLKs
ns
µ
s
pF
0.5
Frequency f(OSC) [MHz]
0
01020304050607080
External capacitor size COSC(pF
Fig. 13 Standard characteristic example of f(OSC)–COSC
12
Page 13
MITSUBISHI LINEAR IC’s
M35502AFP
FLD CONTROLLER
Serial I/O clock
output port
CL
Fig.14 Output switching characteristics measurement circuit diagram
CS
S
CLK
tsu(CS)
RL
P-channel output port
VEE
trec(S
CLK
)
CL
th(CS)
CLK
S
S
DATA
S
DATA
Fig.15 Timing diagram
(input)
(output)
0.2V
td(S
CLK-SDATA
CC
tWL(S
tsu(S
CLK
)
DATA-SCLK
0.8V
0.2V
)
tC(S
CLK
) th(S
CC
CC
)
0.8V
CC
CLK-SDATA
tWH(S
CLK
)
)
tv(S
CLK-SDATA
)
13
Page 14
PACKAGE OUTLINE
MITSUBISHI LINEAR IC’s
M35502AFP
FLD CONTROLLER
36P2R-G
EIAJ Package Code
SSOP36-P-450-0.80
E
E
H
G
Z
1
JEDEC Code
—
36 19
1
Weight(g)
0.53
D
e
y
b
z
Detail G
Plastic 36pin 450mil SSOP
Lead Material
Alloy 42
1
e
F
Recommended Mount Pad
Symbol
18
A
A
A
1
2
A
b
c
A
2
A
1
D
E
e
H
E
L
1
1
L
L
c
Detail F
L
z
Z
1
y
b
2
e
1
I
2
e
b
2
2
I
Dimension in Millimeters
Min Nom Max
—
—
—
10.1
—
—
—
—
—
0
0.1
.02
.250
.100
.814
.28
.30
.150
.015
.48
.80
.410
.30
.50
.01
0.7
—
—
.32
0.2
—
.40
.220
.215
.68
—
.710
.70
—
—
0.85
.150
0¡ — 10¡
—.50—
—
.4311
.271
—
—
—
14
Page 15
HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN
Keep safety first in your circuit designs!
• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to
personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable
material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
• These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property
rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
• Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples
contained in these materials.
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Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com).
• When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision
on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.
• Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric
Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical,
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• The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
• If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved
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Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
• Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
© 2000 MITSUBISHI ELECTRIC CORP.
New publication, effective Apr. 2000.
Specifications subject to change without notice.
Page 16
REVISION DESCRIPTION LIST M35502AFP DATA SHEET
Rev. Rev.
No. date
1.0 First Edition 990726
1.1 Font error is revised. 000414
Revision Description
(1/1)
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