■ Compatible with SPI Bus Serial Interface
(Positive Clock SPI Modes)
■ Single Supply Voltage: 4.5 V to 5.5 V
■ 5 MHz Clock Rate (maximum)
■ Sixteen 16-bit Increment al Regist ers
■ BYTE and PAGE WRITE (u p to 32 Bytes)
(except for the Incremental Registers)
■ Self-Tim e d P ro g r amming Cycle
■ Hardware Protection of the Status Register
■ Resizeable Read-Only EEPROM Area
■ Enhanced ESD Protection
■ 1 Million Erase/Write Cycles (minimum)
■ 40 Year Data Retention (minimum)
DESCRIPTION
The M35080 device consists of 1024x8 bits of low
power EEPROM, fabricated with
STMicroelectronics’ proprietary High Endurance
Double Polysilicon CMOS technology.
The device is accessed by a simple SPI-compatible serial interface. The bus signals consist of a
serial clock input (C), a serial data input (D) and a
serial data output (Q), as shown in Table 1.
The device is selected when t he chip s elect input
) is held low. Data is clocked in during the low to
(S
high transition of the clock, C. Data is clocked out
during the high to low transition of the clock.
M35080
8 Kbit Serial SPI Bus EEPROM
With Incremental Registers
PRELIMINARY DATA
8
1
PSDIP8 (BN)
0.25 mm frame
8
1
SO8 (MN)
150 mil width
Figure 1. Logic Diagram
V
CC
D
Q
Table 1. Signal Names
W
C
S
M35080
V
SS
C Serial Clock
D Serial Data Input
Q Serial Data Output
S
W
V
CC
V
SS
June 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Chip Select
Write Protect
Supply Voltage
Ground
AI02143
1/18
M35080
Figure 2. DIP and SO Connections
M35080
V
SS
Note: 1. NC = Not Connected.
W
1
S
2
3
4
Q
8
7
6
5
AI02144B
V
D
C
NC
CC
The memory is organized in pages of 32 bytes.
However, the first page is not treated in the sam e
way as the others. Instead, it is considered to consist of sixteen 16-bit incremental registers. Each
register can be modified using the conventional
write instructions, but the new value will only be
accepted if it is greater than the current value.
Thus, each register is restricted t o b eing mo dified
monotonically upwards.
This is useful in applications where it is necessary
to implement a counter that is protected from
fraudulent tampering (such as in a car odometer,
an electricity meter, or a tally for remaining credit).
SIGNAL DESCRIPTION
Seria l O utput ( Q )
The output pin is used to transfer data serially out
of the Memory. Data is shifted out on the falling
edge of the serial clock.
Serial Inpu t ( D )
The input pin is used to transfer data serially into
the device. Instructions, addresses, and the data
to be written, are each received t his way. Input is
latched on the rising edge of the serial clock.
Serial Clock (C)
The serial clock provides the timing for the serial
interface (as shown in Figure 3). Instructions, addresses, or data are latched, from the input pin, on
the rising edge of the clock input. The output dat a
on the Q pin changes state after the falling edge of
the clock input.
Chip Select (S
When S
is high, the memory device is deselected,
)
and the Q output pin is held in its high impe dance
state. Unless an internal write operation is underway, the memory device is placed in its stand-by
power mode.
After power-on, a high-to-low transition on S
is re-
quired prior to the start of any operation.
Write Protect (W
)
The protection features of t he m em ory device are
summarized in Table 3.
The hardware write protection, controlled by the W
pin, restricts write access to the Status Register
Table 2. Absolute Maximum Ratings
Symbol Parameter Value Unit
T
A
T
STG
T
LEAD
V
O
V
I
V
CC
V
ESD
Note: 1. Except for the rating “Operating Temperature Ra nge”, stres ses above those listed in the Table “Absolute Maximum Ratings” may
2/18
cause perm anent damage to the device. These are stress ratings only and op eration of th e device at these or any othe r
conditions above thos e i ndi cated in the O perating sec tions of this specificat i on i s not implied. Exposure to Absolute Ma xim um
Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and
other relevant quality documents .
2. MIL-STD-883C, 3015.7 (100 pF , 1500W).
3. EIAJ IC- 121 (Condi tion C) (200pF , 0W).
Ambient Operating Temperature -40 to 125 °C
Storage Temperature -65 to 150 °C
Lead Temperature during Soldering
Output Voltage Range
Input Voltage Range -0.3 to 6.5 V
Supply Voltage Range -0.3 to 6.5 V
Electrostatic Discharge Voltage (Human Body model)
Electrostatic Discharge Voltage (Machine model)
1
PSDIP8: 10 sec
SO8: 40 sec
2
3
260
215
-0.3 to V
+0.6
CC
4000 V
400 V
°C
V
Table 3. Write Protection Control
SRWD
W
Bit
Mode Status Register
M35080
Data Bytes
Protected Area Unprotected Area
0 or 1 0 Software
11
01
Protected
(SPM)
Hardware
Protected
(HPM)
Writeable (if the WREN
instruction has set the
WEL bit)
Hardware write protected
(though not to the WIP and WEL bits, which are
set or reset by the device’s internal logic).
Bit 7 of the status register (as shown in Table 4) is
the Status Register Write Disable bit (SRWD).
When this is set to 0 (its initial delivery state) it is
possible to write to the status register if the WEL
bit (Write Enable Latch) has been set by the
WREN instruction (irrespective of the l evel being
applied to the W
input).
When bit 7 (SRWD) of the status reg ister is set to
1, the ability to write to the status register depends
on the logic level being presented at pin W
pin is high, it is possible to write to the sta-
–If W
:
tus register, after having set the WEL bit using
the WREN instruction (Write Enable Latch).
–If W
pin is low, any attempt to modify the status
register is ignored by the device, even if the
WEL bit has been set. As a consequence, all the
data bytes in the EE PROM area, protected by
the BP1 and BP0 bits of the status register, are
also hardware protected against data corruption, and appear as a Read Only EEPROM area
for the microcontroller. This mode is called the
Hardware Protected Mode (HPM).
Software write protected
by the BP0 and BP1 bits
of the status register
Hardware write protected
by the BP0 and BP1 bits
of the status register
Writeable (if the WREN
instruction has set the
WEL bit)
Writeable (if the WREN
instruction has set the
WEL bit)
It is possible to enter the Hardware Protected
Mode (HPM) either by s etting the SRWD bi t after
pulling low the W
pin, or by pulling low the W pin
after setting the SRWD bit.
The only way to abort the Hardware Protected
Mode, once entered, is to pull high the W
pin is permanently t ied to the hi gh level, the
If W
pin.
Hardware Protected Mode is never activated, and
the memory device only allows the user to protect
a part of the memory, using the BP1 and BP0 bits
of the status register, in the Software Protected
Mode (SPM).
IMPORTANT: if W pin is left floating, not driven by
the application, W
is read as a logical ’0’.
Table 4. Status Register Format
b7 b0
SRWD UV X INC BP1 BP0 WEL WIP
Note: 1. BP0, BP1: Read and wri te bits
2. UV, INC, WEL, WIP: Read only bits.
3. SRWD: Read and Write bit.
Figure 3. Dat a and Clock Timi ng
CPOL
CPHA
0
1
0
1
C
C
D or Q
MSB LSB
AI01438
3/18
M35080
Figure 4. EEPR OM and SPI Bus
SPI Interface with
(CPOL, CPHA) =
('0', '0') or ('1', '1')
Master
(ST6, ST7, ST9,
ST10, Others)
CS3 CS2 CS1
D
Q
C
CQD
M35xxx
S
OPERATIONS
All instructions, addresses and data are shifted serially in and out of the chip (along the bus, as
shown in Figure 4). The most significant bit is presented first, with the data input (D) sampled on the
first rising edge of the clock (C) after the chip se-
) goes low (as shown in Figure 5, Figure 9,
lect (S
and Figure 12).
Every instruction, as summarized in Table 5, starts
with a single -byte cod e. If an invalid instructio n is
sent (one not contained in Table 5), the chip automatically deselects itself.
The instruction code is entered via the data input
(D), and latched on the rising edge of the clock input (C). To enter an instruction code, the device
must have been previously selected (S
held low).
CQD
M35xxx
S
CQD
M35xxx
S
AI02148C
Protection of the First 32 Bytes
The first 32-byte page is organized as 16 words
(two bytes each). The initial content of each word
on this page is 0000h. When writing to byt e-pair, a
logic comparator verifies that the new two-byte
value is larger than the val ue currently stored. If
the new value is sm aller than the current on e, no
operation is performed. It is impossible to write a
value lower than the previous one, irrespective of
the state of W
pin and status register, as indicated
in Table 6.
Write Enable (WREN) and Write Disable (WRDI)
The write enable latch, inside the memory device,
must be set prior to each WRITE and WRSR operation. The WREN instruction (write enable) sets
this latch, and the WRDI instruction (write disable)
resets it.
Table 5. Instruction Set
Instruction Description Instruction Format
WREN Set Write Enable Latch 0000 0110
WRDI Reset Write Enable Latch 0000 0100
RDSR Read Status Register 0000 0101
WRSR Write Status Register 0000 0001
READ Read Data from Memory Array 0000 0011
WRITE Write Data to Memory Array 0000 0010
WRINC Write Data to Secure Array 0000 0111
4/18
Figure 5. Rea d EEPRO M Arr a y Oper a t ion Sequence
S
21 345678910 2021222324252627
0
C
INSTRUCTION 16 BIT ADDRESS
15
D
1413 3210
M35080
28 29 30
HIGH IMPEDANCE
Q
Note: 1. The most signific ant address bi ts, A15-A 10, are treated as Don’t Care.
The latch becomes reset by any of the f ollowing
events:
– Power on
– WRDI instruction completion
– WRSR in s t ru ctio n completio n
– WRITE instruction completion.
As soon as the WREN or WRDI instruction is re-
ceived, the memory device first executes the instruction, then enters a wait mode until the device
is deselected.
Read Status Register (RDSR)
The RDSR instruction allows the status register to
be read, and can be sent at any time, even during
a Write operation. Indeed, when a Write is in
progress, it is recommended th at the value of t he
Write-In-Progress (WIP) bit be checked. The value
in the WIP bit (whose position in the status register
is shown in Table 4) can be continuously p olled,
before sending a new WRITE instruction. This can
be performed in one of two ways:
■ Repeated RDSR instructions (each one
consisting of S
being taken low, C being clocked
8 times for the instruction and 8 times for the
read operation, and S
being taken high)
■ A single, prolonged RDSR instruction
(consisting of S
clocked 8 times for the instruction and kept
running for repeated read operations), as
shown in Figure 6.
The Write-In-Process (WIP) bit is read-only, and
indicates whether the memory is busy with a Write
operation. A ’1’ indicates that a write is in progress,
and a ’0’ that no write is in progress.
The Write Enable Latch (WEL) bit indicates the
status of the write enable latch. It, too, is read-only.
Its value can only be changed by one of the events
listed earlier, or as a result of executing WREN or
WRDI instruction. It cannot be changed using a
WRSR instruction. A ’1’ i ndicates that the latch is
set (the forthcoming Write instruction will be executed), and a ’0’ that it is reset (and any forthcoming Write instructions will be ignored).
The Block Protect (BP0 and BP1) bits indicate the
amount of the memory that is to be write-protected. These two bits are non-volatile. They are set
using a WRSR instruction.
During a Write operation (whether it be to the
memory area or to the status register), all bits of
the status register remain valid, and can be read
using the RDSR instruction. However, during a
Write operation, the values of the no n-vo latile bits
DATA OUT
765432 0
MSB
1
being taken low, C being
AI01793
Table 6. Memory Mapping
Address Protection
000h-01Fh
020h-3FFh No specific protection except the one as of Table 7
Incremental area: a word (2 bytes) can be written only if the new value to write is larger
than the value already stored
5/18
M35080
Figure 6. RDSR: Read Status Register Sequence
S
21 3456789101112131415
0
C
INSTRUCTION
D
Q
HIGH IMPEDANCE
STATUS REG. OUT
7 6543210
MSB
(SRWD, BP0, BP1) be come frozen at a constant
value. The updated value of these bi ts becomes
available when a new RDSR instruction is executed, after completion of the write cycle. On the other hand, the two read-only bits (WEL, WIP) are
dynamically updated during internal write cycles.
Using this facility, it is possible to poll the WIP bit
to detect the end of the internal write cycle.
The Comparator bit (INC) indicates if the new val-
ue written in the 16 first word is lower ‘1’ or higher
‘0’ than the previous stored value.
The UV bit indicates if the memory chip has been
erased.
Write Status Register (WRSR)
The format of the WRSR instruction is shown in
Figure 7. After the instruction and the eigh t bits of
the status register have been latched-in, the internal Write cycle is triggered by the rising edge of
line. This must occur after the falling edge of
the S
STATUS REG. OUT
the 16
the 17
7 6543210
MSB MSB
th
clock pulse, and before the rising edge of
th
clock (as indicated in Figure 7), otherwise
7
AI02031
the internal write sequence is not performed.
The WRSR instruction is used for the following:
■ to select the size of memory area that is to be
write-protected
■ to select between SPM (Software Protected
Mode) and HPM (Hardware Protected Mode).
The size of the write-protection area applies equally in SPM and HPM. The BP 1 and BP0 b its of the
status register have the appropriate value (see Table 7) written into them after the contents of the
protecte d ar ea of t he EEPROM have been written.
The initial delivery state of the BP1 and BP0 bits is
00, indicating a write-protection size of 0.
Figure 7. WRSR: Write Status Register Sequence
S
21 3456789101112131415
0
C
INSTRUCTION STATUS REG.
D
MSB
HIGH IMPEDANCE
Q
6/18
765432 0
1
AI01797
Table 7. Write Protected Block Size
Status Register Bits
BP1 BP0 M35080
00
0 1 Upper quarter 0300h - 03FFh
1 0 Upper half 0200h - 03FFh
Note: 1. Except for the first sixteen pai rs of bytes (s ee Table 6).
Protected Block
1
none
M35080
Array Addresses Protected
1
none
Software Protected Mode (SPM)
The act of writing a non-zero value to the BP1 and
BP0 bits causes the Software Protected Mode
(SPM) to be started. All attempts to write a byte or
page in the protected area are ignored, even if the
Write Enable Latch is set. However, writing is still
allowed in the unprotected area of the memory array and to the SRWD, BP1 and BP0 bits of the status register, provided that the WEL bit is first set.
Hardware Prot ected Mode (H P M)
The Hardware Protected Mode (HPM) offers a
higher level of protection, and can be selected by
setting the SRWD bit after pulling down the W
or by pulling down the W
pin after setting the
pin
SRWD bit. The SR WD i s set by t he WS R instruction, provided that the WEL bit is first set. The setting of the SRWD b it can b e made independent ly
of, or at the sam e time as, writing a new valu e to
the BP1 and BP0 bits.
Once the device is in the Hardware Protected
Mode, the data bytes in the protected area of the
and
memory array,
the content of the status register, are write-protected. The only way to re-enable
writing new values to the status register is to pull
pin high. This cause the device to leave the
the W
Hardware Protected Mode, an d to revert t o being
in the Software Protected Mode. (The value in the
BP1 and BP0 bits will not have been changed).
Further details of the operation of the Write Protect
) are given earlier, on page 2.
pin (W
Typical Use of HPM and SPM
pin can be dynamically driven by an output
The W
port of a microcontroller. It is also possible,
though, to connect it permanently to V
(by a sol-
SS
der connection, or through a pull-down resistor).
The manufacturer of such a printed circuit board
can take the mem o r y dev ic e, s til l in its initia l de liv ery state, and can solder it directly on to the board.
After power on, the microcontroller can be instructed to write the protected data into the appropriate
area of the memory. When it has finished, the appropriate values are written to the BP1, BP0 and
SRWD bits, thereby putting the device in the hardware protected mode.
An alternative method is to write the protected data, and to set the BP1, BP0 and SRWD bits, before
soldering the memory device to the board. Again,
this results in the memory device being placed in
its hardware protected mode.
If the W
pin has been connect ed to VSS by a pulldown resistor, the mem ory device can be taken
out of the hardware protected mode by driving the
pin high, to override the pull-down resistor.
W
If the W
pin has been directly soldered to VSS,
there is only one way of taking the memory device
out of the hardware protect ed mode: t he memory
device must be de-soldered from the board, and
connected to external equipment in which the W
pin is allowed to be taken high.
Read Operation
The chip is first selected by holding S
low. The serial one byte read instruction is followed by a two
byte address (A15-A0), each bit being latched-in
during the rising edge of the clock (C). The data
stored in the memory, at the selected address, is
shifted out on the Q output pin. Each bit is s hi fted
out during the falling edge of the clock (C) as
shown in Figure 5.
The internal address counter is automatically incremented to the next higher address after each
byte of data has been shifted out. The data stored
in the memory, at the next address, can be read by
successive clock pulses. When the highest address is reached, the address counter rolls over to
“0000h”, allowing the read cycle to be continued
indefinitely. The read operation is terminated by
deselecting the chip. The chip can be deselected
at any time during data output. If a read instruction
is received during a write cycle, it is rejected, and
the memory device deselects itself.
Byte Write Operat ion
Before any write can take place, the WEL bit must
be set, using the WREN instruction, as sho wn in
Figure 8. The write state is entered by selecting
the chip, issuing three bytes of instruction and address, and one byte of data . Chip Select ( S
) must
remain low throughout the operat ion , as shown in
Figure 9. The device must be deselected just after
the eighth bit of the data byte has been latched in,
7/18
M35080
Figure 8. Write Enable Latch Sequence
S
C
D
Q
21 34567
0
HIGH IMPEDANCE
AI01794
as shown in Figure 9, otherwise the write process
is cancelled. As soon as the memory device is deselected , th e s e l f-timed int er na l w r ite cy c le is initiated. While the write is in progress, the status
register may be read to check the status of the SRWD, BP1, BP0, WEL an d WIP bits. In particular,
WIP contains a ‘1’ during the self-timed write cycle, and a ‘0 ’ when the cycle is com plete, (at which
point the write enable latch is also reset).
Write Data In the Incremental Registers
Due to the special control on the first page of the
memory, the byte write operation is not usable on
the first 32 bytes. Instead, the WRINC instruction
must be used, the timing of which is shown in Figure 10.
Prior to any write attempt, the write enable latch
must be set by issuing the WREN instru ction. Firs t
the device is selected (by taking S
low) and a seri-
al WREN instruction is issued. Then the device is
Figure 9. Byt e Wr i te Operation Se quence
S
21 345678910 2021222324252627
0
C
deselected, by taking S
high for at least t
SHSL
. The
device sets the write e nable latch, and rem ain s in
its stand-by state, until it is deselected. Then the
write state is entered by selecting the chip, by taking S
low. The WRI NC instruction is issued, and
the address is sent (always an even address, with
A0=0) along with two bytes of data. The Chip Select input (S
) must remain low for the entire dura-
ti on of the operation.
The device must be deselected just after the
eighth bit of the second data byte has been
latched in. Otherwise, the write process is cancelled. As a further protecti on, t he WRINC in st ruction is cancelled if its duration is not exactly equal
to 40 clock pulses.
As soon as the device is deselected, the self-timed
write cycle is initiated. While the write is in
progress, the status register may be read, to check
the values of the UV, INC, BP1, BP0, WEL and
28 29 30
31
INSTRUCTION 16 BIT ADDRESS
15
D
HIGH IMPEDANCE
Q
Note: 1. The most signific ant address bi ts, A15-A 10, are treated as Don’t Care.
8/18
1413 3210
DATA BYTE
765432 0
1
AI01795
Figure 10. Write Data to Incremental Registers (WRINC)
S
21 345678910 2021222324252627
0
C
28 29 30
M35080
31
INSTRUCTION 16 BIT ADDRESS
15
D
S
3433 35 36 37 38 3932
C
DATA BYTE 2
D
Note: 1. The most signific ant address bi ts, A15-A 10, are treated as Don’t Care.
765432 0
1
WIP bits. WIP is high during the self-timed write
cycle. When the cycle is completed, the w rite enable latch is reset.
Page Write Operation
A maximum of 32 bytes of data can be written during one Write time, t
, provided that they are all to
W
the same page (see Figure 11). The Page Write
operation is the same as the Byte Write operation,
except that instead of deselecting the device after
the first byte of data, up to 31 additional bytes can
be shifted in (and the device is deselected after the
last byte).
Any address of the memory can be chosen as the
first address to be wri tten. If the addres s counter
reaches the end of the page (an add ress of the
1413 3210
correctly formulated commands. The m ain sec urity measures can be summarized as follows:
– The WEL bit is reset at power-up.
–S
tiple thereof) in order to start a non-volatile write
cycle (in the memory array or in the status register).
– Accesses to the memory array are ignored dur-
ing the non-volatile programming cycle, and the
programming cycle continues unaffected.
– After execution of a WREN, WRDI, or RDSR in-
struction, the device enters a wait state, and
waits to be deselected.
– Inva lid S
form xxxx xxxx xxx1 1111) and the clock continues, the counter rolls over to the first address of
the same page (xxxx xxxx xxx0 0000) and overwrites any previously written data.
As before, the Write cycle only starts if the S
transition occurs just after the eighth bit of the last data
byte has been received, as shown in Figure 12.
DATA BYTE 1
765432 0
1
AI02146B
must rise after the eighth clock count (or mul-
transitions are ignored.
DATA PROTECTION AND PROTOCOL SAFETY
To protect the data in the memory from inadvertent
corruption, the memory device only responds to
9/18
M35080
Figure 11. Block Diagram
W
S
C
D
Q
Control Logic
I/O Shift Register
Address Register
and Counter
Y Decoder
High Voltage
Generator
Data Register
& Comparators
32 Bytes
Status
Register
AnAn - 31
Size of the
Read only
EEPROM
area
Note: 1. An is the top address of the memory.
001Fh0000h Incremental Register
X Decoder
AI02145C
10/18
Figure 12. Page Write Operation Sequence
S
21 345678910 2021222324252627
0
C
28 29 30
M35080
31
INSTRUCTION 16 BIT ADDRESS
15
D
S
3433 35 36 37 38 39 40 41 42 44 45 46 4732
C
DATA BYTE 2
D
Note: 1. The most signific ant address bi ts, A15-A 10, are treated as Don’t Care.
2. The number of clock pul ses must be a multiple of 8. Ot herwise, th e write is aborted.
765432 0
1
POWE R O N STATE
After power-on, the memory device is in the follow-
1413 3210
43
DATA BYTE 3
765432 0
Table 8. Initial Status Register Format
b7 b0
ing state:
– low power stand-by state
0 0010000
– deselected (after power-on, a high-to-low transi-
tion is required on the S
tions can be started).
– the WEL bit is reset
– the SRWD, BP1 and BP0 bits of the status reg-
ister are unchanged from the previous power-
down (they are non-volatile bits).
input before any opera-
INITIAL DELIVERY STATE
The device is delivered with the memory array in a
fully erased state. With the exception of the first 32
bytes, all data bits are set to ‘1’, and hence all data
bytes are at FFh. The first 32 bytes are s et to all
‘0’s, and hence the first 16 words at 0000h.
The status register bits are initialized to ‘0’, except
for bit b4, which is set to ‘1’, as shown in Table 8.
1
DATA BYTE 1
765432 0
DATA BYTE N
65432 0
1
1
AI01796
11/18
M35080
Table 9. DC Characteristics
(T
= 0 to 70°C, –40 to 85°C or –40 to 125°C; VCC = 4.5V to 5.5V)
A
Symbol Parameter Test Condition Min Max Unit
I
LI
I
LO
I
CC
I
CC1
V
IL
V
IH
V
OL
V
OH
Note: 1. The device meets output requ i rem ents for b ot h TT L and CMOS s ta n dards.
2. Test perf ormed at –40 to 125°C temperature range, Grade 3.
Input Leakage Current ±2 µA
Output Leakage Current ±2 µA
Supply Current
Standby Current
C = 0.1 V
C = 0.1 V
V
CC
S
= VCC, VIN = VSS or VCC, VCC = 5V
S
= VCC, VIN = VSS or VCC, VCC = 5V,
/0.9 VCC, @ 5 MHz,
CC
V
= 5V, Q = Open
CC
/0.9 VCC, @ 2 MHz,
CC
= 5V, Q = Open, Note
2
Note
Input Low Voltage –0.3
Input High Voltage
I
= 2mA, VCC = 5V
1
Output Low Voltage
1
Output High Voltage
OL
= 2mA, VCC = 5V, Note
I
OL
I
= –2mA, VCC = 5V 0.8 VCC
OH
= –2mA, VCC = 5V, Note
I
OH
3mA
2
3mA
10 µA
20 µA
0.7 V
CC
0.3 V
CC
VCC + 1
V
V
0.4 V
2
0.4 V
V
2
0.8 VCC
V
Table 10. Input Parameters 1
(T
= 25 C, f = 5 MHz)
A
Symbol Parameter Min Max Unit
C
IN
C
IN
t
LPF
Note: 1. Sampled only, not 100% tested.
Table 11. AC Measurement Conditions
Input Rise and Fall Times ≤ 50ns
Input Pulse Voltages
Input and Output Timing
Reference Voltages
Output Load
Note: 1. Output Hi-Z is defined as the point where data is no long-
12/18
er driven.
Input Capacitance (D) 8 pF
Input Capacitance (other pins) 6 pF
Input Signal Pulse Width Filtered Out 10 ns
Figure 13. AC Tes ti ng Input Output
0.2V
to 0.8V
0.3V
C
= 100pF
L
CC
CC
to 0.7V
CC
CC
0.8V
0.2V
CC
CC
0.7V
0.3V
AI00825
CC
CC
Table 12. AC Characteristics
Symbol Alt. Parameter
M35080
V
= 4.5V to 5.5V,
CC
T
= 0 to 70°C,
A
T
= –40 to 85°C
A
= 4.5V to 5.5V ,
V
CC
T
= –40 to 125°C
A
Min Max Min Max
M35080
Unit
f
C
t
SLCH
t
CHSL
(1)
t
CH
(1)
t
CL
t
CLCH
t
CHCL
t
DVCH
t
CHDX
t
DLDH
t
DHDL
t
CHSH
t
SHCH
t
SHSL
t
SHQZ
t
CLQV
t
CLQX
(2)
t
QLQH
(2)
t
QHQL
t
W
Note: 1. tCH + tCL ≥1/fc
2. Value guaranteed by characteri zation, not 100% tested in production.
t
CSS
t
CLH
t
t
t
t
DSU
t
t
CSH
t
t
t
t
t
f
Clock Frequency D.C. 5 D.C. 2.1 MHz
C
S Active Setup Time 100 100 ns
S Not Active Hold Time 100 100 ns
Clock High Time 60 200 ns
Clock Low Time 80 200 ns
CLL
Clock Rise Time 1 1 µs
RC
Clock Fall Time 1 1 µs
FC
Data In Setup Time 20 50 ns
Data In Hold Time 30 60 ns
DH
t
Data In Rise Time 1 1 µs
RI
t
Data In Fall Time 1 1 µs
FI
S Active Hold Time 200 200 ns
S Not Active Setup Time 100 100 ns
S Deselect Time 200 200 ns
Output Disable Time 100 150 ns
DIS
t
Clock Low to Output Valid 60 300 ns
V
Output Hold Time 0 0 ns
HO
Output Rise Time 100 100 ns
RO
Output Fall Time 100 100 ns
FO
Write Cycle Time 10 10 ms
WP
13/18
M35080
Figure 14. Serial Input Timing
S
C
tDVCH
tSLCH
tSHSL
tCHSHtCHSL
tSHCH
tCHCL
D
Q
Figure 15. Output Timing
S
C
tCLQX
tCHDX
MSB IN
HIGH IMPEDANCE
tCLQV
tDLDH
tDHDL
tCLCH
tCH
LSB IN
tCL
AI01447
tSHQZ
14/18
Q
ADDR.LSB IN
D
LSB OUT
tQLQH
tQHQL
AI01449B
M35080
ORDERING INFORMATION
The notation used for the device number is as
shown in Table 13. For a list of available options
(speed, package, etc.) or for further information on
any aspect of this device, please contact the ST
Sales Office nearest to you.
Table 13. Ordering Information Scheme
Example: M35080 –MN6T
Package
BN PSDIP8 (0.25 mm frame)
MN SO8 (150 mil width)
Temperature Range Option
6 –40 °C to 85 °C T Tape and Reel Packing
–40 °C to 125 °C
3
15/18
M35080
Table 14. PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame
Symb.
Typ. Min. Max. Typ. Min. Max.
A 3.90 5.90 0.1 54 0.232
A1 0.49 – 0.019 –
A2 3.30 5.30 0.1 30 0.209
B 0.36 0.56 0.0 14 0.022
B1 1.15 1.65 0.0 45 0.065
C 0 .20 0.36 0.008 0.014
D 9 .20 9.90 0.362 0.390
E 7.62 – – 0.300 – –
E1 6.00 6.70 0.2 36 0.264
e1 2.54 – – 0.100 – –
eA 7.80 – 0.307 –
eB 10.00 0.394
L 3 .00 3.80 0.118 0.150
mm inches
N8 8
Figure 16. PSDIP8 (BN)
A2
A1AL
B
N
1
e1
B1
D
E1 E
eA
eB
C
PSDIP-a
Note: 1. Drawing is not to scale.
16/18
Table 15. SO8 - 8 lead Plastic Small Outline, 150 mils body width
mm inches
Symb.
Typ. Min. Max. Typ. Min. Max.
A 1.35 1.75 0.0 53 0.069
A1 0.10 0.25 0.0 04 0.010
B 0.33 0.51 0.0 13 0.020
C 0 .19 0.25 0.007 0.010
D 4 .80 5.00 0.189 0.197
E 3.80 4.00 0.1 50 0.157
e 1 .27 – – 0.050 – –
H 5 .80 6.20 0.228 0.244
h 0 .25 0.50 0.010 0.020
L 0 .40 0.90 0.016 0.035
α 0° 8° 0° 8°
N8 8
CP 0.10 0.004
M35080
Figure 17. SO8 narrow (MN)
B
SO-a
Note: 1. Drawing is not to scale.
h x 45˚
A
e
D
N
1
CP
E
H
C
LA1 α
17/18
M35080
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or otherwise under any patent or p atent rights of STMi croelectr oni cs. Spec i fications mentioned i n this publicatio n are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as cri tical comp onents in life support dev i ces or systems wi t hout expres s written approval of STMi croelectr o nics.
© 1999 STMicroelectronics - All Rights Reserved
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18/18
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