Datasheet M34D64-W Datasheet (SGS Thomson Microelectronics)

M34D64

64 Kbit Serial I²C Bus EEPROM

With Hardware Write Control on Top Quarter of Memory

FEATURES SUMMARY

■ Two Wire I

2

C Serial Interface

Supports 400 kHz Protocol

■ Single Supply Voltage:

– 2.5V to 5.5V for M34D64-W
– 1.8V to 5.5V for M34D64-R

■ Hardware Write Control of the top quarter of

memory

■ BYTE and PAGE WRITE (up to 32 Bytes)

■ RANDOM and SEQUENTIAL READ Modes

■ Self-Tim e d P rogramming Cycle

■ Automatic Address Incrementing

■ Enhanced ESD/Latch-Up Behavior

■ More than 1M Erase/Write Cycles

■ More than 40 Year Data Retention

Figure 1. Packages

8

1

SO8 (MN)

150 mil width

TSSOP8 (DW)

169 mil width

1/21April 2003

M34D64

SUMMARY DESCRIPTION

2

These I

C-compatible electrically erasable
programmable memory (EEPROM) devices are
organized as 8192 x 8.

Figure 2. Logic Diagram

V

CC

3

E0-E2 SDA

SCL

WC

M34D64

V

SS

AI02850B

Table 1. Signal Names

E0, E1, E2 Chip Enable
SDA Serial Data
SCL Serial Clock
WC
V

CC

V

SS

Power On Reset: V

Write Control
Supply Voltage
Ground

Lock-Out Write Protect

CC

In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until V

has reached the POR

CC

threshold value, and all operations are disabled –
the device will not respond to any command. In the
same way, when V

drops from the operating

CC

voltage, below the POR threshold value, all
operations are disabled and the device will not
respond to any com ma nd. A s table a nd v alid V

CC

must be applied before applying any logic signal.

These devices are compatible with the I

2

memory protocol. This is a two wire serial interface
that uses a bi-directional data bus and serial clock.
The devices carry a built-in 4-bit Device Type
Identifier code (1010) in accordance with the I

2

bus definition.
The device behaves as a slave in the I

2

C protocol,
with all memory operations synchronized by the
serial clock. Read and Write operations are
initiated by a Start condition, generated by the bus
master. The Start condition is followed by a Device
Select Code and RW

bit (as described in Table 2),

terminated by an acknowledge bit.
When writing data to the memory, the device

inserts an acknowledge bit during the 9

th

bit time,

following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.

C

Figure 3. SO and TSSOP Connections

C

M34D64

1

E0 V

2
3

E2

4

SS

Note: 1. See page 17 (onwards) for package dimensions, and how

to identify pin-1.

8
7
6
5

AI02851C

CC

WCE1
SCL
SDAV

2/21

SIGNAL DESCRIPTION
Serial Clock (SCL)

This input signal is used to strobe all data in and
out of the device. In applications where this signal
is used by slave devices to synchronize the bus to
a slower clock, the bus master must have an open
drain output, and a pull-up resistor must be con­nected from Serial Clock (SCL) to V

. (Figure 5

CC

indicates how the value of the pull-up resist or can
be calculated). In most applications, thoug h, this
method of synchronization is no t employed, and
so the pull-up resistor is not necessary, provided
that the bus maste r has a push-pull (rather than
open drain) output.

Serial Data (SDA)

This bi-directional signal is used to transfer data in
or out of the device. It is an open drain output that

may be wire-OR’ed with other open drain or open
collector signals on the bus. A pull up resistor must
be connected from Serial Data (SDA) to V

CC

. (Fig­ure 5 indicates how the value of the pull-up resistor
can be calculated).

Chip Enable (E0, E1, E2)

These input signals are used to set the value that
is to be looked for on the three least significant bits
(b3, b2, b1) of the 7-bit Device Select Code. These
inputs must be tied to V

or VSS, to establish the

CC

Device Select Code.

Write Control (WC

The hardware Write Control pin (WC

)

) is useful for
protecting the top quarter of the memory (as
shown in Figure 4) from inadvertent erase or write.
The Write Control signal is used to enable

M34D64

(WC

=VIL) or disable (WC=VIH) write instructions to
the top quarter of the memory area. When uncon­nected, the WC
write operations are allowed.

Figure 4. Me m ory Map showing Write Cont rol Area

input is internally read as VIL, and

1FFFh

Write Controlled

Area

1800h

1000h

0800h

0000h

AI03114C

Figure 5. Maximum R

20

16

12

8

Maximum RP value (kΩ)

4

0

10 1000

Value versus Bus Capacitance (C

L

fc = 100kHz

fc = 400kHz

100

C

(pF)

BUS

) for an I2C Bus

BUS

MASTER

V

CC

R

SDA

SCL

R

C

BUS

L

C

BUS

AI01665

3/21

L

M34D64

Figure 6. I2C Bus Protocol

SCL

SDA

SCL

SDA

SCL

SDA

START

Condition

START

Condition

1 23 789

MSB

1 23 789

MSB ACK

SDA

Input

SDA

Change

STOP

Condition

ACK

STOP

Condition

AI00792B

Table 2. Device Select Code

Device Type Identifier

1

Chip Enable Address

b7 b6 b5 b4 b3 b2 b1 b0

Device Select Code 1 0 1 0 E2 E1 E0 RW

Note: 1. The most si gnifican t bit, b7, is se nt first.

2. E0 , E 1 and E2 are compared agai nst the respective external pins on the memory device.

2

RW

Table 3. Most Significant Byte Table 4. Least Significant Byte

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

4/21

M34D64

DEVICE OPERATION

2

The device supports the I

C protocol. This is
summarized in Figure 6. Any device that sends
data on to the bus is defined to be a transmitte r,
and any device that reads the data to be a
receiver. The device that controls the data transfer
is known as the bus master, and the other as the
slave device. A data transfer can only be initiated
by the bus master, which will also provide the
serial clock for synchronization. The M34D64
device is always a slave in all communication.

Start Condition

Start is identified by a falling edge of Serial Data
(SDA) while Serial Clock (SCL) is stable in the
High state. A Start condition must precede any
data transfer command. The devi ce continuously
monitors (except duri ng a Write cycle ) Se ri a l Data
(SDA) and Serial Clock (SCL) for a Start condition,
and will not respond unless one is give n.

Stop Condition

Stop is identified by a rising edg e of Serial Data
(SDA) while Serial Clock (SCL) is stable and
driven High. A Stop condition terminates
communication between the device and the bus
master. A Read command that is followed by
NoAck can be followed by a Stop condition to force
the device into the Stand-by mode. A Stop
condition at the end of a Write command triggers
the internal EEPRO M Writ e cycle.

Acknowledge Bit (ACK)

The acknowledge bit is used to indicate a
successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases
Serial Data (SDA) after sending eight bits of data.
During the 9

th

clock pulse period, the receiver pulls

Serial Data (SDA) Low to acknowledge the receipt
of the eight data bits.

Data Input

During data input, the device samples Serial Data
(SDA) on the rising edge of Serial Clock (SCL).
For correct device operation, Serial Data (SDA)
must be stable during the rising edge of Serial
Clock (SCL), and the Serial Data (SDA) signal

only

must change

when Serial Clock (SCL) is

driven Low.

Memory Addressing

To start communication betwee n the bus master
and the slave device, the bus mas ter mus t initiate
a Start condition. Following this, t he bus master
sends the Device Select Code, shown in Tabl e 2
(on Serial Data (SDA), most significant bit first).

The Device Select Code consists of a 4-bit Device

Type Identifier, and a 3-bit Chip Enable “Address”
(E2, E1, E0). To address the memory array, t he 4­bit Device Type Identifier is 1010b.

Up to eight memory devices can be connected on
a single I

2

C bus. Each one is given a uniq ue 3-bit
code on the Chip Enable (E0, E1, E2) inputs.
When the Device Select Code is received on
Serial Data (SDA), the device only responds if the
Chip Enable Address is the s ame as the v alue on
the Chip Enable (E0, E1, E2) inputs.

th

The 8

bit is the Read/Write bit (RW). This bi t is

set to 1 for Read and 0 for Write operations.
If a match occurs on the Device Select code , the

corresponding device gives an acknowledgment
on Serial Data (SDA) during the 9

th

bit time. If the
device does not match the Device Select code, it
deselects itself from the bus, and goes into Stand­by mode.

Table 5. Operating Modes

Mode RW bit

Current Address Read 1 X 1 START, Device Select, RW

Random Address Read

Sequential Read 1 X
Byte Write 0 V
Page Write 0 V

Note: 1. X = V

IH

or V

.

IL

0X
1 X reSTART, Device Select, RW

WC

1

IL

IL

Bytes Initial Sequence

1

1 Similar to Current or Random Address Read

≥

1 START, Device Select, RW = 0

32 START, Device Select, RW

≤

START, Device Select, RW

= 1
= 0, Address

= 1

= 0

5/21

M34D64

Figure 7. Wri te Mo de S e qu e nces with WC =0 (data wri te enab led)

WC

ACK

BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN

R/W

START

WC

ACK ACK ACK ACK

PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1

R/W

START

WC (cont'd)

ACKACK

PAGE WRITE
(cont'd)

DATA IN N

ACK ACK ACK

STOP

DATA IN 2

Write Operations

Following a Start condition the bus master sends
a Device Select Code with the RW

bit rese t to 0 .
The device acknowledges this, as shown in Figure
7, and waits for two address bytes. The device re­sponds to each address byte with an acknowledge
bit, and then waits for the data byte(s).

Writing to the memory may be inhibited if Write
Control (WC
with Write Control (WC

) is driven High. Any Write instruction

) driven High (during a pe­riod of time from the Start condition until the end of
the two address bytes) will not modify the contents
of the top quarter of the memory.

Each data byte in the m emory has a 16-bit (two
byte wide) address. The Most Significant Byte (Ta­ble 3) is sent first, followed by the Least Significant
Byte (Table 4). Bits b15 to b0 form t he add ress of
the byte in memory.

When the bus mast er generates a Stop con dition

immediately after the Ack bi t (in t he “10

th

bit” time

slot), either at the end of a Byte Write or a Page

STOP

AI01106C

Write, the internal memory Write cycle is triggered.
A Stop condition at any other time slot does not
trigger the internal Write cycle.

During the internal Write cycle, Serial Da ta (SDA)
is disabled internally, and the devi ce does not re­spond to any requests.

Byte Write

After the Device Select code and the address
bytes, the bus master sends one dat a byte. If the
addressed location is Write-protected (top quarter
of the memory), by Write Control (WC

) being driv­en High, the location is not modified. The bus mas­ter terminates the transfer by generating a Stop
condition, as shown in Figure 7.

Page Write

The Page Write mode allows u p to 32 by tes to be
written in a single Write cycle, provided that they
are all located in the same ’row’ in the memory:
that is, the most significant m emory address bits
(b12-b5) are the same. If more bytes are sent than
will fit up to t he en d of t he row, a condition known
as ‘roll-over’ occurs. This should be avoided, as

6/21

M34D64

data starts to become overwritten in an implemen­tation dependent way.

The bus master sends fr om 1 to 32 bytes of data.
If Write Control (WC

) is High, the contents of the

addressed top quarter of the m emo ry locatio n are

Figure 8. W ri t e C yc le Pol l in g Fl owchart usin g A C K

WRITE Cycle

in Progress

START Condition

DEVICE SELECT

with RW = 0

ACK

NO

Returned

First byte of instruction
with RW = 0 already
decoded by the device

ReSTART

YES

Next

Operation is

Addressing the

Memory

not modified. After each byte is transferred, the in­ternal byte address counter (the 5 least significant
address bits only) is incremented. Th e transfer is
terminated by the bus master generating a Stop
condition.

YESNO

Send Address

and Receive ACK

STOP

DATA for the

WRITE Operation

Continue the

WRITE Operation

Minimizing System Delays by Polling On ACK

During the internal Write cycle, the device
disconnects itself from t he bus , and writes a copy
of the data from its internal latches to the memory
cells. The maximum Write time (t

) is shown in

w

Tables 13 and 14, but the typical time is shorter.
To make use of this, a polling sequence can be
used by the bus master.

The sequence, as shown in Figure 8, is:

– Initial condition: a Write cycle is in progress.

START

Condition

YESNO

DEVICE SELECT

with RW = 1

Continue the

Random READ Operation

AI01847C

– Step 1: the bus master issues a Start condition

followed by a Device Select Code (the first byte
of the new instruction).

– Step 2: if the device is busy with the internal

Write cycle, no Ack will be returned and the bus
master goes back to Step 1. If the device has
terminated the internal Write cycle, it responds
with an Ack, indicating that the device is ready
to receive the second part of the instruction (the
first byte of this instruction having been sent
during Step 1).

7/21

M34D64

Figure 9. Read Mode Sequences

CURRENT ADDRESS READ

RANDOM ADDRESS READ

SEQUENTIAL
CURRENT
READ

SEQUENTIAL
RANDOM
READ

ACK

DEV SEL DATA OUT

R/W

START

ACK

DEV SEL * BYTE ADDR BYTE ADDR

R/W

START

ACK ACK ACK NO ACK

DEV SEL DATA OUT 1

R/W

START

ACK ACK ACK

DEV SEL * BYTE ADDR BYTE ADDR

NO ACK

STOP

ACK ACK ACK

DEV SEL * DATA OUT

R/W

START

DATA OUT N

STOP

ACK ACK

DEV SEL * DATA OUT 1

NO ACK

STOP

R/W

START

ACK NO ACK

DATA OUT N

STOP

Note: 1. The sev en m ost significant bits o f the Device Sel ect Code of a Random Read (in the 1st and 4th bytes) must be identical.

must

Read Operations

Read operations are performed independently of
the state of the Write Control (WC

) signal.

Random Address Read

A dummy Write is performed to load the address
into the address counter (as shown in Figure 9) but

without

sending a Stop condition. Then, t he bus
master sends another Start condition, and repeats
the Device Select Code, with t he RW

bit set to 1.
The device acknowledges this, and outputs the
contents of the addressed byte. The bus master

the transfer with a Stop condition.

Current Address Read

The device has an internal address counter which
is incremented each time a byte is read. For the
Current Address Read operation, following a Start
condition, the bus master only sends a Device
Select Code with the RW
acknowledges this, and outputs the byte
addressed by the internal address counter. The
counter is then incremented. The bus master
terminates the transfer with a Stop condition, as

START

not

acknowledge the byte, and terminates

shown in Figure 9,

R/W

AI01105C

bit set to 1. The device

without

acknowledging the

byte.

8/21

M34D64

Sequenti a l Rea d

This operation can be used after a Current
Address Read or a Random Address Read. The
bus master

does

acknowledge the data byte
output, and sends additional clock pulses s o that
the device continues to output the next byte in
sequence. To terminate the strea m of bytes, the
bus master must

must

and

generate a Stop condition, as shown in

not

acknowledge the last byte,

Figure 9.
The output data comes from consecutive

addresses, with the internal address counter
automatically incremen ted af t er ea ch byt e out put.

After the last memory address, the address

counter ‘rolls-over’, and the device continues to
output data from memory address 00h.

Acknowledge in Read Mode

For all Read commands, the device waits, after
each byte read, for an acknowledgment during the

th

bit time. If the bus master does not drive Serial

9
Data (SDA) Low during this time, the device
terminates the data transfer and switches to its
Stand-by mode.

9/21

M34D64

MAXI MUM RATI N G

Stressing the device ab ove the rating listed in t he
Absolute Maximum Ratings" table may cause per­manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions ab ove those i ndicated in t he
Operating sections of this specificat ion is not im-

Table 6. Absolute Maximum Ratings

Symbol Parameter Min. Max. Unit

T

STG

T

LEAD

V

IO

V

CC

V

ESD Electrostatic Discharge Voltage (Human Body model)

Note: 1. IPC/JEDEC J-STD-020 A

2. JEDEC Std J ESD22-A114A (C1=1 00 pF, R1=1500 Ω, R2=500 Ω)

Storage Temperature –65 150 °C

Lead Temperature during
Soldering

SO: 20 seconds (max)

TSSOP: 20 seconds (max)
Input or Output range –0.6 6.5 V
Supply Voltage –0.3 6.5 V

plied. Exposure to Absolute Maximum Rating con­ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and ot her relevant quality docu­ments.

1

1

2

–4000 4000 V

235
235

°C

10/21

DC AND AC PARAMETERS

This section summarizes the operat ing and mea­surement conditions, and the DC and AC charac­teristics of the device. The parameters in t he DC
and AC Characteristic tables that follow are de­rived from tests performed under the Measure-

ment Conditions summarized in the relevant
tables. Designers should chec k th at the o perat ing
conditions in their circuit matc h the meas urement
conditions when relying on the quoted parame­ters.

Table 7. Operating Conditions (M34D64-W)

Symbol Parameter Min. Max. Unit

M34D64

V

CC

T

A

Supply Voltage 2.5 5.5 V
Ambient Operating Temperature –40 8 5 °C

Table 8. Operating Conditions (M34D64-R)

Symbol Parameter Min. Ma x. Unit

V

CC

T

A

Supply Voltage 1.8 5.5 V
Ambient Operating Temperature –40 8 5 °C

11/21

M34D64

Table 9. AC Measurement Conditions

Symbol Parameter Min. Max. Unit

C

L

Load Capacitance 100 pF
Input Rise and Fall Times 50 ns
Input Levels
Input and Output Timing Reference Levels

Figure 10. AC Measurement I/O Waveform

Input Levels

0.8V

CC

0.2V

CC

Table 10. Input Parameters

Symbol

C

IN

C

IN

Z

WCL

Z

WCH

t

NS

Note: 1. TA = 25 °C, f = 400 kHz

2. Sampled only, not 100% tested.

Input Capacitanc e (SDA) 8 pF
Input Capacitance (other pins) 6 pF
WC Input Impedance VIN < 0.5 V 50 300 k
WC Input Impedance
Pulse width ignored

(Input Filter on SCL and SDA)

Parameter

1,2

to 0.8V

0.2V

0.3V

Input and Output

Timing Reference Levels

0.7V

CC

0.3V

CC

AI00825B

CC

to 0.7V

CC

CC

CC

V
V

Test Condition Min. Max. Unit

Ω

V

> 0.7V

IN

CC

500 k

Ω

Single glitch 100 ns

12/21

Table 11. DC Characteristics (M34D64-W)

Symbol Parameter

Input Leakage Current

I

LI

(SCL, SDA)

Test Condition

(in addition to those in Table 7)

V

= VSS or V

IN

CC

device in Stand-by mode

Min.

M34D64

Max. Unit

± 2 µA

I
I

I

CC1

Output Leakage Current V

LO

Supply Current

CC

Stand-by Supply Current

V

Input Low Voltage

V

V

V

(E2, E1, E0, SCL, SDA)

IL

Input Low Voltage (WC
Input High Voltage

IH

(E2, E1, E0, SCL, SDA, WC
Output Low Voltage IOL = 2.1 mA, VCC = 2.5 V 0.4 V

OL

) –0.3 0.5 V

)

Table 12. DC Characteristics (M34D64-R)

Symbol Parameter

Input Leakage Current

I

LI

(SCL, SDA)

I

I

I

CC1

V

V

Output Leakage Current V

LO

Supply Current

CC

Stand-by Supply Current
Input Low Voltage

(E2, E1, E0, SCL, SDA)

IL

Input Low Voltage (WC
Input High Voltage

IH

(E2, E1, E0, SCL, SDA, WC

) –0.3 0.5 V

V

CC

)

= VSS or V

OUT

=2.5V , fc=400kHz (rise/fall time < 30ns)

CC

= VSS or V

V

IN

V

= VSS or V

IN

SDA in Hi-Z ± 2 µA

CC,

, V

CC

CC

= 5 V

CC

, V

= 2.5 V 2 µA

CC

Test Condition

(in addition to those in Table 8)

V

= VSS or V

IN

CC

device in Stand-by mode

= VSS or V

OUT

SDA in Hi-Z ± 2 µA

CC,

=1.8V , fc=100kHz (rise/fall time < 30ns)

V

= VSS or V

IN

CC

, V

= 1.8 V

CC

–0.3

0.7V

Min.

– 0.3

0.7V

CC

CC

1mA

10 µA

0.3V

CC

VCC+1

Max. Unit

± 2 µA

0.8

0.2

0.3 V

mA

µA

CC

VCC+1 V

V

V

V

V

Output Low Voltage IOL = 0.7 mA, VCC = 1.8 V

OL

0.2

V

13/21

M34D64

Table 13. AC Characteristics (M34D64-W)

Test conditions specified in Table 9 and Table 7

Symbol Alt. Parameter Min. Max. Unit

f

C

t

CHCL

t

CLCH

t

CH1CH2

t

CL1CL2

t

DH1DH2

t

DL1DL2

t

DXCX

t

CLDX

t

CLQX

3

t

CLQV

t

CHDX

t

DLCL

t

CHDH

t

DHDL

t

W

Note: 1. For a reS T A RT conditio n, or following a Write cy cle.

2. Sampled only, not 100% tested.

3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.

4. The Write Time of 5 ms only applies to devices bearing the process identification letter "B" in the package marking (on the top side

f

SCL

t

HIGH

t

LOW

t
t

2

2

1

of the pack-a ge) , oth er wise (f or dev ic es bea ring th e proc ess id ent ifi catio n let ter "N ") t he Wri te Ti me is 10 m s. Fo r furt he r details,
please con tact your nearest ST sale s of f i ce.

t
t

t

SU:DAT

t

HD:DAT

t

DH

t

AA

t

SU:STA

t

HD:STA

t

SU:STO

t

BUF

t

WR

Clock Frequency 400 kHz
Clock Pulse Width High 600 ns
Clock Pulse Width Low 1300 ns
Clock Rise Time 300 ns

R

Clock Fall Time 300 ns

F

SDA Rise Time 20 300 ns

R

SDA Fall Time 20 300 ns

F

Data In Set Up Time 100 ns
Data In Hold Time 0 ns
Data Out Hold Time 200 ns
Clock Low to Next Data Valid (Access Time) 200 900 ns

Start Condition Set Up Time 600 ns
Start Condition Hold Time 600 ns
Stop Condition Set Up Time 600 ns
Time between Stop Condition and Next Start Condition 1300 ns
Write Time

5 or

4

10

ms

14/21

Table 14. AC Characteristics (M34D64-R)

Test conditions specified in Table 9 and Table 8

M34D64

Symbol Alt. Parameter

f

C

t

CHCL

t

CLCH

2

t

DL1DL2

t

DXCX

t

CLDX

t

CLQX

3

t

CLQV

1

t

CHDX

t

DLCL

t

CHDH

t

DHDL

t

W

Note: 1. For a reS T A RT conditio n, or following a Write cy cle.

2. Sampled only, not 100% tested.

3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.

f

SCL

t

HIGH

t

LOW

t

F

t

SU:DAT

t

HD:DAT

t

DH

t

AA

t

SU:STA

t

HD:STA

t

SU:STO

t

BUF

t

WR

Clock Frequency 400 kHz
Clock Pulse Width High 600 ns
Clock Pulse Width Low 1300 ns
SDA Fall Time 20 300 ns
Data In Set Up Time 100 ns
Data In Hold Time 0 ns
Data Out Hold Time 200 ns
Clock Low to Next Data Valid (Access Time) 200 900 ns

Start Condition Set Up Time 600 ns
Start Condition Hold Time 600 ns
Stop Condition Set Up Time 600 ns
Time between Stop Condition and Next Start

Condition
Write Time 10 ms

Min.

1300 ns

Max. Unit

15/21

M34D64

Figure 11. AC Waveforms

SCL

SDA In

SCL

SDA In

SCL

tCHCL

tDLCL

tCHDX

START

Condition

tCHDH

STOP

Condition

tCLQV tCLQX

SDA
Input

tCLCH

SDA

Change

tW

Write Cycle

tDXCXtCLDX

tCHDH tDHDL

tCHDX

START

Condition

STOP

Condition

START

Condition

SDA Out

Data Valid

AI00795C

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PACKAGE MECHANICAL

SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Ou tline

h x 45˚

M34D64

Note: Drawing is not to scale.

B

SO-a

A

e

D

N

1

CP

E

H

C

LA1 α

SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package M echa nical Data

Symb.

Typ. Min. Max. Typ. Min. Max.

A 1.35 1.75 0.053 0.069

mm inches

A1 0.10 0.25 0.004 0.010

B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
E 3.80 4.00 0.150 0.157
e 1.27 – – 0.050 – –

H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 0.90 0.016 0.035

α

0° 8° 0° 8°

N8 8

CP 0.10 0.004

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M34D64

TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline

D

8

1

CP

Notes: 1. Drawing is not to scale.

5

EE1

4

A2A

eb

A1

L1

TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mec han ical Data

Symbol

Typ. Min. Max. Typ. Min. Max.

A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 1.000 0.800 1. 050 0.0394 0.0315 0.0413

b 0. 190 0.300 0.0075 0.0118

c 0.090 0.200 0.0035 0.0079

mm inches

c

α

L

TSSOP8AM

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CP 0.100 0.0039

D 3.000 2. 900 3.100 0.1181 0.1142 0.1220

e 0.650 – – 0.0256 – –

E 6 .400 6.200 6.600 0.2520 0.2441 0.2598
E1 4.400 4.300 4. 500 0.1732 0.1693 0.1772

L 0.600 0. 450 0.750 0.0236 0.0177 0.0295

L1 1 .000 0.0394

α

0° 8° 0° 8°

PART NUMBERING

Table 15. Ordering Information Scheme

Example: M34D64 –WMN6T

Device Type

2

M34 = I
access EEPROM

Device Function

64 = 64 Kbit (8192 x 8)

Operating Voltage

W = V
R = V

Package

MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)

Temperature Range

6 = –40 to 85 °C

C Application Specific Standard Product serial

= 2.5 to 5.5V

CC

= 1.8 to 5.5V

CC

M34D64

Option

T = Tape & Reel Packing

Devices are shipped from the factory with the
memory content set at all 1s (FFh).

For a list of available options (speed, package,
etc.) or for further information on any aspect of this
device, please contact your nearest ST Sales O f­fice.

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M34D64

REVISION HIST ORY

Table 16. Document Revision History

Date Rev. Description of Revision

23-Mar-1999 1.0 Document written
09-Jun-1999 1.1 Memory Map illustration added. Line removed from Tab-2

16-Nov-2000 1.2

13-Sep-2002 2.0 New edition. TSSOP8 package added

04-Apr-2003 2.1

M34D32 removed; PSDIP8 package removed; 4.5 to 5.5V and 1.8 to 3.6V ranges removed; 0

to 70°C and -20 to 85°C ranges removed

Addresses on Memory Map figure corrected.
tW of 5ms offered on certain versions of the device (bearing process identification letter “B”)

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M34D64

Information furnished is believed to be accurate an d rel i able. However, STMicroelectro ni cs assumes no responsibility for the consequen ces
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or otherwise under any patent or patent ri ghts of STM i croelectr onics. Sp ecifications mentioned in thi s publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics product s are not
authorized for use as cri tical comp onents in lif e support devi ces or systems without express written approv al of STMicroel ectronics.

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