Datasheet M34D64 Datasheet (SGS Thomson Microelectronics)

M34D64
M34D32

64/32 Kbit Serial I²C Bus EEPROM

With Hardware Write Control on Top Quarter of Memory

PRELIMINARY DATA

■ Compat ible with I

■ Two Wire I

2

C Extended Addressing

2

C Serial Interface

Supports 400 kHz Protocol

■ Single Supply Voltage:

– 4.5V to 5.5V for M34Dxx
– 2.5V to 5.5V for M34Dxx-W
– 1.8V to 3.6V for M34Dxx-R

■ Hardware Write Control of the top quarter of

memory

■ BYTE and PAGE WRITE (up to 32 Bytes)

■ RANDOM and SEQUENTIAL READ Modes

■ Self-Tim e d P ro g r amming Cycle

■ Automatic Address Incrementing

■ Enhanced ESD/Latch-Up Behavior

■ More than 1 Million Erase/Write Cycles

■ More than 40 Year Data Retention

DESCRIPTION

These electrically erasable programmable
memory (EEPROM) devices are fabricated with
STMicroelectronics’ High Endurance, CMOS
technology. This guarantees an endurance
typically well above one million Erase/Write
cycles, with a data retention of 40 years. The
memories are organized as 8192x8 bits (M34D64)
and 4096x8 bits (M34D32), and operate down to

8

1

PSDIP8 (BN)

0.25 mm frame

8

1

SO8 (MN)

150 mil width

Figure 1. Logic Diagram

V

CC

Table 1. Signal Names

E0, E1, E2 Chip Enable Inputs
SDA Serial Data/Address Input/

Output
SCL Serial Clock
WC
V

CC

V

SS

May 2000

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

Write Control

Supply Voltage

Ground

E0-E2 SDA

SCL

WC

3

M34D64
M34D32

V

SS

AI02850

1/15

M34D64, M34D32

Figure 2A. DIP Connections

M34D64
M34D32

1

E0 V

2
3

E2

4

SS

8
7
6
5

AI02851

Figure 2B. SO C on ne ct i on s

M34D64
M34D32

E0 V

1
2

E2

SS

3
4

8
7
6
5

AI02852

CC

WCE1
SCL
SDAV

CC

WCE1
SCL
SDAV

2.5 V (for the -W version of each device), and
down to 1.8 V (for the -R version of each device).

The M34D64 and M34D32 are available in Plastic
Dual-in-Line and Plastic Small Outline packages.

These memory devices are compatible with the

2

C extended memory standard. This is a two wire

I
serial interface that uses a bi-directiona l data bus
and serial clock. The memory carries a built-in 4­bit unique Device Type Identifier code (1010) in
accordance with the I

The memory behaves as a slave device in the I

2

C bus definition.

2

protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are
initiated by a START condition, genera ted by the
bus master. The START condition is followed by a
Device Select Code and RW

bit (as described in

Table 3), terminated by an acknowledge bit.
When writing data to the memory, the memory

inserts an acknowledge bit during the 9

th

bit time,

following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of t he data b yte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and
after a NoAck for READ.

Power On Reset: V

Lock-Out Write Protect

CC

In order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until the V

voltage has reached

CC

the POR threshold value, and all operations are
disabled – the device will not respond to any
command. In the same way, when V

drops from

CC

the operating voltage, below the POR threshold
value, all operations are disabled an d the device
will not respond to any command. A stable and

C

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

T

A

T

STG

T

LEAD

V

IO

V

CC

V

ESD Electrostatic Discharge Voltage (Human Body model)

Note: 1. Exc ept for the rating “Operating Temperature Ra nge”, stres ses above those listed in the Table “Absolute Maximum Ratings” may

2/15

cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indi cated in t he Operating sect i ons of thi s specifi cation i s not impl i ed. Exposure to Absolute M aximum Rating c ondi­tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.

2. MIL -STD-883C, 3015.7 (1 00 pF, 1500 Ω)

3. EIA J I C-121 (Condition C) (200 pF, 0 Ω)

Ambient Operating Temperature -40 to 125 °C
Storage Temperature -65 to 150 °C

Lead Temperature during Soldering

Input or Output range -0.6 to 6.5 V
Supply Voltage -0.3 to 6.5 V

1

PSDIP8: 10 sec
SO8: 40 sec

2

260
215

4000 V

°C

M34D64, M34D32

Figure 3. Maximum R

20

16

12

8

Maximum RP value (kΩ)

4

0

10 1000

Value versus Bus Capacitance (C

L

fc = 100kHz

fc = 400kHz

100

C

(pF)

BUS

valid VCC must be applied before applying any
logic signal.

SIGNAL DESCRIPTION
Serial Clock (SCL)

The SCL input pin is used to strobe all data in and
out of the memory. In applications where this line
is used by slaves to synchronize the bus to a
slower clock, the master must have an open drain
output, and a pull-up resistor must be c onnected
from the SCL line to V

. (Figure 3 indicates how

CC

the value of the pull-up resistor can be calculated).
In most applications, though, this method of
synchronization is not employed, and so the pull­up resistor is not necessary, provided that the
master has a push-pull (rather than open drain)
output.

Serial Data (SDA)

The SDA pin is bi-directional, and is used to
transfer data in or out of the memory. It is an open

drain output that may be wire-OR’ed with other
open drain or open collector signals on the bus. A
pull up resistor must be connected f rom the SDA
bus to V

. (Figure 3 indicates how t he value of

CC

the pull-up resistor can be calculated).

Chip Enable (E2, E1, E0)

These chip enable inputs are used to set the value
that is to be looked for on the three least significant
bits (b3, b2, b1) of the 7-bit device select code.
These inputs must be tied to V

or VSS to

CC

establish the device select code.

Write Control (WC

The hardware Write Control pin (WC

)

) is useful for
protecting the top quarter of the memory (as
shown in Figure 4) from inadvertent erase or write.
The Write Control signal is used to enable

) for an I2C Bus

BUS

V

CC

R

SDA

MASTER

=VIL) or disable (WC=VIH) write instructions to

(WC

SCL

R

C

BUS

L

C

BUS

AI01665

L

the top quarter of the memory area. When
unconnected, the WC
V

, and write operations are allowed.

IL

input is internally read as

DEVICE OPERATION

2

The memory device supports the I

C protocol.
This is summarized in Figure 5, and is compared
with other serial bus protocols in Application Note

AN1001

. Any device that sends data on to the bus

is defined to be a transm itter, and any device that

Figure 4. Me m ory Map of Write C ont rol Areas

1FFh

Write Controlled

Area

180h

FFh

Write Controlled

C0h

80h

40h

00h

Area

M34D32

100h

80h

000h

M34D64

AI03114

3/15

M34D64, M34D32

2

Figure 5. I

C Bus Protocol

SCL

SDA

SCL

SDA

SCL

SDA

START

CONDITION

START

CONDITION

SDA

INPUT

1 23 789

MSB

1 23 789

MSB ACK

SDA

CHANGE

CONDITION

ACK

STOP

STOP

CONDITION

reads the data to be a receiver. The device that
controls the data transfer is k nown as the master,
and the other as the slave. A data transfer can only
be initiated by the mas ter, which wi ll also provide
the serial clock for synchronization. The memory
device is always a slave device in all
communication.

Start Condition

START is identified by a high t o low transition of
the SDA line while the clock, SCL, is s table i n t he
high state. A START condition must precede any
data transfer command. The memory device
continuously monitors (except during a
programming cycle) the SDA and SCL lines for a
START condition, and will not respond unless one
is given.

Stop Condition

STOP is identified by a low to high transition of the
SDA line while the clock SCL is stable in the high

4/15

AI00792

state. A STOP condition terminates
communication between the m emory device and
the bus master. A STOP condition at the end of a
Read command, after (and only after) a NoAck,
forces the memory device into its standby state. A
STOP condition at the end of a Write com mand
triggers the internal EEPROM write cycle.

Acknowledge Bit (ACK)

An acknowledge signal is used to indicate a
successful byte transfer. The bus transmitter,
whether it be master or slave, releases the SDA
bus after sending eight bits of data. During the 9
clock pulse period, the receiver pulls the SDA bus
low to acknowledge the receipt of the eight data
bits.

Data Input

During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, the SDA signal
must be stable during the clock low-to-high

th

M34D64, M34D32

Table 3. Device Select Code

b7 b6 b5 b4 b3 b2 b1 b0

Device Select Code 1 0 1 0 E2 E1 E 0 RW

Note: 1. The most significant bit, b7, is sent firs t.

transition, and the data must change
the SCL line is low .

Memory Addressing

To start communication betwee n the bus master

1

Device Type Identifier Chip Enable RW

only

when

Table 4. Most Significant Byte

b15 b14 b13 b12 b11 b10 b9 b8

Note: 1. b15 to b13 are Don’ t Care on the M34D64 series.

b15 to b12 are Don’t Care on the M34D3 2 series.

and the slave memory, the master must initiate a
START condition. Following this, the master sends
the 8-bit byte, shown in Table 3, on the SDA bus
line (most significant bit first). This consists of the

Table 5. Least Significant Byte

b7 b6 b5 b4 b3 b2 b1 b0

7-bit Device Select Code, and the 1-bit Read/Write
Designator (RW). The Device Select Code is
further subdivided into: a 4-bit Device Type

Identifier, and a 3-bit Chip Enable “Address” (E2,
E1, E0 ) .

To address the memory array, the 4-bit Device
Type Identifier is 1010b.

If all three chip enable inputs are connected, up to
eight memory devices can be connected on a
single I

2

C bus. Each one is given a unique 3-bit
code on its Chip Enable inputs. When the Device
Select Code is received on the SDA bus, the
memory only responds if t he Chip Select Code is
the same as the pattern applied to its Chip Enable
pins.

th

The 8

bit is th e RW bit. This is set to ‘1’ for read
and ‘0’ for write operations. If a match occurs on
the Device Select Code, the corresponding
memory gives an acknowledgment on the SDA
bus during the 9

th

bit time. If the memory does not
match the Device Sel ect Code, it deselects itself
from the bus, and goes into stand-by mode.

There are two modes both for read and write.
These are summarized in Table 6 and described

later. A communication between the m aster and
the slave is ended with a STOP condition.

Each data byte in the m emory has a 16-bit (two
byte wide) address. The Most Significant Byte
(Table 4) is sent first, followed by the Least
significant Byte (Table 5). B its b15 to b0 form the
address of the byte in memory. Bits b15 to b13 are
treated as a Don’t Care bit on the M34D64
memory. Bits b15 to b12 are treated as Don’t Care
bits on the M34D32 memory.

Write Operations

Following a START con dition the ma ster sends a
Device Select Code with the RW

bit set to ’0’, as
shown in Table 6. The memory acknowledges this,
and waits for two address bytes. The memory
responds to each address byte with an
acknowledge bit, and then waits for the data byte.

Writing to the memory may be inhibited if the WC
input pin is taken high. Any write command with
WC

=1 (during a period o f time from the START
condition until the end of the two address bytes)
will not mo dify the cont ents of the top quarter of
the memo r y.

Table 6. Operating Modes

Mode RW bit

Current Address Read 1 X 1 START, Device Select, RW

Random Address Read

Sequential Read 1 X
Byte Write 0 V
Page Write 0 V

Note: 1. X = V

IH

or V

.

IL

0X
1 X reSTART, Device Select, RW

WC

1

IL

IL

Bytes Initial Sequence

1

1 Similar to Current or Random Address Read

≥

1 START, Device Select, RW = ‘0’

32 START, Device Select, RW

≤

START, Device Select, RW

= ‘1’
= ‘0’, Address

= ‘1’

= ‘0’

5/15

M34D64, M34D32

Figure 6. Wri te Mo de S e qu e nces

ACK

BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN

R/W

START

ACK ACK ACK ACK

PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1 DATA IN 2

R/W

START

ACKACK

PAGE WRITE
(cont'd)

DATA IN N

ACK ACK ACK

STOP

STOP

Byte Write

In the Byte Write mode, after the Device Select
Code and the address bytes, the master sends
one data byte. If the addressed lo cation is write
protected by the WC

pin, the location is not
modified. The master terminates the transfer by
generating a STOP condition.

Page Write

The Page Write mode allows u p to 32 by tes to be
written in a single write cycle, provided that they
are all located in the same “row” in the m emory:
that is the most significant memory add ress bits
(b12-b5 for the M34D64 and b11-b5 for the
M34D32) are the same. If more bytes are sent
than will fit up to the end of t he row, a conditi on
known as ‘roll-over’ occurs. Data starts to become
overwritten (in a way not formally specified in this
data sheet).

The master sends from one up to 32 bytes of data,
each of which is acknow ledged by the memory if
the WC

pin is low. If the WC pin is high, the

AI02853

contents of the addressed memory location are
not modified. After each byte is transferred, the
internal byte address counter (the 5 least
significant bits only) is incremented. The transfer is
terminated by the master generating a STOP
condition.

When the master generates a STOP condition

immediately after the Ack bi t (in t he “10

th

bit” time
slot), either at the end of a byte write or a page
write, the internal memory write cycle is triggered.
A STOP condition at any other time does not
trigger the internal write cycle.

During the internal write cycle, the SDA input is
disabled internally, and the device does not
respond to any requests.

Minimizing System Delays by Polling On ACK

During the internal write cycle, the memory
disconnects itself from the bus, and copies the
data from its internal latches to the memory cells.
The maximum write time (t

) is shown in Table 9,

w

but the typical time is shorter. To make use of this,

6/15

Figure 7. Wri te Cy cle Pol l in g Fl owchart usin g A C K

WRITE Cycle

in Progress

START Condition

DEVICE SELECT

with RW = 0

ACK

NO

Returned

M34D64, M34D32

First byte of instruction
with RW = 0 already
decoded by M24xxx

ReSTART

STOP

YES

Next

Operation is

Addressing the

Memory

WRITE Operation

an Ack polling sequence can be used by the
master.

The sequence, as shown in Figure 7, is:
– Initial condition: a Write is in progress.
– Step 1: the m aster issues a START condition

followed by a Device Select Code (the first byte
of the new instruction).

– Step 2: if the memory is bus y with the internal

write cycle, no Ack will be returned and the
master goes back to Step 1. If the memory has
terminated the internal write cycle, it responds
with an Ack, indicating that the memory is ready
to receive the second part of the next instruction
(the first byte of this instruction having been sent
during Step 1).

Read Operations

Read operations are performed independently of
the state of the WC

pin.

YESNO

Send

Byte Address

Proceed

Proceed

Random Address

READ Operation

AI01847

Random Address Read

A dummy write is performed to load the address
into the address counter, as shown in Figure 8.
Then,

without

sending a STOP condition, the
master sends another START condition, and
repeats the Device Select Code, with the RW

set to ‘1’. The memory acknowledges this, and
outputs the contents of the addressed byte. The

not

master must

acknowledge the byte output, and

terminates the transfer with a STOP condition.

Current Address Read

The device has an internal address counter which
is incremented each time a byte is read. For the
Current Address Read m ode, following a START
condition, the master sends a Device Select Code
with the RW

bit set to 1. The memory
acknowledges this, and outputs the byte
addressed by the internal address counter. The
counter is then incremented. The master
terminates the transfer with a STOP condition, as

bit

7/15

M34D64, M34D32

Figure 8. Read Mode Sequences

CURRENT
ADDRESS
READ

RANDOM
ADDRESS
READ

SEQUENTIAL
CURRENT
READ

SEQUENTIAL
RANDOM
READ

ACK

DEV SEL DATA OUT

R/W

START

ACK

DEV SEL * BYTE ADDR BYTE ADDR

R/W

START

ACK ACK ACK NO ACK

DEV SEL DATA OUT 1

R/W

START

ACK ACK ACK

DEV SEL * BYTE ADDR BYTE ADDR

NO ACK

STOP

ACK ACK ACK

DEV SEL * DATA OUT

R/W

START

DATA OUT N

STOP

ACK ACK

DEV SEL * DATA OUT 1

NO ACK

STOP

R/W

START

ACK NO ACK

DATA OUT N

STOP

Note: 1. The seven most significan t bits of the Dev i ce Select Co de of a Random Read (in the 1st and 4th bytes) must b e i d entical.

shown in Figure 8,

without

acknowledging the byte

output.

Sequenti a l Rea d

This mode can be initiated with either a Current
Address Read or a Random Address Read. The

does

master

acknowledge the data byte output in
this case, and the memory continues to output the
next byte in sequence. To terminate the stream of
bytes, the master must
byte output, and

must

not

acknowledge the last

generate a STOP condition.

After the last memory address, the address

counter ‘rolls-over’ and the memory continues to
output data from the start of the memory block.

Acknowledge in Read Mode

In all read modes, the memory waits, after each
byte read, for an acknowledgment during the 9
bit time. If the master does n ot pull the SDA line
low during this time, the memory terminates the
data transfer and switches to its standby state.

START

R/W

AI01105C

The output data comes from consecutive
addresses, with the internal address counter
automatically incremen ted af t er ea ch byt e out put.

th

8/15

M34D64, M34D32

Table 7. DC Characteristics

(T

= 0 to 70 °C or –40 to 85 °C; VCC = 4.5 to 5.5 V or 2.5 to 5.5 V)

A

(T

= 0 to 70 °C or –20 to 85 °C; VCC = 1.8 to 3.6 V 1)

A

Symbol Parameter Test Condition Min. Max. Unit

Input Leakage Current

I

LI

(SCL, SDA)

0V ≤ V

IN

≤ V

CC

± 2 µA

I

I

I

CC1

I

CC2

I

CC3

V

V

V
V

V

Note: 1. This is preliminary data.

Output Leakage Current 0 V ≤ V

LO

Supply Current

CC

Supply Current (Stand-by) V
Supply Current (Stand-by) V

Supply Current (Stand-by) V
Input Low Voltage

IL

(E0-E2, SCL, SDA)
Input High Voltage

IH

(E0-E2, SCL, SDA)
Input Low Voltage (WC) –0.3 0.5 V

ILW

Input High Voltage (WC)

IHW

Output Low

OL

Voltage

V

=5V, fc=400kHz (rise/fall time < 30ns)

CC

V

-W series:

-R series:

=2.5V, fc=400kHz (rise/fall time < 30ns)

CC

V

=1.8V, fc=100kHz (rise/fall time < 30ns)

CC

-W series: I

-R series:

≤ V

OUT

SDA in Hi-Z ± 2 µA

CC,

2mA
1mA

0.8

= VSS or V

IN

= VSS or V

IN

= VSS or V

IN

CC

CC

, V

CC

= 5 V 10 µA

CC

, V

= 2.5 V 2 µA

CC

, V

= 1.8 V

CC

1

1

–0.3 0.3 V

CC

CC

VCC+1 V

VCC+1

0.4 V

0.2

0.7V

0.7V

I

= 3 mA, VCC = 5 V

OL

= 2.1 mA, VCC = 2.5 V 0.4 V

OL

I

= 0.15 mA, VCC = 1.8 V

OL

1

mA

µA

V

CC

V

1

V

Table 8. Input Parameters1 (TA = 25 °C, f = 400 kHz)

Symbol Parameter Test Condition Min. Max. Unit

C

IN

C

IN

Z

WCL

Z

WCH

t

NS

Note: 1. Sampled only, not 100% tested.

Input Capacitance (SDA) 8 pF
Input Capacitance (other pins) 6 pF
WC Input Impedance VIN < V
WC Input Impedance VIN > V

Pulse width ignored
(Input Filter on SCL and SDA)

ILW

IHW

Single glitch 50 ns

50 300 k

500 k

Ω
Ω

9/15

M34D64, M34D32

Table 9. AC Characteristics

M34D64 / M34D32

=1.8 to 3.6 V

V

CC

T

=0 to 70°C or

A

–20 to 85°C

Symbol Alt. Parameter

=4.5 to 5.5 V

V

CC

T

=0 to 70°C or

A

–40 to 85°C

=2.5 to 5.5 V

V

CC

T

=0 to 70°C or

A

–40 to 85°C

Min Max Min Max Min Max

t

t

CH1CH2

t

CL1CL2

2

t

DH1DH2

2

t

DL1DL2

1

t

CHDX

t

CHCL

t

DLCLtHD:STA

t

CLDXtHD:DAT

t

CLCH

t

DXCXtSU:DAT

t

CHDHtSU:STO

t

DHDL

t

CLQV

t

CLQX

t

Note: 1. For a r eS T ART condi tion, or following a writ e cy cl e.

t

3

f

C

W

2. Samp l ed only, not 100% tes ted.

3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.

4. This i s preliminary data.

Clock Rise Time 300 300 1000 ns

R

t

Clock Fall Time 300 300 300 ns

F

t

SDA Rise Time 20 300 20 300 20 1000 ns

R

t

SDA Fall Time 20 300 20 300 20 300 ns

F

Clock High to Input Transition 600 600 4700 ns

SU:STA

t

Clock Pulse Width High 600 600 4000 ns

HIGH

Input Low to Clock Low (START) 600 600 4000 ns
Clock Low to Input Transition 0 0 0 µs

t

Clock Pulse Width Low 1.3 1.3 4.7 µs

LOW

Input Transition to Clock
Transition

100 100 250 ns

Clock High to Input High (STOP) 600 600 4000 ns
Input High to Input Low (Bus

t

BUF

Free)

t

Clock Low to Data Out Valid 200 900 200 900 200 3500 ns

AA

Data Out Hold Time After Clock

t

DH

Low

f

Clock Frequency 400 400 100 kHz

SCL

t

Write Time 10 10 10 ms

WR

1.3 1.3 4.7 µs

200 200 200 ns

Unit

4

Table 10. AC Measurement Conditions

Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing

Reference Voltages

10/15

0.2V

0.3V

50 ns

≤

CC

CC

to 0.8V

to 0.7V

CC

CC

Figure 9. AC Testing Input Output Waveforms

0.8V

0.2V

CC

CC

0.7V

0.3V

AI00825

CC

CC

Figure 10. AC Waveforms

M34D64, M34D32

SCL

SDA IN

SCL

SDA OUT

SCL

tCHCL

tDLCL

tCHDX

START

CONDITION

tCLQV tCLQX

tCLDX

SDA

INPUT

DATA VALID

DATA OUTPUT

SDA

CHANGE

tW

tCLCH

tDXCX

tCHDH

tDHDL

STOP &

BUS FREE

SDA IN

tCHDH

STOP

CONDITION

WRITE CYCLE

tCHDX

START

CONDITION

AI00795B

11/15

M34D64, M34D32

Table 11. Ordering Information Scheme

Example: M34D64 –W MN 1 T

Memory Capacity Option

64 64 Kbit (8K x 8) T Tape and Reel Packing
32 32 Kbit (4K x 8)

Operating Voltage

blank 4.5 V to 5.5 V
W 2.5 V to 5.5 V

2

1.8 V to 3.6 V

R

Package Temperature Range

1

BN PSDIP8 (0.25 mm frame)
MN SO8 (150 mil width) 6 –40 °C to 85 °C

Note: 1. Temperature ra nge availabl e only on re quest.

2. The -R version (V

range 1.8 V t o 3. 6 V) only avail able in temperature ra nges 5 or 1.

CC

0 °C to 70 °C

1

5 –20 °C to 85 °C

ORDERING INFORMATION

Devices are shipped from the factory with the
memory content set at all 1s (FFh).

The notation used for the device number is as
shown in Table 11. For a list of available options
(speed, package, etc.) or for further information on
any aspect of this device, please contact your
nearest ST Sales Office.

12/15

Table 12. PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame

mm inches

Symb.

Typ. Min. Max. Typ. Min. Max.

A 3.90 5.90 0.154 0.232

A1 0 .49 – 0.019 –

A2 3 .30 5.30 0.1 30 0.209

B 0.36 0.56 0.014 0.022

B1 1 .15 1.65 0.0 45 0.065

C 0.20 0.36 0.008 0.014
D 9.20 9.90 0.362 0.390

E 7.62 – – 0. 300 – –
E1 6 .00 6.70 0.2 36 0.264
e1 2.54 – – 0. 100 – –
eA 7 .80 – 0.307 –
eB 10.00 0.394

L 3.00 3.80 0.118 0.150

N8 8

M34D64, M34D32

Figure 11. PSDIP8 (BN)

Note: 1. Drawing is not to scale.

A2

A1AL

B

N

1

e1

B1

D

E1 E

eA
eB

C

PSDIP-a

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M34D64, M34D32

Table 13. SO8 - 8 lead Plastic Small Outline, 150 mils body width

Symb.

Typ. Min. Max. Typ. Min. Max.

A 1.35 1 .75 0.053 0.069
A1 0 .10 0.25 0.0 04 0.010

B 0.33 0 .51 0.013 0.020

C 0.19 0.25 0.007 0.010

D 4.80 5.00 0.189 0.197

E 3.80 4 .00 0.150 0.157

e 1.27 – – 0.050 – –

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020
L 0.40 0.90 0.016 0.035

α

N8 8

CP 0.10 0.004

mm inches

0° 8° 0° 8°

Figure 12. SO8 narrow (MN)

B

SO-a

Note: 1. Drawing is not to scale.

h x 45˚

A

e

D

N

1

CP

E

H

C

LA1 α

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M34D64, M34D32

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