Datasheet M30612M8A-XXXGP, M30612M8A-XXXFP, M30612M4A-XXXGP, M30612M4A-XXXFP, M30612E4GP Datasheet (Mitsubishi)
...Page 1
Mitsubishi microcomputers
M16C / 61 Group
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
The M16C/61 group of single-chip microcomputers are built using the high-performance silicon gate
CMOS process using a M16C/60 Series CPU core and are packaged in a 100-pin plastic molded QFP.
These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, they are capable of executing instructions at high
speed. They also feature a built-in multiplier and DMAC, making them ideal for controlling office, communications, industrial equipment, and other high-speed processing applications.
The M16C/61 group includes a wide range of products with different internal memory types and sizes and
various package types.
Features
• Memory capacity............................................ROM (See Figure 1.1.4. ROM Expansion)
RAM 4K to 10K bytes
• Shortest instruction execution time................ 100ns (f(XIN)=10MHZ)
• Supply voltage ............................................... 4.0 to 5.5V (f(XIN)=10MHZ)
2.7 to 5.5V (f(XIN)=7MHZ with software one-wait)
• Low power consumption ................................18mW ( f(XIN)=7MHZ, with software one-wait, VCC = 3V)
• Interrupts........................................................20 internal and 5 external interrupt sources, 4 software
interrupt sources; 7 levels (including key input interrupt)
• Multifunction 16-bit timer................................5 output timers + 3 input timers
• Serial I/O (UART or clock synchronous)........ 3 channels
• DMAC ............................................................ 2 channels (trigger: 16 sources)
• A-D converter.................................................10 bits X 8 channels
(Expandable up to 10 channels)
• D-A converter.................................................8 bits X 2 channels
• CRC calculation circuit...................................1 circuit
• Watchdog timer..............................................1 line
• Programmable I/O .........................................87 lines
• Input port........................................................
• Memory expansion ........................................Available (to a maximum of 1M bytes)
• Chip select output ..........................................4 lines
• Clock generating circuit .................................2 built-in clock generation circuits
1 line (P85 shared with NMI pin)
(built-in feedback resistor, and external ceramic or quartz oscillator)
_______
Applications
Audio, cameras, office equipment, communications equipment, portable equipment
------Table of Contents------
Central Processing Unit (CPU) .....................11
Reset.............................................................14
Processor Mode............................................ 19
Clock Generating Circuit ...............................30
Protection......................................................39
Interrupts.......................................................40
Watchdog Timer............................................59
DMAC ...........................................................61
Timer.............................................................70
Serial I/O .......................................................87
A-D Converter .............................................114
D-A Converter .............................................124
CRC Calculation Circuit ..............................126
Programmable I/O Ports .............................128
Electrical Characteristics.............................142
1
Page 2
Description
Pin Configuration
Figures 1.1.1 and 1.1.2 show the pin configurations (top view).
PIN CONFIGURATION (top view)
)
8
/D
0
P1
9
/D
1
P1
10
/D
2
P1
11
/D
3
P1
12
/D
4
P1
13
/D
5
P1
14
/D
6
P1
15
/D
7
P1
/-)
0
(/D
0
/A
0
P2
)
0
/D
1
(/D
1
/A
1
P2
)
1
/D
2
(/D
2
/A
2
P2
)
2
/D
3
(/D
3
/A
3
P2
3
/D
4
(/D
4
/A
4
P2
)
4
/D
5
(/D
5
/A
5
P2
)
5
/D
6
(/D
6
/A
6
P2
)
6
/D
7
(/D
7
/A
7
P2
Vss
)
7
(/-/D
8
/A
0
P3
Vcc
9
/A
1
P3
10
/A
2
P3
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
14
/A
6
P3
15
/A
7
P3
16
/A
0
P4
17
/A
1
P4
18
/A
2
P4
19
/A
3
P4
11
/A
3
P3
12
/A
4
P3
13
/A
5
P3
P07/D7
P06/D6
P05/D5
P04/D4
P03/D3
P02/D2
P01/D1
P00/D0
P107/AN7/KI3
P106/AN6/KI2
P105/AN5/KI1
P104/AN4/KI0
P103/AN3
P102/AN2
P101/AN1
AVSS
P100/AN0
VREF
AVcc
P97/ADTRG
70
11
COUT
/X
6
P8
68
69
13
12
OUT
X
RESET
67
66
14
15
IN
SS
X
V
62
63
64
65
17
16
CC
V
/NMI
5
P8
18
2
/INT
4
P8
19
1
/INT
3
P8
61
20
0
/INT
2
P8
60
21
IN
/TA4
1
P8
59
22
OUT
/TA4
0
P8
58
23
IN
/TA3
7
P7
57
24
OUT
/TA3
6
P7
56
25
IN
/TA2
5
P7
55
26
OUT
/TA2
4
P7
54
27
IN
/TA1
2
/RTS
2
/CTS
3
P7
51
52
53
P44/CS0
P45/CS1
P46/CS2
P47/CS3
P50/WRL/WR
P51/WRH/BHE
2/RD
P5
P53/BCLK
P54/HLDA
P55/HOLD
P56/ALE
P57/RDY/CLKOUT
P60/CTS0/RTS0
P61/CLK0
P62/RxD0
P63/TXD0
P64/
CTS1/RTS1/CTS0/CLKS
P65/CLK1
P66/RxD1
P67/TXD1
Package: 100P6S-A
28
OUT
/TA1
2
/CLK
2
P7
30
29
(Note)
(Note)
IN
OUT
/TA0
2
/TA0
2
/RxD
1
/TxD
0
P7
P7
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
1
79
80
77
78
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
00
1
2
1
4
3
0
1
/DA
/DA
3
4
/ANEX1
/ANEX0
P9
P9
6
5
P9
P9
73
74
75
76
71
72
M16C/61 Group
8
7
6
5
IN
/TB2
2
P9
IN
/TB1
1
P9
IN
/TB0
0
P9
9
BYTE
CNVss
10
CIN
/X
7
P8
Note: P70 and P71 are N channel open-drain output pin.
Figure 1.1.1. Pin configuration (top view)
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Page 3
Description
PIN CONFIGURATION (top view)
P107/AN7/KI
P106/AN6/KI
P105/AN5/KI
P104/AN4/KI
P95/ANEX0
P12/D
P103/AN
P102/AN
P101/AN
P100/AN
P97/AD
P9
6
/ANEX1
P11/D
P10/D
P07/D
P06/D
P05/D
P04/D
P03/D
P02/D
P01/D
P0
0/D0
AV
V
AVcc
REF
TRG
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
)
)
)
)
)
)
)
2
1
0
/D
/D
/D
/-)
3
2
1
0
(/D
(/D
(/D
12
11
/D
/D
4
3
P1
P1
74
75
10
SS
76
9
77
8
78
7
79
6
80
5
81
4
82
3
83
2
84
1
85
86
3
87
88
2
89
1
90
0
91
3
92
2
93
1
94
95
0
96
97
98
99
100
2
1
(/D
3
2
1
15
14
13
0
/A
/A
/A
/A
/D
/D
/D
5
P1
73
6
P1
72
7
P1
71
0
P2
70
1
P2
3
2
P2
P2
67
68
69
M16C/61 Group
9
8
7
6
5
4
3
3
/D
4
(/D
4
/A
4
P2
66
10
4
/D
5
(/D
5
/A
5
P2
65
11
5
/D
6
(/D
6
/A
6
P2
64
12
6
/D
7
(/D
7
/A
7
P2
63
13
)
7
(/-/D
9
8
/A
/A
1
0
P3
Vcc
P3
Vss
62
59
60
61
15
14
17
16
10
/A
2
P3
58
18
11
/A
3
P3
57
19
12
/A
4
P3
56
20
13
/A
5
P3
55
21
14
/A
6
P3
54
22
15
/A
7
P3
53
23
16
/A
0
P4
52
24
17
/A
1
P4
51
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P42/A
18
P43/A
19
P4
4
/CS0
P45/CS1
P46/CS2
P47/CS3
P50/WRL/WR
P51/WRH/BHE
P5
2
/RD
P53/BCLK
P54/HLDA
P5
5
/HOLD
P56/ALE
P57/RDY/CLK
P60/CTS0/RTS
P61/CLK
0
P62/RxD
0
P63/TXD
0
P6
4/
CTS1/RTS1/CTS0/CLKS
P65/CLK
1
P66/RxD
1
P67/TXD
1
P70/TxD2/TA0
P71/RxD2/TA0
P72/CLK2/TA1
OUT
0
OUT
IN
OUT
1
(Note)
(Note)
0
1
/DA
4
P9
/DA
3
P9
IN
/TB2
2
P9
IN
/TB1
1
P9
IN
/TB0
0
P9
BYTE
CNVss
CIN
/X
7
P8
COUT
/X
6
P8
Note: P70 and P71 are N channel open-drain output pin.
Figure 1.1.2. Pin configuration (top view)
OUT
X
RESET
IN
CC
SS
X
V
V
/NMI
5
P8
/INT
4
P8
/INT
3
P8
/INT
2
P8
IN
/TA4
1
P8
OUT
/TA4
0
P8
IN
/TA3
7
P7
OUT
/TA3
6
P7
IN
/TA2
5
P7
OUT
/TA2
4
P7
IN
/TA1
2
/RTS
2
Package: 100P6Q-A
/CTS
3
0
1
2
P7
3
Page 4
Description
A
A
AAAA
A
A
Block Diagram
Figure 1.1.3 is a block diagram of the M16C/61 group.
Block diagram of the M16C/61 group
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
8
I/O ports
Internal peripheral functions
Timer TA0 (16 bits)
Timer TA1 (16 bits)
Timer TA2 (16 bits)
Timer TA3 (16 bits)
Timer TA4 (16 bits)
Timer TB0 (16 bits)
Timer TB1 (16 bits)
Timer TB2 (16 bits)
Watchdog timer
D-A converter
(8 bits X 2 channels)
Note 1: ROM size depends on MCU type.
Note 2: RAM size depends on MCU type.
Note 3: One of serial I/O can use for SIM interface.
Port P08Port P18Port P28Port P38Port P48Port P58Port P6
Timer
(15 bits)
DMAC
(2 channels)
A-D converter
(10 bits X 8 channels
Expandable up to 10 channels)
UART/clock synchronous SI/O
(8 bits X 3channels) (Note 3)
CRC arithmetic circuit (CCITT )
(Polynomial : X
M16C/60 series16-bit CPU core
Registers
R1H R1L
R1H R1L
R2
R2
R3
R3
A0
A0
A1
A1
FB
FB
SB FLG
16+X12+X5
R0LR0H
R0LR0H
+1)
Program counter
PC
Vector table
INTB
Stack pointer
ISP
USP
System clock generator
X
IN-XOUT
X
CIN-XCOUT
Memory
ROM
(Note 1)
AAAA
RAM
AAAA
(Note 2)
Multiplier
AA
Port P7
8
Port P8
7
Port P8
5
Port P9
8
Port P10
8
4
Figure 1.1.3. Block diagram of M16C/61 group
Page 5
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Performance Outline
Table 1.1.1 is a performance outline of M16C/61 group.
Table 1.1.1. Performance outline of M16C/61 group
Item Performance
Number of basic instructions 91 instructions
Shortest instruction execution time 100ns(f(XIN)=10MHZ)
Memory ROM (See the Figure 4. ROM Expansion)
capacity RAM 4K to 10K bytes
I/O port P0 to P10 (except P85) 8 bits x 10, 7 bits x 1
Input port P85 1 bit x 1
Multifunction TA0, TA1, TA2, TA3, TA4 16 bits x 5
timer TB0, TB1, TB2 16 bits x 3
Serial I/O UART0, UART1, UART2 (UART or clock synchronous) x 3
A-D converter 10 bits x (8 + 2) channels
D-A converter 8 bits x 2
DMAC 2 channels (trigger: 16 sources)
CRC calculation circuit CRC - CCITT
Watchdog timer 15 bits x 1 (with prescaler)
Interrupt
Clock generating circuit 2 built-in clock generation circuits
Supply voltage 4.0 to 5.5V (f(XIN ) = 10MHZ)
Power consumption
I/O I/O withstand voltage 5V
characteristics Output current 5mA
Memory expansion Available (to a maximum of 1M bytes)
Device configuration CMOS silicon gate
Package 100-pin plastic mold QFP
20 internal and 5 external sources, 4 software sources, 7 levels
(built-in feedback resistor, and external ceramic or quartz oscillator)
2.7 to 5.5V(f(XIN)=7MHZ with software one-wait)
18mW (f(XIN) = 7MHZ with software one-wait,VCC = 3V)
Mitsubishi microcomputers
M16C / 61 Group
5
Page 6
Mitsubishi microcomputers
M16C / 61 Group
Description
Mitsubishi plans to release the following products in the M16C/61 group:
(1) Support for mask ROM version, external ROM version, one-time PROM version, and EPROM version
(2) ROM capacity
(3) Package
100P6S-A : Plastic molded QFP (mask ROM version and one-time PROM version)
100P6Q-A : Plastic molded QFP (mask ROM version and one-time PROM version)
100D0 : Ceramic LCC (EPROM version)
ROM
Size(Byte)
External
ROM
128 K
96 K
M30610MCA-XXXFP/GP
M30612MCA-XXXFP/GP
M30610MAA-XXXFP/GP
M30612MAA-XXXFP/GP
M30610ECFP/GP M30610ECFS
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M30612SAFP/GP
M30610SAFP/GP
64 K
32 K
M30610M8A-XXXFP/GP
M30612M8A-XXXFP/GP
M30612M4A-XXXFP/GP
M30612E4FP/GP
Mask ROM version One-time PROM version EPROM version External ROM version
Figure 1.1.4. ROM expansion
The M16C/61 group products currently supported are listed in Table 2.
Table 1.1.2. M16C/61 group
RAM capacityROM capacity Package type RemarksType No
M30612M4A-XXXFP
M30612M4A-XXXGP 100P6Q-A
M30610M8A-XXXFP
M30610M8A-XXXGP
M30612M8A-XXXFP
M30612M8A-XXXGP 100P6Q-A
M30610MAA-XXXFP
M30610MAA-XXXGP 100P6Q-A
M30612MAA-XXXFP
M30612MAA-XXXGP
M30610MCA-XXXFP
M30610MCA-XXXGP
M30612MCA-XXXFP
M30612MCA-XXXGP 100P6Q-A
M30612E4FP 100P6S-A
M30612E4GP 100P6Q-A
M30610ECFP
M30610ECGP 100P6Q-A
M30610SAFP 100P6S-A
M30610SAGP 100P6Q-A
M30612SAFP 100P6S-A
M30612SAGP 100P6Q-A
Note: Do not use the EPROM version for mass production, because it is a tool for program development
(for evaluation).
32K byte 4K byte
10K byte
64K byte
4K byte
10K byte
96K byte
4K byte
10K byte
128K byte
5K byte
32K byte 4K byte
128K byte 10K byte
10K byteM30610ECFS 128K byte 100D0
10K byte
4K byte
100P6S-A
100P6S-A
100P6Q-A
100P6S-A
100P6S-A
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
100P6S-A
100P6S-A
Mask ROM version
One-time PROM version
EPROM version (Note)
External ROM version
Apr. 1999
6
Page 7
Description
Type No. M 3 0 6 1 2 M 4 – X X X F P
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Package type:
FP : Package 100P6S-A
GP : 100P6Q-A
FS : 100D0
ROM No.
Omitted for blank one-time PROM version
and EPROM version
ROM capacity:
4 : 32K bytes A : 96K bytes
8 : 64K bytes C : 128K bytes
Memory type:
M : Mask ROM version
E : EPROM or one-time PROM version
S : External ROM version
Figure 1.1.5. Type No., memory size, and package
Shows RAM capacity, pin count, etc
(The value itself has no specific meaning)
M16C/61 Group
M16C Family
7
Page 8
Pin Description
Pin Description
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin name
VCC, VSS
CNVSS
RESET
XIN
XOUT
BYTE
AV
CC
AVSS
VREF
Signal name
Power supply
input
CNV
SS
Reset input
Clock input
Clock output
External data
bus width
select input
Analog power
supply input
Analog power
supply input
Reference
voltage input
I/O type
Input
Input
Input
Output
Input
Input
Function
Supply 2.7 to 5.5 V to the V
CC pin. Supply 0 V to the VSS pin.
This pin switches between processor modes. Connect it to the
V
SS pin when operating in single-chip or memory expansion mode.
Connect it to the V
CC pin when in microprocessor mode.
A “L” on this input resets the microcomputer.
These pins are provided for the main clock generating circuit.Connect
a ceramic resonator or crystal between the X
use an externally derived clock, input it to the X
X
OUT pin open.
IN and the XOUT pins. To
IN pin and leave the
This pin selects the width of an external data bus. A 16-bit width is
selected when this input is “L”; an 8-bit width is selected when this
input is “H”. This input must be fixed to either “H” or “L”. When
operating in single-chip mode,connect this pin to V
SS.
This pin is a power supply input for the A-D converter. Connect this
pin to V
CC.
This pin is a power supply input for the A-D converter. Connect this
pin to V
SS.
This pin is a reference voltage input for the A-D converter.
P00 to P07
D0 to D7
P10 to P17
D8 to D15
P20 to P27
A0 to A7
A0/D0 to
A
7/D7
A0, A1/D0
to A7/D6
P30 to P37
A8 to A15
A8/D7,
A
9 to A15
P40 to P47
I/O port P0
I/O port P1
I/O port P2
I/O port P3
I/O port P4
Input/output
Input/output
Input/output
Input/output
Input/output
Output
Input/output
Output
Input/output
Input/output
Output
Input/output
Output
Input/output
This is an 8-bit CMOS I/O port. It has an input/output port direction
register that allows the user to set each pin for input or output
individually. When used for input in single-chip mode, the port can be
set to have or not have a pull-up resistor in units of four bits by
software. In memory expansion and microprocessor modes, selection
of the internal pull-resistor is not available.
When set as a separate bus, these pins input and output data (D
0–D7).
This is an 8-bit I/O port equivalent to P0.
When set as a separate bus, these pins input and output data
(D8–D15).
This is an 8-bit I/O port equivalent to P0.
These pins output 8 low-order address bits (A
0–A7).
If the external bus is set as an 8-bit wide multiplexed bus, these pins
input and output data (D
(A
0–A7) separated in time by multiplexing.
0–D7) and output 8 low-order address bits
If the external bus is set as a 16-bit wide multiplexed bus, these pins
input and output data (D
in time by multiplexing. They also output address (A
0–D6) and output address (A1–A7) separated
0).
This is an 8-bit I/O port equivalent to P0.
These pins output 8 middle-order address bits (A
8–A15).
If the external bus is set as a 16-bit wide multiplexed bus, these pins
input and output data (D
by multiplexing. They also output address (A
7) and output address (A8) separated in time
9–A15).
This is an 8-bit I/O port equivalent to P0.
CS
0 to CS3,
A
16 to A19
Output
Output
These pins output CS0–CS3 signals and A16–A19. CS0–CS3 are chip
select signals used to specify an access space. A
16–A19 are 4 high-
order address bits.
8
Page 9
Pin Description
Pin Description
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Signal name FunctionPin name I/O type
0 to P57
P5
WRL / WR,
WRH / BHE,
RD,
BCLK,
HLDA,
HOLD,
ALE,
RDY
P60 to P67
P70 to P77
I/O port P5 Input/output
Output
Output
Output
Output
Output
Input
Output
Input
I/O port P6
I/O port P7
Input/output
Input/output
This is an 8-bit I/O port equivalent to P0. In single-chip mode, P57 in
this port outputs a divide-by-8 or divide-by-32 clock of X
the same frequency as X
CIN as selected by software.
IN or a clock of
Output WRL, WRH (WR and BHE), RD, BCLK, HLDA, and ALE
signals. WRL and WRH, and BHE and WR can be switched using
software control.
WRL, WRH, and RD selected
With a 16-bit external data bus, data is written to even addresses
when the WRL signal is “L” and to the odd addresses when the WRH
signal is “L”. Data is read when RD is “L”.
WR, BHE, and RD selected
Data is written when WR is “L”. Data is read when RD is “L”. Odd
addresses are accessed when BHE is “L”. Use this mode when using
an 8-bit external data bus.
While the input level at the HOLD pin is “L”, the microcomputer is
placed in the hold state. While in the hold state, HLDA outputs a “L”
level. ALE is used to latch the address. While the input level of the
RDY pin is “L”, the microcomputer is in the ready state.
This is an 8-bit I/O port equivalent to P0. When used for input in singlechip, memory expansion, and microprocessor modes, the port can be
set to have or not have a pull-up resistor in units of four bits by
software. Pins in this port also function as UART0 and UART1 I/O pins
as selected by software.
This is an 8-bit I/O port equivalent to P6 (P7
open-drain output). Pins in this port also function as timer A
0 and P71 are N channel
0–A3 or
UART2 I/O pins as selected by software.
P8
0 to P84,
P8
6,
P87,
5
P8
P90 to P97
P100 to P107
I/O port P8
I/O port P8
I/O port P9
I/O port P10
5
Input/output
Input/output
Input/output
Input
Input/output
Input/output
P80 to P84, P86, and P87 are I/O ports with the same functions as P6.
Using software, they can be made to function as the I/O pins for timer
A4 and the input pins for external interrupts. P8
6 and P87 can be set
using software to function as the I/O pins for a sub clock generation
circuit. In this case, connect a quartz oscillator between P8
pin) and P8
7 (XCIN pin). P85 is an input-only port that also functions
6 (XCOUT
for NMI. The NMI interrupt is generated when the input at this pin
changes from “H” to “L”. The NMI function cannot be cancelled using
software. The pull-up cannot be set for this pin.
This is an 8-bit I/O port equivalent to P6. Pins in this port also function
as Timer B0–B2 input pins, D-A converter output pins, A-D converter
extended input pins, or A-D trigger input pins as selected by software.
This is an 8-bit I/O port equivalent to P6. Pins in this port also function
as A-D converter input pins. Furthermore, P10
4–P107 also function as
input pins for the key input interrupt function.
9
Page 10
Mitsubishi microcomputers
A
A
M16C / 61 Group
Memory
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Operation of Functional Blocks
The M16C/61 group accommodates certain units in a single chip. These units include ROM and RAM to
store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations.
Also included are peripheral units such as timers, serial I/O, D-A converter, DMAC, CRC calculation circuit,
A-D converter, and I/O ports.
The following explains each unit.
Memory
Figure 1.4.1 is a memory map of the M16C/61 group. The address space extends the 1M bytes from
address 0000016 to FFFFF16. From FFFFF16 down is ROM. For example, in the M30612M4A-XXXFP,
there is 32K bytes of internal ROM from F800016 to FFFFF16. The vector table for fixed interrupts such as
the reset and NMI are mapped to FFFDC16 to FFFFF16. The starting address of the interrupt routine is
stored here. The address of the vector table for timer interrupts, etc., can be set as desired using the
internal register (INTB). See the section on interrupts for details.
From 0040016 up is RAM. For example, in the M30612M4A-XXXFP, 4K bytes of internal RAM is mapped
to the space from 0040016 to 013FF16. In addition to storing data, the RAM also stores the stack used when
calling subroutines and when interrupts are generated.
The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for peripheral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Any part of the SFR area that is not
occupied is reserved and cannot be used for other purposes.
The special page vector table is mapped to FFE0016 to FFFDB16. If the starting addresses of subroutines
or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions
can be used as 2-byte instructions, reducing the number of program steps.
In memory expansion mode and microprocessor mode, a part of the spaces are reserved and cannot be
used. For example, in the M30612M4A-XXXFP, the following spaces cannot be used.
• The space between 0140016 and 03FFF16
• The space between D000016 and F7FFF16 (When external area do not expand in memory expansion
mode)
Do not expand the external area in single chip mode. A part of internal memory cannot be used depending
on MCU.
_______
Type No. Address YYYYY
M30610M8A
M30610MAA
M30610MCA/EC
M30612M4A/E4
M30612M8A
M30612MAA
M30612MCA
Address XXXXX
02BFF
02BFF
02BFF
013FF
013FF
013FF
017FF
Figure 1.4.1. Memory map
10
00000
16
00400
XXXXX
04000
16
F0000
E8000
E0000
F8000
F0000
E8000
E0000
16
16
D0000
16
16
16
16
16
16
16
YYYYY
FFFFF
Note 1: During memory expansion and microprocessor modes, can not be used.
Note 2: When external area do not expand in memory expansion mode.
16
16
16
16
16
16
16
16
SFR area
For details, see Figure
1.7.1 and Figure 1.7.2
16
Internal RAM area
16
Internal reserved
area (Note 1)
AAA
External area
AAA
Internal reserved
area (Note 2)
16
Internal ROM area
16
FFE00
FFFDC
FFFFF
16
Special page
vector table
16
Undefined instruction
BRK instruction
Address match
Single step
Watchdog timer
16
Overflow
DBC
NMI
Reset
Page 11
Mitsubishi microcomputers
A
M16C / 61 Group
CPU
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Central Processing Unit (CPU)
The CPU has a total of 13 registers shown in Figure 1.5.1. Seven of these registers (R0, R1, R2, R3, A0,
A1, and FB) come in two sets; therefore, these have two register banks.
R0
R1
R2
R3
A0
A1
FB
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
b15
b15
b15
b15
b15
b15
b15
b8 b7 b0
H
b8 b7 b0
H
L
b19
L
PC
b0
Program counter
Data
b0
registers
INTB
b19
H
b0
L
Interrupt table
register
b0
b0
b15
USP
b15
ISP
b0
User stack pointer
b0
Interrupt stack
pointer
Address
b0
b0
registers
Frame base
registers
SB
FLG
b15
b15
b0
Static base
register
b0
Flag register
IPL
CDZSBOIU
Note: These registers consist of two register banks.
Figure 1.5.1. Central processing unit register
(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and
arithmetic/logic operations.
Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H),
and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can
use as 32-bit data registers (R2R0/R3R1).
(2) Address registers (A0 and A1)
Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data
registers. These registers can also be used for address register indirect addressing and address register
relative addressing.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
11
Page 12
Mitsubishi microcomputers
M16C / 61 Group
CPU
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) Frame base register (FB)
Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
(4) Program counter (PC)
Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.
(5) Interrupt table register (INTB)
Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector
table.
(6) Stack pointer (USP/ISP)
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag).
This flag is located at the position of bit 7 in the flag register (FLG).
(7) Static base register (SB)
Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
(8) Flag register (FLG)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.5.2 shows the flag
register (FLG). The following explains the function of each flag:
• Bit 0: Carry flag (C flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag)
This flag enables a single-step interrupt.
When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is
cleared to “0” when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
• Bit 3: Sign flag (S flag)
This flag is set to
• Bit 4: Register bank select flag (B flag)
This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is
selected when this flag is “1”.
• Bit 5: Overflow flag (O flag)
This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
• Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to
“0” when the interrupt is acknowledged.
“1”
when an arithmetic operation resulted in a negative value; otherwise, cleared to
“0”
.
12
Page 13
Mitsubishi microcomputers
M16C / 61 Group
CPU
• Bit 7: Stack pointer select flag (U flag)
Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected
when this flag is “1”.
This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software
interrupt Nos. 0 to 31 is executed.
• Bits 8 to 11: Reserved area
• Bits 12 to 14: Processor interrupt priority level (IPL)
Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight
processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt
is enabled.
• Bit 15: Reserved area
The C, Z, S, and O flags are changed when instructions are executed. See the software manual for
details.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
IPL
b0b15
Flag register (FLG)
CDZSBOIU
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Figure 1.5.2. Flag register (FLG)
13
Page 14
Mitsubishi microcomputers
M16C / 61 Group
Reset
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset.
(See “Software Reset” for details of software resets.) This section explains on hardware resets.
When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the
reset pin level “L” (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to the “H”
level while main clock is stable, the reset status is cancelled and program execution resumes from the
address in the reset vector table.
Figure 1.6.1 shows the example reset circuit. Figure 1.6.2 shows the reset sequence.
RESET
Example when V
V
CC
Figure 1.6.1. Example reset circuit
X
IN
More than 20 cycles are needed
Microprocessor
mode BYTE = “H”
RESET
BCLK
Address
RD
BCLK 24cycles
CC
= 5V
5V
V
CC
0V
5V
RESET
0V
4.0V
0.8V
.
Content of reset vector
FFFFC
16
FFFFD
16
FFFFE
16
WR
CS0
Microprocessor
mode BYTE = “L”
Address
RD
WR
CS0
Single chip
mode
Address
Figure 1.6.2. Reset sequence
14
FFFFC
FFFFC
16
16
FFFFE
FFFFE
16
Content of reset vector
16
Content of reset vector
Page 15
Reset
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.6.1 shows the statuses of the other pins while the RESET pin level is “L”. Figure 1.6.3 shows the
____________
internal status of the microcomputer immediately after the reset is cancelled.
Table 1.6.1. Pin status when RESET pin level is “L”
____________
Status
Pin name
P0
P1
P2, P3, P4
P44
P45 to P47
P50
P51
P52
P53
0 to P43
CNVSS = VSS
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
BYTE = VSS BYTE = VCC
Data input (floating)
Data input (floating)
Address output (undefined)
CS0 output (“H” level is output)
Input port (floating)
WR output (“H” level is output)
BHE output (undefined)
RD output (“H” level is output)
BCLK output
CNVSS = VCC
Data input (floating)
Input port (floating)
Address output (undefined)
CS0 output (“H” level is output)
Input port (floating)
WR output (“H” level is output)
BHE output (undefined)
RD output (“H” level is output)
BCLK output
P54
P55
P56
P57
P6, P7, P80 to P84,
6, P87, P9, P10
P8
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
HLDA output (The output value
depends on the input to the
HOLD pin)
HOLD input (floating)
ALE output (“L” level is output)
RDY input (floating)
Input port (floating) Input port (floating)
HLDA output (The output value
depends on the input to the
HOLD pin)
HOLD input (floating)
ALE output (“L” level is output)
RDY input (floating)
15
Page 16
Reset
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Processor mode register 0 (Note)
(2) Processor mode register 1
(3) System clock control register 0
(4) System clock control register 1
(5) Chip select control register
(6) Address match interrupt enable register
(7) Protect register
(8) Watchdog timer control register
(9) Address match interrupt register 0
(10)Address match interrupt register 1
(11)DMA0 control register
(12)DMA1 control register
Bus collision detection interrupt control
(13)
register
(14)DMA0 interrupt control register
(15)DMA1 interrupt control register
(16)Key input interrupt control register
(17)A-D conversion interrupt control register
(18)UART2 transmit interrupt control register
(19)UART2 receive interrupt control register
(20)UART0 transmit interrupt control register
(21)UART0 receive interrupt control register
(22)UART1 transmit interrupt control register
(23)UART1 receive interrupt control register
(24)Timer A0 interrupt control register
(25)Timer A1 interrupt control register
(26)Timer A2 interrupt control register
(27)Timer A3 interrupt control register
(28)Timer A4 interrupt control register
(29)Timer B0 interrupt control register
(30)Timer B1 interrupt control register
(31)Timer B2 interrupt control register
(32)INT0 interrupt control register
(33)INT1 interrupt control register
(34)INT2 interrupt control register
(35)UART2 transmit/receive mode register
(36)UART2 transmit/receive control register 0
(37)UART2 transmit/receive control register 1
(38)Count start flag
(39)
One-shot start flag(40)
Trigger select flag
(41)
Up-down flag(42)
(0004
(0005
(0006
(0007
(0008
(0009
(000A
(000F
(0010
(0011
(0012
(0014
(0015
(0016
(002C
(003C
(004A
(004B
(004C
(004D
(004E
(004F
(0050
(0051
(0052
(0053
(0054
(0055
(0056
(0057
(0058
(0059
(005A
(005B
(005C
(005D
(005E
(005F
(0378
(037C
(037D
(0380
(0381
(0382
(0383
(0384
16)···
16)···
00
16)···
0000100
1
16)···
00010000
16)···
00000010
16)···
16)···
16)···
00?0????
16)···
16)···
16)···
16)···
16)···
16)···
16)···
0000?00
0
16)···
00000?00
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···Clock prescaler reset flag
0
16)···
0
000000
16)···
16)···
00
00
00
16
00
0016
0016
0
0016
0016
0
?
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 000
? 000
? 000
0016
0016
0016
0016
0
0
0
0 0 0
0 0 0
0 0 0
00000001
01000000
Timer A0 mode register(43)
0
Timer A1 mode register(44)
Timer A2 mode register
(45)
Timer A3 mode register(46)
(47)
0
0
Timer B0 mode register(48)
Timer B1 mode register(49)
Timer B2 mode register(50)
UART0 transmit/receive mode register(51)
UART0 transmit/receive control register 0(52)
UART0 transmit/receive control register 1(53)
UART1 transmit/receive mode register(54)
UART1 transmit/receive control register 0(55)
UART1 transmit/receive control register 1(56)
UART transmit/receive control register 2(57)
DMA0 cause select register(58)
DMA1 cause select register(59)
A-D control register 2(60)
A-D control register 0(61)
A-D control register 1(62)
D-A control register(63)
Port P0 direction register(64)
Port P1 direction register(65)
Port P2 direction register(66)
Port P3 direction register(67)
Port P4 direction register(68)
Port P5 direction register(69)
Port P6 direction register(70)
Port P7 direction register(71)
Port P8 direction register(72)
Port P9 direction register(73)
Port P10 direction register(74)
Pull-up control register 0(75)
Pull-up control register 1(76)
Pull-up control register 2(77)
Data registers (R0/R1/R2/R3)(78)
Address registers (A0/A1)(79)
Frame base register (FB)(80)
Interrupt table register (INTB)(81)
User stack pointer (USP)(82)
Interrupt stack pointer (ISP)(83)
Static base register (SB)(84)
(85)
Flag register (FLG)
x : Nothing is mapped to this bit
? : Undefined
(0396
(0397
(0398
(0399
(039A
(039B
(039C
(039D
(03A0
(03A4
(03A5
(03A8
(03AC
(03AD
(03B0
(03B8
(03BA
(03D4
(03D6
(03D7
(03DC
(03E2
(03E3
(03E6
(03E7
(03EA
(03EB
(03EE
(03EF
(03F2
(03F3
(03F6
(03FC
(03FD
(03FE
16)···
16)···
16)···
16)···
16)···Timer A4 mode register
16)···
0
0? 0000
16)···
00? 0000
16)···
00? 0000
16)···
16)···
000 1000
16)···
000 0010
16)···
16)···
000 1000
16)···
000 0010
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
000000
0
0000
000 0???0
00 00000
000016
000016
000016
0000016
000016
000016
000016
000016
0016
0016
0016
0016
0016
0016
0
0
0016
0
0
0016
0016
0
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values
must therefore be set.
Note: When the V
CC level is applied to the CNVSS pin, it is 0316 at a reset.
Figure 1.6.3. Device's internal status after a reset is cleared
16
Page 17
SFR
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
000016
000116
000216
000316
000416
Processor mode register 0 (PM0)
000516
Processor mode register 1(PM1)
000616
System clock control register 0 (CM0)
000716
System clock control register 1 (CM1)
000816
Chip select control register (CSR)
000916
Address match interrupt enable register (AIER)
000A16
Protect register (PRCR)
000B16
000C16
000D16
000E16
Watchdog timer start register (WDTS)
000F16
Watchdog timer control register (WDC)
001016
001116
Address match interrupt register 0 (RMAD0)
001216
001316
001416
001516
Address match interrupt register 1 (RMAD1)
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
DMA0 source pointer (SAR0)
002116
002216
002316
002416
DMA0 destination pointer (DAR0)
002516
002616
002716
002816
DMA0 transfer counter (TCR0)
002916
002A16
002B16
002C16
DMA0 control register (DM0CON)
002D16
002E16
002F16
003016
DMA1 source pointer (SAR1)
003116
003216
003316
003416
DMA1 destination pointer (DAR1)
003516
003616
003716
003816
DMA1 transfer counter (TCR1)
003916
003A16
003B16
003C16
DMA1 control register (DM1CON)
003D16
003E16
003F16
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
Bus collision detection interrupt control register (BCNIC)
004A16
DMA0 interrupt control register (DM0IC)
004B16
DMA1 interrupt control register (DM1IC)
004C16
Key input interrupt control register (KUPIC)
004D16
A-D conversion interrupt control register (ADIC)
004E16
UART2 transmit interrupt control register (S2TIC)
004F16
UART2 re c e ive in terru p t c o n trol re g iste r (S 2 RIC)
005016
UART0 transmit interrupt control register (S0TIC)
005116
UART0 re c e ive in terru p t c o n trol re g iste r (S 0 RIC)
005216
UART1 transmit interrupt control register (S1TIC)
005316
UART1 re c e ive in terru p t c o n trol re g iste r (S 1 RIC)
005416
Timer A0 interrupt control register (TA0IC)
005516
Timer A1 interrupt control register (TA1IC)
005616
Timer A2 interrupt control register (TA2IC)
005716
Timer A3 interrupt control register (TA3IC)
005816
Timer A4 interrupt control register (TA4IC)
005916
Timer B0 interrupt control register (TB0IC)
005A16
Timer B1 interrupt control register (TB1IC)
005B16
Timer B2 interrupt control register (TB2IC)
005C16
INT0 interrupt control register (INT0IC)
005D16
INT1 interrupt control register (INT1IC)
005E16
INT2 interrupt control register (INT2IC)
005F16
036316
036416
036516
036616
036716
036816
036916
036A16
036B16
036C16
036D16
036E16
036F16
037016
037116
037216
037316
037416
037516
037616
037716
037816
UART2 transmit/receive mode register (U2MR)
037916
UART2 bit rate generator (U2BRG)
037A16
UART2 transmit buffer register (U2TB)
037B16
037C16
UART2 transmit/receive control register 0 (U2C0)
037D16
UART2 transmit/receive control register 1 (U2C1)
037E16
UART2 receive buffer register (U2RB)
037F16
Figure 1.7.1. Location of peripheral unit control registers
17
Page 18
SFR
0380
16
Count start flag (TABSR)
0381
16
Clock prescaler reset flag (CPSRF)
0382
16
One-shot start flag (ONSF)
0383
16
Trigger select register (TRGSR)
0384
16
Up-down flag (UDF)
0385
16
0386
16
Timer A0 (TA0)
0387
16
0388
16
Timer A1 (TA1)
0389
16
038A
16
Timer A2 (TA2)
038B
16
038C
16
Timer A3 (TA3)
038D
16
038E
16
Timer A4 (TA4)
038F
16
0390
16
Timer B0 (TB0)
0391
16
0392
16
Timer B1 (TB1)
0393
16
0394
16
Timer B2 (TB2)
0395
16
0396
16
Timer A0 mode register (TA0MR)
0397
16
Timer A1 mode register (TA1MR)
0398
16
Timer A2 mode register (TA2MR)
0399
16
Timer A3 mode register (TA3MR)
039A
16
Timer A4 mode register (TA4MR)
039B
16
Timer B0 mode register (TB0MR)
039C
16
Timer B1 mode register (TB1MR)
039D
16
Timer B2 mode register (TB2MR)
039E
16
039F
16
03A0
16
UART0 transmit/receive mode register (U0MR)
03A1
16
UART0 bit rate generator (U0BRG)
03A2
16
UART0 transmit buffer register (U0TB)
03A3
16
03A4
16
UART0 transmit/receive control register 0 (U0C0)
03A5
16
UART0 transmit/receive control register 1 (U0C1)
03A6
16
UART0 receive buffer register (U0RB)
03A7
16
03A8
16
UART1 transmit/receive mode register (U1MR)
03A9
16
UART1 bit rate generator (U1BRG)
03AA
16
UART1 transmit buffer register (U1TB)
03AB
16
03AC
16
UART1 transmit/receive control register 0 (U1C0)
03AD
16
UART1 transmit/receive control register 1 (U1C1)
03AE
16
UART1 receive buffer register (U1RB)
03AF
16
03B0
16
UART transmit/receive control register 2 (UCON)
03B1
16
03B2
16
03B3
16
03B4
16
03B5
16
03B6
16
03B7
16
03B8
16
DMA0 cause select register (DM0SL)
03B9
16
03BA
16
DMA1 cause select register (DM1SL)
03BB
16
03BC
16
CRC data register (CRCD)
03BD
16
03BE
16
CRC input register (CRCIN)
03BF
16
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
03C0
16
A-D register 0 (AD0)
03C1
16
03C2
16
A-D register 1 (AD1)
03C3
16
03C4
16
A-D register 2 (AD2)
03C5
16
03C6
16
A-D register 3 (AD3)
03C7
16
03C8
16
A-D register 4 (AD4)
03C9
16
03CA
16
A-D register 5 (AD5)
03CB
16
03CC
16
A-D register 6 (AD6)
03CD
16
03CE
16
A-D register 7 (AD7)
03CF
16
03D0
16
03D1
16
03D2
16
03D3
16
03D4
16
A-D control register 2 (ADCON2)
03D5
16
03D6
16
A-D control register 0 (ADCON0)
03D7
16
A-D control register 1 (ADCON1)
03D8
16
D-A register 0 (DA0)
03D9
16
03DA
16
D-A register 1 (DA1)
03DB
16
03DC
16
D-A control register (DACON)
03DD
16
03DE
16
03DF
16
03E0
16
Port P0 (P0)
03E1
16
Port P1 (P1)
03E2
16
Port P0 direction register (PD0)
03E3
16
Port P1 direction register (PD1)
03E4
16
Port P2 (P2)
03E5
16
Port P3 (P3)
03E6
16
Port P2 direction register (PD2)
03E7
16
Port P3 direction register (PD3)
03E8
16
Port P4 (P4)
03E9
16
Port P5 (P5)
03EA
16
Port P4 direction register (PD4)
03EB
16
Port P5 direction register (PD5)
03EC
16
Port P6 (P6)
03ED
16
Port P7 (P7)
03EE
16
Port P6 direction register (PD6)
03EF
16
Port P7 direction register (PD7)
03F0
16
Port P8 (P8)
03F1
16
Port P9 (P9)
03F2
16
Port P8 direction register (PD8)
03F3
16
Port P9 direction register (PD9)
03F4
16
Port P10 (P10)
03F5
16
03F6
16
Port P10 direction register (PD10)
03F7
16
03F8
16
03F9
16
03FA
16
03FB
16
03FC
16
Pull-up control register 0 (PUR0)
03FD
16
Pull-up control register 1 (PUR1)
03FE
16
Pull-up control register 2 (PUR2)
03FF
16
Mitsubishi microcomputers
M16C / 61 Group
Figure 1.7.2. Location of peripheral unit control registers
18
Page 19
Mitsubishi microcomputers
M16C / 61 Group
Software Reset
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software Reset
Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the
microcomputer. A software reset has almost the same effect as a hardware reset. The contents of internal
RAM are preserved.
Processor Mode
(1) Types of Processor Mode
One of three processor modes can be selected: single-chip mode, memory expansion mode, and microprocessor mode. The functions of some pins, the memory map, and the access space differ according to
the selected processor mode.
• Single-chip mode
In single-chip mode, only internal memory space (SFR, internal RAM, and internal ROM) can be
accessed. Ports P0 to P10 can be used as programmable I/O ports or as I/O ports for the internal
peripheral functions.
• Memory expansion mode
In memory expansion mode, external memory can be accessed in addition to the internal memory
space (SFR, internal RAM, and internal ROM).
In this mode, some of the pins function as the address bus, the data bus, and as control signals. The
number of pins assigned to these functions depends on the bus and register settings. (See “Bus
Settings” for details.)
• Microprocessor mode
In microprocessor mode, the SFR, internal RAM, and external memory space can be accessed. The
internal ROM area cannot be accessed.
In this mode, some of the pins function as the address bus, the data bus, and as control signals. The
number of pins assigned to these functions depends on the bus and register settings. (See “Bus
Settings” for details.)
(2) Setting Processor Modes
The processor mode is set using the CNVSS pin and the processor mode bits (bits 1 and 0 at address
000416). Do not set the processor mode bits to “102”.
Regardless of the level of the CNVSS pin, changing the processor mode bits selects the mode. Therefore,
never change the processor mode bits when changing the contents of other bits. Also do not attempt to
shift to or from the microprocessor mode within the program stored in the internal ROM area.
• Applying VSS to CNVSS pin
The microcomputer begins operation in single-chip mode after being reset. Memory expansion mode
is selected by writing “012” to the processor mode is selected bits.
• Applying VCC to CNVSS pin
The microcomputer starts to operate in microprocessor mode after being reset.
Figure 1.8.1 shows the processor mode register 0 and 1. Figure 1.9.1 shows the memory maps applicable for each of the modes.
19
Page 20
Processor Mode
Processor mode register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
PM0 0004
16
00
16
(Note 2)
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
WR
PM00
PM01
PM02
PM03
PM04
PM05
PM06
PM07
Bit name FunctionBit symbol
Processor mode bit
R/W mode select bit
Software reset bit
Multiplexed bus space
select bit
Port P40 to P43 function
select bit (Note 3)
BCLK output disable bit
b1 b0
0 0: Single-chip mode
0 1: Memory expansion mode
1 0: Inhibited
1 1: Microprocessor mode
0 : RD,BHE,WR
1 : RD,WRH,WRL
The device is reset when this bit is set
to “1”. The value of this bit is “0” when
read.
b5 b4
0 0 : Multiplexed bus is not used
0 1 : Allocated to CS2 space
1 0 : Allocated to CS1 space
1 1 : Allocated to entire space (Note4)
0 : Address output
1 : Port function
(Address is not output)
0 : BCLK is output
1 : BCLK is not output
(Pin is left floating)
Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new
values to this register.
Note 2: If the V
CC
reset is 03
voltage is applied to the CNVSS, the value of this register when
16.
(PM00 and PM01 both are set to “1”.)
Note 3: Valid in microprocessor and memory expansion modes.
Note 4: If the entire space is of multiplexed bus in memory expansion mode, choose
an 8-bit width.The processor operates using the separate bus after reset is
revoked, so the entire space multiplexed bus cannot be chosen in microprocessor
mode.
The higher-order address becomes a port if the entire space multiplexed
bus is chosen, so only 256 bytes can be used in each chip select.
Processor mode register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
000
Symbol Address When reset
PM1 0005
0
Bit name FunctionBit symbol
Reserved bit
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
Reserved bit
PM16
PM17
External memory area
expansion bit (Note 2)
Wait bit
Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing
new values to this register.
Note 2: When this bit is set to “1” in memory expansion mode, M30612M4A/E4
provides the means of using part of internal reserved area as an external
area. Set this bit to “0” except M30612M4A/E4. Set this bit to “0” in single
chip mode.
Figure 1.8.1. Processor mode register 0 and 1
16
00XXXXX0
2
Must always be set to “0”
Must always be set to “0”
0 : Do not expand
1 : Expand
0 : No wait state
1 : Wait state inserted
WR
20
Page 21
Processor Mode
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
00000
16
0040016
XXXXX16
0400016
D000016
YYYYY16
FFFFF16
Type No.
M30610M8A
M30610MCA/EC
M30612M4A/E4
M30612M8A
M30612MAA
M30612MCA
Single-chip mode
SFR area
Internal RAM
area
Inhibited
Internal ROM
area (Note 2)
Address
16
XXXXX
Address
YYYYY
F0000
E80001602BFF16M30610MAA
E00001602BFF16
F8000
F0000
E8000
E000016017FF16
Memory expansion mode
SFR area
Internal RAM
area
Internally
reserved area
External area
Internally reserved
area (Note 1)
Internal ROM
area
External area : Accessing this area allows the user to
16
1602BFF16
16013FF16
16013FF16
16013FF16
Note 1: This area becomes external area when PM16 (external
memory area expansion bit ) = “1” in M30612M4A/E4.
Set “0” except M30612M4A/E4.
Note 2: Set “0” to PM16 (external memory area expansion bit)
in single chip mode.
Microprocessor mode
SFR area
Internal RAM
area
Internally
reserved area
External area
access a device connected externally
to the microcomputer.
Figure 1.9.1. Memory maps in each processor mode
21
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Mitsubishi microcomputers
M16C / 61 Group
Bus Settings
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Settings
The BYTE pin and bits 4 to 6 of the processor mode register 0 (address 000416) are used to change the bus
settings.
Table 1.10.1 shows the factors used to change the bus settings.
Table 1.10.1. Factors for switching bus settings
Bus setting Switching factor
Switching external address bus width Bit 6 of processor mode register 0
Switching external data bus width BYTE pin
Switching between separate and multiplex bus Bits 4 and 5 of processor mode register 0
(1) Selecting external address bus width
The address bus width for external output in the 1M bytes of address space can be set to 16 bits (64K
bytes address space) or 20 bits (1M bytes address space). When bit 6 of the processor mode register 0
is set to “1”, the external address bus width is set to 16 bits, and P2 and P3 become part of the address
bus. P40 to P43 can be used as programmable I/O ports. When bit 6 of processor mode register 0 is set
to “0”, the external address bus width is set to 20 bits, and P2, P3, and P40 to P43 become part of the
address bus.
(2) Selecting external data bus width
The external data bus width can be set to 8 or 16 bits. (Note, however, that only the separate bus can be
set.) When the BYTE pin is “L”, the bus width is set to 16 bits; when “H”, it is set to 8 bits. (The internal bus
width is permanently set to 16 bits.) While operating, fix the BYTE pin either to “H” or to “L”.
(3) Selecting separate/multiplex bus
The bus format can be set to multiplex or separate bus using bits 4 and 5 of the processor mode register 0.
• Separate bus
In this mode, the data and address are input and output separately. The data bus can be set using the
BYTE pin to be 8 or 16 bits. When the BYTE pin is “H”, the data bus is set to 8 bits and P0 functions as
the data bus and P1 as a programmable I/O port. When the BYTE pin is “L”, the data bus is set to 16
bits and P0 and P1 are both used for the data bus.
When the separate bus is used for access, a software wait can be selected.
• Multiplex bus
In this mode, data and address I/O are time multiplexed. With an 8-bit data bus selected (BYTE pin =
“H”), the 8 bits from D0 to D7 are multiplexed with A0 to A7.
With a 16-bit data bus selected (BYTE pin = “L”), the 8 bits from D0 to D7 are multiplexed with A1 to A8.
D8 to D15 are not multiplexed. In this case, the external devices connected to the multiplexed bus are
mapped to the microcomputer’s even addresses (every 2nd address). To access these external devices, access the even addresses as bytes.
The ALE signal latches the address. It is output from P56.
Before using the multiplex bus for access, be sure to insert a software wait.
If the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width.
The processor operates using the separate bus after reset is revoked, so the entire space multiplexed
bus cannot be chosen in microprocessor mode.
The higher-order address becomes a port if the entire space multiplexed bus is chosen, so only 256
bytes can be used in each chip select.
22
Page 23
Bus Settings
P00 to P0
7
I/O port Data bus Data bus Data bus Data bus I/O port
Either CS1 or CS2 is for
multiplexed bus and others
are for separate bus
(separate bus)
multiplexed
bus for the
entire
space
Single-chip
mode
Memory expansion mode/microprocessor modes
Memory
expansion mode
Data bus width
BYTE pin level
Port P40 to P4
3
function select bit = 0
“01”, “10” “00”
“11” (Note 1)
8 bit
“H”
8 bits
“H”
16 bits
“L”
8 bits
“H”
16 bits
“L”
Note 1: If the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width.
The processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be
chosen in microprocessor mode.
The higher-order address becomes a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used
in each chip select.
Note 2: Address bus when in separate bus mode.
Processor mode
Multiplexed bus
space select bit
CS (chip select) or programmable I/O port
(For details, refer to “Bus control”)
Outputs RD, WRL, WRH, and BCLK or RD, BHE, WR, and BCLK
(For details, refer to “Bus control”)
Port P40 to P4
3
function select bit = 1
P1
0
to P1
7
I/O port I/O port Data bus I/O port Data bus I/O port
P2
1
to P2
7
I/O port
Address bus Address bus
Address bus Address bus Address bus
/data bus
(Note 2)
/data bus
(Note 2)
/data bus
P2
0
I/O port
Address bus
Address bus Address bus Address bus Address bus
/data bus
(Note 2)
/data bus
P3
0
I/O port Address bus
Address bus
Address bus Address bus A8/D
7
/data bus
(Note 2)
P31 to P3
7
I/O port Address bus Address bus Address bus Address bus I/O port
P4
0
to P4
3
I/O port I/O port I/O port /O port I/O port I/O port
P4
0
to P4
3
I/O port Address bus Address bus Address bus Address bus I/O port
P4
4
to P4
7
I/O port
P5
0
to P5
3
I/O port
P5
4
I/O port HLDA HLDA HLDA HLDA HLDA
P5
5
I/O port HOLD HOLD HOLD HOLD HOLD
P5
6
I/O port ALE ALE ALE ALE ALE
P5
7
I/O port RDY RDY RDY RDY RDY
Table 1.10.2. Pin functions for each processor mode
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
23
Page 24
Mitsubishi microcomputers
M16C / 61 Group
Bus Control
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
The following explains the signals required for accessing external devices and software waits. The signals
required for accessing the external devices are valid when the processor mode is set to memory expansion
mode and microprocessor mode. The software waits are valid in all processor modes.
(1) Address bus/data bus
The address bus consists of the 20 pins A0 to A19 for accessing the 1M bytes of address space.
The data bus consists of the pins for data I/O. When the BYTE pin is “H”, the 8 ports D0 to D7 function as
the data bus. When BYTE is “L”, the 16 ports D0 to D15 function as the data bus.
Both the address and data bus retain their previous states when internal ROM or RAM is accessed. Also,
when a change is made from single-chip mode to memory expansion mode, the value of the address bus
is undefined until external memory is accessed.
(2) Chip select signal
The chip select signal is output using the same pins as P4 4 to P47. Bits 0 to 3 of the chip select control
register (address 000816) set each pin to function as a port or to output the chip select signal. The chip
select control register is valid in memory expansion mode and microprocessor mode. In single-chip
mode, P44 to P47 function as programmable I/O ports regardless of the value in the chip select control
register.
In microprocessor mode, only CS0 outputs the chip select signal after the reset state has been cancelled.
_______ _______ _______ _______
CS1 to CS3 function as input ports. Therefore, when using CS1 to CS3, external pull-up resistors are
required. Figure 1.11.1 shows the chip select control register.
The chip select signal can be used to split the external area into as many as four blocks. Table 1.11.1
shows the external memory areas specified using the chip select signal.
_______
Table 1.11.1. External areas specified by the chip select signals
Chip select
CS0
CS1
CS2
CS3
Memory expansion mode Microprocessor mode
30000
16
to CFFFF16(640K)
30000
16
to F7FFF
2800016 to 2FFFF
08000
16
to 27FFF16(128K)
16
04000
to 07FFF
16
16
16
Specified address range
(800K)
(Note)
(32K)
(16K)
30000
28000
08000
04000
16
to FFFFF16(832K)
16
to 2FFFF16(32K)
16
to 27FFF16(128K)
16
to 07FFF
16
(16K)
Note: When PM16 (External memory area expansion bit) = “1”. (Only M30612M4A/E4 is valid.)
Chip select control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
CSR 0008
Bit symbol
CS0
CS1
CS2
CS3
CS0W
CS1W
CS2W
CS3W
Bit name
CS0 output enable bit
CS1 output enable bit
CS2 output enable bit
CS3 output enable bit
CS0 wait bit
CS1 wait bit
CS2 wait bit
CS3 wait bit
16
01
16
0 : Chip select output disabled
(Normal port pin)
1 : Chip select output enabled
0 : Wait state inserted
1 : No wait state
Function
R
W
Figure 1.11.1. Chip select control register
24
Page 25
Mitsubishi microcomputers
M16C / 61 Group
Bus Control
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) Read/write signals
With a 16-bit data bus (BYTE pin =“L”), bit 2 of the processor mode register 0 (address 000416) select the
combinations of RD, BHE, and WR signals or RD, WRL, and WRH signals. With an 8-bit data bus (BYTE
pin = “H”), use the combination of RD, WR, and BHE signals. (Set bit 2 of the processor mode register 0
(address 000416) to “0”.) Tables 1.11.2 and 1.11.3 show the operation of these signals.
After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically selected.
When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of the
processor mode register 0 (address 000416) has been set (Note).
Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect
register (address 000A16) to “1”.
_____ ________ ______ _____ ________ _________
_____ ______ _______
_____ ______ ________
_____ _________ _________
Table 1.11.2. Operation of RD, WRL, and WRH signals
_____ ________ _________
Data bus width
16-bit
(BYTE = “L”)
L
H
H
H
_____ ______ ________
H
L
H
L
WRHWRLRD
H
H
L
L
Read data
Write 1 byte of data to even address
Write 1 byte of data to odd address
Write data to both even and odd addresses
Status of external data bus
Table 1.11.3. Operation of RD, WR, and BHE signals
Data bus width A0
16-bit
(BYTE = “L”)
RD
BHEWR
HLL
LHL
HLH
LHH
H
H
HLLL
LHLL
8-bit
(BYTE = “H”)
HL H / L
LH H / L
Not used
Not used
Write 1 byte of data to odd address
Read 1 byte of data from odd address
L
L
Write 1 byte of data to even address
Read 1 byte of data from even address
Write data to both even and odd addresses
Read data from both even and odd addresses
Write 1 byte of data
Read 1 byte of data
Status of external data bus
(4) ALE signal
The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the
ALE signal falls.
When BYTE pin = “H”
ALE
D
0/A0
to D7/A
A8 to A
7
19
Address Data (Note 1)
Address (Note 2)
Note 1: Floating when reading.
Note 2: When multiplexed bus for the entire space is selected, these are I/O ports.
Figure 1.11.2. ALE signal and address/data bus
When BYTE pin = “L”
ALE
0/A1
to D7/A
D
A9 to A
0
A
8
19
Address Data (Note 1)
Address
Address
25
Page 26
Mitsubishi microcomputers
M16C / 61 Group
Bus Control
________
(5) The RDY signal
________
RDY is a signal that facilitates access to an external device that requires long access time. As shown in
Figure 1.11.3, if an “L” is being input to the RDY at the BCLK falling edge, the bus turns to the wait state.
________
If an “H” is being input to the RDY pin at the BCLK falling edge, the bus cancels the wait state. Table
1.11.4 shows the state of the microcomputer with the bus in the wait state, and Figure 1.11.3 shows an
example in which the RD signal is prolonged by the RDY signal.
________
____ ________
The RDY signal is valid when accessing the external area during the bus cycle in which bits 4 to 7 of the
chip select control register (address 000816) are set to “0”. The RDY signal is invalid when setting “1” to all
bits 4 to 7 of the chip select control register (address 000816), but the RDY pin should be treated as
properly as in non-using.
Table 1.11.4. Microcomputer status in ready state (Note)
Item Status
Oscillation On
___ _____
R/W signal, address bus, data bus, CS
__________
ALE signal, HLDA, programmable I/O ports
Internal peripheral circuits On
________
Note: The RDY signal cannot be received immediately prior to a software wait.
________
Maintain status when RDY signal received
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
________
________
________
In an instance of separate bus
BCLK
RD
CS
i
(i=0 to 3)
RDY
Accept timing of RDY signal
In an instance of multiplexed bus
BCLK
RD
CS
i
(i=0 to 3)
RDY
: Wait using RDY signal
: Wait using software
tsu(RDY - BCLK)
tsu(RDY - BCLK)
Accept timing of RDY signal
Figure 1.11.3. Example of RD signal extended by RDY signal
_____ ________
26
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Mitsubishi microcomputers
M16C / 61 Group
Bus Control
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(6) Hold signal
The hold signal is used to transfer the bus privileges from the CPU to the external circuits. Inputting “L” to
__________
the HOLD pin places the microcomputer in the hold state at the end of the current bus access. This status
__________ __________
is maintained and “L” is output from the HLDA pin as long as “L” is input to the HOLD pin. Table 1.11.5
shows the microcomputer status in the hold state.
__________
Bus-using priorities are given to HOLD, DMAC, and CPU in order of decreasing precedence.
__________
HOLD > DMAC > CPU
Figure 1.11.4. Bus-using priorities
Table 1.11.5. Microcomputer status in hold state
Item Status
Oscillation ON
___ _____ _______
R/W signal, address bus, data bus, CS, BHE Floating
Programmable I/O ports P0, P1, P2, P3, P4, P5 Floating
__________
HLDA Output “L”
Internal peripheral circuits ON (but watchdog timer stops)
ALE signal Undefined
P6, P7, P8, P9, P10 Maintains status when hold signal is received
(7) External bus status when the internal area is accessed
Table 1.11.6 shows the external bus status when the internal area is accessed.
Table 1.11.6. External bus status when the internal area is accessed
Item SFR accessed Internal ROM/RAM accessed
Address bus Address output Maintain status before accessed
address of external area
Data bus When read Floating Floating
When write Output data Undefined
RD, WR, WRL, WRH RD, WR, WRL, WRH output Output "H"
BHE BHE output Maintain status before accessed
status of external area
CS Output "H" Output "H"
ALE Output "L" Output "L"
27
Page 28
Mitsubishi microcomputers
M16C / 61 Group
Bus Control
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(8) BCLK output
The user can choose the BCLK output by use of bit 7 of processor mode register 0 (000416) (Note).
When set to “1”, the output floating.
Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect
register (address 000A16) to “1”.
(9) Software wait
A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address
000516) (Note) and bits 4 to 7 of the chip select control register (address 000816).
A software wait is inserted in the internal ROM/RAM area and in the external memory area by setting the
wait bit of the processor mode register 1. When set to “0”, each bus cycle is executed in one BCLK cycle.
When set to “1”, each bus cycle is executed in two or three BCLK cycles. After the microcomputer has been
reset, this bit defaults to “0”. When
cycles), regardless of the contents of bits 4 to 7 of the chip select control register
to the recommended operating conditions (main clock input oscillation frequency) of the electric characteristics.
However, when the user is using the RDY signal, the relevant bit in the chip select control register’s
bits 4 to 7 must be set to “0”.
When the wait bit of the processor mode register 1 is “0”, software waits can be set independently for
each of the 4 areas selected using the chip select signal. Bits 4 to 7 of the chip select control register
_______ _______
correspond to chip selects CS0 to CS3. When one of these bits is set to “1”, the bus cycle is executed in
one BCLK cycle. When set to “0”, the bus cycle is executed in two or three BCLK cycles. These bits
default to “0” after the microcomputer has been reset.
The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits. Also,
insert a software wait if using the multiplex bus to access the external memory area.
Table 1.11.7 shows the software wait and bus cycles. Figure 1.11.5 shows example bus timing when
using software waits.
set to “1”, a wait is applied to all memory areas (two or three BCLK
. Set this bit after referring
________
Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect
register (address 000A16) to “1”.
Table 1.11.7. Software waits and bus cycles
Area Bus status Wait bit
SFR
Internal
ROM/RAM
Separate bus
External
memory
area
Note: When using the RDY signal, always set to “0”.
Separate bus
Separate bus
Multiplex bus 0 0 3 BCLK cycles
Multiplex bus
Invalid Invalid 2 BCLK cycles
0 Invalid 1 BCLK cycle
0 1 1 BCLK cycle
0 0 2 BCLK cycles
1 0 (Note) 2 BCLK cycles
1 3 BCLK cycles0 (Note)
Bits 4 to 7 of chip select
control register
Invalid1 2 BCLK cycles
Bus cycle
28
Page 29
Bus Control
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
< Separate bus (no wait) >
BCLK
Write signal
Read signal
Data bus
Address bus
Chip select
< Separate bus (with wait) >
BCLK
Write signal
Bus cycle
Address
Bus cycle
Output
Input
Address
Read signal
Data bus
Address bus
Chip select
< Multiplexed bus >
Write signal
Read signal
Address bus
Address bus/
Data bus
BCLK
ALE
Address
Address
Bus cycle
Address
Data output
Output
Address
Input
Address
Address
Input
Chip select
Figure 1.11.5. Typical bus timings using software wait
29
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Mitsubishi microcomputers
M16C / 61 Group
Clock Generating Circuit
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the
CPU and internal peripheral units.
Table 1.12.1. Main clock and sub-clock generating circuits
Main clock generating circuit Sub-clock generating circuit
Use of clock • CPU’s operating clock source • CPU’s operating clock source
• Internal peripheral units’ • Timer A/B’s count clock
operating clock source source
Usable oscillator Ceramic or crystal oscillator Crystal oscillator
Pins to connect oscillator XIN, XOUT XCIN, XCOUT
Oscillation stop/restart function Available Available
Oscillator status immediately after reset
Other Externally derived clock can be input
Oscillating Stopped
Example of oscillator circuit
Figure 1.12.1 shows some examples of the main clock circuit, one using an oscillator connected to the
circuit, and the other one using an externally derived clock for input. Figure 1.12.2 shows some examples
of sub-clock circuits, one using an oscillator connected to the circuit, and the other one using an externally
derived clock for input. Circuit constants in Figures 1.12.1 and 1.12.2 vary with each oscillator used. Use
the values recommended by the manufacturer of your oscillator.
Microcomputer
(Built-in feedback resistor)
X
IN
C
IN
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between X
and X
OUT
X
OUT
(Note)
R
d
C
OUT
following the instruction.
Figure 1.12.1. Examples of main clock
Microcomputer
(Built-in feedback resistor)
X
IN
Externally derived clock
Vcc
Vss
X
OUT
Open
IN
Microcomputer
(Built-in feedback resistor)
X
CIN
C
CIN
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between X
and X
COUT
X
COUT
(Note)
R
Cd
C
COUT
following the instruction.
Figure 1.12.2. Examples of sub-clock
30
Microcomputer
(Built-in feedback resistor)
X
CIN
Externally derived clock
Vcc
Vss
X
COUT
Open
CIN
Page 31
Clock Generating Circuit
Clock Control
Figure 1.12.3 shows the block diagram of the clock generating circuit.
X
CIN
X
COUT
CM04
Sub clock
RESET
Software reset
NMI
Interrupt request
level judgment
output
CM10 “1”
Write signal
WAIT instruction
Q
S
R
QS
R
CM05
X
IN
Main clock
X
OUT
CM02
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
C32
f
1/32
f
C
f
1
f
AD
f
8
f
32
c
b
a
Divider
d
f
C
CM07=0
CM07=1
f1SIO2
f8SIO2
f32SIO2
BCLK
CM0i : Bit i at address 0006
CM1i : Bit i at address 0007
WDCi : Bit i at address 000F
16
16
16
Figure 1.12.3. Clock generating circuit
a
b
1/2 1/2 1/2 1/2
CM06=1
CM06=0
CM17,CM16=01
CM06=0
CM17,CM16=00
CM06=0
CM17,CM16=10
1/2
CM06=0
CM17,CM16=11
Details of divider
c
d
31
Page 32
Mitsubishi microcomputers
M16C / 61 Group
Clock Generating Circuit
The following paragraphs describes the clocks generated by the clock generating circuit.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Main clock
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to
the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping the
clock, after switching the operating clock source of CPU to the sub-clock, reduces the power dissipation.
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock
oscillation circuit can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716).
Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit
changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
(2) Sub-clock
The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset.
After oscillation is started using the port Xc select bit (bit 4 at address 000616), the sub-clock can be
selected as the BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure
that the sub-clock oscillation has fully stabilized before switching.
After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock
oscillation circuit can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616).
Reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. This bit
changes to “1” when shifting to stop mode and at a reset.
(3) BCLK
The BCLK is the clock that drives the CPU, and is fc or the clock is derived by dividing the main clock by
1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset. The BCLK signal can
be output from BCLK pin by the BCLK output disable bit (bit 7 at address 000416) in the memory expansion and the microprocessor modes.
The main clock division select bit 0(bit 6 at address 000616) changes to “1” when shifting from highspeed/medium-speed to stop mode and at reset. When shifting from low-speed/low power dissipation
mode to stop mode, the value before stop mode is retained.
(4) Peripheral function clock(f1, f8, f32, f1SIO2, f8SIO2,f32SIO2,fAD)
The clock for the peripheral devices is derived from the main clock or by dividing it by 1, 8, or 32. The
peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function
clock stop bit (bit 2 at 000616) to “1” and then executing a WAIT instruction.
(5) fC32
This clock is derived by dividing the sub-clock by 32. It is used for the timer A and timer B counts.
(6) fC
This clock has the same frequency as the sub-clock. It is used for the BCLK and for the watchdog timer.
32
Page 33
Clock Generating Circuit
Figure 1.12.4 shows the system clock control registers 0 and 1.
System clock control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
CM0 0006
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
16
48
16
CM00
CM01
CM02
CM03
CM04
CM05
CM06
CM07
Bit name FunctionBit symbol
Clock output function
select bit
(Valid only in single-chip
mode)
WAIT peripheral function
clock stop bit
X
CIN-XCOUT
select bit (Note 2)
Port XC select bit 0 : I/O port
Main clock (XIN-X
stop bit (Note 3, 4, 5)
Main clock division select
bit 0 (Note 7)
System clock select bit
(Note 6)
drive capacity
OUT
b1 b0
0 0 : I/O port P5
0 1 : fC output
1 0 : f
8
output
32
output
1 1 : f
0 : Do not stop peripheral function clock in wait mode
1 : Stop peripheral function clock in wait mode (Note 8)
0 : LOW
1 : HIGH
CIN-XCOUT
1 : X
)
0 : On
1 : Off
0 : CM16 and CM17 valid
1 : Division by 8 mode
0 : XIN, X
1 : X
CIN
, X
OUT
COUT
7
generation
WR
Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: Changes to “1” when shiffing to stop mode and at a reset.
Note 3: When entering power saving mode, main clock stops using this bit. When returning from stop mode and
IN
operating with X
, set this bit to “0”. When main clock oscillation is operating by itself, set system clock select
bit (CM07) to “1” before setting this bit to “1”.
Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable.
Note 5: If this bit is set to “1”, X
pulled up to X
OUT
OUT
turns “H”. The built-in feedback resistor remains being connected, so XIN turns
(“H”) via the feedback resistor.
Note 6: Set port Xc select bit (CM04) to “1” and stabilize the sub-clock oscillating before setting to this bit from “0” to “1”.
Do not write to both bits at the same time. And also, set the main clock stop bit (CM05) to “0” and stabilize the
main clock oscillating before setting this bit from “1” to “0”.
Note 7: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 8: f
C32
is not included.
System clock control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
00
00
Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 3: Can be selected when bit 6 of the system clock control register 0 (address 0006
fixed at 8.
Note 4: If this bit is set to “1”, X
impedance state.
Symbol Address When reset
CM1 0007
16
20
16
Bit name FunctionBit symbol
CM10
Reserved bit
Reserved bit
Reserved bit
Reserved bit
CM15
CM16
CM17
All clock stop control bit
(Note4)
X
IN-XOUT
drive capacity
select bit (Note 2)
Main clock division
select bit 1 (Note 3)
OUT
turns “H”, and the built-in feedback resistor is cut off. X
0 : Clock on
1 : All clocks off (stop mode)
Always set to
Always set to
Always set to
Always set to
0 : LOW
1 : HIGH
b7 b6
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
“0”
“0”
“0”
“0”
16
) is “0”. If “1”, division mode is
CIN
and X
COUT
turn high-
WR
Figure 1.12.4. Clock control registers 0 and 1
33
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Mitsubishi microcomputers
M16C / 61 Group
Clock Generating Circuit
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Output
In single-chip mode, the clock output function select bits (bits 0 and 1 at address 000616) enable f8, f32, or
fC to be output from the P57/CLKOUT pin. When the WAIT peripheral function clock stop bit (bit 2 at address
000616) is set to “1”, the output of f8 and f32 stops when a WAIT instruction is executed.
Stop Mode
Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcomputer enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC remains above 2V.
Because the oscillation, BCLK, f1 to f32, f1SIO2 to f32SIO2, fC, fC32, and fAD stops in stop mode, peripheral
functions such as the A-D converter and watchdog timer do not function. However, timer A and timer B
operate provided that the event counter mode is set to an external pulse, and UARTi(i = 0 to 2) functions
provided an external clock is selected. Table 1.12.2 shows the status of the ports in stop mode.
Stop mode is cancelled by a hardware reset or interrupt. If an interrupt is to be used to cancel stop mode,
that interrupt must first have been enabled.
When shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division
select bit 0 (bit 6 at address 000616) is set to “1”. When shifting from low-speed/low power dissipation mode
to stop mode, the value before stop mode is retained.
Table 1.12.2. Port status during stop mode
Pin Memory expansion mode Single-chip mode
Microprocessor mode
Address bus, data bus, CS0 to CS3
_____ ______ ________ ________ _________
_______ _______
Retains status before stop mode
RD, WR, BHE, WRL, WRH “H”
__________
HLDA, BCLK “H”
ALE “H”
Port
Retains status before stop mode
CLKOUT When fC selected Valid only in single-chip mode “H”
When f8, f32 selected Valid only in single-chip mode
Retains status before stop mode
Retains status before stop mode
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Mitsubishi microcomputers
M16C / 61 Group
Wait Mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Wait Mode
When a WAIT instruction is executed, BCLK stops and the microcomputer enters the wait mode. In this
mode, oscillation continues but BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral function
clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral
functions, allowing power dissipation to be reduced. Table 1.12.3 shows the status of the ports in wait
mode.
Wait mode is cancelled by a hardware reset or an interrupt. If an interrupt is used to cancel wait mode, the
microcomputer restarts from the interrupt routine using as BCLK, the clock that had been selected when the
WAIT instruction was executed.
Table 1.12.3. Port status during wait mode
Pin Memory expansion mode Single-chip mode
Address bus, data bus, CS0 to CS3
_______ _______
_____ ______ ________ ________ _________
RD, WR, BHE, WRL, WRH “H”
__________
HLDA,BCLK “H”
ALE “H”
Port
CLKOUT When fC selected Valid only in single-chip mode Does not stop
When f8, f32 selected Valid only in single-chip mode Doesnot stop when the WAIT
Microprocessor mode
Retains status before wait mode
Retains status before wait mode Retains status before wait mode
peripheral function clock stop
bit is “0”.
When the WAIT peripheral
function clock stop bit is “1”,
the status immediately prior
to entering wait mode is maintained.
35
Page 36
Mitsubishi microcomputers
M16C / 61 Group
Status Transition Of BCLK
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Status Transition Of BCLK
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for
BCLK. Table 1.13.4 shows the operating modes corresponding to the settings of system clock control
registers 0 and 1.
When reset, the device starts in division by 8 mode. The main clock division select bit 0(bit 6 at address
000616) changes to “1” when shifting from high-speed/medium-speed to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
The following shows the operational modes of BCLK.
(1) Division by 2 mode
The main clock is divided by 2 to obtain the BCLK.
(2) Division by 4 mode
The main clock is divided by 4 to obtain the BCLK.
(3) Division by 8 mode
The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this
mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4
mode, the main clock must be oscillating stably. When going to low-speed or lower power consumption
mode, make sure the sub-clock is oscillating stably.
(4) Division by 16 mode
The main clock is divided by 16 to obtain the BCLK.
(5) No-division mode
The main clock is divided by 1 to obtain the BCLK.
(6) Low-speed mode
fC is used as the BCLK. Note that oscillation of both the main and sub-clocks must have stabilized before
transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the subclock starts. Therefore, the program must be written to wait until this clock has stabilized immediately
after powering up and after stop mode is cancelled.
(7) Low power dissipation mode
fC is the BCLK and the main clock is stopped.
Note : Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which
the count source is going to be switched must be oscillating stably. Allow a wait time in software for
the oscillation to stabilize before switching over the clock.
Table 1.12.4. Operating modes dictated by settings of system clock control registers 0 and 1
CM17 CM16 CM07 CM06 CM05 CM04 Operating mode of BCLK
01000Invalid Division by 2 mode
10000Invalid Division by 4 mode
Invalid Invalid 0 1 0 Invalid Division by 8 mode
11000Invalid Division by 16 mode
00000Invalid No-division mode
Invalid Invalid 1 Invalid 0 1 Low-speed mode
Invalid Invalid 1 Invalid 1 1 Low power dissipation mode
36
Page 37
Power control
Power control
The following is a description of the three available power control modes:
Modes
Power control is available in three modes.
(a) Normal operation mode
• High-speed mode
Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the internal
clock selected. Each peripheral function operates according to its assigned clock.
• Medium-speed mode
Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the
BCLK. The CPU operates according to the internal clock selected. Each peripheral function operates according to its assigned clock.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Low-speed mode
fC becomes the BCLK. The CPU operates according to the fc clock. The fc clock is supplied by the
secondary clock. Each peripheral function operates according to its assigned clock.
• Low power consumption mode
The main clock operating in low-speed mode is stopped. The CPU operates according to the fC
clock. The fC clock is supplied by the secondary clock. The only peripheral functions that operate
are those with the sub-clock selected as the count source.
(b) Wait mode
The CPU operation is stopped. The oscillators do not stop.
(c) Stop mode
All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three
modes listed here, is the most effective in decreasing power consumption.
Figure 1.12.5 is the state transition diagram of the above modes.
37
Page 38
Power control
Transition of stop mode, wait mode
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
All oscillators stopped
Stop mode
All oscillators stopped
Stop mode
All oscillators stopped
Stop mode
CM10 = “1”
Interrupt
Interrupt
CM10 = “1”
CM10 = “1”
Interrupt
Transition of normal mode
Main clock is oscillating
Sub clock is stopped
Medium-speed mode
(divided-by-8 mode)
CM06 = “1”
Main clock is oscillating
Sub clock is oscillating
High-speed mode
BCLK : f(XIN)
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0”
Medium-speed mode
(divided-by-4 mode)
BCLK : f(XIN)/4
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
CM07 = “0” CM06 = “1”
CM04 = “0”
Medium-speed mode
(divided-by-2 mode)
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
Medium-speed mode
(divided-by-16 mode)
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
BCLK : f(XIN)/8
CM04 = “1”
(Notes 1, 3)
BCLK : f(XIN)/2
BCLK : f(XIN)/16
CPU operation stopped
Wait mode
CPU operation stopped
Wait mode
CPU operation stopped
Wait mode
Medium-speed mode
(divided-by-8 mode)
High-speed/medium-
speed mode
Low-speed/low power
dissipation mode
WAIT
instruction
Interrupt
WAIT
instruction
Interrupt
WAIT
instruction
Interrupt
Normal mode
(Refer to the following for the transition of normal mode.)
CM07 = “0” (Note 1)
CM06 = “1”
CM04 = “0”
Main clock is oscillating
Medium-speed mode
(divided-by-8 mode)
BCLK : f(XIN)/8
CM07 = “0”
CM06 = “1”
CM07 = “0”
(Note 1, 3)
CM07 = “1”
(Note 2)
Sub clock is oscillating
Low-speed mode
BCLK : f(X
CM05 = “0” CM05 = “1”
CM07 = “1”
CIN
)
CM04 = “0” CM04 = “1”
Main clock is oscillating
Sub clock is stopped
Medium-speed mode
CM06 = “0”
(Notes 1,3)
High-speed mode
BCLK : f(XIN)
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0”
Medium-speed mode
(divided-by-4 mode)
BCLK : f(XIN)/4
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
(divided-by-2 mode)
BCLK : f(XIN)/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
Medium-speed mode
(divided-by-16 mode)
BCLK : f(XIN)/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
Note 1: Switch clock after oscillation of main clock is sufficiently stable.
Note 2: Switch clock after oscillation of sub clock is sufficiently stable.
Note 3: Change CM06 after changing CM17 and CM16.
Note 4: Transit in accordance with arrow.
Figure 1.12.5. State transition diagram of Power control mode
38
CM07 = “1” (Note 2)
CM05 = “1”
CM07 = “0” (Note 1)
CM06 = “0” (Note 3)
CM04 = “1”
Main clock is stopped
Sub clock is oscillating
Low power dissipation mode
BCLK : f(X
CM07 = “1”
CIN
)
Page 39
Mitsubishi microcomputers
M16C / 61 Group
Protection
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Protection
The protection function is provided so that the values in important registers cannot be changed in the event
that the program runs out of control. Figure 1.12.6 shows the protect register. The values in the processor
mode register 0 (address 000416), processor mode register 1 (address 000516), system clock control register 0 (address 000616), system clock control register 1 (address 000716) and port P9 direction register
(address 03F316) can only be changed when the respective bit in the protect register is set to “1”. Therefore, important outputs can be allocated to port P9.
If, after “1” (write-enabled) has been written to the port P9 direction register write-enable bit (bit 2 at address
000A16), a value is written to any address, the bit automatically reverts to “0” (write-inhibited). However, the
system clock control registers 0 and 1 write-enable bit (bit 0 at 000A16) and processor mode register 0 and
1 write-enable bit (bit 1 at 000A16) do not automatically return to “0” after a value has been written to an
address. The program must therefore be written to return these bits to “0”.
Protect register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
PRCR 000A
16 XXXXX0002
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
Note: Writing a value to an address after “1” is written to this bit returns the bit
Figure 1.12.6. Protect register
Bit nameBit symbol
16
) (Note)
0 : Write-inhibited
1 : Write-enabled
0 : Write-inhibited
16
1 : Write-enabled
0 : Write-inhibited
1 : Write-enabled
PRC0
PRC1
PRC2
Enables writing to system clock
control registers 0 and 1 (addresses
0006
16
and 0007
Enables writing to processor mode
registers 0 and 1 (addresses 0004
and 0005
Enables writing to port P9 direction
register (address 03F3
to “0” . Other bits do not automatically return to “0” and they must therefore
be reset by the program.
16
)
16
)
Function
WR
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Interrupt
Overview of Interrupt
Type of Interrupts
Figure 1.13.1 lists the types of interrupts.
Software
Interrupt
Hardware
Special
Peripheral I/O (Note)
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
INT instruction
Reset
_______
NMI
________
DBC
Watchdog timer
Single step
Address matched
Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system.
Figure 1.13.1. Classification of interrupts
• Maskable interrupt : An interrupt which can be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority can be changed by priority level.
• Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority cannot be changed by priority level.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable
interrupts.
• Undefined instruction interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
• Overflow interrupt
An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to
“1”. The following are instructions whose O flag changes by arithmetic:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
• BRK interrupt
A BRK interrupt occurs when executing the BRK instruction.
• INT interrupt
An INT interrupt occurs when assiging one of software interrupt numbers 0 through 63 and executing
the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O interrupts,
so executing the INT instruction allows executing the same interrupt routine that a peripheral I/O
interrupt does.
The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is
involved.
So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack
pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to “0” and
select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from
the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt request. So far as software numbers 32 through 63 are concerned, the stack pointer does not make a
shift.
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Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts.
(1) Special interrupts
Special interrupts are non-maskable interrupts.
• Reset
Reset occurs if an “L” is input to the RESET pin.
_______
• NMI interrupt
_______ _______
An NMI interrupt occurs if an “L” is input to the NMI pin.
________
• DBC interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances.
• Watchdog timer interrupt
Generated by the watchdog timer.
• Single-step interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug
flag (D flag) set to “1”, a single-step interrupt occurs after one instruction is executed.
• Address match interrupt
An address match interrupt occurs immediately before the instruction held in the address indicated by
the address match interrupt register is executed with the address match interrupt enable bit set to “1”.
If an address other than the first address of the instruction in the address match interrupt register is set,
no address match interrupt occurs. For address match interrupt, see 2.11 Address match Interrupt.
____________
Mitsubishi microcomputers
M16C / 61 Group
(2) Peripheral I/O interrupts
A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral functions are dependent on classes of products, so the interrupt factors too are dependent on classes of
products. The interrupt vector table is the same as the one for software interrupt numbers 0 through
31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts.
• Bus collision detection interrupt
This is an interrupt that the serial I/O bus collision detection generates.
• DMA0 interrupt, DMA1 interrupt
These are interrupts that DMA generates.
• Key-input interrupt
___
A key-input interrupt occurs if an “L” is input to the KI pin.
• A-D conversion interrupt
This is an interrupt that the A-D converter generates.
• UART0, UART1 and UART2 transmission interrupt
These are interrupts that the serial I/O transmission generates.
• UART0, UART1 and UART2 reception interrupt
These are interrupts that the serial I/O reception generates.
• Timer A0 interrupt through timer A4 interrupt
These are interrupts that timer A generates
• Timer B0 interrupt through timer B2 interrupt
These are interrupts that timer B generates.
________ ________
• INT0 interrupt through INT2 interrupt
______ ______
An INT interrupt occurs if either a rising edge or a falling edge is input to the INT pin.
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Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts and Interrupt Vector Tables
If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector
table. Set the first address of the interrupt routine in each vector table. Figure 1.13.2 shows the format for
specifying the address.
Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed and
variable vector table in which addresses can be varied by the setting.
Vector address + 0
Vector address + 1
Vector address + 2
Vector address + 3
MSB
Low address
Mid address
0 0 0 0 High address
0 0 0 0 0 0 0 0
LSB
Figure 1.13.2. Format for specifying interrupt vector addresses
• Fixed vector tables
The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area
extending from FFFDC16 to FFFFF16. One vector table comprises four bytes. Set the first address of
interrupt routine in each vector table. Table 1.13.1 shows the interrupts assigned to the fixed vector
tables and addresses of vector tables.
Table 1.13.1. Interrupts assigned to the fixed vector tables and addresses of vector tables
Interrupt source Vector table addresses Remarks
Address (L) to address (H)
Undefined instruction FFFDC16 to FFFDF16 Interrupt on UND instruction
Overflow FFFE016 to FFFE316 Interrupt on INTO instruction
BRK instruction FFFE416 to FFFE716
If the vector contains FF16, program execution starts from
the address shown by the vector in the variable vector table
Address match FFFE816 to FFFEB16 There is an address-matching interrupt enable bit
Single step (Note) FFFEC16 to FFFEF16 Do not use
Watchdog timer FFFF016 to FFFF316
________
DBC (Note) FFFF416 to FFFF716 Do not use
NMI FFFF816 to FFFFB16
External interrupt by input to NMI pin
_______
Reset FFFFC16 to FFFFF16
Note: Interrupts used for debugging purposes only.
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A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
M16C / 61 Group
Interrupt
• Variable vector tables
The addresses in the variable vector table can be modified, according to the user’s settings. Indicate
the first address using the interrupt table register (INTB). The 256-byte area subsequent to the address the INTB indicates becomes the area for the variable vector tables. One vector table comprises
four bytes. Set the first address of the interrupt routine in each vector table. Table 1.13.2 shows the
interrupts assigned to the variable vector tables and addresses of vector tables.
Table 1.13.2. Interrupts assigned to the variable vector tables and addresses of vector tables
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software interrupt number Interrupt source
AAAAAAAAAAAAAAAAAAAAAA
Vector table address
Address (L) to address (H)
Remarks
Cannot be masked I flag+0 to +3 (Note) BRK instructionSoftware interrupt number 0
AAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAA
Software interrupt number 29
AAAAAAAAAAAAAAAAAAAAAA
Software interrupt number 30
AAAAAAAAAAAAAAAAAAAAAA
Software interrupt number 31
AAAAAAAAAAAAAAAAAAAAAA
Software interrupt number 32
AAAAAAAAAAAAAAAAAAAAAA
Note: Address relative to address in interrupt table register (INTB)
+40 to +43 (Note) Bus collision detectionSoftware interrupt number 10
+44 to +47 (Note) DMA0Software interrupt number 11
+48 to +51 (Note) DMA1Software interrupt number 12
+52 to +55 (Note) Key input interruptSoftware interrupt number 13
+56 to +59 (Note) A-DSoftware interrupt number 14
+60 to +63 (Note) UART2 transmitSoftware interrupt number 15
+64 to +67 (Note) UART2 receiveSoftware interrupt number 16
+68 to +71 (Note) UART0 transmitSoftware interrupt number 17
+72 to +75 (Note) UART0 receiveSoftware interrupt number 18
+76 to +79 (Note) UART1 transmitSoftware interrupt number 19
+80 to +83 (Note) UART1 receiveSoftware interrupt number 20
+84 to +87 (Note) Timer A0Software interrupt number 21
+88 to +91 (Note) Timer A1Software interrupt number 22
+92 to +95 (Note) Timer A2Software interrupt number 23
+96 to +99 (Note) Timer A3Software interrupt number 24
+100 to +103 (Note) Timer A4Software interrupt number 25
+104 to +107 (Note) Timer B0Software interrupt number 26
+108 to +111 (Note) Timer B1Software interrupt number 27
+112 to +115 (Note) Timer B2Software interrupt number 28
+116 to +119 (Note) INT0
+120 to +123 (Note) INT1
+124 to +127 (Note) INT2
+128 to +131 (Note)
toto
+252 to +255 (Note)Software interrupt number 63
Software interrupt
Cannot be masked I flag
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Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt Control
Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the
priority to be accepted. What is described here does not apply to non-maskable interrupts.
Enable or disable a non-maskable interrupt using the interrupt enable flag (I flag), interrupt priority level
selection bit, or processor interrupt priority level (IPL). Whether an interrupt request is present or absent is
indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit
are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the
IPL are located in the flag register (FLG).
Figure 1.13.3 shows the memory map of the interrupt control registers.
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Interrupt
Interrupt control register
b7 b6 b5 b4 b3 b2 b1 b0
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Symbol Address When reset
16
BCNIC 004A
DMiIC(i=0, 1) 004B16, 004C
KUPIC 004D
ADIC 004E
SiTIC(i=0 to 2) 005116, 005316, 004F
SiRIC(i=0 to 2) 005216, 005416, 0050
TAiIC(i=0 to 4) 005516 to 0059
TBiIC(i=0 to 2) 005A16 to 005C
16
16
16
16
16
16
16
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
Mitsubishi microcomputers
M16C / 61 Group
2
2
2
2
2
2
2
2
b7 b6 b5 b4 b3 b2 b1 b0
0
WR
ILVL0
Bit name FunctionBit symbol
Interrupt priority level
select bit
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
ILVL1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
ILVL2
IR
Interrupt request bit
1 1 0 : Level 6
1 1 1 : Level 7
0 : Interrupt not requested
1 : Interrupt requested
(Note 1)
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminate.
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the
interrupt request for that register. For details, see the precautions for interrupts.
Symbol Address When reset
INTiIC(i=0 to 2) 005D
Bit name FunctionBit symbol
ILVL0
Interrupt priority level
select bit
to 005F16 XX00X000
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
2
WR
16
0 0 1 : Level 1
ILVL1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
ILVL2
1 1 0 : Level 6
1 1 1 : Level 7
IR
POL
Reserved bit
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminate.
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the
interrupt request for that register. For details, see the precautions for interrupts.
Figure 1.13.3. Interrupt control registers
46
Interrupt request bit
Polarity select bit
0: Interrupt not requested
1: Interrupt requested
0 : Selects falling edge
1 : Selects rising edge
Always set to “0”
(Note 1)
Page 47
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Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt Enable Flag (I flag)
The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this
flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set
to “0” after reset.
Interrupt Request Bit
The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is
accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The
interrupt request bit can also be set to "0" by software. (Do not set this bit to "1").
Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)
Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits
of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared
with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL.
Therefore, setting the interrupt priority level to “0” disables the interrupt.
Table 1.13.3 shows the settings of interrupt priority levels and Table 1.13.4 shows the interrupt levels
enabled, according to the consist of the IPL.
The following are conditions under which an interrupt is accepted:
· interrupt enable flag (I flag) = 1
· interrupt request bit = 1
· interrupt priority level > IPL
The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are
independent, and they are not affected by one another.
Table 1.13.3. Settings of interrupt priority levels
Table 1.13.4.
Interrupt levels enabled according
to the contents of the IPL
Interrupt priority
level select bit
b2 b1 b0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
Interrupt priority
level
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Priority
order
Low
IPL
IPL2 IPL1 IPL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
Enabled interrupt priority levels
0
Interrupt levels 1 and above are enabled
Interrupt levels 2 and above are enabled
Interrupt levels 3 and above are enabled
Interrupt levels 4 and above are enabled
Interrupt levels 5 and above are enabled
1 0 1
1 1 0
1 1 1
Level 5
Level 6
Level 7
High
1 0 1
1 1 0
1 1 1
Interrupt levels 6 and above are enabled
Interrupt levels 7 and above are enabled
All maskable interrupts are disabled
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Rewrite the interrupt control register
To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for
that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after
the interrupt is disabled. The program examples are described as follow:
Example 1:
INT_SWITCH1:
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
NOP ;
NOP
FSET I ; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
MOV.W MEM, R0 ; Dummy read.
FSET I ; Enable interrupts.
Four NOP instructions are required when using HOLD function.
Example 3:
INT_SWITCH3:
PUSHC FLG ; Push Flag register onto stack
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
POPC FLG ; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted
before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the
interrupt control register is rewritten due to effects of the instruction queue.
When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below instructions to change
the register.
Instructions : AND, OR, BCLR, BSET
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the
instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,
the processor temporarily suspends the instruction being executed, and transfers control to the interrupt
sequence.
In the interrupt sequence, the processor carries out the following in sequence given:
(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading ad-
dress 0000016.
(2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence
in the temporary register (Note) within the CPU.
(3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to
“0” (the U flag, however does not change if the INT instruction, in software interrupt numbers 32
through 63, is executed)
(4) Saves the content of the temporary register (Note 1) within the CPU in the stack area.
(5) Saves the content of the program counter (PC) in the stack area.
(6) Sets the interrupt priority level of the accepted instruction in the IPL.
After the interrupt sequence is completed, the processor resumes executing instructions from the first
address of the interrupt routine.
Note: This register cannot be utilized by the user.
Interrupt Response Time
'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first
instruction within the interrupt routine has been executed. This time comprises the period from the
occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the
time required for executing the interrupt sequence (b). Figure 1.13.4 shows the interrupt response time.
Interrupt request acknowledgedInterrupt request generated
Time
Instruction Interrupt sequence
(a) (b)
Interrupt response time
Figure 1.13.4. Interrupt response time
Instruction in
interrupt routine
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Interrupt
Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the
DIVX instruction (without wait).
Time (b) is as shown in Table 1.13.5.
Table 1.13.5. Time required for executing the interrupt sequence
Stack pointer (SP) valueInterrupt vector address 16-Bit bus, without wait 8-Bit bus, without wait
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Even
Even
Odd (Note 2)
Odd (Note 2)
Even
Odd
Even
Odd
________
18 cycles (Note 1)
19 cycles (Note 1)
19 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address coincidence
interrupt or of a single-step interrupt.
Note 2: Locate an interrupt vector address in an even address, if possible.
123456789101112 13 14 15 16 17 18
BCLK
Address bus
Data bus
R
W
Address
0000
Interrupt
information
The indeterminate segment is dependent on the queue buffer.
If the queue buffer is ready to take an instruction, a read cycle occurs.
Indeterminate SP-2 SP-4 vec vec+2
Indeterminate
Indeterminate
SP-2
contents
SP-4
contents
contents
vec
vec+2
contents
PC
Figure 1.13.5. Time required for executing the interrupt sequence
Variation of IPL when Interrupt Request is Accepted
If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.
If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown
in Table 1.13.6 is set in the IPL.
Table 1.13.6. Relationship between interrupts without interrupt priority levels and IPL
Interrupt sources without priority levels
_______
Watchdog timer, NMI
Reset
Other
Value set in the IPL
7
0
Not changed
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Saving Registers
In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter
(PC) are saved in the stack area.
First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8
lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the
program counter. Figure 1.13.6 shows the state of the stack as it was before the acceptance of the
interrupt request, and the state the stack after the acceptance of the interrupt request.
Save other necessary registers at the beginning of the interrupt routine using software. Using the
PUSHM instruction alone can save all the registers except the stack pointer (SP).
Address
MSB LSB
m – 4
m – 3
m – 2
m – 1
m
m + 1
Stack area
Content of previous stack
Content of previous stack
Stack status before interrupt request
is acknowledged
[SP]
Stack pointer
value before
interrupt occurs
Address
MSB LSB
m – 4
m – 3
m – 2
m – 1
m
m + 1
Stack status after interrupt request
is acknowledged
Stack area
Program counter (PC
Program counter (PC
Flag register (FLG
Flag register
(FLG
Content of previous stack
Content of previous stack
H
)
Program
counter (PCH)
L
M
L
)
Figure 1.13.6. State of stack before and after acceptance of interrupt request
[SP]
)
)
New stack
pointer value
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The operation of saving registers carried out in the interrupt sequence is dependent on whether the
content of the stack pointer, at the time of acceptance of an interrupt request, is even or odd. If the
content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the
program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at
a time. Figure 1.13.7 shows the operation of the saving registers.
Note: Stack pointer indicated by U flag.
(1) Stack pointer (SP) contains even number
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Address
[SP] – 5 (Odd)
[SP] – 4 (Even)
[SP] – 3(Odd)
[SP] – 2 (Even)
[SP] – 1(Odd)
[SP] (Even)
Stack area
Program counter (PC
Program counter (PC
Flag register (FLG
Flag register
(FLG
H
)
counter (PC
L
)
Program
L
)
M
)
Sequence in which order
registers are saved
(2) Saved simultaneously,
(1) Saved simultaneously,
H
)
Finished saving registers
in two operations.
(2) Stack pointer (SP) contains odd number
Address
[SP] – 5 (Even)
Stack area
Sequence in which order
registers are saved
all 16 bits
all 16 bits
[SP] – 4(Odd)
[SP] – 3 (Even)
[SP] – 2(Odd)
[SP] – 1 (Even)
[SP] (Odd)
Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Program counter (PC
Program counter (PCM)
Flag register (FLG
Flag register
(FLG
H
)
counter (PC
Figure 1.13.7. Operation of saving registers
52
L
)
Program
L
)
(3)
(4)
Saved simultaneously,
all 8 bits
(1)
H
)
(2)
Finished saving registers
in four operations.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Returning from an Interrupt Routine
Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register
(FLG) as it was immediately before the start of interrupt sequence and the contents of the program counter
(PC), both of which have been saved in the stack area. Then control returns to the program that was being
executed before the acceptance of the interrupt request, so that the suspended process resumes.
Return the other registers saved by software within the interrupt routine using the POPM or similar instruction before executing the REIT instruction.
Interrupt Priority
If there are two or more interrupt requests occurring at a point in time within a single sampling (checking
whether interrupt requests are made), the interrupt assigned a higher priority is accepted.
Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level
select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware
priority is accepted.
Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority),
watchdog timer interrupt, etc. are regulated by hardware.
Figure 1.13.8 shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
_______ ________
Reset > NMI > DBC > Watchdog timer > Peripheral I/O > Single step > Address match
Figure 1.13.8. Hardware interrupts priorities
Interrupt resolution circuit
When two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highest
priority level. Figure 1.13.9 shows the circuit that judges the interrupt priority level.
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Priority level of each interrupt
INT1
Timer B2
Timer B0
Timer A3
Timer A1
INT2
INT0
Timer B1
Timer A4
Timer A2
UART1 reception
UART0 reception
UART2 reception
Level 0 (initial value)
High
Priority of peripheral I/O interrupts
(if priority levels are same)
A-D conversion
DMA1
Bus collision detection
Timer A0
UART1 transmission
UART0 transmission
UART2 transmission
Key input interrupt
DMA0
Processor interrupt priority level (IPL)
Interrupt enable flag (I flag)
Address match
Watchdog timer
DBC
NMI
Low
Interrupt
request
accepted
Reset
Figure 1.13.9. Maskable interrupts priorities (peripheral I/O interrupts)
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________
NMI Interrupt
______
INT Interrupt
________ ________
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M16C / 61 Group
INT0 to INT2 are triggered by the edges of external inputs. The edge polarity is selected using the polarity
select bit.
______
NMI Interrupt
______ ______ ______
An NMI interrupt is generated when the input to the P85/NMI pin changes from “H” to “L”. The NMI interrupt
is a non-maskable external interrupt. The pin level can be checked in the port P85 register (bit 5 at address
03F016).
This pin cannot be used as a normal port input.
Key Input Interrupt
If the direction register of any of P104 to P107 is set for input and a falling edge is input to that port, a key
input interrupt is generated. A key input interrupt can also be used as a key-on wakeup function for cancelling the wait mode or stop mode. However, if you intend to use the key input interrupt, do not use P104 to
P107 as A-D input ports. Figure 1.13.10 shows the block diagram of the key input interrupt. Note that if an
“L” level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as
an interrupt.
Port P104-P107 pull-up
Pull-up
transistor
P107/KI
P106/KI
P105/KI
P104/KI
3
2
1
0
Pull-up
transistor
Pull-up
transistor
Pull-up
transistor
Port P107 direction register
Port P106 direction
register
Port P10
register
Port P10
register
select bit
Port P107 direction
register
5
direction
4
direction
Figure 1.13.10. Block diagram of key input interrupt
Key input interrupt control register
Interrupt control circuit
(address 004D16)
Key input interrupt
request
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Mitsubishi microcomputers
A
A
M16C / 61 Group
Address Match Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Address Match Interrupt
An address match interrupt is generated when the address match interrupt address register contents match
the program counter value. Two address match interrupts can be set, each of which can be enabled and
disabled by an address match interrupt enable bit. Address match interrupts are not affected by the interrupt enable flag (I flag) and processor interrupt priority level (IPL). The value of the program counter (PC)
for an address match interrupt varies depending on the instruction being executed.
Figure 1.13.11 shows the address match interrupt-related registers.
Address match interrupt enable register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
AIER 0009
AIER0
AAAAAAAAAAAA
AIER1
AAAAAAAAAAAA
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminated.
Address match interrupt register i (i = 0, 1)
(b23)
b7
(b19) (b16)
(b15) (b8)
b0 b7 b0b3
Address setting register for address match interrupt
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminated.
b7 b0
16 XXXXXX002
Bit nameBit symbol
Address match interrupt 0
enable bit
Address match interrupt 1
enable bit
Symbol Address When reset
RMAD0 0012
RMAD1 001616 to 001416 X0000016
Function Values that can be set
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Function
16 to 001016 X0000016
0000016 to FFFFF16
WR
WR
Figure 1.13.11. Address match interrupt-related registers
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Mitsubishi microcomputers
M16C / 61 Group
Precautions for Interrupts
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Precautions for Interrupts
(1) Reading address 0000016
• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and
interrupt request level) in the interrupt sequence.
The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”.
Reading address 0000016 by software sets enabled highest priority interrupt source request bit to “0”.
Though the interrupt is generated, the interrupt routine may not be executed.
Do not read address 0000016 by software.
(2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt
before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in
_______
the stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack point
at the beginning of a program. Concerning the first instruction immediately after reset, generating any
interrupts including the NMI interrupt is prohibited.
_______
_______
(3) The NMI interrupt
• As for the NMI interrupt pin, an interrupt cannot be disabled. Connect it to the VCC pin via a resistor
(pull-up) if unused. Be sure to work on it.
• The NMI pin also serves as P85, which is exclusively input. Reading the contents of the P8 register
allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time
when the NMI interrupt is input.
• Do not reset the CPU with the input to the NMI pin being in the “L” state.
• Do not attempt to go into stop mode with the input to the NMI pin being in the “L” state. With the input to
the NMI being in the “L” state, the CM10 is fixed to “0”, so attempting to go into stop mode is turned
down.
• Do not attempt to go into wait mode with the input to the NMI pin being in the “L” state. With the input to
the NMI pin being in the “L” state, the CPU stops but the oscillation does not stop, so no power is saved.
In this instance, the CPU is returned to the normal state by a later interrupt.
• Signals input to the NMI pin require an "L" level of 1 clock or more, from the operation clock of the CPU.
_______
_______
_______
_______
_______
_______
_______
_______
_______
(4) External interrupt
• Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0
through INT2 regardless of the CPU operation clock.
• When the polarity of the INT0 to INT2 pins is changed, the interrupt request bit is sometimes set to "1".
After changing the polarity, set the interrupt request bit to "0". Figure 1.13.12 shows the procedure for
changing the INT interrupt generate factor.
________
________ ________
______
________
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Precautions for Interrupts
Clear the interrupt enable flag to “0”
(Disable interrupt)
Set the interrupt priority level to level 0
(Disable
INTi interrupt)
Set the polarity select bit
Clear the interrupt request bit to “0”
Set the interrupt priority level to level 1 to 7
(Enable the accepting of INTi interrupt request)
Set the interrupt enable flag to “1”
(Enable interrupt)
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure 1.13.12. Switching condition of INT interrupt request
______
(5) Rewrite the interrupt control register
• To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for
that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after
the interrupt is disabled. The program examples are described as follow:
Example 1:
INT_SWITCH1:
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
NOP ;
NOP
FSET I ; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
MOV.W MEM, R0 ; Dummy read.
FSET I ; Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC FLG ; Push Flag register onto stack
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
POPC FLG ; Enable interrupts.
Four NOP instructions are required when using HOLD function.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted
before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the
interrupt control register is rewritten due to effects of the instruction queue.
• When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below instructions to change
the register.
Instructions : AND, OR, BCLR, BSET
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Mitsubishi microcomputers
M16C / 61 Group
Watchdog Timer
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Watchdog Timer
The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is
a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog
timer interrupt is generated when an underflow occurs in the watchdog timer. When XIN is selected for the
BCLK, bit 7 of the watchdog timer control register (address 000F16) selects the prescaler division ratio (by
16 or by 128). When XCIN is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7
of the watchdog timer control register (address 000F16). Thus the watchdog timer's period can be calculated as given below. The watchdog timer's period is, however, subject to an error due to the pre-scaler.
With XIN chosen for BCLK
Watchdog timer period =
pre-scaler dividing ratio (16 or 128) X watchdog timer count (32768)
BCLK
With XCIN chosen for BCLK
Watchdog timer period =
pre-scaler dividing ratio (2) X watchdog timer count (32768)
BCLK
For example, suppose that BCLK runs at 10 MHZ and that 16 has been chosen for the dividing ratio of the
pre-scaler, then the watchdog timer's period becomes approximately 52.4 ms.
The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when
a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is
reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by
writing to the watchdog timer start register (address 000E16).
Figure 1.14.1 shows the block diagram of the watchdog timer. Figure 1.14.2 shows the watchdog timerrelated registers.
Prescaler
“CM07 = 0”
“WDC7 = 0”
1/16
“CM07 = 0”
BCLK
HOLD
Write to the watchdog timer
start register
(address 000E
RESET
16
)
1/128
1/2
“WDC7 = 1”
“CM07 = 1”
Figure 1.14.1. Block diagram of watchdog timer
Watchdog timer
Set to
“7FFF
Watchdog timer
interrupt request
16
”
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Watchdog Timer
Watchdog timer control register
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
b7 b6 b5 b4 b3 b2 b1 b0
00
High-order bit of watchdog timer
Reserved bit
Reserved bit Must always be set to “0”
WDC7
Watchdog timer start register
b7 b0
The watchdog timer is initialized and starts counting after a write instruction to
this register. The watchdog timer value is always initialized to “7FFF
regardless of whatever value is written.
Symbol Address When reset
WDC 000F
Bit name
Prescaler select bit 0 : Divided by 16
Symbol Address When reset
WDTS 000E
16
16
Function
000XXXXX
Must always be set to “0”
1 : Divided by 128
Indeterminate
2
FunctionBit symbol WR
16
”
WR
Figure 1.14.2. Watchdog timer control and start registers
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Mitsubishi microcomputers
M16C / 61 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to
memory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given a
higher right of using the bus than the CPU, which leads to working the cycle stealing method. On this
account, the operation from the occurrence of DMA transfer request signal to the completion of 1-word (16bit) or 1-byte (8-bit) data transfer can be performed at high speed. Figure 1.15.1 shows the block diagram
of the DMAC. Table 1.15.1 shows the DMAC specifications. Figure 1.15.2 to Figure 1.15.3 show the registers used by the DMAC.
Address bus
DMA0 source pointer SAR0(20)
16
(addresses 0022
DMA0 destination pointer DAR0 (20)
DMA0 forward address pointer (20) (Note)
to 002016)
(addresses 002616 to 002416)
DMA0 transfer counter reload register TCR0 (16)
(addresses 002916, 002816)
DMA0 transfer counter TCR0 (16)
DMA1 transfer counter reload register TCR1 (16)
(addresses 0039
DMA1 transfer counter TCR1 (16)
Data bus low-order bits
Data bus high-order bits
16
, 003816)
DMA1 source pointer SAR1 (20)
(addresses 003216 to 003016)
DMA1 destination pointer DAR1 (20)
(addresses 003616 to 003416)
DMA1 forward address pointer (20) (Note)
DMA latch high-order bits
Note: Pointer is incremented by a DMA request.
DMA latch low-order bits
Figure 1.15.1. Block diagram of DMAC
Either a write signal to the software DMA request bit or an interrupt request signal is used as a DMA transfer
request signal. But the DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the
interrupt priority level. The DMA transfer doesn't affect any interrupts either.
If the DMAC is active (the DMA enable bit is set to 1), data transfer starts every time a DMA transfer request
signal occurs. If the cycle of the occurrences of DMA transfer request signals is higher than the DMA
transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the
number of transfers. For details, see the description of the DMA request bit.
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DMAC
Table 1.15.1. DMAC specifications
Item Specification
No. of channels 2 (cycle steal method)
Transfer memory space • From any address in the 1M bytes space to a fixed address
• From a fixed address to any address in the 1M bytes space
• From a fixed address to a fixed address
(Note that DMA-related registers [002016 to 003F16] cannot be accessed)
Maximum No. of bytes transferred
DMA request factors (Note)
Channel priority
Transfer unit 8 bits or 16 bits
Transfer address direction forward/fixed (forward direction cannot be specified for both source and
Transfer mode •Single transfer mode
DMA interrupt request generation timing
Active When the DMA enable bit is set to “1”, the DMAC is active.
Inactive • When the DMA enable bit is set to “0”, the DMAC is inactive.
Forward address pointer and
load timing for transfer
counter
Writing to register
Reading the register Can be read at any time.
Note: DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the interrupt enable
flag (I flag) nor by the interrupt priority level.
128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
________ ________ ________ ________
Falling edge of INT0 or INT1 (INT0 can be selected by DMA0, INT1 by DMA1)
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B2 interrupt requests
UART0 transmission and reception interrupt requests
UART1 transmission and reception interrupt requests (UART1 transmission can be selected by DMA0, UART1 reception by DMA1)
UART2 transmission and reception interrupt requests
A-D conversion interrupt requests
Software triggers
DMA0 takes precedence if DMA0 and DMA1 requests are generated simultaneously
destination simultaneously)
After the transfer counter underflows, the DMA enable bit turns to
“0”, and the DMAC turns inactive
• Repeat transfer mode
After the transfer counter underflows, the value of the transfer counter
reload register is reloaded to the transfer counter.
The DMAC remains active unless a “0” is written to the DMA enable bit.
When an underflow occurs in the transfer counter
When the DMAC is active, data transfer starts every time a DMA
transfer request signal occurs.
• After the transfer counter underflows in single transfer mode
At the time of starting data transfer immediately after turning the DMAC active,
the value of one of source pointer and destination pointer - the one specified for the
forward direction - is reloaded to the forward direction address pointer,and the value
of the transfer counter reload register is reloaded to the transfer counter.
Registers specified for forward direction transfer are always write enabled.
Registers specified for fixed address transfer are write-enabled when
the DMA enable bit is “0”.
However, when the DMA enable bit is “1”, reading the register set up as the
forward register is the same as reading the value of the forward address pointer.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
re
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DMAC
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAi request cause select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
DMiSL(i=0,1) 03B8
Bit symbol
DSEL0
DMA request cause
Bit name
DSEL1
DSEL2
DSEL3
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
DSR
Software DMA request bit
select bit
16
,03BA
16
00
16
Function
b3 b2 b1 b0
0 0 0 0 : Falling edge of INT0 / INT1
pin (Note 1)
0 0 0 1 : Software trigger
0 0 1 0 : Timer A0
0 0 1 1 : Timer A1
0 1 0 0 : Timer A2
0 1 0 1 : Timer A3
0 1 1 0 : Timer A4
0 1 1 1 : Timer B0
1 0 0 0 : Timer B1
1 0 0 1 : Timer B2
1 0 1 0 : UART0 transmit
1 0 1 1 : UART0 receive
1 1 0 0 : UART2 transmit
1 1 0 1 : UART2 receive
1 1 1 0 : A-D conversion
1 1 1 1 : UART1 transmit / UART1
receive (Note 2)
If software trigger is selected, a
DMA request is generated by
setting this bit to “1” (When read,
the value of this bit is always “0”)
Note 1: Address 03B816 is for INT0 ; address 03BA16 is for INT1.
Note 2: Address 03B8
16
is for UART1 transmit ; address 03BA16 is for UART1 receive.
RW
DMAi control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
DMiCON(i=0,1) 002C
DMBIT
DMASL
DMAS
DMAE
DSD
DAD
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
Note 1: DMA request can be cleared by resetting the bit.
Note 2: This bit can only be set to “0”.
Note 3: Source address direction select bit and destination address direction select bit
Figure 1.15.2. DMAC register (1)
16
, 003C
Bit name FunctionBit symbol
Transfer unit bit select bit
Repeat transfer mode
select bit
DMA request bit (Note 1)
DMA enable bit
Source address direction
select bit (Note 3)
Destination address
direction select bit (Note 3)
cannot be set to “1” simultaneously.
16
00000X00
2
0 : 16 bits
1 : 8 bits
0 : Single transfer
1 : Repeat transfer
0 : DMA not requested
1 : DMA requested
0 : Disabled
1 : Enabled
0 : Fixed
1 : Forward
0 : Fixed
1 : Forward
RW
(Note 2)
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DMAC
DMAi source pointer (i = 0, 1)
(b23)
b7
b3 b0 b7 b0 b7 b0
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(b8)(b16)(b15)(b19)
Symbol Address When reset
SAR0 0022
SAR1 0032
16
to 0020
16
to 0030
16
16
Indeterminate
Indeterminate
• Source pointer
Stores the source address
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
DMAi destination pointer (i = 0, 1)
(b23)
b7
b3 b0 b7 b0 b7 b0
• Destination pointer
Stores the destination address
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
DMAi transfer counter (i = 0, 1)
b7 b0 b7 b0
(b8)(b15)
• Transfer counter
Set a value one less than the transfer count
16
, 0028
16
, 0038
Transfer count
specification
00000
16
to FFFFF
16
to 0024
16
to 0034
Transfer count
specification
00000
16
to FFFFF
16
16
Transfer count
specification
0000
16
to FFFF
16
16
Indeterminate
Indeterminate
Function
(b8)(b15)(b16)(b19)
Symbol Address When reset
DAR0 0026
DAR1 0036
Function
Symbol Address When reset
TCR0 0029
TCR1 0039
Function
RW
16
Indeterminate
Indeterminate
RW
16
RW
16
Figure 1.15.3. DMAC register (2)
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Mitsubishi microcomputers
M16C / 61 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Transfer cycle
The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area
(source read) and the bus cycle in which the data is written to memory or to the SFR area (destination
write). The number of read and write bus cycles depends on the source and destination addresses. In
memory expansion mode and microprocessor mode, the number of read and write bus cycles also depends on the level of the BYTE pin. Also, the bus cycle itself is longer when software waits are inserted.
(a) Effect of source and destination addresses
When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd
addresses, there are one more source read cycle and destination write cycle than when the source
and destination both start at even addresses.
(b) Effect of BYTE pin level
When transferring 16-bit data over an 8-bit data bus (BYTE pin = “H”) in memory expansion mode and
microprocessor mode, the 16 bits of data are sent in two 8-bit blocks. Therefore, two bus cycles are
required for reading the data and two are required for writing the data. Also, in contrast to when the
CPU accesses internal memory, when the DMAC accesses internal memory (internal ROM, internal
RAM, and SFR), these areas are accessed using the data size selected by the BYTE pin.
(c) Effect of software wait
When the SFR area or a memory area with a software wait is accessed, the number of cycles is
increased for the wait by 1 bus cycle. The length of the cycle is determined by BCLK.
Figure 1.15.4 shows the example of the transfer cycles for a source read. For convenience, the destination write cycle is shown as one cycle and the source read cycles for the different conditions are shown.
In reality, the destination write cycle is subject to the same conditions as the source read cycle, with the
transfer cycle changing accordingly. When calculating the transfer cycle, remember to apply the respective conditions to both the destination write cycle and the source read cycle. For example (2) in Figure 36,
if data is being transferred in 16-bit units on an 8-bit bus, two bus cycles are required for both the source
read cycle and the destination write cycle.
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DMAC
(1) 8-bit transfers
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
16-bit transfers from even address and the source address is even.
BCLK
Address
bus
CPU use
Destination
Dummy
cycle
CPU useSource
RD signal
WR signal
Data
bus
CPU use CPU use
Source
Destination
Dummy
cycle
(2) 16-bit transfers and the source address is odd
Transferring 16-bit data on an 8-bit data bus (In this case, there are also two destination write cycles).
BCLK
Address
bus
CPU use
Source + 1
Destination
Dummy
cycle
CPU useSource
RD signal
WR signal
Data
bus
CPU use
Source
Source + 1
Destination
Dummy
cycle
CPU use
(3) One wait is inserted into the source read under the conditions in (1)
BCLK
Address
bus
CPU use
Destination
Dummy
cycle
CPU useSource
RD signal
WR signal
Data
bus
CPU use CPU use
Source
Destination
Dummy
cycle
(4) One wait is inserted into the source read under the conditions in (2)
(When 16-bit data is transferred on an 8-bit data bus, there are two destination write cycles).
BCLK
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use CPU use
Source
Source + 1
Source + 1
Destination
Dummy
cycle
Destination
Dummy
cycle
CPU useSource
Note: The same timing changes occur with the respective conditions at the destination as at the source.
Figure 1.15.4. Example of the transfer cycles for a source read
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DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) DMAC transfer cycles
Any combination of even or odd transfer read and write addresses is possible. Table 1.15.2 shows the
number of DMAC transfer cycles.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k
Table 1.15.2. No. of DMAC transfer cycles
Single-chip mode Memory expansion mode
Transfer unit Bus width Access address Microprocessor mode
No. of read No. of write No. of read No. of write
cycles cycles cycles cycles
16-bit Even 1111
8-bit transfers (BYTE= “L”) Odd 1111
(DMBIT= “1”) 8-bit Even — — 1 1
(BYTE = “H”) Odd — — 1 1
16-bit Even 1111
16-bit transfers (BYTE = “L”) Odd 2222
(DMBIT= “0”) 8-bit Even — — 2 2
(BYTE = “H”) Odd — — 2 2
Coefficient j, k
Internal memory External memory
Internal ROM/RAM Internal ROM/RAM
No wait With wait No wait With wait bus
122123
SFR area Separate bus Separate bus Multiplex
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Mitsubishi microcomputers
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DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMA enable bit
Setting the DMA enable bit to 1 makes the DMAC active. The DMAC carries out the following operations at
the time data transfer starts immediately after DMAC is turned active.
(1) Reloads the value of one of the source pointer and the destination pointer - the one specified for the
forward direction - to the forward direction address pointer.
(2) Reloads the value of the transfer counter reload register to the transfer counter.
Thus overwriting 1 to the DMA enable bit with the DMAC being active carries out the operations given
above, so the DMAC operates again from the initial state at the instant 1 is overwritten to the DMA enable
bit.
DMA request bit
The DMAC can generate a DMA transfer request signal triggered by a factor chosen in advance out of DMA
request factors for each channel.
DMA request factors include the following.
* Factors effected by using the interrupt request signals from the built-in peripheral functions and software
DMA factors (internal factors) effected by a program.
* External factors effected by utilizing the input from external interrupt signals.
For the selection of DMA request factors, see the descriptions of the DMAi factor selection register.
The DMA request bit turns to 1 if the DMA transfer request signal occurs regardless of the DMAC's state
(regardless of whether the DMA enable bit is set 1 or to 0). It turns to 0 immediately before data transfer
starts.
In addition, it can be set to 0 by use of a program, but cannot be set to 1.
There can be instances in which a change in DMA request factor selection bit causes the DMA request bit
to turn to 1. So be sure to set the DMA request bit to 0 after the DMA request factor selection bit is changed.
The DMA request bit turns to 1 if a DMA transfer request signal occurs, and turns to 0 immediately before
data transfer starts. If the DMAC is active, data transfer starts immediately, so the value of the DMA request
bit, if read by use of a program, turns out to be 0 in most cases. To examine whether the DMAC is active,
read the DMA enable bit.
Here follows the timing of changes in the DMA request bit.
(1) Internal factors
Except the DMA request factors triggered by software, the timing for the DMA request bit to turn to 1 due
to an internal factor is the same as the timing for the interrupt request bit of the interrupt control register to
turn to 1 due to several factors.
Turning the DMA request bit to 1 due to an internal factor is timed to be effected immediately before the
transfer starts.
(2) External factors
An external factor is a factor caused to occur by the leading edge of input from the INTi pin (i depends on
which DMAC channel is used).
Selecting the INTi pins as external factors using the DMA request factor selection bit causes input from
these pins to become the DMA transfer request signals.
The timing for the DMA request bit to turn to 1 when an external factor is selected synchronizes with the
signal's edge applicable to the function specified by the DMA request factor selection bit (synchronizes
with the trailing edge of the input signal to each INTi pin, for example).
With an external factor selected, the DMA request bit is timed to turn to 0 immediately before data transfer
starts similarly to the state in which an internal factor is selected.
68
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Mitsubishi microcomputers
M16C / 61 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) The priorities of channels and DMA transfer timing
If a DMA transfer request signal falls on a single sampling cycle (a sampling cycle means one period from
the leading edge to the trailing edge of BCLK), the DMA request bits of applicable channels concurrently
turn to 1. If the channels are active at that moment, DMA0 is given a high priority to start data transfer.
When DMA0 finishes data transfer, it gives the bus right to the CPU. When the CPU finishes single bus
access, then DMA1 starts data transfer and gives the bus right to the CPU.
An example in which DMA transfer is carried out in minimum cycles at the time when DMA transfer
request signals due to external factors concurrently occur.
Figure 1.15.5 An example of DMA transfer effected by external factors.
An example in which DMA transmission is carried out in minimum
cycles at the time when DMA transmission request signals due to
external factors concurrently occur.
BCLK
DMA0
DMA1
CPU
INT0
DMA0
request bit
INT1
DMA1
request bit
Figure 1.15.5. An example of DMA transfer effected by external factors
Obtainm
ent of the
bus right
69
Page 70
Mitsubishi microcomputers
M16C / 61 Group
Timer
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer
There are eight 16-bit timers. These timers can be classified by function into timers A (five) and timers B
(three). All these timers function independently. Figure 1.16.1 shows the block diagram of timers.
Clock prescaler
f
TA0
TA1
X
IN
1/8
1/4
f
1 f8 f32 fC32
IN
IN
Noise
filter
Noise
filter
1
f
8
f
32
X
CIN
Clock prescaler reset flag (bit 7
at address 0381
• Timer mode
• One-shot mode
• PWM mode
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
• Event counter mode
16
1/32
Reset
) set to “1”
Timer A0
Timer A1
f
C32
Timer A0 interrupt
Timer A1 interrupt
TA2
TA3
TA4
TB0
TB1
• Timer mode
• One-shot mode
• PWM mode
Timer A2 interrupt
IN
IN
Noise
filter
Noise
filter
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
Timer A2
Timer A3 interrupt
Timer A3
Timer A4 interrupt
IN
IN
IN
Noise
filter
Noise
filter
Noise
filter
• Event counter mode
• Timer mode
• Pulse width measuring mode
• Event counter mode
• Timer mode
• Pulse width measuring mode
• Event counter mode
Timer A4
Timer B0
Timer B1
Timer B0 interrupt
Timer B1 interrupt
TB2
IN
Noise
filter
Figure 1.16.1. Block diagram of timer
70
• Timer mode
• Pulse width measuring mode
Timer B2
• Event counter mode
Timer B2 interrupt
Page 71
Mitsubishi microcomputers
M16C / 61 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Figure 1.16.2 shows the block diagram of timer A. Figures 1.16.3 to 1.16.5 show the timer A-related
registers.
Except in event counter mode, timers A0 through A4 all have the same function. Use the timer Ai mode
register (i = 0 to 4) bits 0 and 1 to choose the desired mode.
Timer A has the four operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer over flow.
• One-shot timer mode: The timer stops counting when the count reaches “000016”.
• Pulse width modulation (PWM) mode: The timer outputs pulses of a given width.
Clock source
f
f
f
f
C32
1
8
32
selection
• Timer
• One shot
• PWM
• Timer
(gate function)
• Event counter
Polarity
selection
TAi
IN
(i = 0 to 4)
TB2 overflow
TAj overflow
(j = i – 1. Note, however, that j = 4 when i = 0)
TAk overflow
(k = i + 1. Note, however, that k = 0 when i = 4)
TAi
(i = 0 to 4)
OUT
Pulse output
Clock selection
External
trigger
Figure 1.16.2. Block diagram of timer A
Count start flag
(Address 038016)
Down count
Up/down flag
(Address 038416)
Toggle flip-flop
Data bus high-order bits
Data bus low-order bits
Low-order
8 bits
Reload register (16)
Counter (16)
Up count/down count
Always down count except
in event counter mode
TAi Addresses TAj TAk
Timer A0 0387
Timer A1 0389
Timer A2 038B
Timer A3 038D
Timer A4 038F
High-order
8 bits
16
0386
16
16
16
16
16
Timer A4 Timer A1
0388
16
Timer A0 Timer A2
038A16Timer A1 Timer A3
038C16Timer A2 Timer A4
038E16Timer A3 Timer A0
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
TAiMR(i=0 to 4) 0396
TMOD0
TMOD1
MR0
MR1
MR2
MR3
TCK0
TCK1
Figure 1.16.3. Timer A-related registers (1)
16
to 039A
16
00
16
Bit name FunctionBit symbol
Operation mode select bit
Function varies with each operation mode
Count source select bit
(Function varies with each operation mode)
b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation
(PWM) mode
WR
71
Page 72
Timer A
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Ai register (Note)
(b15) (b8)
b7 b0b7 b0
• Timer mode 000016 to FFFF
Counts an internal count source
• Event counter mode 000016 to FFFF16
Counts pulses from an external source or timer overflow
• One-shot timer mode 000016 to FFFF
Counts a one shot width
• Pulse width modulation mode (16-bit PWM)
Functions as a 16-bit pulse width modulator
• Pulse width modulation mode (8-bit PWM)
Timer low-order address functions as an 8-bit
prescaler and high-order address functions as an 8-bit
pulse width modulator
Note: Read and write data in 16-bit units.
Count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
TABSR 0380
Symbol Address When reset
TA0 0387
TA1 0389
TA2 038B
TA3 038D
TA4 038F
Function
16
16
16
16
16
16
00
,0386
,0388
,038A
,038C
,038E
16
16
Indeterminate
16
Indeterminate
16
Indeterminate
16
Indeterminate
16
Values that can be set
0000
(Both high-order
Indeterminate
16
to FFFE
00
16
to FE
and low-order
addresses)
WR
16
16
16
16
Up/down flag
b7 b6 b5 b4 b3 b2 b1 b0
Bit name FunctionBit symbol
TA0S
TA1S
TA2S
TA3S
TA4S
TB0S
TB1S
TB2S
Timer A0 count start flag
Timer A1 count start flag
0 : Stops counting
1 : Starts counting
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
Symbol Address When reset
UDF 0384
16
00
Bit name FunctionBit symbol
TA0UD
TA1UD
TA2UD
TA3UD
TA4UD
TA2P
TA3P
TA4P
Timer A0 up/down flag
Timer A1 up/down flag
Timer A2 up/down flag
Timer A3 up/down flag
Timer A4 up/down flag
Timer A2 two-phase pulse
signal processing select bit
Timer A3 two-phase pulse
signal processing select bit
Timer A4 two-phase pulse
signal processing select bit
0 : Down count
1 : Up count
This specification becomes valid
when the up/down flag content is
selected for up/down switching
cause
0 : two-phase pulse signal
processing disabled
1 : two-phase pulse signal
processing enabled
When not using the two-phase
pulse signal processing function,
set the select bit to “0”
WR
16
WR
Figure 1.16.4. Timer A-related registers (2)
72
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Timer A
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
One-shot start flag
b7 b6 b5 b4 b3 b2 b1 b0
Trigger select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
ONSF 0382
16
00X00000
2
Bit name FunctionBit symbol
TA0OS
TA1OS
TA2OS
TA3OS
TA4OS
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be
TA0TGL
TA0TGH
Timer A0 one-shot start flag
Timer A1 one-shot start flag
Timer A2 one-shot start flag
Timer A3 one-shot start flag
Timer A4 one-shot start flag
Timer A0 event/trigger
select bit
1 : Timer start
When read, the value is “0”
b7 b6
0 0 :
Input on TA0IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA4 overflow is selected
1 1 : TA1 overflow is selected
Note: Set the corresponding port direction register to “0”.
Symbol Address When reset
TRGSR 0383
16
00
16
Bit name FunctionBit symbol
TA1TGL
TA1TGH
TA2TGL
TA2TGH
TA3TGL
TA3TGH
TA4TGL
TA4TGH
Timer A1 event/trigger
select bit
Timer A2 event/trigger
select bit
Timer A3 event/trigger
select bit
Timer A4 event/trigger
select bit
b1 b0
0 0 :
Input on TA1IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA0 overflow is selected
1 1 : TA2 overflow is selected
b3 b2
0 0 :
Input on TA2IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA1 overflow is selected
1 1 : TA3 overflow is selected
b5 b4
Input on TA3IN is selected (Note)
0 0 :
0 1 : TB2 overflow is selected
1 0 : TA2 overflow is selected
1 1 : TA4 overflow is selected
b7 b6
Input on TA4IN is selected (Note)
0 0 :
0 1 : TB2 overflow is selected
1 0 : TA3 overflow is selected
1 1 : TA0 overflow is selected
Note: Set the corresponding port direction register to “0”.
i
ndeterminate.
WR
WR
Clock prescaler reset flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
CPSRF 0381
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
CPSR
Clock prescaler reset flag
Figure 1.16.5. Timer A-related registers (3)
16
Bit name FunctionBit symbol
0XXXXXXX
2
WR
0 : No effect
1 : Prescaler is reset
(When read, the value is “0”)
73
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Mitsubishi microcomputers
M16C / 61 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.16.1.) Figure 1.16.6
shows the timer Ai mode register in timer mode.
Table 1.16.1. Specifications of timer mode
Item Specification
Count source f1, f8, f32, fC32
Count operation • Down count
•
When the timer underflows, it reloads the reload register contents before continuing counting
Divide ratio 1/(n+1) n : Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
TAiIN pin function Programmable I/O port or gate input
TAiOUT pin function Programmable I/O port or pulse output
Read from timer Count value can be read out by reading timer Ai register
Write to timer • When counting stopped
Select function • Gate function
When the timer underflows
When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Counting can be started and stopped by the TAiIN pin’s input signal
• Pulse output function
Each time the timer underflows, the TAiOUT pin’s polarity is reversed
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
00
Symbol Address When reset
TAiMR(i=0 to 4) 0396
TMOD0
TMOD1
MR0
MR1
MR2
MR3
TCK0
TCK1
Operation mode
select bit
Pulse output function
select bit
Gate function select bit
0 (Must always be fixed to “0” in timer mode)
Count source select bit
16
Bit name FunctionBit symbol WR
Note 1: The settings of the corresponding port register and port direction register
are invalid.
Note 2: The bit can be “0” or “1”.
Note 3: Set the corresponding port direction register to “0”.
Figure 1.16.6. Timer Ai mode register in timer mode
to 039A
16
00
16
b1 b0
0 0 : Timer mode
0 : Pulse is not output
(TA
iOUT
1 : Pulse is output (Note 1)
(TA
b4 b3
0 X
1 0 : Timer counts only when TA
1 1 : Timer counts only when TA
b7 b6
0 0 : f
0 1 : f8
1 0 : f
1 1 : f
pin is a normal port pin)
iOUT
pin is a pulse output pin)
(Note 2)
: Gate function not available
(TAiIN pin is a normal port pin)
held “L” (Note 3)
held “H” (Note 3)
1
32
C32
iIN
iIN
pin is
pin is
74
Page 75
Mitsubishi microcomputers
M16C / 61 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer’s overflow. Timers A0 and A1 can
count a single-phase external signal. Timers A2, A3, and A4 can count a single-phase and a two-phase
external signal. Table 1.16.2 lists timer specifications when counting a single-phase external signal.
Figure 1.16.7 shows the timer Ai mode register in event counter mode.
Table 1.16.3 lists timer specifications when counting a two-phase external signal. Figure 1.16.8 shows
the timer Ai mode register in event counter mode.
Table 1.16.2.
Count source
Count operation • Up count or down count can be selected by external signal or software
Divide ratio 1/ (FFFF16 - n + 1) for up count
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
TAiIN pin function Programmable I/O port or count source input
TAiOUT pin function Programmable I/O port, pulse output, or up/down count select input
Read from timer Count value can be read out by reading timer Ai register
Write to timer • When counting stopped
Select function • Free-run count function
Note: This does not apply when the free-run function is selected.
Timer specifications in event counter mode (when not processing two-phase pulse signal)
Item Specification
•
External signals input to TAiIN pin (effective edge can be selected by software)
• TB2 overflow, TAj overflow
• When the timer overflows or underflows, it reloads the reload register con
tents before continuing counting (Note)
1/ (n + 1) for down count n : Set value
The timer overflows or underflows
When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Even when the timer overflows or underflows, the reload register content is not reloaded to it
• Pulse output function
Each time the timer overflows or underflows, the TAiOUT pin’s polarity is reversed
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
010
Symbol Address When reset
TAiMR(i = 0, 1) 0396
Bit symbol Bit name Function
TMOD0
TMOD1
Note 1: In event counter mode, the count source is selected by the event / trigger select bit
Note 2: The settings of the corresponding port register and port direction register are invalid.
Note 3: Valid only when counting an external signal.
Note 4: When an “L” signal is input to the TAi
Operation mode select bit
Pulse output function
MR0
select bit
Count polarity
MR1
select bit (Note 3)
MR2
Up/down switching
cause select bit
MR3
0 (Must always be fixed to “0” in event counter mode)
TCK0
Count operation type
select bit
Invalid in event counter mode
TCK1
Can be “0” or “1”
(addresses 0382
the upcount is activated. Set the corresponding port direction register to “0”.
16
16
and 038316).
, 0397
16
00
b1 b0
0 1 : Event counter mode
0 : Pulse is not output
iOUT
pin is a normal port pin)
(TA
1 : Pulse is output (Note 2)
(TA
iOUT
pin is a pulse output pin)
0 : Counts external signal's falling edge
1 : Counts external signal's rising edge
0 : Up/down flag's content
1 : TA
iOUT
pin's input signal (Note 4)
0 : Reload type
1 : Free-run type
OUT
pin, the downcount is activated. When “H”,
Figure 1.16.7. Timer Ai mode register in event counter mode
16
RW
WR
(Note 1)
75
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Mitsubishi microcomputers
TAi
OUT
TAi
IN
(i=3,4)
Count up all edges
Count up all edges
Count down all edges
Count down all edges
M16C / 61 Group
Timer A
Table 1.16.3. Timer specifications in event counter mode (when processing two-phase pulse
signal with timers A2, A3, and A4)
Item Specification
Count source • Two-phase pulse signals input to TAiIN or TAiOUT pin
Count operation • Up count or down count can be selected by two-phase pulse signal
• When the timer overflows or underflows, the reload register content is
reloaded and the timer starts over again (Note)
Divide ratio 1/ (FFFF16 - n + 1) for up count
1/ (n + 1) for down count n : Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
TAiIN pin function Two-phase pulse input
TAiOUT pin function Two-phase pulse input
Read from timer Count value can be read out by reading timer A2, A3, or A4 register
Write to timer • When counting stopped
Select function • Normal processing operation
Timer overflows or underflows
When a value is written to timer A2, A3, or A4 register, it is written to both
reload register and counter
• When counting in progress
When a value is written to timer A2, A3, or A4 register, it is written to only
reload register. (Transferred to counter at next reload time.)
The timer counts up rising edges or counts down falling edges on the TAiIN
pin when input signal on the TAiOUT pin is “H”
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
TAi
OUT
TAi
IN
(i=2,3)
• Multiply-by-4 processing operation
If the phase relationship is such that the TAiIN pin goes “H” when the input
signal on the TAiOUT pin is “H”, the timer counts up rising and falling edges
on the TAiOUT and TAiIN pins. If the phase relationship is such that the
TAiIN pin goes “L” when the input signal on the TAiOUT pin is “H”, the timer
counts down rising and falling edges on the TAiOUT and TAiIN pins.
Note: This does not apply when the free-run function is selected.
Up
count
Up
count
Up
count
Down
count
Down
count
Down
count
76
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Timer A
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Ai mode register
(When not using two-phase pulse signal processing)
b7 b6 b5 b4 b3 b2 b1 b0
010
Symbol Address When reset
16
to 039A
16
00
TAiMR(i = 2 to 4) 0398
Bit symbol Bit name Function
TMOD0
TMOD1
MR0
Operation mode select bit
Pulse output function
select bit
16
b1 b0
0 1 : Event counter mode
0 : Pulse is not output
(TAi
OUT
pin is a normal port pin)
WR
1 : Pulse is output (Note 1)
(TAi
OUT
pin is a pulse output pin)
MR1
MR2
MR3
TCK0
TCK1
Count polarity
select bit (Note 2)
Up/down switching
cause select bit
0 : (Must always be “0” in event counter mode)
Count operation type
select bit
Two-phase pulse signal
processing operation
select bit (Note 4)(Note 5)
0 : Counts external signal's falling edges
1 : Counts external signal's rising edges
0 : Up/down flag's content
1 : TA
iOUT
pin's input signal (Note 3)
0 : Reload type
1 : Free-run type
0 : Normal processing operation
1 : Multiply-by-4 processing operation
Note 1: The settings of the corresponding port register and port direction register are invalid.
Note 2: This bit is valid when only counting an external signal.
Note 3: Set the corresponding port direction register to “0”.
Note 4: This bit is valid for the timer A3 mode register.
For timer A2 and A4 mode registers, this bit can be “0 ”or “1”.
Note 5: When performing two-phase pulse signal processing, make sure the two-phase pulse
signal processing operation select bit (address 0384
sure to set the event/trigger select bit (addresses 0382
16
) is set to “1”. Also, always be
16
and 038316) to “00”.
Timer Ai mode register
(When using two-phase pulse signal processing)
b7 b6 b5 b4 b3 b2 b1 b0
010
001
Symbol Address When reset
TAiMR(i = 2 to 4) 0398
16
to 039A
Bit symbol Bit name Function
TMOD0
TMOD1
MR0
MR1
MR2
MR3
TCK0
TCK1
Note 1: This bit is valid for timer A3 mode register.
Note 2: When performing two-phase pulse signal processing, make sure the two-phase pulse
Operation mode select bit
0 (Must always be “0” when using two-phase pulse signal
processing)
0 (Must always be “0” when using two-phase pulse signal
processing)
1 (Must always be “1” when using two-phase pulse signal
processing)
0 (Must always be “0” when using two-phase pulse signal
processing)
Count operation type
select bit
Two-phase pulse
processing operation
select bit (Note 1)(Note 2)
For timer A2 and A4 mode registers, this bit can be “0” or “1”.
signal processing operation select bit (address 0384
sure to set the event/trigger select bit (addresses 0382
16
00
16
b1 b0
0 1 : Event counter mode
0 : Reload type
1 : Free-run type
0 : Normal processing operation
1 : Multiply-by-4 processing operation
16
) is set to “1”. Also, always be
16
and 038316) to “00”.
WR
Figure 1.16.8. Timer Ai mode register in event counter mode
77
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Mitsubishi microcomputers
p
M16C / 61 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) One-shot timer mode
In this mode, the timer operates only once. (See Table 1.16.4.) When a trigger occurs, the timer starts up
and continues operating for a given period. Figure 1.16.9 shows the timer Ai mode register in one-shot
timer mode.
Table 1.16.4. Timer specifications in one-shot timer mode
Item Specification
Count source f1, f8, f32, fC32
Count operation • The timer counts down
• When the count reaches 000016, the timer stops counting after reloading a new count
• If a trigger occurs when counting, the timer reloads a new count and restarts counting
Divide ratio 1/n n : Set value
Count start condition • An external trigger is input
• The timer overflows
• The one-shot start flag is set (= 1)
Count stop condition • A new count is reloaded after the count has reached 000016
• The count start flag is reset (= 0)
Interrupt request generation timing
TAiIN pin function Programmable I/O port or trigger input
TAiOUT pin function Programmable I/O port or pulse output
Read from timer When timer Ai register is read, it indicates an indeterminate value
Write to timer • When counting stopped
The count reaches 000016
When a value is written to timer Ai register, it is written to both reload
register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
100
Symbol Address When reset
TAiMR(i = 0 to 4) 0396
Bit symbol
TMOD0
TMOD1
MR0
MR1
MR2
MR3
TCK0
TCK1
Note 1: The settings of the corresponding port register and port direction register are invalid.
Note 2: Valid only when the TA
Note 3: Set the corres
Operation mode select bit
Pulse output function
select bit
External trigger select
bit (Note 2)
Trigger select bit
0 (Must always be “0” in one-shot timer mode)
Count source select bit
(addresses 0382
16
to 039A
16
00
16
Bit name
b1 b0
1 0 : One-shot timer mode
0 : Pulse is not output
(TA
iOUT
1 : Pulse is output (Note 1)
(TAi
OUT
0 : Falling edge of TAiIN pin's input signal (Note 3)
1 : Rising edge of TAi
0 : One-shot start flag is valid
1 : Selected by event/trigger select
register
b7 b6
0 0 : f
1
0 1 : f
8
1 0 : f
32
1 1 : f
C32
iIN
pin is selected by the event/trigger select bit
16
and 038316). If timer overflow is selected, this bit can be “1” or “0”.
onding port direction register to “0”.
Figure 1.16.9. Timer Ai mode register in one-shot timer mode
Function
pin is a normal port pin)
pin is a pulse output pin)
IN
pin's input signal (Note 3)
WR
78
Page 79
Mitsubishi microcomputers
M16C / 61 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(4) Pulse width modulation (PWM) mode
In this mode, the timer outputs pulses of a given width in succession. (See Table 1.16.5.) In this mode, the counter functions
as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure 1.16.10 shows the configuration of the
timer Ai mode register in pulse width modulation mode. Figure 1.16.11 shows an example of how a 16-bit pulse width
modulator operates. Figure 1.16.12 shows an example of how an 8-bit pulse width modulator operates.
Table 1.16.5. Timer specifications in pulse width modulation mode
Item Specification
Count source f1, f8, f32, fC32
Count operation • T
16-bit PWM • High level width n / fi n : Set value
8-bit PWM
Count start condition • External trigger is input
Count stop condition • The count start flag is reset (= 0)
Interrupt request generation timing
TAiIN pin function Programmable I/O port or trigger input
TAiOUT pin function Pulse output
Read from timer When timer Ai register is read, it indicates an indeterminate value
Write to timer • When counting stopped
he timer counts down (operating as an 8-bit or a 16-bit pulse width modulator)
•
The timer reloads a new count at a rising edge of PWM pulse and continues counting
• The timer is not affected by a trigger that occurs when counting
• Cycle time (216 -
•
High level widthn X (m+1) / fi n : values set to timer Ai register’s high-order address
•
Cycle time (28 - 1) X (m +1) / fim : values set to timer Ai register’s low-order address
1) / fi fixed
• The timer overflows
• The count start flag is set (= 1)
PWM pulse goes “L”
When a value is written to timer Ai register, it is written to both reload
register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
111
Symbol Address When reset
TAiMR(i=0 to 4) 0396
TMOD0
TMOD1
MR0
MR1
MR2
MR3
TCK0
TCK1
Note 1: Valid only when the TA
Note 2: Set the corresponding port direction register to “0”.
Operation mode
select bit
1 (Must always be fixed to “1” in PWM mode)
External trigger select
bit (Note 1)
Trigger select bit
16/8-bit PWM mode
select bit
Count source select bit
(addresses 0382
16
to 039A
16
00
16
Bit name FunctionBit symbol
iIN
16
and 038316). If timer overflow is selected, this bit can be “1” or “0
b1 b0
1 1 : PWM mode
0: Falling edge of TAiIN pin's input signal (Note 2)
1: Rising edge of TAi
0: Count start flag is valid
1: Selected by event/trigger select register
0: Functions as a 16-bit pulse width modulator
1: Functions as an 8-bit pulse width modulator
b7 b6
0 0 : f
1
0 1 : f
8
1 0 : f
32
1 1 : f
C32
pin is selected by the event/trigger select bit
IN
pin's input signal (Note 2)
Figure 1.16.10. Configuration of timer Ai mode register in pulse width modulation mode
WR
79
Page 80
Timer A
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Condition : Reload register = 000316, when external trigger
(rising edge of TA
Count source
TA
iIN
pin
input signal
PWM pulse output
iOUT
from TA
Timer Ai interrupt
request bit
pin
fi : Frequency of count source
(f
Note: n = 0000
“H”
“L”
“H”
“L”
“1”
“0”
1
, f8, f32, f
C32
)
16
iIN
pin input signal) is selected
1 / fi X (2 – 1)
Trigger is not generated by this signal
1 / f
Cleared to “0” when interrupt request is accepted, or cleared by software
to FFFE16.
16
i
X
n
Figure 1.16.11. Example of how a 16-bit pulse width modulator operates
Condition : Reload register high-order 8 bits = 02
Reload register low-order 8 bits = 02
External trigger (falling edge of TA
Count source (Note1)
TA
iIN
pin input signal
Underflow signal of
8-bit prescaler (Note2)
PWM pulse output
from TA
iOUT
pin
Timer Ai interrupt
request bit
“H”
“L”
“H”
“L”
“H”
“L”
“1”
“0”
fi : Frequency of count source
(f
1
, f8, f32, f
C32
)
Cleared to “0” when interrupt request is accepted, or cleaerd by software
16
16
iIN
pin input signal) is selected
1 / fi X (m + 1) X (2 – 1)
1 / fi X (m + 1)
1 / fi X (m + 1) X n
8
Note 1: The 8-bit prescaler counts the count source.
Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.
Note 3: m = 00
16
to FE16; n = 0016 to FE16.
Figure 1.16.12. Example of how an 8-bit pulse width modulator operates
80
Page 81
Mitsubishi microcomputers
M16C / 61 Group
Timer B
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
Figure 1.16.13 shows the block diagram of timer B. Figures 1.16.14 and 1.16.15 show the timer B-related
registers.
Use the timer Bi mode register (i = 0 to 2) bits 0 and 1 to choose the desired mode.
Timer B has three operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer overflow.
• Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or
pulse width.
Data bus high-order bits
Clock source selection
f
IN
TBi
(i = 0 to 2)
f
f
f
C32
1
8
32
Polarity switching
and edge pulse
Can be selected in only
event counter mode
TBj overflow
(j = i – 1. Note, however,
j = 2 when i = 0)
• Timer
• Pulse period/pulse width measurement
• Event counter
Figure 1.16.13. Block diagram of timer B
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
TBiMR(i = 0 to 2) 039B
Count start flag
(address 038016)
Counter reset circuit
16
to 039D
16
Data bus low-order bits
Low-order 8 bits
Reload register (16)
Counter (16)
TBi Address TBj
Timer B0 0391
Timer B1 0393
Timer B2 039516 039416 Timer B1
00XX00002
16
039016Timer B2
16
039216Timer B0
High-order 8 bits
TMOD0
TMOD1
MR0
MR1
MR2
MR3
TCK0
TCK1
Note 1: Timer B0.
Note 2: Timer B1, timer B2.
Operation mode select bit
Function varies with each operation mode
Count source select bit
(Function varies with each operation mode)
Figure 1.16.14. Timer B-related registers (1)
Bit name
b1 b0
FunctionBit symbol
0 0 : Timer mode
0 1 : Event counter mode
1 0 : Pulse period/pulse width
measurement mode
1 1 : Inhibited
WR
(Note 1)
(Note 2)
81
Page 82
Timer B
A
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Bi register (Note)
(b15) (b8)
b7 b0b7 b0
• Timer mode 000016 to FFFF16
Counts the timer's period
• Event counter mode 000016 to FFFF
Counts external pulses input or a timer overflow
• Pulse period / pulse width measurement mode
Measures a pulse period or width
Note: Read and write data in 16-bit units.
Count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
TABSR 0380
Bit symbol
TA0S
TA1S
TA2S
TA3S
TA4S
TB0S
TB1S
TB2S
Symbol Address When reset
TB0 0391
TB1 0393
TB2 0395
Function
16
Bit name
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
16
, 039016Indeterminate
16
, 039216Indeterminate
16
, 039416Indeterminate
Values that can be set
00
16
Function
0 : Stops counting
1 : Starts counting
WR
16
WR
Clock prescaler reset flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
CPSRF 0381
Bit symbol
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
CPSR
AAAAAAAAAAAAA
Figure 1.16.15. Timer B-related registers (2)
82
16
Bit name Function
Clock prescaler reset flag
0XXXXXXX
0 : No effect
1 : Prescaler is reset
(When read, the value is “0”)
2
WR
Page 83
Mitsubishi microcomputers
M16C / 61 Group
Timer B
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.16.6.) Figure 1.16.16
shows the timer Bi mode register in timer mode.
Table 1.16.6. Timer specifications in timer mode
Item Specification
Count source f1, f8, f32, fC32
Count operation • Counts down
• When the timer underflows, it reloads the reload register contents before
continuing counting
Divide ratio 1/(n+1) n : Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
TBiIN pin function Programmable I/O port
Read from timer Count value is read out by reading timer Bi register
Write to timer • When counting stopped
The timer underflows
When a value is written to timer Bi register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol Address When reset
TBiMR(i=0 to 2) 039B
0
Bit symbol WR
TMOD0
TMOD1
MR0
MR1
MR2
MR3
TCK0
TCK1
Note 1: Timer B0.
Note 2: Timer B1, timer B2.
Operation mode select bit
Invalid in timer mode
Can be “0” or “1”
0 (Fixed to “0” in timer mode ; i = 0)
Nothing is assiigned (i = 1,2).
In an attempt to write to this bit, write “0” . The value, if read, turns out
to be indeterminate.
Invalid in timer mode.
In an attempt to write to this bit, write “0” . The value, if read in
timer mode, turns out to be indeterminate.
Count source select bit
16
to 039D
Bit name Function
Figure 1.16.16. Timer Bi mode register in timer mode
16
00XX0000
b1 b0
0 0 : Timer mode
b7 b6
1
0 0 : f
0 1 : f
8
1 0 : f
32
1 1 : f
C32
2
(Note 1)
(Note 2)
83
Page 84
Mitsubishi microcomputers
M16C / 61 Group
Timer B
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 1.16.7.)
Figure 1.16.17 shows the timer Bi mode register in event counter mode.
Table 1.16.7. Timer specifications in event counter mode
Item Specification
Count source •External signals input to TBiIN pin
• Effective edge of count source can be a rising edge, a falling edge, or falling
and rising edges as selected by software
Count operation • Counts down
• When the timer underflows, it reloads the reload register contents before
continuing counting
Divide ratio 1/(n+1) n : Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
TBiIN pin function Count source input
Read from timer Count value can be read out by reading timer Bi register
Write to timer •When counting stopped
The timer underflows
When a value is written to timer Bi register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
01
Symbol Address When reset
TBiMR(i=0 to 2) 039B
TMOD0
TMOD1
MR0
MR1
MR2
MR3
TCK0
TCK1
Note 1: Valid only when input from the TBiIN pin is selected as the event clock.
Note 2: Timer B0.
Note 3: Timer B1, timer B2.
Note 4: Set the corresponding port direction register to “0”.
Operation mode select bit
Count polarity select
bit
(Note 1)
0 (Fixed to “0” in event counter mode; i = 0)
Nothing is assigned (i = 1, 2).
In an attempt to write to this bit, write “0” . The value, if read,
turns out to be indeterminate.
Invalid in event counter mode.
In an attempt to write to this bit, write “0” . The value, if read
in event counter mode, turns out to be indeterminate.
Invalid in event counter mode.
Can be “0” or “1”.
Event clock select
If timer's overflow is selected, this bit can be “0” or “1”.
16 to 039D16 00XX00002
Bit name FunctionBit symbol
b1 b0
0 1 : Event counter mode
b3 b2
0 0 : Counts external signal's
falling edges
0 1 : Counts external signal's
rising edges
1 0 : Counts external signal's
falling and rising edges
1 1 : Inhibited
0 : Input from TBi
1 : TBj overflow
(j = i – 1; however, j = 2 when i = 0)
IN pin (Note 4)
WR
(Note 2)
(Note 3)
Figure 1.16.17. Timer Bi mode register in event counter mode
84
Page 85
Mitsubishi microcomputers
M16C / 61 Group
Timer B
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) Pulse period/pulse width measurement mode
In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 1.16.8.)
Figure 1.16.18 shows the timer Bi mode register in pulse period/pulse width measurement mode. Figure
1.16.19 shows the operation timing when measuring a pulse period. Figure 1.16.20 shows the operation
timing when measuring a pulse width.
Table 1.16.8. Timer specifications in pulse period/pulse width measurement mode
Item Specification
Count source f1, f8, f32, fC32
Count operation • Up count
• Counter value “000016” is transferred to reload register at measurement
pulse's effective edge and the timer continues counting
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
TBiIN pin function Measurement pulse input
Read from timer When timer Bi register is read, it indicates the reload register’s content
Write to timer Cannot be written to
Note 1:
Note 2:
An interrupt request is not generated when the first effective edge is input after the timer has started counting.
The value read out from the timer Bi register is indeterminate until the second effective edge is input after the timer.
• When measurement pulse's effective edge is input (Note 1)
• When an overflow occurs. (Simultaneously, the timer Bi overflow flag
changes to “1”. The timer Bi overflow flag changes to “0” when the count
start flag is “1” and a value is written to the timer Bi mode register.)
(measurement result) (Note 2)
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
01
Symbol Address When reset
TBiMR(i=0 to 2) 039B
TMOD0
TMOD1
MR0
MR1
MR2
MR3
TCK0
TCK1
Note 1: The timer Bi overflow flag changes to “0” when the count start flag is “1” and a value is written to the
Note 2: Timer B0.
Note 3: Timer B1, timer B2.
Operation mode
select bit
Measurement mode
select bit
0 (Fixed to “0” in pulse period/pulse width measurement mode; i = 0)
Nothing is assigned (i = 1, 2).
In an attempt to write to this bit, write “0” . The value, if read, turns out to be
indeterminate.
Timer Bi overflow
flag ( Note 1)
Count source
select bit
timer Bi mode register. This flag cannot be set to “1” by software.
16
to 039D1600XX0000
Bit nameBit symbol
b1 b0
1 0 : Pulse period / pulse width
measurement mode
b3 b2
0 0 : Pulse period measurement (Interval between
measurement pulse's falling edge to falling edge)
0 1 : Pulse period measurement (Interval between
measurement pulse's rising edge to rising edge)
1 0 : Pulse width measurement (Interval between
measurement pulse's falling edge to rising edge,
and between rising edge to falling edge)
1 1 : Inhibited
0 : Timer did not overflow
1 : Timer has overflowed
b7 b6
1
0 0 : f
0 1 : f
8
1 0 : f
32
1 1 : f
C32
2
Function
WR
(Note 2)
(Note 3)
Figure 1.16.18. Timer Bi mode register in pulse period/pulse width measurement mode
85
Page 86
Timer B
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
When measuring measurement pulse time interval from falling edge to falling edge
Count source
Measurement pulse
“H”
“L”
Transfer
(indeterminate value)
Reload register counter
transfer timing
Timing at which counter
reaches “0000
Count start flag
Timer Bi interrupt
request bit
16
”
“1”
“0”
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software.
Timer Bi overflow flag
“1”
“0”
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Figure 1.16.19. Operation timing when measuring a pulse period
Transfer
(measured value)
(Note 1)(Note 1)
(Note 2)
Count source
Measurement pulse
Reload register counter
“H”
“L”
Transfer
(indeterminate
value)
Transfer
(measured value)
transfer timing
Timing at which counter
16
reaches “0000
Count start flag
Timer Bi interrupt
request bit
Timer Bi overflow flag
”
“1”
“0”
“1”
“0”
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software.
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Figure 1.16.20. Operation timing when measuring a pulse width
Transfer
(measured
value)
(Note 1)
Transfer
(measured value)
(Note 1)(Note 1)(Note 1)
(Note 2)
86
Page 87
Mitsubishi microcomputers
M16C / 61 Group
Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
Serial I/O is configured as three channels: UART0, UART1 and UART2. UART0, UART1 and UART2 each
have an exclusive timer to generate a transfer clock, so they operate independently of each other.
Figure 1.17.1 shows the block diagram of UART0, UART1 and UART2. Figure 1.17.2 and figure 1.17.3
show the block diagram of the transmit/receive unit.
UARTi (i = 0 to 2) has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous
serial I/O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses
03A016, 03A816 and 037816) determine whether UARTi is used as a clock synchronous serial I/O or as a
UART.
UART0 through UART2 are almost equal in their functions with minor exceptions. UART2, in particular, is
compliant with the SIM interface with some extra settings added in clock-asynchronous serial I/O mode
(Note). It also has the bus collision detection function that generates an interrupt request if the TXD pin and
the RXD pin are different in level.
Note: SIM : Subscriber Identity Module
Table 1.17.1 shows the comparison of functions of UART0 through UART2, and Figures 1.17.4 through
1.17.8 show the registers related to UARTi.
Table 1.17.1. Comparison of functions of UART0 through UART2
UART0 UART1 UART2Function
CLK polarity selection
LSB first / MSB first selection
Continuous receive mode selection
Transfer clock output from multiple
pins selection
Separate CTS/RTS pins
Sleep mode selection Impossible
Possible (Note 1)
Possible (Note 1)
Possible (Note 1)
Impossible
Possible
ImpossibleSerial data logic switch Impossible
Possible (Note 3)
ImpossibleTxD, RxD I/O polarity switch Impossible Possible
Possible (Note 1)
Possible (Note 1)
Possible (Note 1)
Possible (Note 1)
Impossible Impossible
Possible (Note 3)
Possible (Note 1)
Possible (Note 2)
Possible (Note 1)
Impossible
Possible (Note 4)
CMOS outputTxD, RxD port output format CMOS output
ImpossibleParity error signal output Impossible
ImpossibleBus collision detection Impossible Possible
Note 1: Only when clock synchronous serial I/O mode.
Note 2: Only when clock synchronous serial I/O mode and 8-bit UART mode.
Note 3: Only when UART mode.
Note 4: Using for SIM interface.
N-channel open-drain
output
Possible (Note 4)
87
Page 88
Serial I/O
(UART0)
CTS0 / RTS
RxD
0
Clock source selection
f
1
f
8
f
32
CLK
CLK
polarity
0
reversing
circuit
0
Bit rate generator
Internal
(address 03A1
1 / (n0+1)
External
Clock synchronous type
(when internal clock is selected)
CTS/RTS selected
Vcc
CTS/RTS disabled
CTS/RTS separated
CTS0 from UART1
1/16
16
)
1/16
1/2
CTS/RTS disabled
UART reception
Clock synchronous type
UART transmission
Clock synchronous type
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is
selected)
RTS
0
CTS
0
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
TxD
Reception
control circuit
Transmission
control circuit
Receive
clock
Transmit
clock
Transmit/
receive
unit
0
(UART1)
CTS1 / RTS
CTS0/ CLKS
(UART2)
RxD
CTS2 / RTS
RxD
1
Clock source selection
f
1
f
8
f
32
CLK
CLK
polarity
1
reversing
circuit
1
1
2
Clock source selection
f
1
f
8
f
32
CLK
2
polarity
reversing
circuit
CLK
2
Bit rate generator
(address 03A9
Internal
1 / (n1+1)
External
Clock synchronous type
(when internal clock is selected)
Clock output pin
select switch
RxD polarity
reversing circuit
Bit rate generator
Internal
(address 0379
1 / (n2+1)
External
Clock synchronous type
(when internal clock is selected)
CTS/RTS
selected
CTS/RTS disabled
Vcc
1/16
Clock synchronous type
16
)
1/16
Clock synchronous type
1/2
CTS/RTS separated
V
CTS
1/16
Clock synchronous type
16
)
1/16
Clock synchronous type
1/2
CTS/RTS disabled
UART reception
UART transmission
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is
selected)
CTS/RTS disabled
CC
CTS/RTS disabled
0
UART reception
UART transmission
Clock synchronous type
(when internal clock is selected)
CTS0 to UART0
Clock synchronous type
(when external clock is
selected)
RTS
2
CTS
2
n0 : Values set to UART0 bit rate generator (BRG0)
n1 : Values set to UART1 bit rate generator (BRG1)
n2 : Values set to UART2 bit rate generator (BRG2)
Transmission
control circuit
RTS
1
CTS
1
Reception
control circuit
Transmission
control circuit
Reception
control circuit
Receive
clock
Transmit
clock
Receive
clock
Transmit
clock
Transmit/
receive
unit
Transmit/
receive
unit
reversing
TxD
polarity
circuit
TxD
TxD
1
2
Figure 1.17.1. Block diagram of UARTi (i = 0 to 2)
88
Page 89
Serial I/O
RxDi
1SP
SP SP
2SP
PAR
PAR
disabled
PAR
enabled
Clock
synchronous
type
UART
Clock
synchronous type
UART (7 bits)
UART (8 bits)
UART (9 bits)
UART (7 bits)
Clock
synchronous type
UART (8 bits)
UART (9 bits)
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi receive register
0000000
D
D7D6D5D4D3D2D1D
8
MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
MSB/LSB conversion circuit
D7D6D5D4D3D2D1D
UART (8 bits)
UART (9 bits)
Clock synchronous
type
UART (7 bits)
SP SP
2SP
1SP
PAR
PAR
enabled
PAR
disabled
“0”
UART
Clock
synchronous
type
D
8
UART (9 bits)
UART (7 bits)
UART (8 bits)
Clock synchronous
type
Figure 1.17.2. Block diagram of UARTi (i = 0, 1) transmit/receive unit
UARTi transmit register
SP: Stop bit
PAR: Parity bit
0
UARTi transmit
0
buffer register
UARTi receive
buffer register
Address 03A616
Address 03A716
Address 03AE16
Address 03AF16
Address 03A216
Address 03A316
Address 03AA16
Address 03AB16
TxDi
89
Page 90
Serial I/O
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
RxD2
RxD data
reverse circuit
1SP
SP SP
2SP
SP SP
No reverse
Reverse
Clock
synchronous type
Clock
PAR
synchronous
disabled
PAR
enabled
type
UART
UART
(9 bits)
PAR
0000000
UART
(9 bits)
UART
(7 bits)
UART
(8 bits)
Clock
synchronous type
2SP
1SP
PAR
PAR
enabled
PAR
disabled
“0”
UART
Clock
synchronous
type
UART
(7 bits)
UART
(8 bits)
D
8
UART(7 bits)
Clock
synchronous type
UART
(8 bits)
UART
(9 bits)
D7D6D5D4D3D2D1D
Logic reverse circuit + MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
Logic reverse circuit + MSB/LSB conversion circuit
D
8
D7D6D5D4D3D2D1D
UART
(8 bits)
UART
(9 bits)
Clock
synchronous type
UART(7 bits)
Error signal output
disable
Error signal output
enable
UART2 receive register
UART2 transmit register
Error signal
output circuit
No reverse
Reverse
SP: Stop bit
PAR: Parity bit
TxD data
reverse circuit
0
0
UART2 receive
buffer register
Address 037E
Address 037F
UART2 transmit
buffer register
Address 037A
Address 037B
TxD2
16
16
16
16
Figure 1.17.3. Block diagram of UART2 transmit/receive unit
90
Page 91
Serial I/O
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit buffer register
(b15) (b8)
b7 b0
b7 b0
UARTi receive buffer register
(b15) (b8)
b7 b0
b7 b0
Symbol Address When reset
U0TB 03A3
U1TB 03AB
U2TB 037B
16
, 03A216Indeterminate
16
, 03AA16Indeterminate
16
, 037A16Indeterminate
Function
Transmit data
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
Symbol Address When reset
U0RB 03A7
U1RB 03AF
U2RB 037F
Bit
symbol
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
OER
FER
PER
SUM
Note: Bits 15 through 12 are set to “0” when the serial I/O mode select bit (bits 2 to 0 at addresses 03A0
03A8
(Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when the
lower byte of the UARTi receive buffer register (addresses 03A6
Bit name
Overrun error flag (Note)
Framing error flag (Note)
Parity error flag (Note)
Error sum flag (Note)
16
and 037816) are set to “0002” or the receive enable bit is set to “0”.
16
, 03A616Indeterminate
16
, 03AE16Indeterminate
16
, 037E16Indeterminate
Function
(During clock synchronous
serial I/O mode)
Receive data
0 : No overrun error
1 : Overrun error found
Invalid
Invalid
Invalid
Function
(During UART mode)
Receive data
0 : No overrun error
1 : Overrun error found
0 : No framing error
1 : Framing error found
0 : No parity error
1 : Parity error found
0 : No error
1 : Error found
16
, 03AE16 and 037E16) is read out.
WR
WR
16
,
UARTi bit rate generator
b7 b0
Assuming that set value = n, BRGi divides the count source by
n + 1
Symbol Address When reset
U0BRG 03A1
U1BRG 03A9
U2BRG 0379
Figure 1.17.4. Serial I/O-related registers (1)
Function
16
Indeterminate
16
Indeterminate
16
Indeterminate
Values that can be set
0016 to FF
16
WR
91
Page 92
Serial I/O
UARTi transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
UiMR(i=0,1) 03A0
16, 03A816 0016
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bit
symbol
SMD0
SMD1
SMD2
CKDIR
STPS
PRY
PRYE
SLEP
Bit name
Serial I/O mode select bit
Internal/external clock
select bit
Stop bit length select bit
Odd/even parity select bit
Parity enable bit
Sleep select bit
UART2 transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
U2MR 0378
Function
(During clock synchronous
serial I/O mode)
Must be fixed to 001
b2 b1 b0
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
0 : Internal clock
1 : External clock
Invalid
Invalid
Invalid
Must always be “0”
16 0016
Function
(During UART mode)
b2 b1 b0
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
0 : Internal clock
1 : External clock
0 : One stop bit
1 : Two stop bits
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
0 : Parity disabled
1 : Parity enabled
0 : Sleep mode deselected
1 : Sleep mode selected
WR
Bit
symbol
SMD0
SMD1
SMD2
CKDIR
STPS
PRY
PRYE
IOPOL
Bit name
Serial I/O mode select bit
Internal/external clock
select bit
Stop bit length select bit
Odd/even parity select bit
Parity enable bit
TxD, RxD I/O polarity
reverse bit
Figure 1.17.5. Serial I/O-related registers (2)
Function
(During clock synchronous
serial I/O mode)
Must be fixed to 001
b2 b1 b0
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
0 : Internal clock
1 : External clock
Invalid
Invalid
Invalid
0 : No reverse
1 : Reverse
Usually set to “0”
Function
(During UART mode)
b2 b1 b0
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
Must always be “0”
0 : One stop bit
1 : Two stop bits
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
0 : Parity disabled
1 : Parity enabled
0 : No reverse
1 : Reverse
Usually set to “0”
WR
92
Page 93
Serial I/O
UARTi transmit/receive control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
UiC0(i=0,1) 03A4
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
16, 03AC16 0816
Bit
symbol
CLK0
Bit name
BRG count source
select bit
CLK1
CRS
CTS/RTS function
select bit
TXEPT
Transmit register empty
flag
CRD
CTS/RTS disable bit
NCH
Data output select bit
CKPOL
CLK polarity select bit
UFORM Transfer format select bit
Note 1: Set the corresponding port direction register to “0”.
Note 2: The settings of the corresponding port register and port direction register are invalid.
Function
(During clock synchronous
serial I/O mode)
b1 b0
1 is selected
0 0 : f
0 1 : f
8 is selected
1 0 : f
32 is selected
1 1 : Inhibited
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
0 : Data present in transmit
register (during transmission)
1 : No data present in transmit
register (transmission
completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P6
0 and P64 function as
programmable I/O port)
0 : TXDi pin is CMOS output
1 : TXDi pin is N-channel
open-drain output
0 : Transmit data is output at
falling edge of transfer clock
and receive data is input at
rising edge
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
0 : LSB first
1 : MSB first
b1 b0
0 0 : f
0 1 : f
1 0 : f
1 1 : Inhibited
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
0 : Data present in transmit register
1 : No data present in transmit
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
0: TXDi pin is CMOS output
1: TXDi pin is N-channel
Must always be “0”
Must always be “0”
Function
(During UART mode)
1 is selected
8 is selected
32 is selected
(during transmission)
register (transmission completed)
(P6
0 and P64 function as
programmable I/O port)
open-drain output
WR
UART2 transmit/receive control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
U2C0 037C
Bit
symbol
CLK0
Bit name
BRG count source
select bit
CLK1
CRS
CTS/RTS function
select bit
TXEPT
Transmit register empty
flag
CRD
CTS/RTS disable bit
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.
CKPOL
CLK polarity select bit
Transfer format select bit
UFORM
(Note 3)
Note 1: Set the corresponding port direction register to “0”.
Note 2: The settings of the corresponding port register and port direction register are invalid.
Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid.
16 0816
Function
(During clock synchronous
serial I/O mode)
b1 b0
0 0 : f1 is selected
0 1 : f
8 is selected
1 0 : f
32 is selected
1 1 : Inhibited
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
0 : Data present in transmit
register (during transmission)
1 : No data present in transmit
register (transmission
completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P7
3 functions
programmable I/O port)
0 : TXDi pin is CMOS output
1 : TXDi pin is N-channel
open-drain output
0 : Transmit data is output at
falling edge of transfer clock
and receive data is input at
rising edge
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
0 : LSB first
1 : MSB first
Function
(During UART mode)
b1 b0
1 is selected
0 0 : f
0 1 : f
8 is selected
1 0 : f
32 is selected
1 1 : Inhibited
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P7
3 functions programmable
I/O port)
0: TXDi pin is CMOS output
1: TXDi pin is N-channel
open-drain output
Must always be “0”
0 : LSB first
1 : MSB first
WR
Figure 1.17.6. Serial I/O-related registers (3)
93
Page 94
Serial I/O
UARTi transmit/receive control register 1
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
UiC1(i=0,1) 03A5
Bit
symbol
TE
TI
RE
RI
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
Bit name
Transmit enable bit
Transmit buffer
empty flag
Receive enable bit
Receive complete flag
UART2 transmit/receive control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
U2C1 037D
16,03AD16 0216
Function
(During clock synchronous
serial I/O mode)
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Reception disabled
1 : Reception enabled
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
16 0216
Function
(During UART mode)
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Reception disabled
1 : Reception enabled
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
WR
Bit
symbol
TE
TI
RE
RI
U2IRS UART2 transmit interrupt
U2RRM UART2 continuous
U2LCH
U2ERE Error signal output
Bit name
Transmit enable bit
Transmit buffer
empty flag
Receive enable bit
Receive complete flag
cause select bit
receive mode enable bit
Data logic select bit 0 : No reverse
enable bit
Function
(During clock synchronous
serial I/O mode)
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Reception disabled
1 : Reception enabled
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
0 : Transmit buffer empty
(TI = 1)
1 : Transmit is completed
(TXEPT = 1)
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
1 : Reverse
Must be fixed to “0” 0 : Output disabled
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in
1 : No data present in
0 : Reception disabled
1 : Reception enabled
0 : No data present in
1 : Data present in
0 : Transmit buffer empty
1 : Transmit is completed
Invalid
0 : No reverse
1 : Reverse
1 : Output enabled
Function
(During UART mode)
transmit buffer register
transmit buffer register
receive buffer register
receive buffer register
(TI = 1)
(TXEPT = 1)
WR
Figure 1.17.7. Serial I/O-related registers (4)
94
Page 95
Serial I/O
UART transmit/receive control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
UCON 03B0
16
X0000000
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2
Bit
symbol
U0IRS
U1IRS
U0RRM
U1RRM
CLKMD0
CLKMD1
RCSP
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate.
Note: When using multiple pins to output the transfer clock, the following requirements must be met:
• UART1 internal/external clock select bit (bit 3 at address 03A8
Bit name
UART0 transmit
interrupt cause select bit
UART1 transmit
interrupt cause select bit
UART0 continuous
receive mode enable bit
UART1 continuous
receive mode enable bit
CLK/CLKS select bit 0
CLK/CLKS select
bit 1 (Note)
Separate CTS/RTS bit
Function
(During clock synchronous
serial I/O mode)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enable
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
Valid when bit 5 = “1”
0 : Clock output to CLK1
1 : Clock output to CLKS1
0 : Normal mode
(CLK output is CLK1 only)
1 : Transfer clock output
from multiple pins
function selected
0 : CTS/RTS shared pin
1 : CTS/RTS separated
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
Invalid
Invalid
Invalid
Must always be “0”
0 : CTS/RTS shared pin
1 : CTS/RTS separated
Function
(During UART mode)
(TXEPT = 1)
(TXEPT = 1)
16
) = “0”.
WR
Figure 1.17.8. Serial I/O-related registers (5)
95
Page 96
Mitsubishi microcomputers
M16C / 61 Group
Clock synchronous serial I/O mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Clock synchronous serial I/O mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 1.17.2
and table 1.17.3 list the specifications of the clock synchronous serial I/O mode. Figure 1.17.9 shows the
UARTi transmit/receive mode register.
Table 1.17.2. Specifications of clock synchronous serial I/O mode (1)
Item Specification
Transfer data format • Transfer data length: 8 bits
Transfer clock • When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816
= “0”) : fi/ 2(n+1) (Note 1) fi = f1, f8, f32
• When external clock is selected (bit 3 at addresses 03A016, 03A816, 037816
= “1”) : Input from CLKi pin
Transmission/reception control
Transmission start condition
Reception start condition • To start reception, the following requirements must be met:
Interrupt request
generation timing
Error detection • Overrun error (Note 2)
Note 1: “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator.
Note 2: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
the UARTi receive interrupt request bit is not set to “1”.
_______ _______ _______ _______
• CTS function/RTS function/CTS, RTS function chosen to be invalid
• To start transmission, the following requirements must be met:
_
Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1”
_
Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0”
_
When CTS function selected, CTS input level = “L”
•
Furthermore, if external clock is selected, the following requirements must also be met:
_
CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “0”:
_______ _______
CLKi input level = “H”
_
CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “1”:
CLKi input level = “L”
_
Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = “1”
_
Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1”
_
Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0”
• Furthermore, if external clock is selected, the following requirements must
also be met:
_
CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “0”:
CLKi input level = “H”
_
CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “1”:
CLKi input level = “L”
• When transmitting
_
Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at
address 037D16) = “0”: Interrupts requested when data transfer from UARTi
transfer buffer register to UARTi transmit register is completed
_
Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at
address 037D16) = “1”: Interrupts requested when data transmission from
UARTi transfer register is completed
• When receiving
_
Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
96
Page 97
Mitsubishi microcomputers
M16C / 61 Group
Clock synchronous serial I/O mode
Table 1.17.3. Specifications of clock synchronous serial I/O mode (2)
Item Specification
Select function • CLK polarity selection
Whether transmit data is output/input at the rising edge or falling edge of the
transfer clock can be selected
• LSB first/MSB first selection
Whether transmission/reception begins with bit 0 or bit 7 can be selected
• Continuous receive mode selection
Reception is enabled simultaneously by a read from the receive buffer register
• Transfer clock output from multiple pins selection (UART1) (Note)
UART1 transfer clock can be chosen by software to be output from one of
the two pins set
• Separate CTS/RTS pins (UART0) (Note)
UART0 CTS and RTS pins each can be assigned to separate pins
• Switching serial data logic (UART2)
Whether to reverse data in writing to the transmission buffer register or
reading the reception buffer register can be selected.
• TXD, RXD I/O polarity reverse (UART2)
This function is reversing TXD port output and RXD port input. All I/O data
level is reversed.
Note: The transfer clock output from multiple pins and the separate CTS/RTS pins functions cannot be
selected simultaneously.
_______ _______
_______ _______
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
_______ _______
97
Page 98
Clock synchronous serial I/O mode
UARTi transmit/receive mode registers
b7 b6 b5 b4 b3 b2 b1 b0
0
010
Symbol Address When reset
UiMR(i=0,1) 03A0
SMD0
SMD1
SMD2
CKDIR
STPS
PRY
PRYE
SLEP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
16
, 03A8
16
00
16
Bit name FunctionBit symbol WR
Serial I/O mode select bit
Internal/external clock
select bit
Invalid in clock synchronous serial I/O mode
0 (Must always be “0” in clock synchronous serial I/O mode)
b2 b1 b0
0 0 1 : Clock synchronous serial
I/O mode
0 : Internal clock
1 : External clock
Mitsubishi microcomputers
M16C / 61 Group
UART2 transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
010
Symbol Address When reset
U2MR 0378
SMD0
SMD1
SMD2
CKDIR
STPS
PRY
PRYE
IOPOL
Note: Usually set to “0”.
Serial I/O mode select bit
Internal/external clock
select bit
Invalid in clock synchronous serial I/O mode
TxD, RxD I/O polarity
reverse bit (Note)
Bit name FunctionBit symbol WR
16
00
16
b2 b1 b0
0 0 1 : Clock synchronous serial
I/O mode
0 : Internal clock
1 : External clock
0 : No reverse
1 : Reverse
Figure 1.17.9. UARTi transmit/receive mode register in clock synchronous serial I/O mode
98
Page 99
Clock synchronous serial I/O mode
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.17.4 lists the functions of the input/output pins during clock synchronous serial I/O mode. This
table shows the pin functions when the transfer clock output from multiple pins and the separate CTS/
_______
RTS pins functions are not selected. Note that for a period from when the UARTi operation mode is
selected to when transfer starts, the TXDi pin outputs a “H”. (If the N-channel open-drain is selected, this
pin is in floating state.)
Table 1.17.4. Input/output pin functions in clock synchronous serial I/O mode
Pin name Function Method of selection
TxDi
3
, P67, P70)
(P6
RxDi
2
, P66, P71)
(P6
CLKi
1
, P65, P72)
(P6
CTSi/RTSi
0
, P64, P73)
(P6
Serial data output
Serial data input
Transfer clock output
Transfer clock input
CTS input
(Outputs dummy data when performing reception only)
Port P62, P66 and P71 direction register (bits 2 and 6 at address 03EE16,
16
bit 1 at address 03EF
)= “0”
(Can be used as an input port when performing transmission only)
Internal/external clock select bit (bit 3 at address 03A0
Internal/external clock select bit (bit 3 at address 03A0
1
Port P6
bit 2 at address 03EF
CTS/RTS disable bit (bit 4 at address 03A4
, P65 and P72 direction register (bits 1 and 5 at address 03EE16,
16
) = “0”
16
, 03AC16, 037C16) =“0”
CTS/RTS function select bit (bit 2 at address 03A4
0
Port P6
bit 3 at address 03EF
, P64 and P73 direction register (bits 0 and 4 at address 03EE16,
16
) = “0”
16
, 03A816, 037816) = “0”
16
, 03A816, 037816) = “1”
16
, 03AC16, 037C16) = “0”
_______
RTS output
Programmable I/O port
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C
CTS/RTS function select bit (bit 2 at address 03A4
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “1”
_______ _______
16
16)
= “0”
, 03AC16, 037C16) = “1”
(when transfer clock output from multiple pins and separate CTS/RTS pins functions are not selected)
99
Page 100
Clock synchronous serial I/O mode
• Example of transmit timing (when internal clock is selected)
Tc
Transfer clock
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Transmit enable
bit (TE)
Transmit buffer
empty flag (Tl)
CTSi
“1”
“0”
Data is set in UARTi transmit buffer register
“1”
“0”
“H”
“L”
T
CLK
Transferred from UARTi transmit buffer register to UARTi transmit register
Stopped pulsing because CTS = “H”
CLKi
D
TxDi
Transmit
register empty
flag (TXEPT)
Transmit interrupt
request bit (IR)
D
D
0
“1”
“0”
“1”
“0”
3
D
2
D
1
D
4
7
D
D
5
D
6
0
D
3
D
2
D
1
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• Internal clock is selected.
• CTS function is selected.
• CLK polarity select bit = “0”.
• Transmit interrupt cause select bit = “0”.
Tc = TCLK = 2(n + 1) / fi
fi: frequency of BRGi count source (f
n: value set to BRGi
• Example of receive timing (when external clock is selected)
Stopped pulsing because transfer enable bit = “0”
D
D
4
7
D
5
D
6
D
0
D
1
1
, f8, f32)
D
3
D
2
D
4
D
7
D
5
D
6
“H”
“L”
“1”
“0”
“1”
“0”
“1”
“0”
Dummy data is set in UARTi transmit buffer register
Transferred from UARTi transmit buffer register to UARTi transmit register
1 / f
EXT
Receive enable
bit (RE)
Transmit enable
bit (TE)
Transmit buffer
empty flag (Tl)
RTSi
CLKi
Receive data is taken in
D
RxDi
Receive complete
flag (Rl)
Receive interrupt
request bit (IR)
D
0
Transferred from UARTi receive register
“1”
“0”
“1”
“0”
to UARTi receive buffer register
3
D
2
D
1
D
4
D
5
D
6
D
0
D
2
D
D
7
Read out from UARTi receive buffer register
1
D
5
D
4
D
3
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• External clock is selected.
• RTS function is selected.
• CLK polarity select bit = “0”.
f
EXT
: frequency of external clock
Meet the following conditions are met when the CLK
input before data reception = “H”
• Transmit enable bit “1”
• Receive enable bit “1”
• Dummy data write to UARTi transmit buffer register
Figure 1.17.10. Typical transmit/receive timings in clock synchronous serial I/O mode
100
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