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M2V56S20AKT-5
Datasheet (Mitsubishi)
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Datasheet M2V56S40AKT-7, M2V56S40AKT-6, M2V56S40AKT-5, M2V56S20AKT-7, M2V56S20AKT-6 Datasheet (Mitsubishi)

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Page 1
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
Single Data Rate
MITSUBISHI LSIs
July '01
256M Synchronous DRAM
Some of contents are subject to change without notice.
DESCRIPTION
M2V56S20AKT is a 4-bank x 16777216-word x 4-bit, M2V56S30AKT is a 4-bank x 8388608-word x 8-bit, M2V56S40AKT is a 4-bank x 4194304-word x 16-bit, synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M2V56S20/30/40AKT achieve very high speed data rate up to 100MHz (-7) , 133MHz (-6), 166MHz(-5) and are suitable for main memory or graphic memory in computer systems.
FEATURES
- Single 3.3v±0.3V power supply
- Max. Clock frequency -5:PC166<3-3-3> / -6:PC133<3-3-3> / -7:PC100<2-2-2>
- Fully Synchronous operation referenced to clock rising edge
- Single Data Rate
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/full page (programmable)
- Burst type- sequential / interleave (programmable)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- 8192 refresh cycles /64ms (4 banks concurrent refresh)
- Auto refresh and Self refresh
- Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)
- LVTTL Interface
- 10.65mm width x 13.1mm length, 64-pin STSOP(II) with 0.4mm lead pitch
Max. Frequency
@CL2
M2V56S20/30/40AKT-5
Max. Frequency
@CL3
Standard
PC133 (CL2)166 MHz133 MHz
M2V56S20/30/40AKT-6
M2V56S20/30/40AKT-7
100MHz
100 MHz
133 MHz
100MHz
MITSUBISHI ELECTRIC
PC133 (CL3)
PC100 (CL2)
1
Page 2
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
Single Data Rate
MITSUBISHI LSIs
July '01
VDD VDD VDD
NC DQ0 DQ0
VDDQ VDDQ VDDQ
NC NC DQ1
DQ0 DQ1 DQ2
VSSQ VSSQ VSSQ
NC NC DQ3 NC DQ2 DQ4
VDDQ VDDQ VDDQ
NC NC DQ5
DQ1 DQ3 DQ6
VSSQ VSSQ VSSQ
NC NC DQ7 NC NC NC NC NC NC NC NC NC
VDD VDD VDD
NC NC NC NC NC LDQM
/WE /WE /WE /CAS /CAS /CAS /RAS /RAS /RAS
/CS /CS /CS
NC NC NC BA0 BA0 BA0 BA1 BA1 BA1
A10/AP A10/AP A10/AP
A0 A0 A0
A1 A1 A1
A2 A2 A2 A3 A3 A3
VDD VDD VDD
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TOP VIEW
x4 x8
x16
256M Synchronous DRAM
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VSS VSS VSS DQ15 DQ7 NC VSSQ VSSQ VSSQ DQ14 NC NC DQ13 DQ6 DQ3
VDDQ VDDQ VDDQ
DQ12 NC NC DQ11 DQ5 NC
VSSQ VSSQ VSSQ
DQ10 NC NC
DQ9 DQ4 DQ2
VDDQ VDDQ VDDQ
DQ8 NC NC
NC NC NC NC NC NC NC NC NC NC NC NC
VSS VSS VSS
UDQM DQM DQM
NC NC NC CLK CLK CLK CKE CKE CKE
NC NC NC
A12 A12 A12 A11 A11 A11
A9 A9 A9 A8 A8 A8 A7 A7 A7 A6 A6 A6 A5 A5 A5 A4 A4 A4
VSS VSS VSS
CLK : Master Clock CKE : Clock Enable /CS : Chip Select /RAS : Row Address Strobe
/CAS : Column Address Strobe /WE : Write Enable DQ0-15 : Data I/O DQM, DQMU/L : Output Disable / Write Mask A0-12 : Address Input BA0,1 : Bank Address Input
Vdd : Power Supply VddQ : Power Supply for Output Vss : Ground VssQ : Ground for Output
MITSUBISHI ELECTRIC
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Page 3
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
BLOCK DIAGRAM
/CS
/RAS
/CAS
/WE
DQMU/L
Control Circuitry
Address Buffer
A0-12
BA0,1
CLK
CKE
Control Signal Buffer
Single Data Rate
MITSUBISHI LSIs
July '01
Memory
Array
Bank #0
Mode Register
I/O Buffer
Memory
Array
Bank #1
256M Synchronous DRAM
DQ0-3 (x4), 0-7 (x8), 0 - 15 (x16)
Memory
Array
Bank #2
Memory
Array
Bank #3
Type Designation Code
M 2 V 56 S 4 0 A KT - 5
Clock Buffer
This rule is applied to only Synchronous DRAM family.
Speed Grade 5: 166MHz@CL3, 133MHz@CL2
6: 133MHz@CL3, 100MHz@CL2 7: 100MHz@CL2
Package Type KT: STSOP(II)
Process Generation A:2nd. gen. Function Reserved for Future Use
Organization 2n 2: x4, 3: x8, 4: x16
SDRAM Data Rate Type S:Single Data Rate
Density 56: 256M bits Interface V:LVTTL Memory Style (DRAM) Mitsubishi Main Designation
MITSUBISHI ELECTRIC
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Page 4
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
Din Mask / Output Disable: When DQMU/L is high in burst write, Din for
PIN FUNCTION
Single Data Rate
MITSUBISHI LSIs
July '01
CLK
CKE
/RAS, /CAS, /WE
A0-12
Input
Input
Input
256M Synchronous DRAM
Master Clock: All other inputs are referenced to the rising edge of CLK.Input
Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE becomes asynchronous input. Self refresh is maintained as long as CKE is low.
Chip Select: When /CS is high, any command means No OperationInput/CS
Combination of /RAS, /CAS, /WE defines basic commands.
A0-12 specify the Row / Column Address in conjunction with BA0,1. The Row Address is specified by A0-12. The Column Address is specified by A0-9,11. A10 is also used to indicate precharge option. When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, all banks are precharged.
BA0,1
DQ0-15
DQM
DQMU/L
Vdd, Vss
VddQ, VssQ
Input
Input / Output
Input
Power Supply
Power Supply
Bank Address: BA0,1 specifies one of four banks to which a command is applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands.
Data In and Data out are referenced to the rising edge of CLK.
the current cycle is masked. When DQMU/L is high in burst read, Dout is disabled at the next but one cycle.
Power Supply for the memory array and peripheral circuitry.
VddQ and VssQ are supplied to the Output Buffers only.
MITSUBISHI ELECTRIC
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Page 5
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
Single Data Rate
MITSUBISHI LSIs
July '01
256M Synchronous DRAM
BASIC FUNCTIONS
The M2V56S20/30/40AKT provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and precharge option, respectively. To know the detailed definition of commands, please see the command truth table.
CLK /CS /RAS /CAS /WE CKE A10
Chip Select : L=select, H=deselect Command Command Command Refresh Option @refresh command Precharge Option @precharge or read/write command
define basic commands
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto­precharge,READA)
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write (auto-precharge, WRITEA).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates burst read /write operation. When A10 =H at this command, all banks are deactivated (precharge all, PREA ).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address are generated internally. After this command, the banks are precharged automatically.
MITSUBISHI ELECTRIC
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Page 6
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
COMMAND TRUTH TABLE
CKE
Single Data Rate
MITSUBISHI LSIs
July '01
COMMAND MNEMONIC
Deselect DESEL H X H X X X X X X
No Operation NOP H X L H H H X X X
Row Address Entry &
Bank Activate
Single Bank Precharge PRE H X L L H L V L X
Precharge All Banks PREA H X L L H L H X
Column Address Entry
& Write
Column Address Entry
& Write with
Auto-Precharge
Column Address Entry
& Read
ACT H X L L H H V V V
WRITE H X L H L L V L V
WRITEA H X L H L L V H V
READ H X L H L H V L V
n-1
CKE
n
/CS /RAS /CAS /WE BA0,1
256M Synchronous DRAM
A10
A0-9,
/AP
11-12
X
note
Column Address Entry
& Read with
Auto-Precharge
Auto-Refresh REFA H H L L L H X X X
Self-Refresh Entry REFS H L L L L H X X X
Self-Refresh Exit REFSX
Burst Terminate TBST H X L H H L X X X
Mode Register Set MRS H X L L L L L L V
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE:
1. A7-9,11-12=L, A0-A6 =Mode Address
READA H X L H L H V H V
L H H X X X X X X L H L H H H X X X
1
MITSUBISHI ELECTRIC
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Page 7
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
Single Data Rate
MITSUBISHI LSIs
July '01
FUNCTION TRUTH TABLE
Current State
IDLE
ROW ACTIVE
/CS /RAS /CAS /WE Address Command Action
H X X X X DESEL NOP
L H H H X NOP NOP L H H L X TBST ILLEGAL*2
L H L X BA, CA, A10 READ / WRITE ILLEGAL*2 L L H H BA, RA ACT Bank Active, Latch RA L L H L BA, A10 PRE / PREA NOP*4 L L L H X REFA Auto-Refresh*5
L L L L
H X X X X DESEL NOP
L H H H X NOP NOP L H H L X TBST NOP
L H L H BA, CA, A10 READ / READA
Op-Code, Mode-Add
256M Synchronous DRAM
MRS Mode Register Set*5
Begin Read, Latch CA, Determine Auto-Precharge
READ
L H L L BA, CA, A10
L L H H BA, RA ACT Bank Active / ILLEGAL*2 L L H L BA, A10 PRE / PREA Precharge / Precharge All L L L H X REFA ILLEGAL
L L L L
H X X X X DESEL NOP (Continue Burst to END)
L H H H X NOP NOP (Continue Burst to END) L H H L X TBST Terminate Burst
L H L H BA, CA, A10 READ / READA
L H L L BA, CA, A10
L L H H BA, RA ACT Bank Active / ILLEGAL*2 L L H L BA, A10 PRE / PREA Terminate Burst, Precharge
Op-Code, Mode-Add
WRITE /
WRITEA
MRS ILLEGAL
WRITE /
WRITEA
Begin Write, Latch CA, Determine Auto-Precharge
Terminate Burst, Latch CA, Begin New Read, Determine Auto-Precharge*3
Terminate Burst, Latch CA, Begin Write, Determine Auto­Precharge*3
L L L H X REFA ILLEGAL
L L L L
Op-Code, Mode-Add
MITSUBISHI ELECTRIC
MRS ILLEGAL
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Page 8
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
FUNCTION TRUTH TABLE (continued)
Single Data Rate
MITSUBISHI LSIs
July '01
Current State /CS /RAS /CAS /WE Address Command Action
WRITE H X X X X DESEL NOP (Continue Burst to END)
L H H H X NOP NOP (Continue Burst to END) L H H L X TBST Terminate Burst
L H L H BA, CA, A10 READ / READA
WRITE /
WRITEA
MRS ILLEGAL
READ with
AUTO
PRECHARGE
L H L L BA, CA, A10
L L H H BA, RA ACT Bank Active / ILLEGAL*2 L L H L BA, A10 PRE / PREA Terminate Burst, Precharge
L L L H X REFA ILLEGAL
L L L L
H X X X X DESEL NOP (Continue Burst to END)
L H H H X NOP NOP (Continue Burst to END) L H H L X TBST ILLEGAL L H L H BA, CA, A10 READ / READA ILLEGAL
Op-Code, Mode-Add
256M Synchronous DRAM
Terminate Burst, Latch CA, Begin Read, Determine Auto-
Precharge*3 Terminate Burst, Latch CA,
Begin Write, Determine Auto­Precharge*3
WRITE with
AUTO
PRECHARGE
L H L L BA, CA, A10
L L H H BA, RA ACT Bank Active / ILLEGAL*2 L L H L BA, A10 PRE / PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
H X X X X DESEL NOP (Continue Burst to END)
L H H H X NOP NOP (Continue Burst to END) L H H L X TBST ILLEGAL L H L H BA, CA, A10 READ / READA ILLEGAL
L H L L BA, CA, A10
L L H H BA, RA ACT Bank Active / ILLEGAL*2 L L H L BA, A10 PRE / PREA ILLEGAL*2 L L L H X REFA ILLEGAL
L L L L
Op-Code, Mode-Add
Op-Code, Mode-Add
WRITE /
WRITEA
MRS ILLEGAL
WRITE /
WRITEA
MRS ILLEGAL
ILLEGAL
ILLEGAL
MITSUBISHI ELECTRIC
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Page 9
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
FUNCTION TRUTH TABLE (continued)
Single Data Rate
MITSUBISHI LSIs
July '01
Current State /CS /RAS /CAS /WE Address Command Action
PRE -
CHARGING
ROW
ACTIVATING
H X X X X DESEL NOP (Idle after tRP)
L H H H X NOP NOP (Idle after tRP) L H H L X TBST ILLEGAL*2
L H L X BA, CA, A10 READ / WRITE ILLEGAL*2 L L H H BA, RA ACT ILLEGAL*2 L L H L BA, A10 PRE / PREA NOP*4 (Idle after tRP) L L L H X REFA ILLEGAL
L L L L
H X X X X DESEL NOP (Row Active after tRCD)
L H H H X NOP NOP (Row Active after tRCD) L H H L X TBST ILLEGAL*2 L H L X BA, CA, A10 READ / WRITE ILLEGAL*2 L L H H BA, RA ACT ILLEGAL*2
Op-Code, Mode-Add
MRS ILLEGAL
256M Synchronous DRAM
WRITE RE­COVERING
L L H L BA, A10 PRE / PREA ILLEGAL*2 L L L H X REFA ILLEGAL
L L L L
H X X X X DESEL NOP
L H H H X NOP NOP L H H L X TBST ILLEGAL*2 L H L X BA, CA, A10 READ / WRITE ILLEGAL*2 L L H H BA, RA ACT ILLEGAL*2 L L H L BA, A10 PRE / PREA ILLEGAL*2 L L L H X REFA ILLEGAL
L L L L
Op-Code, Mode-Add
Op-Code, Mode-Add
MRS ILLEGAL
MRS ILLEGAL
MITSUBISHI ELECTRIC
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Page 10
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
FUNCTION TRUTH TABLE (continued)
Single Data Rate
MITSUBISHI LSIs
July '01
Current State /CS /RAS /CAS /WE Address Command Action
RE-
FRESHING
MODE
REGISTER
SETTING
H X X X X DESEL NOP (Idle after tRC)
L H H H X NOP NOP (Idle after tRC) L H H L X TBST ILLEGAL
L H L X BA, CA, A10 READ / WRITE ILLEGAL L L H H BA, RA ACT ILLEGAL L L H L BA, A10 PRE / PREA ILLEGAL L L L H X REFA ILLEGAL
L L L L
H X X X X DESEL NOP (Idle after tRSC)
L H H H X NOP NOP (Idle after tRSC) L H H L X TBST ILLEGAL L H L X BA, CA, A10 READ / WRITE ILLEGAL L L H H BA, RA ACT ILLEGAL
Op-Code, Mode-Add
MRS ILLEGAL
256M Synchronous DRAM
L L H L BA, A10 PRE / PREA ILLEGAL L L L H X REFA ILLEGAL
L L L L
ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No OPeration
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and/or data-integrity are not guaranteed.
Op-Code, Mode-Add
MRS ILLEGAL
MITSUBISHI ELECTRIC
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SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
FUNCTION TRUTH TABLE for CKE
Single Data Rate
MITSUBISHI LSIs
July '01
Current State
SELF-
REFRESH*1
POWER
DOWN
ALL BANKS
IDLE*2
256M Synchronous DRAM
CKE
CKE
n-1
H X X X X X X INVALID L H H X X X X Exit Self-Refresh (Idle after tRC) L H L H H H X Exit Self-Refresh (Idle after tRC) L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP (Maintain Self-Refresh) H X X X X X X INVALID L H X X X X X Exit Power Down to Idle L L X X X X X NOP (Maintain Power Down) H H X X X X X Refer to Function Truth Table H L L L L H X Enter Self-Refresh
/CS /RAS /CAS /WE Add Action
n
H L H X X X X Enter Power Down H L L H H H X Enter Power Down H L L H H L X ILLEGAL H L L H L X X ILLEGAL H L L L X X X ILLEGAL L X X X X X X Refer to Current State =Power Down
ANY STATE
other than
listed above
ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care
NOTES:
1. CKE Low to High transition will re-enable CLK and other inputs asynchronously . A minimum setup time must be satisfied before any command other than EXIT.
2. Self-Refresh can be entered only from the All Banks Idle State.
3. Must be legal command.
H H X X X X X Refer to Function Truth Table H L X X X X X Begin CLK Suspend at Next Cycle*3 L H X X X X X Exit CLK Suspend at Next Cycle*3 L L X X X X X Maintain CLK Suspend
MITSUBISHI ELECTRIC
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SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
SIMPLIFIED STATE DIAGRAM
REGISTER
ACTIVE
Single Data Rate
MITSUBISHI LSIs
July '01
MODE
SET
CLK
SUSPEND
MRS
CKEL
IDLE
ACT
REFS
CKEH
REFSX
REFA
CKEL
256M Synchronous DRAM
SELF
REFRESH
AUTO
REFRESH
POWER
DOWN
WRITE
SUSPEND
WRITEA
SUSPEND
POWER APPLIED
CKEH
ROW
TBST TBST
WRITE
PRE
WRITEA
READ
WRITE
WRITEA
PRE
PRE PRE
PRE
CHARGE
CKEL
WRITE
CKEH
WRITEA READA
CKEL
WRITEA
CKEH
POWER
ON
READ
READA
READ
READA
READA
CKEL
CKEH
CKEL
CKEH
READ
SUSPEND
READA
SUSPEND
MITSUBISHI ELECTRIC
Automatic Sequence Command Sequence
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Page 13
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
POWER ON SEQUENCE
Single Data Rate
MITSUBISHI LSIs
July '01
256M Synchronous DRAM
Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP condition at the inputs.
2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 100µs.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register. After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register (MRS). The mode register stores these data until the next MRS command, which may be issued when all banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for
CLK /CS /RAS /CAS
new command.
BA0 BA1 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 SW 0 0 LTMODE BT BL
LATENCY
MODE
SW
CL /CAS LATENCY 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
Single Write
1
R R 2 3 R R R R
Burst Write
0
BURST
LENGTH
BURST
TYPE
/WE
BA0,1 A12-A0
BL BT=0 BT=1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
0 1
1 2 4 8 R R R
Full Page
SEQUENTIAL INTERLEAVED
V
1 2 4 8 R R R R
R: Reserved for Future Use
MITSUBISHI ELECTRIC
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SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
Single Data Rate
MITSUBISHI LSIs
July '01
CLK
Command
Address
DQ
CL= 3 BL= 4
Initial Address BL
A2 A1 A0
0 0 0
256M Synchronous DRAM
Read
Y
Q0 Q1 Q2 Q3 D0 D1 D2 D3
/CAS Latency
Burst Length Burst Length
Burst Type
Column Addressing
Sequential Interleaved
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
Write
Y
0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
- 0 0
- 0 1
- 1 0
- 1 1
- - 0
- - 1
1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4
8
4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 7 0 1 2 0 1 2 3 1 2 3 0
4
2 3 0 1 3 0
0 1
2
1 0
3 4 5 6 3 2 1 0
1 2
7 6 5 4 0 1 2 3 1 0 3 2 2 3 0 1
3 2
0 1 1 0
1 0
MITSUBISHI ELECTRIC
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SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
OPERATIONAL DESCRIPTION
data length is defined by the Burst Length. The address sequence of the burst data is defined by the Burst
Single Data Rate
MITSUBISHI LSIs
July '01
256M Synchronous DRAM
BANK ACTIVATE
One of four banks is activated by an ACT command. An bank is selected by BA0-1. A row is selected by A0-12. Multiple banks can be active state concurrently by issuing multiple ACT commands. Minimum activation interval between one bank and another bank is tRRD.
PRECHARGE
An open bank is deactivated by a PRE command. A bank to be deactivated is designated by BA0-1. When multiple banks are active, a precharge all command (PREA, PRE + A10=H) deactivates all of open banks at the same time. BA0-1 are "Don't Care" in this case. Minimum delay time of an ACT command after a PRE command to the same bank is tRP.
Bank Activation and Precharge All (BL=4, CL=3)
CLK
Command
A0-9,11-12
A10
BA0-1
DQ
ACT READACT PRE ACT
tRRD tRCD tRP
Xa Xb Yb Xa
1Xa Xb 0
00 01 01 00
Qb0 Qb1 Qb2 Qb3
Precharge All
Xa
READ
A READ command can be issued to any active bank. The start address is specified by A0-9,11(x4), A0­9 (x8), A0-8 (x16). 1st output data is available after the /CAS Latency from the READ. The consecutive
Type. Minimum delay time of a READ command after an ACT command to the same bank is tRCD. When A10 is high at a READ command, auto-precharge (READA) is performed. Any command (READ, WRITE, PRE, ACT,TBST) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at the BL after READA. The next ACT command can be issued after (BL + tRP) from the previous READA. In any case, tRCD+BL > tRASmin must be met.
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SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
Single Data Rate
MITSUBISHI LSIs
July '01
CLK
Command
A0-9,11-12
A10
BA0-1
DQ
CLK
256M Synchronous DRAM
Multi Bank Interleaving Read (CL=2, BL=4)
ACT READACT PRE ACT
tRCD tRCD tRP
Xa Xb Yb Xa
00 01 01 00
READ
Ya
0
00
0Xa Xb 0
00
Qa0 Qa1 Qa2 Qa3
Xa
Qb0 Qb1 Qb2 Qb3
Read with Auto-Precharge (CL=2, BL=4)
Command
A0-9,11-12
A10
BA0-1
DQ
ACT ACT
tRCD tRP
Xa Xa
Xa
00 00
READ
Ya
1
00
BL
Xa
Qa0 Qa1 Qa2 Qa3
internal precharge starts
Auto-Precharge Timing (READ, BL=4)
CLK
CommandDQACT ACT
tRCD
CL=2
READ
BL
Qa0 Qa1 Qa2 Qa3
DQ Qa0 Qa1 Qa2 Qa3
CL=3
internal precharge starts
MITSUBISHI ELECTRIC
16
Page 17
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
A0-9 (x8), A0-8 (x16). 1st input data is set at the same cycle as the WRITE. The consecutive data length
Single Data Rate
MITSUBISHI LSIs
July '01
256M Synchronous DRAM
WRITE
A WRITE command can be issued to any active bank.The start address is specified by A0-9,11(x4),
to be written is defined by the Burst Length. The address sequence of burst data is defined by the Burst Type. Minimum delay time of a WRITE command after an ACT command to the same bank is tRCD. From the last input data to the PRE command, the write recovery time (tWR) is required. When A10 is high at a WRITE command, auto-precharge (WRITEA) is performed. Any command (READ, WRITE, PRE, ACT, TBST) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at tWR after the last input data cycle. The next ACT command can be issued after (BL + tWR -1 +tRP) from the previous WRITEA. In any case, tRCD + BL + tWR -1 > tRASmin must be met.
Command
A0-9,11-12
CLK
ACT PRE ACT
tRCD tRP
Xa Xa
Write (BL=4)
Write
BL
Ya
A10
BA0-1
DQ
CLK
Command
A0-9,11-12
A10
BA0-1
0
00 00
00
tWR
Da0 Da1 Da2 Da3
0Xa
Xa
Write with Auto-Precharge (BL=4)
ACT ACT
tRCD tRP
Xa Xa
Xa
00 00
Write
Ya
1
00
BL
Xa
tWR
DQ
Da0 Da1 Da2 Da3
internal precharge starts
MITSUBISHI ELECTRIC
17
Page 18
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
Single Data Rate
MITSUBISHI LSIs
July '01
256M Synchronous DRAM
BURST INTERRUPTION [ Read Interrupted by Read ]
Burst read operation can be interrupted by new read of any active bank. Random column access is allowed. READ to READ interval is minimum 1 CLK.
Read interrupted by Read (CL=2, BL=4)
CLK
Command
A0-9,11-12
A10
BA0-1
DQ
READ
Ya
0
00
Qa0 Qa1 Qa2 Qb0
READ
Yb
0
00
READ
Yc
0
10
Qc0 Qc1 Qc2 Qc3
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of any active bank. Random column access is allowed. In this case, the DQ should be controlled adequately by using the DQM to prevent the bus contention. The output is disabled automatically 2 cycle after WRITE assertion.
Read interrupted by Write (CL=2, BL=4)
CLK
Command
A0-9,11-12
A10
BA0-1
DQM
ACT
Xa
Xa
00
READ
Ya
0
00
Write
Ya
0
00
DQ
Qa0 Da0 Da1 Da2
Output disable by DQM by WRITE
MITSUBISHI ELECTRIC
Da3
18
Page 19
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
Single Data Rate
MITSUBISHI LSIs
July '01
256M Synchronous DRAM
[ Read Interrupted by Precharge ]
A burst read operation can be interrupted by a precharge of the same bank . READ to PRE interval is minimum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency.
Read interrupted by Precharge (BL=4)
CLK
Command
DQ
Command
Q0 Q1 Q2
PREREAD
PREREAD
CL=2
DQ
Q0 Q1
CL=3
Command
DQ
Command
DQ
Command
DQ
Command
DQ
PREREAD
Q0
PREREAD
Q0 Q1 Q2
PREREAD
Q0 Q1
PREREAD
Q0
MITSUBISHI ELECTRIC
19
Page 20
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
Single Data Rate
MITSUBISHI LSIs
July '01
256M Synchronous DRAM
[ Read Interrupted by Burst Terminate ]
Similarly to the precharge, a burst terminate command can interrupt the burst read operation and disable the data output. The terminated bank remains active. READ to TBST interval is minimum 1 CLK. A TBST command to output disable latency is equivalent to the /CAS Latency.
Read interrupted by Terminate (BL=4)
CLK
Command
DQ
Command
TBSTREAD
TBSTREAD
Q0 Q1 Q2
CL=2
DQ
Q0 Q1
CL=3
Command
DQ
Command
DQ
Command
DQ
Command
DQ
TBSTREAD
Q0
TBSTREAD
Q0 Q1 Q2
TBSTREAD
Q0 Q1
TBSTREAD
Q0
MITSUBISHI ELECTRIC
20
Page 21
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
"Don't Care".
Single Data Rate
MITSUBISHI LSIs
July '01
256M Synchronous DRAM
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of any active bank. Random column access is allowed. WRITE to WRITE interval is minimum 1 CLK.
Write interrupted by Write (BL=4)
CLK
Command
A0-9,11-12
A10
BA0-1
DQ
Write
Ya
0
00
Da0 Da1 Da2 Db0
Write
Yb
0
00
Write
Yc
0
10
Dc0 Dc1 Dc2 Dc3
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of any active bank. Random column access is allowed. WRITE to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is
Write interrupted by Read (CL=2, BL=4)
CLK
Command
A0-9,11-12
A10
BA0-1
DQ
ACT
Xa
Xa
00
Write
Ya
0
00
Da0 Da1 Qb0
READ
Yb
0
00
Qb1 Qb2 Qb3
don't care
MITSUBISHI ELECTRIC
21
Page 22
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
Single Data Rate
MITSUBISHI LSIs
July '01
256M Synchronous DRAM
[ Write Interrupted by Precharge ]
Burst write operation can be interrupted by precharge of the same bank. Write recovery time (tWR) is required from the last data to PRE command. During write recovery, data inputs must be masked by DQM.
Write interrupted by Precharge (BL=4)
CLK
Command
A0-9,11-12
A10
BA0-1
DQM
ACT
Xa
0
00
Write
Ya
0
00
tWR
PRE
0
00
ACT
tRP
Xa
0
00
DQ
Da0 Da1
[ Write Interrupted by Burst Terminate ]
Burst terminate command can terminate burst write operation. In this case, the write recovery time is not required and the bank remains active. WRITE to TBST interval is minimum 1 CLK.
Write interrupted by Terminate (BL=4)
CLK
Command
A0-9,11-12
A10
BA0-1
ACT
Xa
0
00
Write
Ya
0
00
TBST Write
Yb
0
00
DQ
Da0 Da1
MITSUBISHI ELECTRIC
Db0 Db1 Db2 Db3
22
Page 23
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
Single Data Rate
MITSUBISHI LSIs
July '01
256M Synchronous DRAM
[ Write with Auto-Precharge Interrupted by Write / Read to another Bank ]
Burst write with auto-precharge can be interrupted by write or read to another bank. Next ACT comand can be issued after (BL+tWR-1+tRP) from the WRITEA. Auto-precharge interruption by a command to the same bank is inhibited.
WRITEA interrupted by WRITE to another bank (BL=4)
CLK
Command
A0-9,11-12
A10
BA0-1
Write
Ya
1
00
Write
BL
Yb
0
10
tRP
tWR
ACT
Xa
Xa
00
DQ Db0 Db1 Db2 Db3
CLK
Command
A0-9,11-12
A10
BA0-1
DQ
Da0 Da1
interruptedauto-precharge activate
WRITEA interrupted by READ to another bank (CL=2, BL=4)
Write
Ya
1
00
Da0 Da1
Read
BL
Yb
0
10
tRP
tWR
Qb0 Qb1 Qb2 Qb3
ACT
Xa
Xa
00
interruptedauto-precharge activate
MITSUBISHI ELECTRIC
23
Page 24
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
Single Data Rate
MITSUBISHI LSIs
July '01
256M Synchronous DRAM
[ Read with Auto-Precharge Interrupted by Read to another Bank ]
Burst read with auto-precharge can be interrupted by read to another bank. Next ACT comand can be issued after (BL+tRP) from the READA. Auto-precharge interruption by a command to the same bank is inhibited.
READA interrupted by READ to another bank (CL=2, BL=4)
CLK
Command
A0-9,11-12
A10
BA0-1
Read
Ya
1
00
Read
BL tRP
Yb
0
10
ACT
Xa
Xa
00
DQ
Qa0 Qa1
interruptedauto-precharge activate
Qb0 Qb1 Qb2 Qb3
Full Page Burst
Full page burst length is available for only the sequential burst type. Full page burst read / write is repeated untill a Precharge or a Burst Terminate command is issued. In case of the full page burst, a read / write with auto-precharge command is illegal.
Single Write
When sigle write mode is set, burst length for write is always one, independently of Burst Length defined by (A2-0).
MITSUBISHI ELECTRIC
24
Page 25
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
command. The refresh address is generated internally. 8192 REFA cycles within 64ms refresh 256Mbit
Single Data Rate
MITSUBISHI LSIs
July '01
256M Synchronous DRAM
AUTO REFRESH
Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= /CAS= L, /WE= /CKE= H)
memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing an auto­refresh, all banks must be in idle state. Auto-refresh to auto-refresh interval is minimum tRFC. Any command must not be issued before tRFC from the REFA command.
Auto-Refresh
CLK
/CS
/RAS
/CAS
NOP or DESELECT
/WE
CKE
A0-12
BA0-1
Auto Refresh on All Banks
minimum tRFC
Auto Refresh on All Banks
MITSUBISHI ELECTRIC
25
Page 26
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh mode,
Single Data Rate
MITSUBISHI LSIs
July '01
256M Synchronous DRAM
SELF REFRESH
Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= L, /WE= H, CKE= L).
CKE is asynchronous and the only enabled input. All other inputs including CLK are disabled and ignored, so that power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then asserting CKE=H. After tRFC from the 1st CLK edge following CKE=H, all banks are in idle state and a new command can be issued, but DESEL or NOP commands must be asserted till then.
Self-Refresh
CLK
Stable CLK NOP
/CS
/RAS
/CAS
/WE
CKE
A0-12
BA0-1
Self Refresh Entry Self Refresh Exit
new command
X
00
minimum tRFC for recovery
MITSUBISHI ELECTRIC
26
Page 27
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
CLK SUSPEND and POWER DOWN
negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output
Single Data Rate
MITSUBISHI LSIs
July '01
256M Synchronous DRAM
CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By
suspend or input suspend. CKE is a synchronous input except during the self-refresh mode. CLK suspend can be performed either when the banks are active or idle. A command at the suspended cycle is ignored.
ext.CLK
tIH tIS tIH tIS
CKE
int.CLK
Power Down by CKE
CLK
CKE
Command
CKE
Command
CLK
CKE
Command
Standby Power Down
PRE NOP NOP NOP
Active Power Down
NOP NOP NOPACT
DQ Suspend by CKE
Write Read
DQ
D0 D1 D2 D3
MITSUBISHI ELECTRIC
Q0 Q1 Q2 Q3
27
Page 28
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
During reads, DQMU/L forces output to Hi-Z word by word. DQMU/L to output Hi-Z latency is 2.
Single Data Rate
MITSUBISHI LSIs
July '01
DQM CONTROL
DQMU/L is a dual functional signal defined as the data mask for writes and the output disable for reads. During writes, DQMU/L masks input data word by word. DQMU/L to Data In latency is 0.
DQM Function
CLK
Command
DQMU/L
DQ
Write Read
D0 D2 D3 Q0 Q1 Q3
256M Synchronous DRAM
masked by DQMU/L=H disabled by DQMU/L=H
MITSUBISHI ELECTRIC
28
Page 29
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Single Data Rate
MITSUBISHI LSIs
July '01
Operating TempratureTopr
Storage TempretureTstg
(Ta=0 ~ 70¡C, unless otherwise noted)
256M Synchronous DRAM
UnitRatingsConditionsParameterSymbol
with respect to VssSupply VoltageVdd
with respect to VssQSupply Voltage for OutputVddQ
with respect to VssInput VoltageVI
with respect to VssQOutput VoltageVO
-0.5 ~ 4.6
-0.5 ~ 4.6
-0.5 ~ Vdd+0.5
-0.5 ~ VddQ+0.5
0~ 70
-65~ 150
V
V
V
V
mA50Output CurrentIO
mW1000Ta=25'CPower DissipationPd
'C
'C
ParameterSymbol
Limits
Max.Typ.Min.
Unit
V3.63.33.0Supply VoltageVdd V000Supply VoltageVss
V3.63.33.0Supply Voltage for OutputVddQ
V000Supply Voltage fo OutputVssQ
VVdd+0.32.0High-Level Input Voltage all inputsVIH
V0.8-0.3Low-Level Input Voltage all inputsVIL
CAPACITANCE
(Ta=0 ~ 70¡C, Vdd = VddQ = 3.3 ± 0.3V, Vss = VssQ = 0V, unless otherwise noted)
Test ConditionParameterSymbol
Limits
Max.Min.
Input Capacitance,address pinCI(A)
Unit
pF3.82.5
Input Capacitance,control pinCI(C)
Input Capacitance,CLK pinCI(K)
CI/O
Input Capacitance,I/O pin
MITSUBISHI ELECTRIC
VI=1.4V
f=1MHz
VI=25mVrms
pF3.82.5 pF3.52.5 pF6.54.0
29
Page 30
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
AVERAGE SUPPLY CURRENT from Vdd
Single Data Rate
MITSUBISHI LSIs
July '01
256M Synchronous DRAM
(Ta=0 ~ 70¡C, Vdd = VddQ = 3.3 ± 0.3V, Vss = VssQ = 0V, Output Open, unless otherwise noted)
Limits(max)
Icc1
Icc2P Icc2PS
Icc2N
Icc2NS
Icc3N
Icc3NS
Operating Current (1bank)
Idle Standby Current in Power Down Mode
Idle Standby Current in Normal Mode
Active Standby Current in Normal Mode
Test ConditionsParameterSymbol
tCLK=min, tRC=min, BL=1
tCLK=min, CKE<VILmax tCLK=L, CKE<VILmax tCLK=min, CKE>VIHmin,
/CS>VIHmin tCLK=L, CKE>VIHmin tCLK=min, CKE>VIHmin,
/CS> VIHmin tCLK=L, CKE>VIHmin
Organi
zation
x4 x8 x16
110 115 120
2 1
30
6
35
15
-6
90 95
100
1.5 1
25
6
30
15
-7-5
80 85 90
1 1
20
6
25
15
mA
mA mA
mA
mA
mA
mA
NoteUnit
1
2
2,3
2,4
3,5
4,5
x4
Icc4
Notes
1. addresses are changed 3 times during tRC, only 1 bank is active & all other banks are idle
2. all banks are idle
3. input signals are changed one time during 3xtCLK
4. input signals are stable
5. all banks are active
Burst Operating Current
tCLK=min, BL=4, gapless data
tCLK=min, tRFC=minAuto-Refresh Current Icc5
x8 x16
110
140
110 120
150 100
180
220
3
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70¡C, Vdd = VddQ = 3.3 ± 0.3V, Vss = VssQ = 0V, unless otherwise noted)
Symbol Parameter Test Conditions
VOH(DC)
High-Level Output Voltage (DC)
IOH=-2mA
Limits
Min. Max.
2.4
90 90140
170
mA
mA
mA33-5/-6/-7CKE<0.2vSelf-Refresh Current Icc6
5
Unit
V VOL(DC) IOZ II
Low-Level Output Voltage (DC) Off-state Output Current Input Current
MITSUBISHI ELECTRIC
IOL= 2mA Q floating Vo=0 ~ VddQ VIH=0 ~ VddQ+0.3V, other input pins=0V
-10
-10
0.4 10 10
V
µA µA
30
Page 31
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
AC TIMING REQUIREMENTS
Single Data Rate
MITSUBISHI LSIs
July '01
256M Synchronous DRAM
(Ta=0 ~ 70¡C, Vdd = VddQ = 3.3 ± 0.3V, Vss = VssQ = 0V, unless otherwise noted) Input Pulse Levels: 0.8V to 2.0V Input Timing Measurement Level: 1.4V
Limits
tCH tCL
tT tIS tIH
tRC
ParameterSymbol
CL=2
CLK cycle timetCLK
CL=3 CLK High pulse width CLK Low pulse width Transition time of CLK Input Setup time (all inputs) Input Hold time (all inputs) Row Cycle time
7.5 6
2.5
2.5
1.5
0.8
60
-5
10
7.5
2.5
2.5
101
1.5
0.8
-7-6 Max.Min.Max.Min.Max.Min.
10 10
3 3
101101 2 1
7067.5
NoteUnit
ns ns ns ns ns ns ns
ns tRFC tRCD
tRAS
tRP
tWR
tRRD
tRSC
tREF
Refresh Cycle time Row to Column Delay
Row Active time
Row Precharge time Write Recovery time ACT to ACT Delay time Mode Register Set Cycle
time Average Refresh Interval
CLK
Signal
60 15
42
15 12 12
12
120000
7.8
1.4V
1.4V
8075 2020
1200005012000045
2020 2015 2015
2015
AC timing is referenced to the input signal crossing through
1.4V.
ns
ns
ns
ns
ns
ns
ns
µs7.87.8
MITSUBISHI ELECTRIC
31
Page 32
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
SWITCHING CHARACTERISTICS
Single Data Rate
MITSUBISHI LSIs
July '01
256M Synchronous DRAM
(Ta=0 ~ 70¡C, Vdd = VddQ = 3.3 ± 0.3V, Vss = VssQ = 0V, unless otherwise noted)
Limits
tAC
tOH
tOLZ
tOHZ
ParameterSymbol
Access Time from CLK
Output Hold Time from CLK
Delay Time, Output Low
impedance from CLK
Delay Time, Output High
impedannce from CLK
CL=2 CL=3 CL=2 CL=3
CL=2 5.43
-5
5.4
5.4 3 3
0
3 3
6
5.4
-7-6 Unit MaxMin.MaxMin.MaxMin.
6
6 3 3
00
6363
ns ns ns ns
ns
ns
ns635.435.43CL=3
Note. If tr (CLK rising time) is > 1ns, (tr/2 - 0.5ns) should be added to the parameters.
Output Load Condition
Vout
50pF
CLK
DQ
tOLZ
tOHZ
1.4V
1.4V
tAC tOH
MITSUBISHI ELECTRIC
32
Page 33
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
/WE
Single Data Rate
MITSUBISHI LSIs
July '01
Burst Write (Single Bank) [BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
/CS
tRAS
/RAS
tRCD
/CAS
CKE
tRC
tWR
256M Synchronous DRAM
tRP
tRCD
tWR
DQM
A0-9,11
A10
A12
BA0,1
DQ
X
X
X
0
ACT#0 WRITE#0 PRE#0 ACT#0 WRITE#0 PRE#0
Y
0
D0 D0 D0 D0
X Y
X
X
0
0 0
0
D0 D0 D0 D0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
33
Page 34
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
/WE
Single Data Rate
MITSUBISHI LSIs
July '01
Burst Write (Multi Bank) [BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
/CS
tRAS
tRRD
/RAS
tRCD
/CAS
CKE
tRC
tRCD
tWR
256M Synchronous DRAM
tRC
tRP
tRCD
tWR
DQM
A0-9,11
A10
A12
BA0,1
DQ
X
X
X
0
ACT#0 WRITE#0 PRE#0 ACT#0 WRITE#0 PRE#0
Y
X
X
X
0
1
D0 D0 D0 D0
ACT#1
WRITEA#1 (Auto-Precharge)
Y
0
1
D1 D1 D1 D1
X Y
X
X
0 0
X
X
X
1
D0 D0 D0 D0
ACT#1
0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
34
Page 35
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
/WE
Single Data Rate
MITSUBISHI LSIs
July '01
Burst Read (Single Bank) [CL=2, BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
tRC
/CS
tRAS tRP
/RAS
tRCD
/CAS
CKE
256M Synchronous DRAM
tRAS
tRCD
DQM
A0-9,11
A10
A12
BA0,1
DQ
X
X
X
0
ACT#0 READ#0 PRE#0 ACT #0 READ#0 PRE#0
Y
0
Q0 Q0 Q0 Q0
0
X Y
X
X
0 0
0
Q0 Q0 Q0 Q0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
35
Page 36
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
/WE
Single Data Rate
MITSUBISHI LSIs
July '01
Burst Read (Multi Bank) [CL=2, BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
tRC
/CS
tRRD
/RAS
tRCD tRCD
tRCD
/CAS
CKE
256M Synchronous DRAM
tRC
tRAS
DQM
A0-9,11
A10
A12
BA0,1
DQ
X
X
X
0
ACT#0 READA#0
Y
0
ACT#1
X
X
X
1
Q0 Q0 Q0 Q0
READA#1
Y
1
X Y
X
X
0 0
Q1 Q1 Q1 Q1
ACT #0 READ#0 PRE#0
X
X
X
1
Q0 Q0 Q0 Q0
ACT #1
0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
36
Page 37
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
/WE
Single Data Rate
MITSUBISHI LSIs
July '01
Write Interrupted by Write [BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
/CS
tRRD
/RAS
tRCD
/CAS
CKE
256M Synchronous DRAM
tWR
DQM
A0-9,11
A10
A12
BA0,1
DQ
X
X
X
0
ACT#0 WRITE#0 WRITE#0 PRE#0
Y
X
X
X
0
1
D0 D0 D0 D0
ACT#1
Y
0
WRITE#0 WRITEA#1 interrupt same bank
Y
1
D0 D1 D1 D1
interrupt other bank
Y
0
D0 D0 D0 D0
interrupt other bank
0
ACT #1
X
X
X
1
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
37
Page 38
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
/WE
Single Data Rate
MITSUBISHI LSIs
July '01
Read Interrupted by Read [CL=2, BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
/CS
tRRD
/RAS
tRCD
tRCD
/CAS
CKE
256M Synchronous DRAM
DQM
A0-9,11
A10
A12
BA0,1
DQ
X
X
X
0
ACT#0 READ#0 READ#0
Y
X
X
X
0
1
ACT#1
Y
1
Q0 Q0
READ#1 READA#1 interrupt other bank
Y
1
Q0 Q1 Q1 Q1
interrupt same bank
Y
0
Q1 Q1 Q0 Q0
interrupt other bank
X
X
X
1
Q0 Q0
ACT #1
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
38
Page 39
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
/WE
Single Data Rate
MITSUBISHI LSIs
July '01
256M Synchronous DRAM
Write Interrupted by Read, Read Interrupted by Write [CL=2, BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
/CS
tRRD
/RAS
tRCD
tRCD
/CAS
CKE
tWR
DQM
A0-9,11
A10
A12
BA0,1
DQ
X
X
X
0
ACT#0 WRITE#0 WRITE#1 PRE#1
ACT#1
X
X
X
1
Y
0
D0 D0
Y
1
READ#1
Q1 Q1
Y
1
D1 D1 D1 D1
1
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
39
Page 40
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
/WE
Single Data Rate
MITSUBISHI LSIs
July '01
Write / Read Terminated by Precharge [CL=2, BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
/CS
tRP
/RAS
tRCD
tRCD
/CAS
tWR
CKE
tRAS
256M Synchronous DRAM
tRC
tRP
DQM
A0-9,11
A10
A12
BA0,1
DQ
X
X
X
0
ACT#0 WRITE#0 READ#0 PRE#0
Y
0
D0 D0
X
X
X
0
PRE#0
Terminate Terminate
0
ACT#0
Y
0
0
Q0 Q0
X
X
X
0
ACT#0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
40
Page 41
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
/WE
Single Data Rate
MITSUBISHI LSIs
July '01
Write / Read Terminated by Burst Terminate [CL=2, BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
/CS
/RAS
tRCD
/CAS
CKE
256M Synchronous DRAM
tWR
DQM
A0-9,11
A10
A12
BA0,1
DQ
X
X
X
0
ACT#0 WRITE#0 READ#0
Y
0
D0 D0
Y
0
TBST
Q0 Q0
TBST
Y
0
D0 D0 D0 D0
WRITE#0
0
PRE#0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
41
Page 42
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
/WE
Single Data Rate
MITSUBISHI LSIs
July '01
Single Write Burst Read [CL=2, BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
/CS
/RAS
tRCD
/CAS
CKE
256M Synchronous DRAM
DQM
A0-9,11
A10
A12
BA0,1
DQ
X
X
X
0
ACT#0 WRITE#0 READ#0
Y
0
D0 Q0 Q0
Y
0
Q0 Q0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
42
Page 43
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
/WE
Minimum 8 REFA cycles
Single Data Rate
MITSUBISHI LSIs
July '01
Power-Up Sequence and Intialize
CLK
100µs
/CS
tRP tRFC
/RAS
/CAS
CKE
256M Synchronous DRAM
tRFC tRSC
DQM
A0-9,11
A10
A12
BA0,1
DQ
Power On
NOP
PRE ALL REFA ACT #0MRSREFA
REFA
MA
0
0
0
X
X
X
0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
43
Page 44
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
/WE
Single Data Rate
MITSUBISHI LSIs
July '01
Auto Refresh
CLK
/CS
/RAS
/CAS
CKE
256M Synchronous DRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
tRFC
tRP
tRCD
DQM
A0-9,11
A10
A12
BA0,1
DQ
PRE ALL REFA
All banks must be idle before REFA is issued.
X
X
X
0
ACT#0
Y
0
D0 D0 D0 D0
WRITE#0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
44
Page 45
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
/WE
Single Data Rate
MITSUBISHI LSIs
July '01
Self Refresh
CLK
/CS
/RAS
/CAS
CKE
256M Synchronous DRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
tRFC
tRP
DQM
A0-9,11
A10
A12
BA0,1
DQ
PRE ALL Self Refresh Entry Self Refresh Exit
All banks must be idle before REFS is issued.
X
X
X
0
ACT#0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
45
Page 46
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
/WE
Single Data Rate
MITSUBISHI LSIs
July '01
CLK Suspension [CL=2, BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
/CS
/RAS
tRCD
/CAS
CKE
256M Synchronous DRAM
DQM
A0-9,11
A10
A12
BA0,1
DQ
X
X
X
0
ACT#0 WRITE#0 READ#0
Y
0
D0 Q0 Q0
D0 D0 D0
internal CLK suspended
Y
0
Q0
internal CLK suspended
Q0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
46
Page 47
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
/WE
Single Data Rate
MITSUBISHI LSIs
July '01
Power Down
CLK
/CS
/RAS
/CAS
CKE
256M Synchronous DRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Standby Power Down Active Power Down
DQM
A0-9,11
A10
A12
BA0,1
DQ
X
X
X
0
PRE ALL ACT #0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
47
Page 48
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
1. These materials are intended as a reference to assist our customers in the selection of the Mitsubishi
other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an
be exported under a license from the Japanese government and cannot be imported into a country other
Single Data Rate
MITSUBISHI LSIs
July '01
256M Synchronous DRAM
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
semiconductor product best suited to the customerÕs application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
2. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-partyÕs rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or
authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.
5. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corp oration or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must
than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
MITSUBISHI ELECTRIC
48
Page 49
SDRAM (Rev.1.01)
M2V56S20/ 30/ 40
-5, -6, -7
Single Data Rate
MITSUBISHI LSIs
July '01
Revison History
256M Synchronous DRAM
Description Date Rev.
1st editionJuly / '011.01
MITSUBISHI ELECTRIC
49
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