Datasheet M29W800DT70N6E Specification

8 Mbit (1Mb x8 or 512Kb x16, Boot Block)

Features

■ Supply voltage

–V

■ Access times: 45, 70, 90ns

■ Programming time

– 10µs pe r Byte /Word typical

■ 19 memory blocks

– 1 Boot block (Top or Bottom location)
– 2 Parameter and 16 main blocks

■ Program/Erase controller

– Embedded Byte/Word Program algorithms

■ Erase Suspend and Resume modes

– Rea d an d Program anot he r Block dur i n g

■ Unlock bypass program command

– Faster production/batch programming

■ Temporary block unprotection mode

■ Common flash interface

– 64-bit Security Code

■ Low power consumption

– Standby and Automatic Standby

■ 100,000 Program/Erase cycles per bloc k

■ Electronic signature

– Manufacturer Code: 0020h
– Top Device Code M29W800DT: 22D7h
– Bottom Device Code M29W800DB: 225Bh

2.7V to 3.6V for Progr am, Er ase an d

CC =

Read

Erase Suspend

M29W800DT

M29W800DB

3V Supply Flash Memory

SO44 (M)

TSOP48 (N)
12 x 20 mm

FBGA

TFBGA48 (ZE)

6 x 8 mm

March 2006 Rev 8 1/49

www.st.com

1

Contents M29W800DT, M29W800DB

Contents

1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

9 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Appendix A Block address table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Appendix B Common Flash Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Appendix C Block protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

C.1 Programmer Technique. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

C.2 In-System Technique. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

2/49

M29W800DT, M29W800DB List of tables

List of tables

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. Bus Operations, BYTE = V
Table 3. Bus Operations, BYTE = V
Table 4. Commands, 16-bit mode, BYTE = V
Table 5. Commands, 8-bit mode, BYTE = V

Table 6. Program, Erase Times and Program, Erase Endurance Cycles. . . . . . . . . . . . . . . . . . . . . 20

Table 7. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 9. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 10. Device Capacitance

Table 11. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 12. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 13. Write AC Characteristics, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 14. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 15. Reset/Block Temporary Unprotect AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 16. SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data . . 32
Table 17. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data. . . 33
Table 18. TFBGA48 6x8mm – 6x8 active ball array – 0.80mm pitch, Package Mechanical Data . . . 34

Table 19. Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 20. Top Boot Block Addresses, M29W800DT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 21. Bottom Boot Block Addresses, M29W800DB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 22. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 23. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 24. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 25. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 26. Primary Algorithm-Specific Extended Query Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 27. Security Code Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 28. Programmer Technique Bus Operations, BYTE = V

Table 29. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

IL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

IH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

IH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

IL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

or V

IH

IL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

3/49

List of figures M29W800DT, M29W800DB

List of figures

Figure 1. Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. SO Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4. TFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 5. Block Addresses (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 6. Block Addresses (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 7. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 8. Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 9. AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 10. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 11. Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 12. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 13. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 14. Reset/Block Temporary Unprotect AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 15. SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Outline . . . . . . . . . 32

Figure 16. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . . . 33

Figure 17. TFBGA48 6x8mm – 6x8 ball array – 0.80mm pitch, Bottom View Package Outline . . . . . 34

Figure 18. Programmer Equipment Block Protect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 19. Programmer Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 20. In-System Equipment Block Protect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 21. In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4/49

M29W800DT, M29W800DB Summary description

1 Summary description

The M29W800D is a 8 Mbit (1Mb x8 or 512Kb x16) non-volatile memory that can be read,
erased and reprogrammed. These operations can be performed using a single low voltage
(2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode where it can be
read in the same way as a ROM or EPROM.

The memory is divided into blocks that can be erased independently so it is possible to
preserve valid data while old data is erased. Each block can be protected independently to
prevent accidental Program or Erase commands from modifying the memory. Program and
Erase commands are written to the Command Interface of the memory. An on-chip
Program/Erase Controller simplifies the process of programming or erasing the memory by
taking care of all of the special operations that are re quired to update the memory contents.

The end of a program or erase operation can be detected and any error conditions
identified. The command set required to control the memory is consistent with JEDEC
standards.

The blocks in the memory are asymmetrically arranged, see Figure 5: Block Addresses (x8)
and Figure 6: Block Addresses (x16). The first or last 6 4 Kbytes have been divided into four
additional blocks. The 16 Kbyte Boot Block can be used for small initialization code to start
the microprocessor, the two 8 Kbyte Parameter Blocks can be used for parameter storage
and the remaining 32K is a small Main Block where the application may be stored.

Chip Enable, Output Enable and Write Enable signals control the bus operation of the
memory. They allow simple connection to most microprocessors, oft en without additional
logic.

The memory is offered in SO44, TSOP48 (12 x 20mm) and TFBGA48 6 x 8 mm (0.8mm
pitch) packages. The memory is supplied with all the bits erased (set to ’1’).

Figure 1. Logic Diagram

V

CC

A0-A18

W

RP

BYTE

19

E

G

M29W800DT
M29W800DB

V

SS

15

DQ0-DQ14

DQ15A–1

RB

AI05470B

5/49

Summary description M29W800DT, M29W800DB

Table 1. Signal Names

Signal Description

A0-A18 Address Inputs
DQ0-DQ7 Data Inputs/Outputs
DQ8-DQ14 Data Inputs/Outputs
DQ15A–1 Data Input/Output or Address Input
E Chip Enable
G Output Enable
W Write Enable
RP Reset/Block Temporary Unprotect
RB
BYTE Byte/Word Organization Select
V

CC

V

SS

NC Not Connected Internally

Ready/Busy Output (not available on SO44 package)

Supply Voltage
Ground

Figure 2. SO Connections

A18
A17 A8

V

DQ0
DQ8

DQ9

DQ10

DQ3

DQ11

RP

A7
A6
A5
A4
A3
A2
A1
A0

SS

1
2
3
4
5
6
7
8
9
10
11

M29W800DT
M29W800DB

12

E

13
14

G

15
16
17DQ1
18
19
20
21

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
2322

W
NC

A9
A10
A11
A12
A13
A14
A15
A16
BYTE
V

SS

DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5DQ2
DQ12
DQ4
V

CC

AI05462b

6/49

M29W800DT, M29W800DB Summary description

Figure 3. TSOP Connections

A15
A14
A13
A12
A11

1

48

A16
BYTE
V

SS

DQ15A–1
DQ7

A10 DQ14

A9

A8
NC
NC

W
RP
NC
NC
RB

A18
A17

A7
A6
A5
A4
A3
A2
A1

12

M29W800DT
M29W800DB

13

24 25

AI05461

37
36

DQ6
DQ13
DQ5
DQ12
DQ4
V

CC

DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
V

SS

E
A0

7/49

Summary description M29W800DT, M29W800DB

Figure 4. TFBGA Connections (Top view through package)

4321

A

B

C

D

E

F

G

A3

A4

G

A7

A5

DQ0

DQ9

RB

NCA17

NC

DQ10DQ8E

W A13

RP A8

DQ12

V

CC

A9

DQ14

DQ13DQ11

65

A12

A14A10NCA18A6A2

A15A11NCA1

A16DQ7DQ5DQ2A0

BYTE

DQ15

A–1

H

SS

DQ3

DQ4

DQ6DQ1V

V

SS

AI00656

8/49

M29W800DT, M29W800DB Summary description

Figure 5. Block Addresses (x8)

M29W800DT

Top Boot Block Addresses (x8)

Bottom Boot Block Addresses (x8)

M29W800DB

FFFFFh

FC000h
FBFFFh

FA000h

F9FFFh

F8000h

F7FFFh

F0000h

EFFFFh

E0000h

1FFFFh

10000h

0FFFFh

00000h

16 KByte

8 KByte

8 KByte

32 KByte

64 KByte

Total of 15

64 KByte Blocks

64 KByte

64 KByte

FFFFFh

F0000h

EFFFFh

E0000h

1FFFFh

10000h

0FFFFh

08000h

07FFFh

06000h

05FFFh

04000h

03FFFh

00000h

64 KByte

64 KByte

Total of 15

64 KByte Blocks

64 KByte

32 KByte

8 KByte

8 KByte

16 KByte

AI05463

Note: Also see Appendix A: Block address table, Table 20 and Table 21 for a full listing of the

Block Addresses.

9/49

Summary description M29W800DT, M29W800DB

Figure 6. Block Addresses (x16)

Top Boot Block Addresses (x16)

M29W800DT

Bottom Boot Block Addresses (x16)

M29W800DB

7FFFFh

7E000h

7DFFFh

7D000h

7CFFFh

7C000h

7BFFFh

78000h

77FFFh

70000h

0FFFFh

08000h

07FFFh

00000h

8 KWord

4 KWord

4 KWord

16 KWord

32 KWord

Total of 15

32 KWord Blocks

32 KWord

32 KWord

7FFFFh

78000h

77FFFh

70000h

0FFFFh

08000h

07FFFh

04000h

03FFFh

03000h

02FFFh

02000h

01FFFh

00000h

32 KWord

32 KWord

Total of 15

32 KWord Blocks

32 KWord

16 KWord

4 KWord

4 KWord

8 KWord

AI05464

Note: Also see Appendix A: Block address table, Table 20 and Table 21 for a full listing of the

Block Addresses.

10/49

M29W800DT, M29W800DB Signal descriptions

2 Signal descriptions

See Figure 1: Logic Diagram and Table 1: Sign al Names for a brief overview of the signals
connected to this device.

Address Inputs (A0-A18)

The Address Inputs select the cells in the memory array to access during Bus Read
operations. During Bus Write operations they control the commands sent to the Command
Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ7)

The Data Inputs/Outputs output the data stor ed at the selected address during a Bus Read
operation. During Bus Write operations the y represen t the commands sent to the Command
Interface of the internal state machine.

Data Inputs/Outputs (DQ8-DQ14)

The Data Inputs/Outputs output the data stor ed at the selected address during a Bus Read
operation when BYTE
high impedance. During Bus Write operations the Command Register does not use these
bits. When reading the Status Register these bits should be ignored.

is High, VIH. When BYTE is Low, VIL, these pins are not used and are

Data Input/Output or Address Input (DQ15A-1)

When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14).
When BYTE
LSB of the Word on the other addresses, DQ15A–1 High will select the MSB. Throughout
the text consider references to the Data Input/Output to include this pin when BYTE
and references to the Address Inputs to include this pin when BYTE
stated explicitly otherwise.

is Low, VIL, this pin behaves as an address pin; DQ15A–1 Low will select the

is High

is Low except when

Chip Enable (E)

The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to
be performed. When Chip Enable is High, V

, all other pins are ignored.

IH

Output Enable (G)

The Output Enable, G, controls the Bus Read operation of the memory.

Write Enable (W)

The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface.

Reset/Block Temporary Unprotect (RP)

The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the
memory or to temporarily unprotect all Blocks that have been protected.

A Hardware Reset is achieved by holding Reset/Block Temporary Unprotect Low, V
least t
ready for Bus Read and Bus Write operations after t
See the Ready/Busy Output section, Tab le 15: Reset/Block Temporary Unprotect AC

. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be

PLPX

PHEL

or t

, whichever occurs last.

RHEL

, for at

IL

11/49

Signal descriptions M29W800DT, M29W800DB

Characteristics and Figure 14: Reset/Block Temporary Unprotect AC Waveforms, for more

details.
Holding RP

and Erase operations on all blocks will be possible. The transition from V
slower than t

at VID will temporarily unprotect the protected Blocks in the memory. Program

to VID must be

IH

PHPHH

.

Ready/Busy Output (RB)

The Ready/Busy pin is an open-drain output that can be used to identify when the device is
performing a Program or Er ase operat ion. During Progr am or Erase op erations Read y/Busy
is Low, V

. Ready/Busy is high-impedance during Read mode, Auto Select mode and

OL

Erase Suspend mode.
After a Hardware Reset, Bu s Read and Bus Write oper ations cannot begin un til Ready/Busy

becomes high-impedance. See Table 15: Reset/Block Temporary Unprotect AC

Characteristics and Figure 14: Reset/Block Temporary Unprotect AC Waveforms.

The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the
memories is busy.

Byte/Word Organization Select (BYTE)

The Byte/Word Organization Select pin is used to switch between the 8-bit and 16-bit Bus
modes of the memory. When Byte/Word Organization Select is Low, V
bit mode, when it is High, V

, the memory is in 16-bit mode.

IH

, the memory is in 8-

IL

VCC Supply Voltage

The VCC Supply Voltage supplies the power for all operations (Read, Program, Erase etc.).
The Command Interface is disabled when the V

Voltage, V

. This prevents Bus Write operations from accidentally damaging the data

LKO

Supply Voltage is less than the Lockout

CC

during power up, power down and power surges . If the Program/Erase Controller is
programming or erasing du ring this time then the o peration aborts and the memory contents
being altered will be invalid.

A 0.1µF capacitor should be connected between the V

Supply Voltage pin and the VSS

CC

Ground pin to decouple the current surges from the power supply. The PCB track widths
must be sufficient to carry the currents required during program and erase operations, I

CC3

VSS Ground

The VSS Ground is the reference for all voltage measurements.

.

12/49

M29W800DT, M29W800DB Bus operations

3 Bus operations

There are five standard bus operations that control the device. These are Bus Read, Bus
Write, Output Disable, Standby and Automatic Standby. See Table 2 and Table 3, Bus
Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write
Enable are ignored by the memory and do not affect bus operations.

Bus Read

Bus Read operations read from the memory cells, or specific registers in the Command
Interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs, applying a Low signal, V
Enable High, V

. The Data Inputs/Outputs will output the value, see Figure 11: Read Mode

IH

AC Waveforms, and Figure 12: Read AC Characteristics for deta ils of when the output

becomes valid.

Bus Write

Bus Write operations write to the Command Interface . A v alid Bus Write operation begin s by
setting the desired address on the Address Inputs. The Address Inputs are latched by the
Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs
last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of
Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, V
during the whole Bus Write operation. See Figure 12 and Figure 13, Write AC Waveforms,
and Table 13 and Table 14, Write AC Characteristics, for details of the timing requirements.

, to Chip Enable and Output Enable and keeping Write

IL

IH

,

Output Disable

The Data Inputs/Outputs are in the high impedance sta te when Output Enable is High, VIH.

Standby

When Chip Enable is High, VIH, the memory enters Standby mode and the Data
Inputs/Outputs pins are placed in the h igh-impedance state . To reduce the Su pply Current to
the Standby Supply Current, I

, Chip Enable should be held within V

CC2

± 0.2V. For the

CC

Standby current level see Table 11: DC Character istics.
During program or erase operations the memory will continue to use the Program/Erase

Supply Current, I

, for Program or Erase operations until the operation completes.

CC3

Automatic Standby

If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 150ns or
more the memory enters Automatic Standb y where the inte rnal Supply Current is reduced to
the Standby Supply Current, I

. The Data Inputs/Outputs will still output data if a Bus

CC2

Read operation is in progress.

Special Bus Operations

Additional bus operations can be performed to read the Electronic Signature and also to
apply and remove Block Protection. These bus operations are intended for use by
programming equipment and are no t usually used in applications. They require V
applied to some pins.

to be

ID

13/49

Bus operations M29W800DT, M29W800DB

Electronic Signature

The memory has two codes, the manufacturer code and the device code, that can be read
to identify the memory. These codes can be read by applying the signals listed in Table 2
and Table 3, Bus Operations.

Block Protection and Blocks Unprotection

Each block can be separately protected against accidental Program or Erase. Protected
blocks can be unprotected t o allow data to be changed.

There are two methods available for protecting and unprotecting the blocks, one for use on
programming equipment and the other for in-system use. Block Protect and Chip Unprotect
operations are described in Appendix C: Block protection.

Table 2. Bus Operations, BYTE = VIL

(1)

Operation E G W

Bus Read V
Bus Write V
Output Disable X V
Standby V

V

IL

V

IL

IH

V

IL
IH
IH

IH

VILCommand Address Hi-Z Data Input

V

IH

X X X Hi-Z Hi-Z

Read
Manufacturer

V

V

IL

V

IL

IH

Code

Read Device Code V

1. X = VIL or VIH.

Table 3. Bus Operations, BYTE = V

V

IL

V

IL

IH

Operation E G W

Bus Read V
Bus Write V

IL
IL

Output Disable X V
Standby V
Read Manufacturer

Code

Read Device Code V

1. X = VIL or VIH.

IH

V

IL

IL

V

IL

V

IH
IH

X X X Hi-Z

V

IL

V

IL

Address Inputs

DQ15A–1, A0-A18

Data Inputs/Outputs

DQ14-DQ8 DQ7-DQ0

Cell Address Hi-Z Data Output

X Hi-Z Hi-Z

A0 = VIL, A1 = VIL, A9 =
VID, Others VIL or V

IH

A0 = VIH, A1 = VIL, A9 =
VID, Others VIL or V

(1)

IH

IH

Address Inputs

A0-A18

V

Cell Address Data Output

IH

V

Command Address Data Input

IL

V

X Hi-Z

IH

A0 = VIL, A1 = VIL, A9 = VID,

V

IH

Others V
A0 = VIH, A1 = VIL, A9 =

V

IH

VID, Others VIL or V

IL

or V

IH

IH

Hi-Z 20h

Hi-Z

D7h (M29W800DT)
5Bh (M29W800DB)

Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

0020h

22D7h (M29W800DT)
225Bh (M29W800DB)

14/49

M29W800DT, M29W800DB Command interface

4 Command interface

All Bus Write operations to the memory are interpreted by the Command Interface.
Commands consist of one or more sequential Bus Write operations. Failure to observe a
valid sequence of Bus Write operations will result in the memory returning to Read mode.
The long command sequences are imposed to maximize data security.

The address used for the commands changes depending on whether the memory is in 16­bit or 8-bit mode. See either Table 4, or Table 5, depending on the configuration that is being
used, for a summary of the commands.

Read/Reset Command

The Read/Reset command returns the memory to its Read mode where it behaves like a
ROM or EPROM, unless otherwise stated. It also resets the errors in the Status Register.
Either one or three Bus Write operations can be used to issue the Read/Reset command.

The Read/Reset Command can be issued, between Bus Write cycles before the start of a
program or erase operation, to return the device to read mode. Once the program or erase
operation has started the Read/Reset command is no longer accepted. The Read/Reset
command will not abort an Erase operation when issued while in Erase Suspend.

Auto Select Command

The Auto Select comman d is used to read t he Manufacturer Code, the Device Code and t he
Block Protection Status. Three consecutive Bus Write operations are required to issue the
Auto Select command. Once the Auto Select command is issued the memory remains in
Auto Select mode until a Read/Reset command is issued. Read CF I Query and Read/Reset
commands are accepted in Auto Select mode, all other commands are ignored.

From the A uto Select m ode the Manuf acturer Cod e can be read using a Bus Read ope ration
with A0 = V

and A1 = VIL. The other address bits may be set to either VIL or VIH. The

IL

Manufacturer Code for STMicroelectronics is 0020h.
The Device Code can be read using a Bus Read operation with A0 = V

other address bits may be set to either V

or VIH. The Device Code for the M29W800DT is

IL

and A1 = VIL. The

IH

22D7h and for the M29W800DB is 225Bh.
The Block Protection Status of each block can be read using a Bus Read operation with A0

= V

, A1 = VIH, and A12-A18 specifying the address of the block. The other address bits

IL

may be set to either V

or VIH. If the addressed block is protected then 01h is output on

IL

Data Inputs/Outputs DQ0-DQ7, otherwise 00h is output.

Program Command

The Program command can be used to progr am a v alue to one address in the memory arra y
at a time. The command requires f our Bus Write oper ations , the fina l write operation lat ches
the address and data in the internal state machine and starts the Program/Erase Controller.

If the address falls in a protected block then the Program command is ignored, the data
remains unchanged. The Status Register is never read and no error condition is given.

During the program operation the memory will ignore all commands. It is not possible to
issue any command to abort or pause the operation. Typical program times are given in

Table 6 Bus Read operations during the program operation will output the Status Register

on the Data Inputs/Outputs. See the section on the Status Register for more details.

15/49

Command interface M29W800DT, M29W800DB

After the program operation has completed the memory will return to the Read mode, unless
an error has occurred. When an error occurs the memory will continue to output the Status
Register. A Read/Reset command must be issued to reset the error condition and return to
Read mode.

Note that the Program command cannot change a bit set at ’0’ bac k to ’1’. One of the Er ase
Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.

Unlock Bypass Command

The Unlock Bypass command is used in conjunction with the Unlock Bypass Program
command to program the memory. When the access time to the device is long (as with
some EPROM programmers) considerable time saving can be made by using these
commands. Three Bus Write operations are required to issue t he Unlock Bypass command.

Once the Unlock Bypass command has been issued the memory will only accept the Unlock
Bypass Program command and the Unlock Bypass Reset command. The memory can be
read as if in Read mode.

Unlock Bypass Program Command

The Unlock Bypass Program command can be used to program one address in memory at
a time. The command requires two Bus Write operations, the final write operation latches
the address and data in the internal state machine and starts the Program/Erase Controller.

The Program operation using the Unlock Bypass Program command behaves identically to
the Program operation using the Program command. A protected block cannot be
programmed; the operation cannot be aborted and the Status Register is read. Errors must
be reset using the Read/Reset command, which leaves the device in Unlock Bypass Mode.
See the Program command for details on the behavior.

Unlock Bypass Reset Command

The Unlock Bypass Reset command can be used to return to Read/Reset mode from
Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass
Reset command. Read/Reset command does not exit from Unlock Bypass Mode.

Chip Erase Command

The Chip Erase command can be used to erase the entire chip. Six Bus Write operations
are required to issue the Chip Erase Command and start the Program/ Erase Controller.

If any blocks are protected then these are ignored and all the other blocks are erased. If all
of the blocks are protected the Chip Erase operation appears to start but will terminate
within about 100µs, leav ing the data u nchanged. No error conditio n is giv en wh en protected
blocks are ignored.

During the erase operation the memory will ignore all commands. It is not possible to issue
any command to abort the operation. Typical chip erase times are given in Table 6 All Bus
Read operations during the Chip Erase operation will output the Status Register on the Data
Inputs/Outputs. See the section on the Status Register for more details.

After the Chip Erase operation has completed the memory will return to the Read Mode,
unless an error has occurred. When an error occurs the memory will continue to output the
Status Register. A Read/Reset command must be issued to reset the error condition and
return to Read Mode.

16/49

M29W800DT, M29W800DB Command interface

The Chip Erase Command sets all of the bits in unprot ected blocks of the memory to ’1’. All
previous data is lost.

Block Erase Command

The Block Erase command can be used t o erase a list of one or more blocks. Six Bus Write
operations are required to select the first b lock in the list. Each additional blo ck in the list can
be selected by repeating the sixth Bus Write operation using the address of the additional
block. The Block Erase operation starts the Program/Erase Controller about 50µs after the
last Bus Write operation. Once the Program/Erase Controller starts it is not possible to
select any more blocks. Each additional bloc k must therefore be selected within 50µs of the
last block. The 50µ s timer restarts when an additional b lock is sele cted. The Status Reg ister
can be read after the sixth Bus Write operation. See the Status Register for details on how
to identify if the Program/Erase Contr oller has started the Block Erase operation.

If any selected blocks are protected then these are ignored and all the other select ed b loc ks
are erased. If all of the selected blocks are protected the Block Erase operation appears to
start but will terminate within about 100µs, leaving the data unchanged. No error condition is
given when protected blocks are ignored.

During the Block Erase operation the memory will ignore all commands except the Erase
Suspend command. Typical block erase times are given in Table 6 All Bus Read operations
during the Block Erase operation will output the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more details.

After the Block Erase operation has completed the memory will return to the Read Mode,
unless an error has occurred. When an error occurs the memory will continue to output the
Status Register. A Read/Reset command must be issued to reset the error condition and
return to Read mode.

The Block Erase Command sets all of the bits in the unprotected selected blocks to ’1’. All
previous data in the selected blocks is lost.

Erase Suspend Command

The Erase Suspend Command may be used to temporarily suspend a Block Erase
operation and return the memory to Read mode. The command requires one Bus Write
operation.

The Program/Erase Controller will suspend within the Erase Suspend Latency Time (refer to

Table 6 for value) of the Erase Suspend Command being issued. Once the Program/Erase

Controller has stopped the memory will be set to Read mode and the Erase will be
suspended. If the Erase Suspend command is issued during the period when the memory is
waiting for an ad ditional b loc k (bef ore the Prog ram/Er ase Controller st arts) then the Erase is
suspended immediately and will start immediately when the Erase Resume Command is
issued. It is not possible to select any further blo cks to erase after the Erase Resume.

During Erase Suspend it is possible to Read and Program cells in blocks that are not being
erased; both Read and Program operations behave as normal on these blocks. If any
attempt is made to progr am in a prote cted b loc k or in the suspended b loc k then the Progr am
command is ignored and the data remai ns unchanged. The Status Register is not read and
no error condition is given. Reading from blocks that are being erased will output the Status
Register.

It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands
during an Erase Suspend. The Read/Reset co mmand must be i ssued to return the de vice to
Read Array mode before the Resume command will be accepted.

17/49

Command interface M29W800DT, M29W800DB

Erase Resume Command

The Erase Resume command must be used to restart the Program/Erase Controller from
Erase Suspend. An erase can be suspended and resumed more than once.

Read CFI Query Command

The Read CFI Query Command is used to read data from the Common Flash Interface
(CFI) Memory Area. This command is valid when the device is in the Read Array mode, or
when the device is in Auto Select mode.

One Bus Write cycle is required to issue the Read CFI Query Command. Once the
command is issued subsequent Bus Read operations read from the Common Flash
Interface Memory Area.

The Read/Reset command must be issued to re turn the device to the previous mode (Read
Array mode or Auto Select mode). A second Read/Reset command would be needed if the
device is to be put in the Read Array mode from Auto Select mode.

See Appendix B: Common Flash Interface (CFI), Table 22, Table 23, Table 24, Table 25,

Table 26 and Table 27 for details on the information contained in the Common Flash

Interface (CFI) memory area.

Block Protect and Chip Unprotect Commands

Each block can be separately protected against accidental Program or Erase. The whole
chip can be unprotected to allow the data inside the blocks to be changed.

Block Protect and Chip Unprotect operations are described in Appendix C: Block protection

18/49

M29W800DT, M29W800DB Command interface

Table 4. Commands, 16-bit mode, BYTE = VIH

(1)

Bus Write Operations

Command

Read/Reset

1X F0

1st 2nd 3rd 4th 5th 6 th

Length

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

3 555 AA 2AA 55 X F0
Auto Select 3 555 AA 2AA 55 555 90
Program 4 555 AA 2AA 55 555 A0 PA PD
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass Program 2 X A0 PA PD
Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30
Read CFI Query 1 55 98

1. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.
All values in the table are in hexadecimal format.
The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A18, DQ8-DQ14 and DQ15
are Don’t Care. DQ15A–1 is A–1 when BYTE

is VIL or DQ15 when BYTE is VIH.

19/49

Command interface M29W800DT, M29W800DB

Table 5. Commands, 8-bit mode, BYTE = V

(1)

IL

Bus Write Operations

Command

1st 2nd 3rd 4th 5th 6th

Length

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

1X F0

Read/Reset

3 AAA AA 555 55 X F0
Auto Select 3 AAA AA 555 55 AAA 90
Program 4 AAA AA 555 55 AAA A0 PA PD
Unlock Bypass 3 AAA AA 555 55 AAA 20
Unlock Bypass

Program

2X A0PAPD

Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10
Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30
Read CFI Query 1 AA 98

1. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.
All values in the table are in hexadecimal.
The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A18, DQ8-DQ14 and DQ15
are Don’t Care. DQ15A–1 is A–1 when BYTE

Table 6. Program, Erase Times and Program, Erase Endurance Cycles

Parameter Min. Typ.

Chip Erase 12 60
Block Erase (64 Kbytes) 0.8 6
Erase Suspend Latency Time 15 25
Program (Byte or Word) 10 200
Chip Program (Byte by Byte) 12 60
Chip Program (Word by Word) 6 30

is VIL or DQ15 when BYTE is VIH.

(1), (2)

Max.

(4)

(3)

(3)

(3)
(4)

(3)

(2)

Unit

s

s
µs
µs

s

s

Program/Erase Cycles (per Block) 100,000 cycles
Data Retention 20 years

1. Typical values measured at room temperature and nominal voltages.

2. Sampled, but not 100% tested.

3. Maximum value measured at worst case conditions for both temperature and V

4. Maximum value measured at worst case conditions for both temperature and V

after 100,000 program/erase cycles.

CC

.

CC

20/49

M29W800DT, M29W800DB Status register

5 Status register

Bus Read operations from an y address alwa ys read the Stat us Register during Progra m and
Erase operations. It is also read during Erase Suspend when an address within a block
being erased is accessed.

The bits in the Status Register are summarized in Table 7: Status Register Bits.

Data Polling Bit (DQ7)

The Data Polling Bit can be used to identify whether the Program/Erase Controller has
successfully completed its operation or if it has responded to an Erase Suspend. The Data
Polling Bit is output on DQ7 when the Status Register is read.

During Program operations the Data Polling Bit outputs the complement of the bit being
programmed to DQ7. After successful completion of the Program operation the memory
returns to Read mode and Bus Read operations from the address just programmed output
DQ7, not its complement.

During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state
of DQ7. After successful completion of the Erase operation the memory returns to Read
Mode.

In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation
within a block being erased. The Data Polling Bit will change from a ’0’ to a ’1’ when the
Program/Erase Controller has suspended the Erase operation.

Figure 7: Data Polling Flowchart gives an example of ho w to use the Da ta P olling Bit. A Valid

Address is the address being programmed or an address within the block being erased.

Toggle Bit (DQ6)

The Toggle Bit can be used to identify whether the Program/Erase Controller has
successfully completed its operation or if it h as responded to an Erase Suspend. The Toggle
Bit is output on DQ6 when the Status Register is read.

During Program and Erase operations the To ggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations at any address. After successful completion of the
operation the memory returns to Read mode.

During Erase Suspend mode the Toggle Bit will output when addressing a cell within a bloc k
being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has
suspended the Erase operation.

If any attempt is made to erase a protected block, the operation is ab orted, no error is
signalled and DQ6 toggles for approximately 100µs. If any attempt is made to program a
protected block or a suspended block, the operation is aborted, no error is signalled and
DQ6 toggles for approximately 1µs.

Figure 8: Data Toggle Flowchart gives an example of how to use the Data Toggle Bit.

Error Bit (DQ5)

The Error Bit can be used to identify errors detected by the Program/Erase Controller. The
Error Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the
correct data to the memory. If the Error Bit is set a Read/Reset command must be issued

21/49

Status register M29W800DT, M29W800DB

before other commands are issued. The Error bit is output on DQ5 when the Status Register
is read.

Note that the Program command cannot change a bit se t t o ’0’ back to ’1’ and attempting to
do so will set DQ5 to ‘1’. A Bus Read operation to that address will show the bit is still ‘0’.
One of the Erase commands must be used to set all the bits in a block or in the whole
memory from ’0’ to ’1’

Erase Timer Bit (DQ3)

The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation
during a Block Erase command. Once the Program/Erase Controller starts erasing the
Erase Timer Bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer Bit
is set to ’0’ and additional blocks to be erased may be written to the Command Inte rface.
The Erase Timer Bit is output on DQ3 when the Status Register is read.

Alternative Toggle Bit (DQ2)

The Alternative Toggle Bit can be used to monitor the Program/Erase controller during
Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is
read.

During Chip Erase and Block Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’,
etc., with successive Bus Read operations fr om addresses within the b locks being er ased. A
protected block is treated the same as a block not being erased. Once the operation
completes the memory returns to Read mode.

During Erase Suspend the Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with
successive Bus Read operations from addre sses within the blocks being erased. Bus Read
operations to addresses within blocks not being erased will output the memory cell data as if
in Read mode.

After an Erase operation that causes the Error Bit to be se t the Alternative To ggle Bit can b e
used to identify which block or blocks have caused the error. The Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses
within blocks that have not erased correctly. The Alternative Toggle Bit does not change if
the addressed block has erased correctly.

22/49

M29W800DT, M29W800DB Status register

Table 7. Status Register Bits

(1)

Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB

Program Any Address DQ7 Toggle 0 – – 0
Program During Erase

Suspend

Any Address DQ7 Toggle 0 – – 0

Program Error A ny Address DQ7 Toggle 1 – – 0
Chip Erase Any Address 0 Toggle 0 1 Toggle 0

Block Erase before
timeout

Erasing Block 0 Toggle 0 0 Toggle 0

Non-Erasing Block 0 Toggle 0 0 No Toggle 0

Erasing Block 0 Toggle 0 1 Toggle 0

Block Erase

Non-Erasing Block 0 Toggle 0 1 No Toggle 0

Erasing Block 1 No Toggle 0 – Toggle 1

Erase Suspend

Non-Erasing Block Data read as normal 1

Good Block Address 0 Toggle 1 1 No Toggle 0

Erase Error

Faulty Block Address 0 Toggle 1 1 Toggle 0

1. Unspecified data bits should be ignored.

Figure 7. Data Polling Flowchart

START

READ DQ5 & DQ7

at VALID ADDRESS

DQ7

DATA

NO

DQ5

READ DQ7

at VALID ADDRESS

DQ7

DATA

FAIL PASS

= 1

YES

=

NO

YES

YES

=

NO

AI03598

23/49

Status register M29W800DT, M29W800DB

Figure 8. Data Toggle Flowchart

START

READ DQ6

READ

DQ5 & DQ6

DQ6

=

TOGGLE

YES

NO

DQ5

= 1

YES

READ DQ6

TWICE

DQ6

=

TOGGLE

YES

FAIL PASS

NO

NO

AI01370C

24/49

M29W800DT, M29W800DB Maximum rating

6 Maximum rating

Stressing the device above the rating listed in the Absolute Maximum Ratings table may
cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions
for extended periods may affect device reliability. These are stress ratings only and
operation of the device at these or any other conditions above those indicated in the
Operating sections of this specification is not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents.

Table 8. Absolute maximum ratings

Symbol Parameter Min Max Unit

T

BIAS

T

STG

V

IO

V

CC

V

ID

1. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions.

2. Maximum voltage may overshoot to V

Temperature Under Bias –50 125 °C
Storage Temperature –65 150 °C
Input or Output Voltage

(1) (2)

–0.6 VCC +0.6 V
Supply Voltage –0.6 4 V
Identification Voltage –0.6 13.5 V

+2V during transition and for less than 20ns during transitions.

CC

25/49

DC and AC parameters M29W800DT, M29W800DB

7 DC and AC parameters

This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions summarized in

Table 9: Operating and AC Measurement Conditions. Designers should check that the

operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.

Table 9. Operating and AC Measurement Conditions

M29W800D

Parameter

Min Max Min Max Min Max

V

Supply Vo ltage 3.0 3.6 2.7 3.6 2.7 3.6 V

CC

Ambient Operating Temperature (Range 6) –40 85 –40 85 –40 85
Ambient Operating Temperature (Range 1) 0 70 0 70 0 70
Load Capacitance (C

) 30 30 100 pF

L

Input Rise and Fall Times 10 10 10 ns
Input Pulse Voltages 0 to V
Input and Output Timing Ref. Voltages V

CC

CC

/2 VCC/2 VCC/2 V

0 to V

CC

0 to V

CC

Figure 9. AC Measurement I/O Waveform

V

CC

VCC/2

0V

AI04498

Unit45 70 90

°C

V

26/49

M29W800DT, M29W800DB DC and AC parameters

Figure 10. AC Measurement Load Circuit

V

CC

0.1µF

CL includes JIG capacitance

Table 10. Device Capacitance

DEVICE
UNDER

TEST

(1)

V

CC

25kΩ

C

L

25kΩ

AI04499

Symbol Parameter Test Condition Min Max Unit

C

IN

C

OUT

1. Sampled only, not 100% tested.

Table 11. DC Characteristics

Input Capacitance VIN = 0V 6 pF
Output Capacitance V

= 0V 12 pF

OUT

Symbol Parameter Test Condition Min Max Unit

I

I

LO

I

CC1

I

CC2

I

CC3

V
V

V

V

V

I

V

LKO

1. Sampled only, not 100% tested.

Input Leakage Current 0V ≤ VIN ≤ V

LI

Output Leakage Current 0V ≤ V

Supply Current (Read)

Supply Current (Standby)

Supply Current

(1)

(Program/Erase)
Input Low Voltage –0.5 0.8 V

IL

Input High Vo ltage 0.7V

IH

Output Low Voltage IOL = 1.8mA 0.45 V

OL

Output High Voltage IOH = –100µAVCC –0.4 V

OH

Identification Voltage 11.5 12.5 V

ID

Identification Current A9 = V

ID

Program/Erase Lockout Supply
Voltage

CC

≤ V

OUT

CC

E = VIL, G = VIH,

f = 6MHz

E = VCC ±0.2V,

= VCC ±0.2V

RP

Program/Erase

Controller active

ID

CC

1.8 2.3 V

±1 µA
±1 µA

10 mA

100

20 mA

VCC +0.3 V

100 µA

µA

27/49

DC and AC parameters M29W800DT, M29W800DB

Figure 11. Read Mode AC Waveforms

tAVAV

A0-A18/
A–1

tAVQV tAXQX

E

VALID

tELQV

tELQX tEHQZ

G

tGLQX tGHQX

tGLQV

DQ0-DQ7/
DQ8-DQ15

tBHQV

BYTE

tELBL/tELBH tBLQZ

Table 12. Read AC Characteristics

Symbol Alt Parameter Test Condition

= VIL,

t

t

AVAV

t

AVQV

(1)

t

ELQX

t

ELQV

(1)

t

GLQX

t

GLQV

(1)

t

EHQZ

(1)

t

GHQZ

t

EHQX

t

GHQX

t

AXQX

t

ELBL

t

ELBH

t

BLQZ

t

BHQV

1. Sampled only, not 100% tested.

t
t

t

Address Valid to Next Address Valid

RC

t

Address Valid to Output Valid

ACC

t

Chip Enable Low to Output Transition G = VILMin000ns

LZ

t

Chip Enable Low to Output Valid G = VILMax 45 70 90 ns

CE

t

Output Enable Low to Output Transition E = V

OLZ

t

Output Enable Low to Output Valid E = VILMax 25 30 35 ns

OE

t

Chip Enable High to Output Hi-Z G = VILMax 20 25 30 ns

HZ

t

Output Enable High to Output Hi-Z E = VILMax 20 25 30 ns

DF

Chip Enable, Output Enable or Address

t

OH

Transition to Output Transition

t

ELFL

Chip Enable to BYTE Low or High Max 5 5 5 ns

ELFH

BYTE Low to Output Hi-Z Max 25 25 30 ns

FLQZ

BYTE High to Output Valid Max 30 30 40 ns

FHQV

E

= V

G

= VIL,

E

G = V

IL

IL

IL

tEHQX

tGHQZ

VALID

AI05448

M29W800D

Unit

45 70 90

Min 45 70 90 ns

Max 45 70 90 ns

Min000ns

Min000ns

28/49

M29W800DT, M29W800DB DC and AC parameters

Figure 12. Write AC Waveforms, Write Enable Controlled

tAVAV

A0-A18/
A–1

tAVWL

E

VALID

tWLAX

tWHEH

tELWL

G

tWLWHtGHWL

W

tDVWH

DQ0-DQ7/
DQ8-DQ15

V

CC

tVCHEL

RB

Table 13. Write AC Characteristics, Write Enable Controlled

VALID

tWHRL

Symbol Alt Parameter

t

AVAV

t

ELWL

t

WLWH

t

DVWH

t

WHDX

t

WHEH

t

WHWL

t

AVWL

t

WLAX

t

GHWL

t

WHGL

(1)

t

WHRL

t

VCHEL

1. Sampled only, not 100% tested.

t

WC

t

CS

t

WP

t

DS

t

DH

t

CH

t

WPH

t

AS

t

AH

t

OEH

t

BUSY

t

VCS

Address Valid to Next Address Valid Min 45 70 90 ns
Chip Enable Low to Write Enable Low Min 0 0 0 ns
Write Enable Low to Write Enable High Min 30 45 50 ns
Input Valid to Write Enable High M in 25 45 50 ns
Write Enable High to Input Transition Min 0 0 0 ns
Write Enable High to Chip Enable High Min 0 0 0 ns
Write Enable High to Write Enable Low Min 30 30 30 ns
Address Valid to Write Enable Low Min 0 0 0 ns
Write Enable Low to Address Transition Min 40 45 50 ns
Output Enable High to Write Enable Low Min 0 0 0 ns
Write Enable High to Output Enable Low Min 0 0 0 ns
Program/Erase Valid to RB Low Max 30 30 35 ns
VCC High to Chip Enable Low Min 50 50 50 µs

tWHGL

tWHWL

tWHDX

AI05449

M29W800D

Unit

45 70 90

29/49

DC and AC parameters M29W800DT, M29W800DB

Figure 13. Write AC Waveforms, Chip Enable Controlled

tAVAV

A0-A18/
A–1

tAVEL

W

VALID

tELAX

tEHWH

tWLEL

G

tELEHtGHEL

E

tDVEH

DQ0-DQ7/
DQ8-DQ15

V

CC

tVCHWL

RB

Table 14. Write AC Characteristics, Chip Enable Controlled

VALID

tEHRL

Symbol Alt Parameter

t

AVAV

t

WLEL

t

ELEH

t

DVEH

t

EHDX

t

EHWH

t

EHEL

t

AVEL

t

ELAX

t

GHEL

t

EHGL

(1)

t

EHRL

t

VCHWL

1. Sampled only, not 100% tested.

t

WC

t

WS

t

CP

t

DS

t

DH

t

WH

t

CPH

t

AS

t

AH

t

OEH

t

BUSY

t

VCS

Address Valid to Ne xt Address Valid Min 45 70 90 ns
Write Enable Low to Chip Enable Low Min 0 0 0 ns
Chip Enable Low to Chip Enable High Min 30 45 50 ns
Input Valid to Chip Enable High Min 25 45 50 ns
Chip Enable High to Input Transition Min 0 0 0 ns
Chip Enable High to Write Enable High Min 0 0 0 ns
Chip Enable High to Chip Enable Low Min 30 30 30 ns
Address Valid to Chip Enable Low Min 0 0 0 ns
Chip Enable Low to Address Transition Min 40 45 50 ns
Output Enable High Chip Enable Low Min 0 0 0 ns
Chip Enable High to Output Enable Low Min 0 0 0 ns
Program/Erase Valid to RB Low Max 30 30 35 ns
VCC High to Write Enable Low Min 50 50 50 µs

tEHGL

tEHEL

tEHDX

AI05450

M29W800D

Unit

45 70 90

30/49

M29W800DT, M29W800DB DC and AC parameters

Figure 14. Reset/Block Temporary Unprotect AC Waveforms

E, G

W,

tPHWL, tPHEL, tPHGL

RB

tRHWL, tRHEL, tRHGL

RP

Table 15. Reset/Block Temporary Unprotect AC Characteristics

Symbol Alt Parameter

(1)

t

PHWL

t

PHEL

(1)

t

PHGL

(1)

t

RHWL

(1)

t

RHEL

(1)

t

RHGL

t

PLPX

(1)

t

PLYH

(1)

t

PHPHH

1. Sampled only, not 100% tested.

t

RH

t

RB

t

RP

t

READY

t

VIDR

tPLPX

tPHPHH

tPLYH

AI06870

M29W800D

Unit

45 70 90

RP High to Write Enable Low, Chip Enable
Low, Output Enable Low

RB High to Write Enable Low, Chip Enable
Low, Output Enable Low

Min 50 50 50 ns

Min000ns

RP Pulse Width Min 500 500 500 ns
RP Low to Read Mode Max 10 10 10 µs
RP Rise Time to V

ID

Min 500 500 500 ns

31/49

Package mechanical data M29W800DT, M29W800DB

8 Package mechanical data

Figure 15. SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Outline

A2

A

C

b

e

CP

D

N

E

EH

1

LA1 α

SO-d

Note: Drawing is not to scale.

Table 16. SO44 – 44 lead Plastic Small Outline, 525 mils bod y width, Package Mechanical Data

Symbol

millimeters inches

Typ Min Max Typ Min Max

A 2.80 0.1102
A1 0.10 0.0039
A2 2.30 2.20 2.40 0.0906 0.0866 0.0945

b 0.40 0.35 0.50 0.0157 0.0138 0.0197

C 0.15 0.10 0.20 0.0059 0.0039 0.0079
CP 0.08 0.0030

D 28.20 28.00 28.40 1.1102 1.1024 1.1181

E 13.30 13.20 13.50 0.5236 0.5197 0.5315
EH 16.00 15.75 16.25 0.6299 0.6201 0.6398

e 1.27 – – 0.0500 – –
L 0.80 0.0315
a8° 8°

N44 44

32/49

M29W800DT, M29W800DB Package mechanical data

Figure 16. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline

1

48

e

D1

24

E1

B

25

A2

L1

A

E

DIE

LA1 α

C

CP

TSOP-G

Note: Drawing is not to scale.

Table 17. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data

Symbol

millimeters inches

Typ Min Max Typ Min Max

A 1.200 0.0472
A1 0.100 0.050 0.150 0.0039 0.0020 0.0059
A2 1.000 0.950 1.050 0.0394 0.0374 0.0413

B 0.220 0.170 0.270 0.0087 0.0067 0.0106

C 0.100 0.210 0.0039 0.0083
CP 0.080 0.0031
D1 12.000 11.900 12.100 0.4724 0.4685 0.4764

E 20.000 19.800 20.200 0.7874 0.7795 0.7953
E1 18.400 18.300 18.500 0.7244 0.7205 0.7283

e 0.500 – – 0.0197 – –
L 0.600 0.500 0.700 0.0236 0.0197 0.0276

L1 0.800 0.0315

a3°0°5°3°0°5°

33/49

Package mechanical data M29W800DT, M29W800DB

Figure 17. TFBGA48 6x8mm – 6x8 ball array – 0.80mm pitch, Bottom View Package Outline

D

D1

SD

SE

ddd

e

FE

E1E

FD

BALL "A1"

e

A

b

A2

A1

BGA-Z32

Note: Drawing is not to scale.

Table 18. TFBGA48 6x8mm – 6x8 active ball array – 0.80mm pitch, Package Mechanical Data

Symbol

A 1.200 0.0472
A1 0.260 0.0102
A2 0.900 0.0354

b 0.350 0.450 0.0138 0.0177

D 6.000 5.900 6.100 0.2362 0.2323 0.2402
D1 4.000 – – 0.1575 – –

ddd 0.100 0.0039

E 8.000 7.900 8.100 0.3150 0.3110 0.3189
E1 5.600 – – 0.2205 – –

e 0.800 – – 0.0315 – –

millimeters inches

Typ Min Max Typ Min Max

FD 1.000 – – 0.0394 – –
FE 1.200 – – 0.0472 – –
SD 0.400 – – 0.0157 – –
SE 0.400 – – 0.0157 – –

34/49

M29W800DT, M29W800DB Part numbering

9 Part numbering

Table 19. Ordering Information Scheme

Example: M29W800DB 90 N 6 T

Device Type

M29

Operating Voltage

W = V

Device Function

800D = 8 Mbit (x8/x16), Boot Block

Array Matrix

T = Top Boot
B = Bottom Boot

Speed

45 = 45ns
70 = 70 ns
90 = 90 ns

= 2.7 to 3.6V

CC

Package

M = SO44
N = TSOP48: 12 x 20 mm
ZE = TFBGA48: 6x8mm, 0.80mm pitch

Temperature Range

6 = –40 to 85 °C
1 = 0 to 70 °C

Option

T = Tape & Reel Packing
E = Lead-free Package, Standard Packing
F = Lead-free Package, Tape & Reel Packing

Devices are shipped from the factory with the memory content bits erased to ’1’.

For a list of a v ailable options (Speed, Pac kage , etc.) or f o r further information on an y aspect
of this device, please contact your nearest ST Sales Office.

35/49

Block address table M29W800DT, M29W800DB

Appendix A Block address table

Table 20. Top Boot Block Addresses, M29W800DT

# Size (Kbytes) Address Range (x8) Address Range (x16)

18 16 FC000h-FFFFFh 7E000h-7FFFFh
17 8 FA000h-FBFFFh 7D000h-7DFFFh
16 8 F8000h-F9FFFh 7C000h-7CFFFh
15 32 F0000h-F7FFFh 78000h-7BFFFh
14 64 E0000h-EFFFFh 70000h-77FFFh
13 64 D0000h-DFFFFh 68000h-6FFFFh
12 64 C0000h-CFFFFh 60000h-67FFFh
11 64 B0000h-BFFFFh 58000h-5FFFFh
10 64 A0000h-AFFFFh 50000h-57FFFh

9 64 90000h-9FFFFh 48000h-4FFFFh
8 64 80000h-8FFFFh 40000h-47FFFh
7 64 70000h-7FFFFh 38000h-3FFFFh
6 64 60000h-6FFFFh 30000h-37FFFh
5 64 50000h-5FFFFh 28000h-2FFFFh
4 64 40000h-4FFFFh 20000h-27FFFh
3 64 30000h-3FFFFh 18000h-1FFFFh
2 64 20000h-2FFFFh 10000h-17FFFh
1 64 10000h-1FFFFh 08000h-0FFFFh
0 64 00000h-0FFFFh 00000h-07FFFh

36/49

M29W800DT, M29W800DB Block address table

Table 21. Bottom Boot Block Addresses, M29W800DB

# Size (Kbytes) Address Range (x8) Address Range (x16)

18 64 F0000h-FFFFFh 78000h-7FFFFh
17 64 E0000h-EFFFFh 70000h-77FFFh
16 64 D0000h-DFFFFh 68000h-6FFFFh
15 64 C0000h-CFFFFh 60000h-67FFFh
14 64 B0000h-BFFFFh 58000h-5FFFFh
13 64 A0000h-AFFFFh 50000h-57FFFh
12 64 90000h-9FFFFh 48000h-4FFFFh
11 64 80000h-8FFFFh 40000h-47FFFh
10 64 70000h-7FFFFh 38000h-3FFFFh

9 64 60000h-6FFFFh 30000h-37FFFh
8 64 50000h-5FFFFh 28000h-2FFFFh
7 64 40000h-4FFFFh 20000h-27FFFh
6 64 30000h-3FFFFh 18000h-1FFFFh
5 64 20000h-2FFFFh 10000h-17FFFh
4 64 10000h-1FFFFh 08000h-0FFFFh
3 32 08000h-0FFFFh 04000h-07FFFh
2 8 06000h-07FFFh 03000h-03FFFh
1 8 04000h-05FFFh 02000h-02FFFh
0 16 00000h-03FFFh 00000h-01FFFh

37/49

Common Flash Interface (CFI) M29W800DT, M29W800DB

Appendix B Common Flash Interface (CFI)

The Common Flash Interf ace is a JEDEC app rov ed, sta ndardized data structure that ca n be
read from the Flash memory device. It allows a system software to query the device to
determine various electrical and timing parameters, density information and functions
supported by the memory. The system can interface easily with the device, enabling the
software to upgrade itself when necessary.

When the CFI Query Command is issued the device enters CFI Query mode and the data
structure is read from the memory. Table 22, Table 23, Table 24, Table 25, Table 26 and

Table 27 show the addresses used to retrieve the data.

The CFI data structure also contains a security area where a 64-b it uniq ue se curity n umb er
is written (see Table 27: Security Code Area). This area can be accessed only in Read
mode by the final user. It is impossible to change the security number after it has been
written by ST. Issue a Read command to return to Read mode.

Table 22. Query Structure Overview

Address

Sub-section Name Description

x16 x8

(1)

10h 20h CFI Query Identification String Command set ID and algorithm data offset
1Bh 36h System Interface Information Device timing & voltage information
27h 4Eh Device Geometry Definition Flash device layout

40h 80h

61h C2h Security Code Area 64 bit unique device number

1. Query data are always presented on the lowest order data outputs.

Primary Algorithm-specific Extended
Query table

Additional information specific to the
Primary Algorithm (optional)

38/49

M29W800DT, M29W800DB Common Flash Interface (CFI)

Table 23. CFI Query Identification String

(1)

Address

Data Description Value

x16 x8

10h 20h 0051h "Q"
11h 22h 0052h Query Unique ASCII String "QR Y" "R"
12h 24h 0059h "Y"
13h 26h 0002h
14h 28h 0000h
15h 2Ah 0040h
16h 2Ch 0000h
17h 2Eh 0000h
18h 30h 0000h
19h 32h 0000h

Primary Algorithm Command Set and Control Interface ID
code 16 bit ID code defining a specific algorithm

Address for Primary Algorithm extended Query table (see

Table 26)

Alternate Vendor Command Set and Control Interface ID
Code second vendor - specified algorithm supported

Address for Alternate Algorithm extended Query table

AMD

Compatible

P = 40h

NA

NA

1Ah 34h 0000h

1. Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

Table 24. CFI Query System Interface Information

Address

Data Description Value

x16 x8

V

Logic Supply Minimum Program/Erase voltage

CC

1Bh 36h 0027h

bit 7 to 4 BCD value in volts
bit 3 to 0 BCD value in 100 mV

Logic Supply Maximum Program/Erase voltage

V

CC

1Ch 38h 0036h

bit 7 to 4 BCD value in volts

bit 3 to 0 BCD value in 100 mV
1Dh 3Ah 0000h V
1Eh 3Ch 0000h V

[Programming] Supply Minimum Program/Erase voltage NA

PP

[Programming] Supply Maximum Program/Erase voltage NA

PP

1Fh 3Eh 0004h Typical timeout per single byte/word program = 2n µs 16µs

n

20h 40h 0 000h Typical timeout for minimum size write buffer program = 2
21h 42h 000Ah Typical timeout per individual block erase = 2
22h 44h 0000h Typical timeout for full chip erase = 2n ms

n

ms 1s

(1)

µs NA

23h 46h 0004h Maximum timeout for byte/word program = 2n times typical 256µs
24h 48h 0000h Maximum timeout for write buffer program = 2
25h 4Ah 0003h Maximum timeout per individual block erase = 2
26h 4Ch 0000h Maximum timeout for chip erase = 2n times typical

1. Not supported in the CFI.

n

times typical NA

n

times typical 8s

(1)

2.7V

3.6V

39/49

Common Flash Interface (CFI) M29W800DT, M29W800DB

Table 25. Device Geometry Definition

Address

Data Description Value

x16 x8

n

27h 4Eh 0014h Device Size = 2
28h

29h

2Ah
2Bh

50h
52h

54h
56h

0002h
0000h

0000h
0000h

Flash Device Interface Code description

Maximum number of bytes in multi-byte program or page =

n

2
Number of Erase Block Regions within the device.

2Ch 58h 0004h

It specifies the number of regions within the device
containing contiguous Erase Blocks of the same size.

2Dh
2Eh

2Fh

30h

5Ah
5Ch

5Eh
60h

0000h
0000h

0040h
0000h

Region 1 Information
Number of identical size erase block = 0000h+1

Region 1 Information
Block size in Region 1 = 0040h * 256 byte

in number of bytes 1 MByte

x8, x16

Async.

NA

4

1

16 Kbyte

31h
32h

33h
34h

35h
36h

37h
38h

39h

3Ah
3Bh

3Ch

62h
64h

66h
68h

6Ah
6Ch

6Eh
70h

72h
74h

76h
78h

0001h
0000h

0020h
0000h

0000h
0000h

0080h
0000h

000Eh
0000h

0000h
0001h

Region 2 Information
Number of identical size erase block = 0001h+1

Region 2 Information
Block size in Region 2 = 0020h * 256 byte

Region 3 Information
Number of identical size erase block = 0000h+1

Region 3 Information
Block size in Region 3 = 0080h * 256 byte

Region 4 Information
Number of identical-size erase block = 000Eh+1

Region 4 Information
Block size in Region 4 = 0100h * 256 byte

2

8 Kbyte

1

32 Kbyte

15

64 Kbyte

40/49

M29W800DT, M29W800DB Common Flash Interface (CFI)

Table 26. Primary Algorithm-Specific Extended Query Table

Address

Data Description Value

x16 x8

40h 80h 0050h
41h 82h 0052h "R"

Primary Algor ithm extended Query table unique ASCII
string “PRI”

42h 84h 0049h "I"
43h 86h 0031h Major version number, ASCII "1"
44h 88h 0030h Minor version number, ASCII "0"

Address Sensitive Unlock (bits 1 to 0)

45h 8Ah 0000h

00 = required, 01= not required
Silicon Revision Number (bits 7 to 2)

46h 8Ch 0002h

47h 8Eh 0001h

48h 90h 0001h

49h 92h 0004h

Erase Suspend
00 = not supported, 01 = Read only, 02 = Read and Write

Block Protection
00 = not supported, x = number of sectors in per group

Temporary Block Unprotect
00 = not supported, 01 = supported

Block Protect /Unprotect

04 = M29W400B
4Ah 94h 0000h Simultaneous Operations, 00 = not supported No
4Bh 96h 0000h Burst Mode, 00 = not supported, 01 = supported No

4Ch 98h 0000h

Table 27. Security Code Area

Page Mode, 00 = not supported, 01 = 4 page word, 02 = 8

page word

"P"

Yes

2

1

Yes

4

No

Address

Data Description

x16 x8

61h C3h, C2h XXXX
62h C5h, C4h XXXX
63h C7h, C6h XXXX
64h C9h, C8h XXXX

64 bit: unique device number

41/49

Block protection M29W800DT, M29W800DB

Appendix C Block protection

Block protection can be used to prevent any operation from modifying the data stored in th e
Flash. Each Block can be protected individually. Once prot ected, Program and Erase
operations on the block fail to change the data.

There are three techniques that can be used to control Block Protection, these are the
Programmer technique, the In-System technique and Temporary Unprotection. Temporary
Unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP
described in the Signal Descr ip tio ns sectio n .

Unlike the Command Interface of the Program/Erase Controller, the techniques for
protecting and unprotecting b locks change between different Flash memory suppliers. For
example, the techniques for AMD parts will not work on STMicroelectronics parts. Care
should be taken when changing drivers for one part to work on another.

C.1 Programmer Technique

The Programmer technique uses high (VID) voltage levels on some of the bus pins. These
cannot be achieved using a standard microprocessor bus, therefore the technique is
recommended only for use in Prog ramming Equipment.

; this is

To protect a bloc k follow the flowchart in Figure 18: Programmer Equipment Block Protect

Flowchart, To unprotect the whole chip it is necessary to protect all of the blocks first, then

all blocks can be unprotect ed at the same time. To unprotect the chip follow Figure19:

Programmer Equipment Chip Unprotect Flo wchart. Table 28: Programmer Technique Bus
Operations, BYTE = VIH or VIL, gives a summary of each operation.

The timing on these flowcharts is critical. Care should be taken to ensure t hat, where a
pause is specified, it is followed as closely as possible. Do not abort the procedure before
reaching the end. Chip Unprotect can take several seconds and a user message should be
provided to show that the operation is progressing.

C.2 In-System Technique

The In-System technique requires a high voltage level on the Reset/Blocks Temporary
Unprotect pin, RP
components on the microprocessor bus , therefore this technique is suitable for use af ter the
Flash has been fitted to the system.

To protect a bloc k follow the flowchart in Figure 20: In-System Equipment Block Protect

Flowchart. To unprotect the whole chip it is necessary to protect all of the blocks first, then

all the blocks can be unprotected at the same time. To unprotect the chip follow Figure 21:

In-System Equipment Chip Unprotect Flowchart.

The timing on these flowcharts is critical. Care should be taken to ensure t hat, where a
pause is specified, it is followed as closely as possible. Do not allow the microprocessor to
service interrupts that will upset the timing and do not abort the procedure before reaching
the end. Chip Unprotect can take several seconds and a user message should be provided
to show that the operation is progressing.

. This can be achiev ed without violating the maximum ratings of the

42/49

M29W800DT, M29W800DB Block protection

Table 28. Programmer Technique Bus Operations, BYTE = VIH or V

Operation E G W

Block Protect V

Chip Unprotect V

Block Protection
Verify

Block Unprotection
Verify

Address Inputs

A0-A18

ILVIDVIL

IDVIDVIL

Pulse

Pulse

A9 = VID, A12-A18 Block Address

Others = X

A9 = V

, A12 = VIH, A15 = VIH

ID

Others = X

A0 = VIL, A1 = VIH, A6 = VIL, A9 = VID,

V

V

IL

V

IL

IH

A12-A18 Block Address

Others = X

A0 = VIL, A1 = VIH, A6 = VIH,

V

V

IL

V

IL

IH

A9 = VID, A12-A18 Block Address

Others = X

IL

Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

X

X

Pass = XX01h

Retry = XX00h

Retry =XX01h

Pass = XX00h

43/49

Block protection M29W800DT, M29W800DB

Figure 18. Programmer Equipment Block Protect Flowchart

START

ADDRESS = BLOCK ADDRESS

W = V

IH

n = 0

G, A9 = VID,

E = V

IL

Wait 4µs

W = V

IL

Wait 100µs

W = V

IH

Verify Protect Set-upEnd

E, G = VIH,

A0, A6 = VIL,

A1 = V

IH

E = V

IL

Wait 4µs

G = V

IL

Wait 60ns

Read DATA

DATA

=

01h

YES

A9 = V

IH

E, G = V

IH

PASS

NO

++n

= 25

A9 = V

E, G = V

NO

YES

IH

IH

44/49

FAIL

AI03469

M29W800DT, M29W800DB Block protection

Figure 19. Programmer Equipment Chip Unprotect Flowchart

START

PROTECT ALL BLOCKS

CURRENT BLOCK = 0

ADDRESS = CURRENT BLOCK ADDRESS

A0 = VIL, A1, A6 = V

n = 0

A6, A12, A15 = V

E, G, A9 = V

Wait 4µs

W = V

IL

Wait 10ms

W = V

IH

E, G = V

IH

E = V

IL

Wait 4µs

(1)

IH

ID

IH

Verify Unprotect Set-upEnd

G = V

IL

Wait 60ns

Read DATA

=

00h

YESNO

DATA

++n

NO

= 1000

YES

A9 = V

IH

E, G = V

IH

FAIL PASS

45/49

CURRENT BLOCK

LAST

BLOCK

YES

A9 = V

IH

E, G = V

IH

INCREMENT

NO

AI03470

Block protection M29W800DT, M29W800DB

Figure 20. In-System Equipment Block Protect Flowchart

START

n = 0

RP = V

ID

Verify Protect Set-upEnd

ADDRESS = BLOCK ADDRESS

ADDRESS = BLOCK ADDRESS

ADDRESS = BLOCK ADDRESS

ADDRESS = BLOCK ADDRESS

A0 = VIL, A1 = VIH, A6 = V

WRITE 60h

A0 = VIL, A1 = VIH, A6 = V

WRITE 60h

A0 = VIL, A1 = VIH, A6 = V

Wait 100µs

WRITE 40h

A0 = VIL, A1 = VIH, A6 = V

Wait 4µs

READ DATA

DATA

RP = V

=

01h

NO

YES

IH

IL

IL

IL

IL

++n

= 25

NO

ISSUE READ/RESET

COMMAND

PASS

46/49

YES

RP = V

IH

ISSUE READ/RESET

COMMAND

FAIL

AI03471

M29W800DT, M29W800DB Block protection

Figure 21. In-System Equipment Chip Unprotect Flowchart

START

PROTECT ALL BLOCKS

n = 0

CURRENT BLOCK = 0

RP = V

ID

WRITE 60h

ANY ADDRESS WITH

A0 = VIL, A1 = VIH, A6 = V

WRITE 60h

ANY ADDRESS WITH

A0 = VIL, A1 = VIH, A6 = V

Wait 10ms

IH

IH

Verify Unprotect Set-upEnd

ADDRESS = CURRENT BLOCK ADDRESS

ADDRESS = CURRENT BLOCK ADDRESS

++n

NO

= 1000

YES

RP = V

IH

ISSUE READ/RESET

COMMAND

FAIL

WRITE 40h

A0 = VIL, A1 = VIH, A6 = V

Wait 4µs

READ DATA

A0 = VIL, A1 = VIH, A6 = V

DATA

YESNO

=

00h

IH

IH

ISSUE READ/RESET

CURRENT BLOCK

LAST

BLOCK

YES

RP = V

IH

COMMAND

PASS

INCREMENT

NO

AI03472

47/49

Revision history M29W800DT, M29W800DB

Revision history

Table 29. Document revision history

Date Version Re v isi on Detai ls

August 2001 1.0 First Issue

Block Protection Appendix added, SO44 drawing and package

03-Dec-2001 2.0

01-Mar-2002 3.0

mechanical data updated, CFI Table 26, address 39h/72h data clarified,
Read/Reset operation during Erase Suspend clarified

Description of Ready/Busy signal clarified (and Figure 14 modified)
Clarified allowable commands during block erase
Clarified the mode the device returns to in the CFI Read Query command

section

11-Apr-2002 4.0

Temperature range 1 added
Document promoted from Preliminary Data to full Data Sheet

Erase Suspend Latency Time (typical and maximum) and Data Retention
parameters added to Table Table 6 : Program, Erase Times and Program,

Erase Endurance Cycles, and Typical after 100k W/E Cycles column

31-Mar-2003 4.1

removed. Minimum voltage corrected for 70ns Speed Class in Table 9:

Operating and AC Measurement Conditions.

Logic Diagram and Data Toggle Flowchart correc ted.
Lead-free package options E and F added to Table 19: Ordering

Information Scheme.

TSOP48 package Outline and Mechanical Data updated.

13-Feb-2004 5.0

TFBGA48 6x8mm – 6x8 active ball array – 0.80mm pitch added.

Table 9: Operating and AC Measurement Conditions updated for 70ns

speed option.

23-Apr-2004 6.0 Figure 2: SO Connections updated.

16-Sep-2004 7.0 45ns speed class added.

21-Mar-2006 8.0

Removed TFBGA48 (ZA) (6 x 9 mm) package. Converted to new ST
Corporate template.

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M29W800DT, M29W800DB

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