Datasheet M29F102BB70N1T, M29F102BB70K1, M29F102BB55N1T, M29F102BB50N1T, M29F102BB50K1 Datasheet (SGS Thomson Microelectronics)
...Page 1
1/21July 2000
M29F102BB
1 Mbit (64Kb x16, Boot Block) Single Supply Flash Memory
■ SINGLE 5V±10% SUPPL Y VOLTAGE for
PROGRAM, ERAS E and READ O PER AT IONS
■ ACCESS TIME: 35ns
■ PROGRAMMING TIME
– 8µs per Word typical
■ 5 MEMORY BLOCKS
– 1 Boot Block (Bottom Location)
– 2 Parameter and 2 Main Blocks
■ PROGRAM/ERA SE CON T ROL LER
– Embedded Word Program algorithm
– Embedded Multi-Block/Chip Erase algorithm
– Status Register Polling and Toggle Bits
■ ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
■ UNLOCK BYPASS PROGRAM COMMAND
– Faster Production/Batch Programming
■ TEMPORARY BLOCK UNPROTECTION
MODE
■ LOW POWER CONSUMPTION
– Standby and Automatic Standby
■ 100,000 PROGRAM/ER ASE CYCL ES per
BLOCK
■ M28F102 COMPATIBLE
– Pin-out and Read Mode
■ 20 YEARS DATA RETENTI ON
– Defectivity below 1 ppm/year
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Bottom Device Code M29F102BB: 0097h
TSOP40 (N)
10 x 14mm
PLCC44 (K)
Figure 1. Logic Diagram
AI02130C
16
A0-A15
W
DQ0-DQ15
V
CC
M29F102BB
E
V
SS
16
G
RP
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M29F102BB
2/21
Figure 2. PLCC Connections
AI02131C
A14
A11
A7
A3
23
DQ6
DQ5
DQ4
DQ3
DQ2
NC
A2
DQ12
DQ8
V
SS
NC
DQ11
DQ10
12
A15
A9
1
DQ15
V
SS
A12
DQ13
A5
44
NC
NC
M29F102BB
DQ14
A13
A4
NC
A6
34
DQ1
DQ9 A10
A8DQ7
DQ0
G
A0
A1
RP
E
W
V
CC
Figure 3. TSOP Connections
DQ6
DQ3
DQ2
DQ13
DQ8
DQ7
DQ10
DQ9
A14
A8
A11
A10
A4
A15
A9
G
A7
A2
DQ1
DQ0
A0
A1
A3
NC
W
E
DQ14
RP
V
CC
DQ15
AI02132C
M29F102BB
10
1
11
20 21
30
31
40
V
SS
A13
A12
A6
A5
DQ11
DQ12
DQ5
DQ4
V
SS
Table 1. Signal Names
A0-A15 Address Inputs
DQ0-DQ15 Data Inputs/Outputs
E
Chip Enable
G
Output Enable
W
Write Enable
RP
Reset/Block Temporary Unprotect
V
CC
Supply Voltage
V
SS
Ground
NC Not Connected Internally
SUMMARY DESCRIPTION
The M29F102BB is a 1 Mbit (64Kb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed
using a single 5V supply. On power-up the memory defaults to its Read m ode where it can be read
in the same way as a ROM or EPROM.
The memory is divided into blocks that can be
erased independently so it is pos sible to pres erve
valid data while old data is erased. Each block can
be protected independently to prev ent accidental
Program or Erase commands from modifying the
memory. Program and Erase com m ands are wri tten to the Command Interface of t he memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase op eration can be de tected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.
Page 3
3/21
M29F102BB
The blocks in the memory are as ymmetrically arranged, see Table 3, Block Addresses. The first 32
Kwords have been divided into four additional
blocks. The 8 Kword Boot Block can be used for
small initialization code to start the microprocessor, the two 4 Kword Parameter Blocks can be
used for parameter storage and th e remaining 16
Kwords are a small Main Block where the application may be stored.
Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory.
They allow simple conne ction to most m icroprocessors, often without additional logic.
The memory is offered in PLCC44 and TSOP40
(10 x 14mm) packages and it is suppl ied with all
the bits erased (set to ’1’).
Table 2. Absolute Maximum Ratings
(1)
Note: 1. Except for the ratin g "Operating Temperat ure Range", stresse s above th ose listed in the Tabl e " A bsolute M aximum Rat i ngs" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indi cated in t he Operating secti ons of thi s specif i cation is not imp l i ed. Exposure to Ab solute Maxi m um Rati ng condi tions for extended per iods may aff ect device reliabilit y. Refer also to the STMicroel ectronics SURE Program an d other relevan t qual ity docum en ts .
2. Mini m um Voltage may undershoot to –2V duri ng transiti on and for less t han 20ns during transit io ns.
Symbol Parameter Value Unit
T
A
Ambient Operating Temperature 0 to 70 °C
T
BIAS
Temperature Under Bias –50 to 125 °C
T
STG
Storage Temperature –65 to 150 °C
V
IO
(2)
Input or Output Voltage –0.6 to 6 V
V
CC
Supply Voltage –0.6 to 6 V
V
ID
Identification Voltage –0.6 to 13.5 V
Table 3. Bottom Boot Block Addresses,
M29F102BB
#
Size
(KWords)
Address Range
4 32 8000h-FFFFh
3 16 4000h-7FFFh
2 4 3000h-3FFFh
1 4 2000h-2FFFh
0 8 0000h-1FFFh
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M29F102BB
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SIGNAL DESCRIPTIONS
See Figure 1, Logic Diagram, and Table 1, Sign al
Names, for a brief overview of the signals connected to this device.
Address Inputs (A0-A15). The Address Inputs
select the cells i n the memory array to a ccess during Bus Read operations. During Bus Write operations they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ15). The Data Inputs/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations DQ0-DQ7 represent the commands sent to the Command Interface of the internal state machine; the Command Interface does
not use DQ8-DQ15 to decode the commands.
Chip Enable (E
). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is
High, V
IH
, all other pins are ignored.
Output Enable (G
). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W
). The Write Enable, W, controls
the Bus Write operation of the memory’s Command Interf a c e .
Reset/Block Temporary Unprotect (RP
). The Re-
set/Block Temporary Unprotect pin can be used to
apply a Hardware Reset to the memory or to temporarily unprotect all blocks that have been protected.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V
IL
, for at least
t
PLPX
. After Reset/Block Temporary Unprotect
goes High, V
IH
, the memory will be ready for Bus
Read and Bus Write operations after t
PHEL
or t
PLYH
, whichever occurs last. See Table 13 and
Figure 11, Reset/Temporary Unprotect AC Characteristics for more details.
Holding RP
at VID will temporarily unprotect the
protected blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from V
IH
to VID must be slower than
t
PHPHH
.
Reset/Block Temporary Unprotect can be left unconnected. A weak internal pull-up resistor ensures that the memory always operates correctly.
V
CC
Supply Voltage. The VCC Supply Voltage
supplies the power for all operations (Read, Program, Erase etc.).
The Command Interface is disabled when the V
CC
Supply Voltage is less than the L ockout Voltage,
V
LKO
. This prevents Bus Write operations from accidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memory contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the V
CC
Supply Voltage pin and the VSS Ground
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, I
CC3
.
Vss Ground. The V
SS
Ground is the reference
for all voltage measurements.
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5/21
M29F102BB
Table 4. Bus Operations
Note: X = VIL or VIH.
Operation E G W Address Inputs
Data
Inputs/Outputs
Bus Read
V
IL
V
IL
V
IH
Cell Address Data Output
Bus Write
V
IL
V
IH
V
IL
Command Address Data Input
Output Disable X
V
IH
V
IH
XHi-Z
Standby
V
IH
XXX Hi-Z
Read Manufacturer
Code
V
IL
V
IL
V
IH
A0 = VIL, A1 = VIL, A9 = VID,
Others V
IL
or V
IH
0020h
Read Device Code
V
IL
V
IL
V
IH
A0 = VIH, A1 = VIL, A9 = VID,
Others V
IL
or V
IH
0097h
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Wri te, Output Disable, Standby and Automatic Standby. See
Table 4, Bus Operations, for a summary. Typically
glitches of less than 5ns on Chip Enabl e o r Write
Enable are ignored by t he mem ory and do not a ffect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs, applying a Low sig nal, V
IL
, to Chip Enable
and Output Enable and keeping Write Enable
High, V
IH
. The Data Inputs/Outputs will output the
value, see Figure 8, Rea d Mode AC Wav eforms,
and Table 11, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desire d address on t he Address Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs a re latched by the Command Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output Enable must remain High, V
IH
, during the whole Bus
Write operation. See Figures 9 and 10, Write AC
Waveforms, and Tables 12 and 13, Write AC
Characteristics, for details of the timing requirements.
Output Disa bl e . The Data Inputs/Outputs are in
the high impedance s tate when Output Enable is
High, V
IH
.
Standby. When Chip Enable is High, V
IH
, the
memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-imped-
ance state. To reduce the S upply Current to the
Standby Supply Current, I
CC2
, Chip Enable should
be held within V
CC
± 0.2V. For the Standby current
level see Table 10, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, I
CC3
, for Program or Erase operations un-
til the operation completes.
Automatic Standby. If CMOS levels (V
CC
± 0.2V)
are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is reduced to the Standby Supply Current, I
CC2
. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protec tion. These bus operations are intended for use by programming equipment and are not usually used in applications.
They require V
ID
to be applied to some pins.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying t he signals
listed in Table 4, Bus Operations.
Block Protection and Blocks Unprotection. Each
block can be separately protected against accidental Program or Erase. Protected blocks can be
unprotected to allow data to be changed.
There are two methods available for protecting
and unprotecting the blocks, one for use on programming equipment and the other for in-system
use. For further information refer to Application
Note AN1122, Applying P rotection and Unp rotection to M29 Series Flash.
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M29F102BB
6/21
COMMAND INTERFACE
All Bus Write operations t o the me mory are in terpreted by the Command Interface. Commands
consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus
Write operations will result in the memory returning to Read mode. The long command sequences
are imposed to maximize data security.
The commands are summarized in Table 5, Commands. Refer to Table 5 in conjunction with the
text descriptions below.
Read/Reset Command. The Read/Reset command returns the memory to its Read mode where
it behaves like a ROM or EPROM. It also resets
the errors in the Status Register. Either one or
three Bus Write operations can be u sed to issue
the Read/Reset command.
If the Read/Reset command is issued during a
Block Erase operation or following a Programming
or Erase error then the memory will take upto 10
µs
to abort. During the abort period no valid data can
be read from the mem ory. Issuing a Read/Reset
command during a Block Erase operation will
leave invalid data in the memory.
Auto Select Command. The Auto Select command is used to read the Manufacturer Code, the
Device Code and the Block Protection Status.
Three consecutive Bus Write operations are required to issue the Auto Select command. Once
the Auto Select comma nd is issued the memory
remains in Auto Select mode unt il another command is issued.
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = V
IL
and A1 = VIL. The other address bits
may be set to either V
IL
or VIH. The Manufa cturer
Code for STMicroelectronics is 0020h.
The Device Code can be read using a B us Read
operation with A0 = V
IH
and A1 = VIL. The other
address bits may be set to e ither V
IL
or VIH. The
Device Code for the M29F102BB is 0097h.
The Block Protecti on St at us of e ac h bl ock can be
read using a Bus Rea d operation with A0 = V
IL
,
A1 = V
IH
, and A12-A15 specifying the add ress of
the block. The other address bits may be set to either V
IL
or VIH. If the addressed block is protected
then 01h is output on Data Inputs/Outputs
DQ0-DQ7, otherwise 00h is output.
Program Command. The Program command
can be used to program a value to one address in
the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data in the internal
state machine and starts the Program/Erase Controller.
If the address falls in a pro tected block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.
During the program operat ion the memo ry will ignore all commands. I t is n ot poss ible t o iss ue any
command to abort or pause the operation. Typical
program times are given in Table 6. Bus Read operations during the program o peration will output
the Status Register on the Data Inputs/Outputs.
See the section on the S tatus Register for more
details.
After the program operation has completed the
memory will return to the Read mode, unle ss an
error has occurred. When an error occurs the
memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.
Note that the Program command cannot change a
bit set at ’0’ bac k to ’1’. One of the E rase Commands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.
Unlock Bypass Command. The Unlock Bypass
command is used in conjunction with the Unlock
Bypass Program command to program the memory. When the access time to the device is long (as
with some EPROM programmers) considerable
time saving can be made by using these commands. Three Bus Write operations are requ ired
to issue the Unlock Bypass command.
Once the Unlock Bypas s command has bee n issued the memory will only accept the Unloc k Bypass Program command and the Unlock Bypass
Reset command. The memory can be read as if in
Read mode.
Unlock Bypass Program Command. The Unlock Bypass Prog ram comma nd can be used to
program one address in memory at a time. The
command requires two B us Write operations, the
final write operation latches the address and data
in the internal stat e machine and starts th e Program/Erase Controller.
The Program operation using the Unlock Bypass
Program command behaves identically to the Program operation using the Program command. A
protected block cannot be programmed; the operation cannot be aborted and the Status Register is
read. Errors must be reset using the Read/Re set
command, which l eaves the d evice in Unlo ck Bypass Mode. See the Program command for details
on the behavior.
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M29F102BB
Table 5. Commands
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.
All values in the table are in hexadecimal.
The Com m and Interface only uses addr ess bits A0-A10 a nd DQ0-DQ7 to ver i f y the commands, the upper address bi ts and the upper data
bits are Do n’ t Care.
Read/Re set. After a Read/Reset command, read the memory as normal until another command is issued.
Auto Select. After an Auto Select com m and, read Manufacturer ID, Device ID or Block Protection Status.
Program, Unlock Bypass Program, Ch ip Erase, Bl o ck E r ase. After these command s read t he St atus R egister until t he Pro gram/Er ase
Controller complet es and the mem o ry returns to Re ad Mode. Add additional B l ocks during B l ock Erase Comm and with addi ti onal Bus Write
Operation s until the Timeout Bit is set .
Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.
Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory as normal until another command is issued.
Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program commands
on non-era sing blocks as normal.
Erase Resume. After the E ras e Res ume c omman d the s uspe nde d Er ase o pe ration re sum es, read th e Stat u s Reg ister u ntil the Prog ram/
Erase Cont roller compl etes and th e m emory returns to Read Mo de.
Command
Length
Bus Write Operations
1st 2nd 3rd 4th 5th 6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read/Reset
1X F0
3 555 AA 2AA 55 X F0
Auto Select 3 555 AA 2AA 55 555 90
Program 4 555 AA 2AA 55 555 A0 PA PD
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass
Program
2X A0PAPD
Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30
Unlock Bypass Reset Command. The Unlock
Bypass Reset command can be used to return t o
Read/Reset mode from Unlock Bypass Mode.
Two Bus Write operations are required to issue the
Unlock Bypass Reset command.
Chip Erase Command. The Chip Erase command can be used to erase the entire chip. Six Bus
Write operations are required to issue the Chip
Erase Command and start the Program/Erase
Controller.
If any blocks are protected then these are ignored
and all the other blocks are erased. If all of the
blocks are protect e d th e Chip Erase op erat i on ap-
pears to start but will terminate within about 100µs,
leaving the data unchanged. No error condition is
given when protected blocks are ignored.
During the erase operation the memory will ignore
all commands. It is not possible to issue any command to abort the operation. Typical chip erase
times are given in Table 6. All Bus Read operations during the Chip E rase operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the S tatus Register for more
details.
After the Chip Erase operation has completed t he
memory will return to the Read Mode, unle ss an
error has occurred. When an error occurs the
memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode.
The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All previous
data is lost.
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M29F102BB
8/21
Block Erase Command. The Block Erase command can be use d to erase a list of one or more
blocks. Six Bus Write operations are required to
select the first block in the list. Each additional
block in the list can be selected by repeating the
sixth Bus Write operation using the address of the
additional block. The Block Erase operation starts
the Program/Erase Controller about 50µs after the
last Bus Write operation. Once the Program/Erase
Controller starts it is not possible to select any
more blocks. Each additional block must therefore
be selected within 50µs of the last block. The 50µs
timer restarts when an additional block is selected.
The Status Register can be read after the sixth
Bus Write operation. See the Status Register for
details on how to identify if the Program/Erase
Controller has started the Block Erase operation.
If any selected blocks are protected then these are
ignored and all the other selected blocks are
erased. If all of the selected blocks are p rotected
the Block Erase operation appears to start but will
terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored.
During the Block Erase operation the me mory wi ll
ignore all commands except the Erase Susp end
and Read/Reset commands. Typical block erase
times are given in Table 6. All Bus Read operations during the B lock E rase o peration will ou tput
the Status Register on the Data Inputs/Outputs.
See the section on the S tatus Register for more
details.
After the Block Erase operation has completed the
memory will return to the Read Mode, unle ss an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to reset the error condition and return to Read mode.
The Block Erase Command sets all of the bits in
the unprotected selected blocks to ’1’. All previous
data in the selected blocks is lost.
Erase Suspend Command. The Erase Suspend
Command may be used to temporarily suspend a
Block Erase operation and return the memory to
Read mode. The command requires one Bus
Write operation.
The Program/Erase Controller will sus pend within
15µs of the Erase Suspend Command being issued. Once the Program/Erase Controller has
stopped the memory will be set to Read mode and
the Erase will be suspended. If the Erase Suspend
command is issued during the period when the
memory is waiting for an additional block (before
the Program/Erase Controller starts) then the
Erase is suspended immediate ly and wi ll start immediately when the Erase Resume Comm and is
issued. It will not be possible to select any further
blocks for erasure after the Erase Resume.
During Erase Suspend it is possible to Read and
Program cells in blocks that are not being erased;
both Read and Program operations behave as
normal on these blocks. Reading from blocks that
are being erased will output the Status Register. It
is also possible to enter the Auto Select mode: the
memory will behave as in the Auto Select mode on
all blocks until a Read/Reset command returns the
memory to Erase Suspend mode.
Erase Resume Command. The Erase Resume
command must be used to restart the Program/
Erase Controller from Erase Suspend. An erase
can be suspended and resumed more than once.
Table 6. Program, Erase Times and Progra m , Erase Endurance Cycles
(T
A
= 0 to 70°C)
Note: 1. TA = 25°C, VCC = 5V.
Parameter Min
Typ
(1)
Typical after
100k W/E Cycles
(1)
Max Unit
Chip Erase (All bits in the memory set to ‘0’) 0.6 0.6 sec
Chip Erase 1.3 1.3 6 sec
Block Erase (32 KWords) 0.6 0.6 4 sec
Program 8 8 150 µs
Chip Program 0.6 0.6 2.5 sec
Program/Erase Cycles (per Block) 100,000 cycles
Page 9
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M29F102BB
STATUS REGISTER
Bus Read operations from any address always
read the Status Register during Program and
Erase operations. It is also read during Erase Suspend when an address within a block being erased
is accessed.
The bits in the Status Register are summarized in
Table 7, Status Register Bits.
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program/Erase
Controller has successfully completed its operation or if it has responded to an Erase Suspend.
The Data Polling Bit is output on DQ7 when the
Status Register is read.
During Program operations the Data Polling Bit
outputs the complement of the bit being programmed to DQ7. After successful completion of
the Program operation the memory returns to
Read mode and Bus Read operations from the address just programmed o utput DQ7, not its complement.
During Er ase ope rations the Data Polling Bit ou t-
puts ’0’, the complement of the erased state of
DQ7. After successful completion of the Erase operation the memory returns to Read Mode.
In Erase Suspend mode the Data Polling Bit will
output a ’1’ during a Bus Read operation within a
block being erased. The Data Polling Bit will
change from a ’0’ to a ’1’ when the Program/Erase
Controller has suspended the Erase operation.
Figure 4, Data Polling Flowchart, gives an example of how to use the Data Polling Bit. A Valid Address is the address being programmed or an
address within the block being erased.
Toggle Bit (DQ6). The Togg le Bit can be used to
identify whether the Program/Erase Controller has
successfully completed its operation or if it has responded to an Erase Suspen d. The Toggle Bit is
output on DQ6 when the Status Register is read.
During Program and Erase operations the Toggle
Bit changes from ’0’ to ’ 1’ to ’ 0’, et c., with su ccessive Bus Read operations at any address. After
successful completion of the operation the memory returns to Read mode.
During Erase Suspend mode the Toggle Bit will
output when addressing a cell within a block being
erased. The Toggle Bit will stop toggling when the
Program/Erase Controller has suspended the
Erase operation.
Figure 5, Data Toggle Flowchart, g ives an example of how to use the Data Toggle Bit.
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program/Erase
Controller. The Error B it is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to
write the correct data to the memory. If the Error
Bit is set a Read/Rese t command must be iss ued
before other commands are issued. The E rror bit
is output on DQ5 when the Status Register is read.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’ and attempting to do so may
or may not set DQ5 at ‘1’. In both cases, a successive Bus Read operation will show the bit is still ‘0’.
One of the Erase commands must be used to set
all the bits in a block or in the whole memory from
’0’ to ’1’.
Table 7. Status Register Bits
Note: Unspecif i ed data bits sh ould be ignored.
Operation Address DQ7 DQ6 DQ5 DQ3 DQ2
Program Any Address DQ7
Toggle 0 ––
Program During Erase Suspend Any Address DQ7
Toggle 0 – –
Program Error Any Address DQ7
Toggle 1 – –
Chip Erase Any Address 0 Toggle 0 1 Toggle
Block Erase before timeout
Erasing Block 0 Toggle 0 0 Toggle
Non-Erasing Block 0 Toggle 0 0 No Toggle
Block Erase
Erasing Block 0 Toggle 0 1 Toggle
Non-Erasing Block 0 Toggle 0 1 No Toggle
Erase Suspend
Erasing Block 1 No Toggle 0 – Toggle
Non-Erasing Block Data read as normal
Erase Error
Good Block Address 0 Toggle 1 1 No Toggle
Faulty Block Address 0 Toggle 1 1 Toggle
Page 10
M29F102BB
10/21
Figure 4. Dat a Po ll i ng Fl o wc h a rt
READ DQ5 & DQ7
at VALID ADDRESS
START
READ DQ7
at VALID ADDRESS
FAIL PASS
AI03598
DQ7
=
DATA
YES
NO
YES
NO
DQ5
= 1
DQ7
=
DATA
YES
NO
Figure 5. Dat a Toggle Flow cha rt
READ DQ6
START
READ DQ6
TWICE
FAIL PASS
AI01370B
DQ6
=
TOGGLE
NO
NO
YES
YES
DQ5
= 1
NO
YES
DQ6
=
TOGGLE
READ
DQ5 & DQ6
Erase Timer Bit (DQ3). The Erase Timer Bit can
be used to identify the start of Program/Erase
Controller operation during a Block Erase command. Once the Program/Erase Controller starts
erasing the Erase Timer Bit is set to ’1’. Before the
Program/Erase Controller starts the Erase Timer
Bit is set to ’0’ and additional block s to be erased
may be written to the Command Interface. The
Erase Timer Bit is output on DQ3 when the Status
Register is read.
Alternative Toggle Bit (DQ2). The Alternative
Toggle Bit can be used to monitor the Program/
Erase controller during Erase operations. The Alternative Toggle Bit is output on DQ2 when the
Status Register is read.
During Chip Erase and Block Erase operations the
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations from addresses
within the blocks being erased. Once t he operatio n
completes the memory returns to Read mode.
During Erase Suspend the Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive
Bus Read operations from addresses within the
blocks being erased. Bus Read operations to addresses within blocks not being erased will ou tput
the memory cell data as if in Read mode.
After an Erase operation that c auses t he Error Bit
to be set the Alternative Toggle Bit can be used to
identify which block or blocks have caused the error. The Alternative Toggle Bit changes from ’0’ to
’1’ to ’0’, etc. with successive Bus Re ad Operations from addresses within blocks that have not
erased correctly. The Alternative Togg le Bit does
not change if the addressed block has erased correctly.
Page 11
11/21
M29F102BB
Figure 6. AC Testing Input Output Waveform
AI01417
3V
0V
1.5V
Figure 7. AC Te s ting Load Circ uit
AI02979
1.3V
OUT
CL = 30pF
CL includes JIG capacitance
3.3kΩ
1N914
DEVICE
UNDER
TEST
Table 9. Capacitance
(T
A
= 25 °C, f = 1 MHz)
Note: Sampled only, not 100% tested.
Symbol Parameter Test Condition Min Max Unit
C
IN
Input Capacitance
V
IN
= 0V
6pF
C
OUT
Output Capacitance
V
OUT
= 0V
12 pF
Table 8. AC Measurement Conditions
Load Capacitance (CL)
30pF
Input Rise and Fall Times
≤
10ns
Input Pulse Voltages 0 to 3V
Input and Output Timing Ref. Voltages 1.5V
Page 12
M29F102BB
12/21
Table 10. DC Characteristics
(T
A
= 0 to 70°C)
Note: 1. Excludi ng the RP i nput.
2. Sampled only, not 100% tested.
3. T
A
= 25°C, VCC = 5V
Symbol Parameter Test Condition Min
Typ
(3)
Max Unit
I
LI
(1)
Input Leakage Current
0V ≤ V
IN
≤ V
CC
±1 µA
I
LR1
RP Leakage Current High
RP
= V
CC
±1 µA
I
LR2
RP Leakage Current Low
RP
= V
SS
–0.2 –10 µA
I
LO
Output Leakage Current
0V ≤ V
OUT
≤ V
CC
±1 µA
I
CC1
Supply Current (Read)
E
= VIL, G = VIH, f = 6MHz
620mA
I
CC2
Supply Current (Standby)
E
= VCC ±0.2V,
RP
= VCC ±0.2V
30 100 µA
I
CC3
(2)
Supply Current (Program/
Erase)
Program/Erase
Controller active
20 mA
V
IL
Input Low Voltage –0.5 0.8 V
V
IH
Input High Voltage 2
V
CC
+0.5
V
V
OL
Output Low Voltage
I
OL
= 5.8mA
0.45 V
V
OH
Output High Voltage
I
OH
= –100µA VCC –0.4
V
V
ID
Identification Voltage 11.5 12.5 V
I
ID
Identification Current
A9 = V
ID
100 µA
V
LKO
(2)
Program/Erase Lockout
Supply Voltage
3.2 4.2 V
Page 13
13/21
M29F102BB
Figure 8. Read Mode AC Waveforms
AI02980
tAVAV
tAVQV tAXQX
tELQX tEHQZ
tGLQV
tGLQX tGHQX
VALID
A0-A15
G
DQ0-DQ15
E
tELQV tEHQX
tGHQZ
VALID
Table 11. Read AC Characteristics
(TA = 0 to 70°C)
Note: 1. This timing refers to a Load Capacitance (CL) of 30pF. If CL is higher, add 1.5ns for eac h extra 10pF.
2. Sampled only, not 100% tested.
Symbol Alt Parameter Test Condition
M29F102BB
Unit
35 45 50 / 55 70
t
AVAV
(1)
t
RC
Address Valid to Next
Address Valid
E
= VIL,
G
= V
IL
Min 35 45 50 70 ns
t
AVQV
(1)
t
ACC
Address Valid to Output
Valid
E
= VIL,
G
= V
IL
Max 35 45 50 70 ns
t
ELQX
(2)
t
LZ
Chip Enable Low to Output
Transition
G
= V
IL
Min 0 0 0 0 ns
t
ELQV
(1)
t
CE
Chip Enable Low to Output
Valid
G
= V
IL
Max 35 45 50 70 ns
t
GLQX
(2)
t
OLZ
Output Enable Low to
Output Tran sition
E
= V
IL
Min 0 0 0 0 ns
t
GLQV
(1)
t
OE
Output Enable Low to
Output Valid
E
= V
IL
Max 20 20 20 30 ns
t
EHQZ
(2)
t
HZ
Chip Enable High to Output
Hi-Z
G
= V
IL
Max 15 15 18 20 ns
t
GHQZ
(2)
t
DF
Output Enable High to
Output Hi-Z
E
= V
IL
Max 15 15 18 20 ns
t
EHQX
t
GHQX
t
AXQX
t
OH
Chip Enable, Output Enable
or Address Transition to
Output Tran sition
Min 0 0 0 0 ns
Page 14
M29F102BB
14/21
Figure 9. Write AC Waveforms, Write Enable Control led
AI02119
E
G
W
A0-A15
DQ0-DQ15
VALID
VALID
V
CC
tVCHEL
tWHEH
tWHWL
tELWL
tAVWL
tWHGL
tWLAX
tWHDX
tAVAV
tDVWH
tWLWHtGHWL
Table 12. Write AC Characteristics, Write Enable Controlled
(T
A
= 0 to 70 °C)
Symbol Alt Parameter
M29F102BB
Unit
35 45 50 / 55 70
t
AVAV
t
WC
Address Valid to Next Address Valid Min 35 45 50 70 ns
t
ELWL
t
CS
Chip Enable Low to Write Enable Low Min 0000ns
t
WLWH
t
WP
Write Enable Low to Write Enable High Min 35 40 40 45 ns
t
DVWH
t
DS
Input Valid to Write Enable High Min 20 25 25 30 ns
t
WHDX
t
DH
Write Enable High to Input Transition Min 0000ns
t
WHEH
t
CH
Write Enable High to Chip Enable High Min 0000ns
t
WHWL
t
WPH
Write Enable High to Write Enable Low Min 20 20 20 20 ns
t
AVWL
t
AS
Address Valid to Write Enable Low Min 0000ns
t
WLAX
t
AH
Write Enable Low to Address Transition Min 35 40 40 45 ns
t
GHWL
Output Enable High to Write Enable Low Min 0000ns
t
WHGL
t
OEH
Write Enable High to Output Enable Low Min 0000ns
t
VCHEL
t
VCSVCC
High to Chip Enable Low
Min 50 50 50 50 µs
Page 15
15/21
M29F102BB
Table 13. Write AC Characteristics, Chip Enable Controlled
(T
A
= 0 to 70 °C)
Symbol Alt Parameter
M29F102BB
Unit
35 45 50 / 55 70
t
AVAV
t
WC
Address Valid to Next Address Valid Min 35 45 50 70 ns
t
WLEL
t
WS
Write Enable Low to Chip Enable Low Min 0000ns
t
ELEH
t
CP
Chip Enable Low to Chip Enable High Min 35 40 40 45 ns
t
DVEH
t
DS
Input Valid to Chip Enable High Min 20 25 25 30 ns
t
EHDX
t
DH
Chip Enable High to Input Transition Min 0000ns
t
EHWH
t
WH
Chip Enable High to Write Enable High Min 0000ns
t
EHEL
t
CPH
Chip Enable High to Chip Enable Low Min 20 20 20 20 ns
t
AVEL
t
AS
Address Valid to Chip Enable Low Min 0000ns
t
ELAX
t
AH
Chip Enable Low to Address Transition Min 35 40 40 45 ns
t
GHEL
Output Enable High Chip Enable Low Min 0000ns
t
EHGL
t
OEH
Chip Enable High to Output Enable Low Min 0000ns
t
VCHWL
t
VCSVCC
High to Write Enable Low
Min 50 50 50 50 µs
Figure 10. Write AC Waveforms, Chip Enable Controlled
AI02120
E
G
W
A0-A15
DQ0-DQ15
VALID
VALID
V
CC
tVCHWL
tEHWH
tEHEL
tWLEL
tAVEL
tEHGL
tELAX
tEHDX
tAVAV
tDVEH
tELEHtGHEL
Page 16
M29F102BB
16/21
Table 14. Reset/Block Temporary Unprotect AC Characteristics
(T
A
= 0 to 70°C)
Note: 1. Sampled only, not 100% tested.
Symbol Alt Parameter
M29F102BB
Unit
50 70 90
t
PHWL
(1)
t
PHEL
t
PHGL
(1)
t
RH
RP High to Write Enable Low, Chip Enable
Low, Output Enable Low
Min 50 50 50 ns
t
PLPX
t
RP
RP Pulse Width Min 500 500 500 ns
t
PLYH
(1)
t
READY
RP Low to Read Mode Max 10 10 10 µs
t
PHPHH
(1)
t
VIDR
RP Rise Time to V
ID
Min 500 500 500 ns
Figure 11. Reset/Block Temporary Unprotect AC Waveforms
AI02943
W,
RP
tPLPX
tPHWL, tPHEL, tPHGL
tPLYH
tPHPHH
E, G
Page 17
17/21
M29F102BB
Table 15. Ordering Information Scheme
Note: The last two characters o f the ordering code m ay be replaced by a letter code for preprogram m ed
parts, otherwise devices are shipped from the factory with the memory content bits erased to ‘1’.
For a list of available options (Speed, Pac kage, etc...) or for furthe r information on any aspect of this device, please contact the ST Sales Office nearest to you.
Example: M29F102BB 50 N 1 T
Device Type
M29
Operating Voltage
F = V
CC
= 5V ± 10%
Device Function
102BB = 1 Mbit (64Kb x16), Bottom Boot Block
Speed
35 = 35ns
45 = 45 ns
50 = 50 ns
55 = 55 ns
70 = 70 ns
Package
K = PLCC44
N = TSOP40:10 x 14mm
Temperature Range
1 = 0 to 70 °C
Option
T = Tape & Reel Packing
Page 18
M29F102BB
18/21
Table 16. Revision History
Date Revision Details
July 1999 First Issue
07/28/00
New document template
Status Register bit DQ5 clarification
Data Polling Flowchart diagram change (Figure 4)
Data Toggle Flowchart diagram change (Figure 5)
Page 19
19/21
M29F102BB
Figure 12. PLCC44 - 44 lead Plastic Leaded Chip Carrier, Package Outline
Drawing is not to scale.
PLCC
D
Ne E1 E
1 N
D1
Nd
CP
B
D2/E2
e
B1
A1
A
R
0.51 (.020)
1.14 (.045)
F
A2
Table 17. PLCC44 - 44 lead Plastic Leaded Chip Carrier, Package Mechanical Data
Symbol
mm inches
Typ Min Max Typ Min Max
A 4.20 4.70 0.1654 0.1850
A1 2.29 3.04 0.0902 0.1197
A2 – 0.51 – 0 .0201
B 0.33 0.53 0.0130 0.0209
B1 0.66 0.81 0.0260 0.0319
D 17.40 17.65 0.6850 0.6949
D1 16.51 16.66 0.6500 0.6559
D2 14.99 16.00 0.5902 0.6299
E 17.40 17.65 0.6850 0.6949
E1 16.51 16.6 6 0.6500 0.6559
E2 14.99 16.0 0 0.5902 0.6299
e 1.27 – – 0.0500 – –
F 0.00 0.25 0.0000 0.0098
R 0.89 – – 0.0350 – –
N44 44
Nd 11 11
Ne 11 11
CP 0.10 0.0039
Page 20
M29F102BB
20/21
Figure 13. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 14mm, Package Outline
Drawing is not to scale.
TSOP-a
D1
E
1 N
CP
B
e
A2
A
N/2
D
DIE
C
LA1 α
Table 18. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 14mm, Package Mechanical Data
Symbol
mm in ches
Typ Min Max Typ Min Max
A 1.20 0.0472
A1 0.05 0.15 0.0020 0.0059
A2 0.95 1.05 0.0374 0.0413
B 0.17 0.27 0.0067 0 .0106
C 0.10 0.21 0.0039 0.0083
D 13.80 14.20 0.5433 0 .5591
D1 12.30 12.50 0.4843 0.4921
E 9.90 10.1 0 0.3898 0.3976
e 0.50 – – 0.0197 – –
L 0.50 0.70 0.0197 0.0276
α
0° 5° 0° 5°
N40 40
CP 0.10 0.0039
Page 21
21/21
M29F102BB
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or otherwise under any patent or patent rights of STMi croelectr onics. Specifications mentioned in thi s publicati on are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
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