Datasheet M29F080A90N6, M29F080A90N1, M29F080A90M6, M29F080A Datasheet (SGS Thomson Microelectronics)
Page 1
1/21April 2000
M29F080A
8 Mbit (1Mb x8, Uniform Block) Single Supply Flash Memory
■ SINGLE 5V±10% SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS
■ ACCESS TIME: 70ns
■ PROGRAMMING TIME
–8µs by Byte typical
■ 16 UNIFORM 64 Kbyte MEMORY BLOCKS
■ PROGRAM/ERASE CONTROLLER
– Embedded Byte Program algorithm
– Embedded Multi-Block/Chip Erase algorithm
– Status Register Polling and Toggle Bits
– Ready/Busy Output Pin
■ ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
■ TEMPORARY BLOCK UNPROTECTION
MODE
■ LOW POWER CONSUMPTION
– Standby and Automatic Standby
■ 100,000 PROGRAM/ERASE CYCLES per
BLOCK
■ 20 YEARS DATA RETENTION
– Defectivity below 1 ppm/year
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: F1h
TSOP40 (N)
10 x 20mm
SO44 (M)
44
1
Figure 1. Logic Diagram
AI00501C
20
A0-A19
W
DQ0-DQ7
V
CC
M29F080A
E
V
SS
8
G
RP
RB
Page 2
M29F080A
2/21
Figure 2. TSOP Connections
A1
DQ1
DQ2A10
A4
A2
A7
A6
A14
NC
A17
A18
DQ7
A13
A19
A0
W
DQ5
DQ3
V
SS
V
CC
DQ4
DQ6
A12
E
RP
A11
NC
V
CC
AI00520B
M29F080A
10
1
11
20 21
30
31
40
A3
A15
A16 G
RB
A8
A9
V
SS
DQ0
NC
A5
Figure 3. SO Connections
A2
A1
A0
A6
NC
NC
A3
A5
A4
A17
NC
A18
A19
W
A16
NC
NC
NC
DQ6DQ2
V
SS
V
CC
V
SS
DQ4
G
A13
E
NC
A7
RP
V
CC
A10
AI00521B
M29F080A
8
2
3
4
5
6
7
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
2322
20
19
18
17DQ0
DQ1
A9
A8
RB
DQ7
44
39
38
37
36
35
34
33
A15
A14
DQ3
21
DQ5
40
43
1
42
41
A11 A12
Table 1. Signal Names
A0-A19 Address Inputs
DQ0-DQ7 Data Inputs/Outputs
E Chip Enable
G Output Enable
W Write Enable
RP Reset/Block Temporary Unprotect
RB Ready/Busy Output
V
CC
Supply Voltage
V
SS
Ground
NC Not Connected Internally
SUMMARY DESCRIPTION
The M29F080A is an 8 Mbit (1Mb x8) non-volatile
memory that can be read, erased and reprogrammed. These operations can be performedus-
ing a single 5V supply. On power-up the memory
defaults to its Read mode where it can be read in
the same way as a ROM or EPROM.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Blocks can be
protected in groups to prevent accidental Program
or Erase commands from modifying the memory.
Program and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controllersimplifiestheprocessof
programming or erasing the memory by taking
care of all of the special operations that are required to update the memory contents. The end of
a program or eraseoperation can be detected and
any error conditions identified. The command set
required to control the memory is consistent with
JEDEC standards.
Chip Enable, Output Enableand Write Enable signals control the bus operation of the memory.
They allow simple connection to most microprocessors, often without additional logic.
The memory is offered in a TSOP40 (10 x 20mm)
and SO44 packages and it is supplied with all the
bits erased (set to ’1’).
Page 3
3/21
M29F080A
SIGNAL DESCRIPTIONS
See Figure 1, Logic Diagram, and Table 1, Signal
Names, forabrief overview of the signals connected to this device.
Address Inputs (A0-A19). The Address Inputs
select the cells in the memory array to access during Bus Read operations. During BusWrite operations they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs output thedatastoredatthe selected
address during a Bus Read operation. During Bus
Write operations they represent the commands
sentto theCommandInterfaceof the internal state
machine.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is
High, VIH, all other pins are ignored.
Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Command Interface.
Reset/Block TemporaryUnprotect (RP). The Reset/Block Temporary Unprotect pin can be usedto
apply a Hardware Reset to the memory or to temporarily unprotect all blocks that have been protected.
Table 2. Absolute Maximum Ratings
(1)
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SUREProgram andotherrelevant quality documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.
Symbol Parameter Value Unit
T
A
Ambient Operating Temperature (Temperature Range Option 1) 0 to 70 °C
Ambient Operating Temperature (Temperature Range Option 6) –40 to 85 °C
Ambient Operating Temperature (Temperature Range Option 3) –40 to 125 °C
T
BIAS
Temperature Under Bias –50 to 125 °C
T
STG
Storage Temperature –65 to 150 °C
V
IO
(2)
Input or Output Voltage –0.6 to 6 V
V
CC
Supply Voltage –0.6 to 6 V
V
ID
Identification Voltage –0.6 to 13.5 V
Table 3. Uniform Block Addresses, M29F080A
#
Size
(Kbytes)
Address Range
Protection
Group
15 64 F0000h-FFFFFh
7
14 64 E0000h-EFFFFh
13 64 D0000h-DFFFFh
6
12 64 C0000h-CFFFFh
11 64 B0000h-BFFFFh
5
10 64 A0000h-AFFFFh
9 64 90000h-9FFFFh
4
8 64 80000h-8FFFFh
7 64 70000h-7FFFFh
3
6 64 60000h-6FFFFh
5 64 50000h-5FFFFh
2
4 64 40000h-4FFFFh
3 64 30000h-3FFFFh
1
2 64 20000h-2FFFFh
1 64 10000h-1FFFFh
0
0 64 00000h-0FFFFh
Page 4
M29F080A
4/21
A 0.1µF capacitor should be connected between
the VCCSupply Voltage pin and the VSSGround
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, I
CC4
.
VSSGround. The VSSGroundis the reference for
all voltage measurements.
BUS OPERATIONS
There arefive standard busoperations that control
the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby. See
Table 4, Bus Operations, for asummary. Typically
glitches of less than 5ns on Chip Enable or Write
Enable are ignored by the memory and do not affect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs, applying a Low signal, VIL, to Chip Enable
and Output Enable and keeping Write Enable
High, VIH. The Data Inputs/Outputs will output the
value, see Figure 8, Read Mode AC Waveforms,
and Table 11, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Address Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable
or WriteEnable, whichever occurs first. OutputEnable must remain High, VIH, during the whole Bus
Write operation. See Figures 9 and 10, Write AC
Waveforms, and Tables 12 and 13, Write AC
Characteristics, for details of the timing requirements.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, VIL, for at least
t
PLPX
. After Reset/Block Temporary Unprotect
goes High, VIH, the memory will be ready for Bus
Read and Bus Write operations after t
PHEL
or
t
RHEL
, whicheveroccurs last.See the Ready/Busy
Output section, Table 14 and Figure 11, Reset/
Temporary Unprotect AC Characteristics for more
details.
Holding RP at VIDwill temporarily unprotect the
protected blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from VIHtoVIDmust be slower than
t
PHPHH
.
Ready/Busy Output (RB). The Ready/Busy pin
is anopen-drain outputthat can be used toidentify
when the memory array can be read. Ready/Busy
is high-impedanceduring Read mode, Auto Select
mode and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy becomes high-impedance. See Table 14 and Figure
11, Reset/Temporary Unprotect AC Characteristics.
During Program or Erase operations Ready/Busy
is Low, VOL. Ready/Busy will remain Low during
Read/Reset commands or Hardware Resets until
the memory is ready to enter Read mode.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
VCCSupply Voltage. The VCCSupply Voltage
supplies the power for all operations (Read, Program, Erase etc.).
The CommandInterface is disabled when the V
CC
Supply Voltage is less than the Lockout Voltage,
V
LKO
. This prevents Bus Write operations from accidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memory contents being altered will be invalid.
Page 5
5/21
M29F080A
Table 4. Bus Operations
Note: X = VILor VIH.
Operation E G W Address Inputs
Data
Inputs/Outpu ts
Bus Read
V
IL
V
IL
V
IH
Cell Address Data Output
Bus Write
V
IL
V
IH
V
IL
Command Address Data Input
Output Disable
XV
IH
V
IH
XHi-Z
Standby
V
IH
XXX Hi-Z
Read Manufacturer
Code
V
IL
V
IL
V
IH
A0 = VIL,A1=VIL,A9=VID,
Others V
IL
or V
IH
20h
Read Device Code
V
IL
V
IL
V
IH
A0 = VIH,A1=VIL,A9=VID,
Others V
IL
or V
IH
F1h
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, VIH.
Standby. When Chip Enable is High, VIH, the
Data Inputs/Outputs pins are placed in the highimpedance state and the Supply Current is reduced to the Standby level.
When Chip Enable is at VIHthe Supply Current is
reduced to the TTL Standby Supply Current, I
CC2
.
To further reduce the Supply Current to the CMOS
Standby Supply Current, I
CC3
, ChipEnable should
be held within VCC± 0.2V. For Standby current
levels see Table 10, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, I
CC4
, for Program or Eraseoperations un-
til the operation completes.
AutomaticStandby. If CMOS levels (VCC± 0.2V)
are usedto drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is reduced to the Standby Supply Current, I
CC3
. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications.
They require VIDto be applied to some pins.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Table 4, Bus Operations.
Block Protection and BlocksUnprotection. Blocks
can be protected in groups against accidental Program or Erase. See Table 3, Block Addresses, for
details of which blocks must be protected together
as a group. Protected blocks can be unprotected
to allow data to be changed. Block Protection and
Block Unprotection operations must only be performed on programming equipment.
For further information refer to Application Note
AN1122, Applying Protection and Unprotection to
M29 Series Flash.
Page 6
M29F080A
6/21
COMMAND INTERFACE
All Bus Write operations to the memory are interpreted by the Command Interface. Commands
consist of one or more sequential Bus Write operations. Failure to observe a validsequence of Bus
Write operations will result in the memory returning toRead mode. In this case, after at least 50ns,
an address transition or Chip Enable going Low is
required before reading correct data. The long
command sequences are imposed to maximize
data security.
The commands are summarized in Table 5, Commands. Refer to Table 5 in conjunction with the
text descriptions below.
Read/Reset Command. The Read/Reset command returnsthe memory to its Read mode where
it behaves like a ROM or EPROM. It also resets
the errors in the Status Register. Either one or
three Bus Write operations can be used to issue
the Read/Reset command.
If the Read/Reset command is issued during a
Block Eraseoperation or following a Programming
or Eraseerror thenthe memory will takeup to10µs
to abort. During the abort period no valid data can
be read from the memory. Issuing a Read/Reset
command during a Block Erase operation will
leave invalid data in the memory.
Auto Select Command. The Auto Select command is used to read the Manufacturer Code, the
Device Code and the Block Protection Status.
Three consecutive Bus Write operations are required to issue the Auto Select command. Once
the Auto Select command is issued the memory
remains in Auto Select mode until another command is issued.
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = VILand A1 = VIL. The otheraddress bits
may be set to either VILor VIH. The Manufacturer
Code for STMicroelectronics is 20h.
The Device Code can be read using a Bus Read
operation with A0 = VIHand A1 = VIL. The other
address bits may be set to either VILor VIH. The
Device Code for the M29F080A is F1h.
The Block Protection Status of each block can be
read using a Bus Read operation with A0 = VIL,
A1 = VIH, and A16-A19 specifying the address of
the block. The other address bits may be set toeither VILor VIH. If the addressed block is protected
then 01his outputon the DataInputs/Outputs, otherwise 00h is output.
Program Command. The Program command
can be used to program a value to one address in
the memory array at a time. The command requires fourBus Writeoperations, the finalwrite operation latches the address and datain the internal
state machine and starts the Program/Erase Controller.
If the address falls in a protected block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.
During the program operation the memory will ignore all commands. It is not possible to issue any
command to abort or pause the operation. Typical
program times are given in Table 6. Bus Read operations during the program operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’. One of the Erase Commands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.
Page 7
7/21
M29F080A
Table 5. Commands
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.
All values in the table are in hexadecimal.
The Command Interface only uses address bits A0-A10 to verify the commands, the upper address bits are Don’t Care.
Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued.
Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.
Program, Chip Erase, Block Erase. After these commands read the Status Register until the Program/Erase Controller completes and the
memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional Bus WriteOperations until the Timeout
Bit is set.
Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue AutoSelect and Program commands
on non-erasing blocks as normal.
Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/
Erase Controller completes and the memory returns to Read Mode.
Command
Length
Bus Write Operations
1st 2nd 3rd 4th 5th 6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read/Reset
1X F0
3 555 AA 2AA 55 X F0
Auto Select 3 555 AA 2AA 55 555 90
Program 4 555 AA 2AA 55 555 A0 PA PD
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30
Chip Erase Command. The Chip Erase command can beused to erasethe entire chip. Six Bus
Write operations are required to issue the Chip
Erase Command and start the Program/Erase
Controller.
If any blocks are protected then these are ignored
and all the other blocks are erased. If all of the
blocks are protected the ChipErase operation appears tostart but willterminate within about 100µs,
leaving the data unchanged. No error condition is
given when protected blocks are ignored.
During the erase operation the memory will ignore
all commands. It is not possible to issue any command to abort the operation. Typical chip erase
times are given in Table 6. All Bus Read operations during the Chip Erase operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the Chip Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode.
TheChip Erase Command sets allof the bits inunprotected blocks of the memory to ’1’. All previous
data is lost.
Page 8
M29F080A
8/21
Block Erase Command. The Block Erase command can be used to erase a list of one or more
blocks. Six Bus Write operations are required to
select the first block in the list. Each additional
block in the list can be selected by repeating the
sixth Bus Write operation using the address of the
additional block. The Block Erase operation starts
the Program/Erase Controller about 50µs after the
last Bus Write operation. Once the Program/Erase
Controller starts it is not possible to select any
more blocks. Each additional block must therefore
be selectedwithin 50µs of the last block.The 50µs
timer restartswhen an additional block isselected.
The Status Register can be read after the sixth
Bus Write operation. See the Status Register for
details on how to identify if the Program/Erase
Controller has started the Block Erase operation.
If any selected blocks areprotected thenthese are
ignored and all the other selected blocks are
erased. If all of the selected blocks are protected
the Block Erase operation appears to start but will
terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored.
During the Block Erase operation the memory will
ignore all commands except the Erase Suspend
and Read/Reset commands. Typical block erase
times are given in Table 6. All Bus Read operations during the Block Erase operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After theBlock Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to reset the error condition and return to Read mode.
The Block Erase Command sets all of the bits in
the unprotected selected blocks to ’1’. All previous
data in the selected blocks is lost.
Erase Suspend Command. The Erase Suspend
Command may be used to temporarily suspend a
Block Erase operation and return the memory to
Read mode. The command requires one Bus
Write operation.
The Program/Erase Controller will suspend within
15µs of the Erase Suspend Command being issued. Once the Program/Erase Controller has
stopped the memory will be set toRead mode and
the Erase will be suspended. If the Erase Suspend
command is issued during the period when the
memory is waiting for an additional block (before
the Program/Erase Controller starts) then the
Erase is suspended immediately and will start immediately when the Erase Resume Command is
issued. It will not be possible to select any further
blocks for erasure after the Erase Resume.
During Erase Suspend it is possible to Read and
Program cells in blocks that are not being erased;
both Read and Program operations behave as
normal on these blocks. Reading from blocks that
are being erased will output the Status Register.It
is also possible to enter theAuto Select mode: the
memorywill behaveas in the Auto Select mode on
all blocks until a Read/Reset command returns the
memory to Erase Suspend mode.
Erase Resume Command. The Erase Resume
command must be used to restart the Program/
Erase Controller from Erase Suspend. An erase
can be suspended and resumed more than once.
Table 6. Program, Erase Times and Program, Erase Endurance Cycles
(TA= 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)
Note: 1. TA=25°C, VCC=5V.
Parameter Min
Typ
(1)
Typical after
100k W/E Cycles
(1)
Max Unit
Chip Erase (All bits in the memory set to ‘0’) 3 3 sec
Chip Erase 8 8 30 sec
Block Erase (64 Kbytes) 0.6 0.6 4 sec
Program 8 8 150 µs
Chip Program 9 9 35 sec
Program/Erase Cycles (per Block) 100,000 cycles
Page 9
9/21
M29F080A
STATUS REGISTER
Bus Read operations from any address always
read the Status Register during Program and
Erase operations. It isalso read during Erase Suspend when anaddress within ablock beingerased
is accessed.
The bits in the Status Register are summarized in
Table 7, Status Register Bits.
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program/Erase
Controller has successfully completed its operation or if it has responded to an Erase Suspend.
The Data Polling Bit is output on DQ7 when the
Status Register is read.
During Program operations the Data Polling Bit
outputs the complement of the bit being programmed to DQ7. After successful completion of
the Program operation the memory returns to
Read mode and Bus Read operationsfrom the address just programmed output DQ7, not its complement.
During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state of
DQ7. After successful completion of the Erase operation the memory returns to Read mode.
In Erase Suspend mode the Data Polling Bit will
output a ’1’ during a Bus Read operation within a
block being erased. The Data Polling Bit will
change from a ’0’ to a ’1’ when the Program/Erase
Controller has suspended the Erase operation.
Figure 4, Data Polling Flowchart, gives an example of how to use the Data Polling Bit. A Valid Ad-
dress is the address being programmed or an
address within the block being erased.
Toggle Bit (DQ6). The Toggle Bit can be used to
identify whether the Program/Erase Controller has
successfully completed its operation or if it has responded to an Erase Suspend. The Toggle Bit is
output on DQ6 when the Status Register is read.
During Program and Erase operations the Toggle
Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations at any address. After
successful completion of the operation the memory returns to Read mode.
During Erase Suspend mode the Toggle Bit will
output when addressing a cell within a block being
erased. The Toggle Bit will stop toggling when the
Program/Erase Controller has suspended the
Erase operation.
Figure 5, Data Toggle Flowchart, gives an example of how to use the Data Toggle Bit.
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program/Erase
Controller. The Error Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to
write the correct data to the memory. If the Error
Bit is set a Read/Reset command must be issued
before other commands are issued. The Error bit
is output onDQ5 whenthe Status Registeris read.
Note that the Program command cannot change a
bit setat ’0’ back to ’1’ and attempting to do so may
or may not set DQ5 at ’1’. In both cases, a successive Bus Read operation will show the bit is still ’0’.
One of the Erase commands must be used to set
all the bits in a block or in the whole memory from
’0’ to ’1’.
Table 7. Status Register Bits
Note: Unspecified data bits should be ignored.
Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB
Program Any Address DQ7 Toggle 0 – – 0
Program During Erase
Suspend
Any Address DQ7 Toggle 0 – – 0
Program Error Any Address DQ7 Toggle 1 – – 0
Chip Erase Any Address 0 Toggle 0 1 Toggle 0
Block Erase before
timeout
Erasing Block 0 Toggle 0 0 Toggle 0
Non-Erasing Block 0 Toggle 0 0 No Toggle 0
Block Erase
Erasing Block 0 Toggle 0 1 Toggle 0
Non-Erasing Block 0 Toggle 0 1 No Toggle 0
Erase Suspend
Erasing Block 1 No Toggle 0 – Toggle 1
Non-Erasing Block Data read as normal 1
Erase Error
Good Block Address 0 Toggle 1 1 No Toggle 0
Faulty Block Address 0 Toggle 1 1 Toggle 0
Page 10
M29F080A
10/21
Figure 4. Data Polling Flowchart
READ DQ5 &
DQ7
at VALID ADDRESS
START
READ
DQ7
at VALID ADDRESS
FAIL PASS
AI03598
DQ7
=
DATA
YES
NO
YES
NO
DQ5
=1
DQ7
=
DATA
YES
NO
Figure 5. Data Toggle Flowchart
READ DQ6
START
READ
DQ6
TWICE
FAIL PASS
AI01370B
DQ6
=
TOGGLE
NO
NO
YES
YES
DQ5
=1
NO
YES
DQ6
=
TOGGLE
READ
DQ5 & DQ6
Erase Timer Bit (DQ3). The Erase Timer Bit can
be used to identify the start of Program/Erase
Controller operation during a Block Erase command.
Once the Program/Erase Controller starts erasing
the Erase Timer Bit is set to ’1’. Before the Program/Erase Controller starts theErase Timer Bit is
set to ’0’ and additional blocks to be erased may
be written to the Command Interface. The Erase
Timer Bit is output on DQ3 when the Status Register is read.
Alternative Toggle Bit (DQ2). The Alternative
Toggle Bit can be used to monitor the Program/
Erase controller during Erase operations. The Alternative Toggle Bit is output on DQ2 when the
Status Register is read.
During ChipErase and Block Erase operations the
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations from addresses
within the blocks being erased. Once the operation
completes the memory returns to Read mode.
During Erase Suspend the Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive
Bus Read operations from addresses within the
blocks being erased. Bus Read operations to addresses within blocks not being erased will output
the memory cell data as if in Read mode.
After an Erase operation that causes the Error Bit
to be set the Alternative Toggle Bit can be used to
identify whichblock or blocks have caused the error. The Alternative Toggle Bit changes from ’0’ to
’1’ to ’0’, etc. with successive Bus Read Operations from addresses within blocks that have not
erased correctly. The Alternative Toggle Bit does
not change if the addressed block has erased correctly.
Page 11
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M29F080A
Figure 6. AC Testing Input Output Waveform
AI01275B
3V
High Speed
0V
1.5V
2.4V
Standard
0.45V
2.0V
0.8V
Figure 7. AC Testing Load Circuit
AI03027
1.3V
OUT
CL= 30pF or100pF
CLincludes JIG capacitance
3.3kΩ
1N914
DEVICE
UNDER
TEST
Table 9. Capacitance
(TA=25°C, f = 1 MHz)
Note: Sampled only, not 100% tested.
Symbol Parameter Test Condition Min Max Unit
C
IN
Input Capacitance
V
IN
=0V
6pF
C
OUT
Output Capacitance
V
OUT
=0V
12 pF
Table 8. AC Measurement Conditions
Parameter
M29F080A
70 90 / 120
ACTest Conditions High Speed Standard
Load Capacitance (C
L
) 30pF 100pF
Input Rise and Fall Times ≤ 10ns ≤ 10ns
Input Pulse Voltages 0 to 3V 0.45 to 2.4V
Input and Output Timing Ref. Voltages 1.5V 0.8V and 2.0V
Page 12
M29F080A
12/21
Table 10. DC Characteristics
(TA= 0 to 70°C, –40 to 85°C or –40 to 125°C)
Note: 1. Sampled only, not 100% tested.
2. T
A
=25°C, VCC=5V.
Symbol Parameter Test Condition Min
Typ.
(2)
Max Unit
I
LI
Input Leakage Current
0V ≤ V
IN
≤ V
CC
±1 µA
I
LO
Output Leakage Current 0V ≤ V
OUT
≤ V
CC
±1 µA
I
CC1
Supply Current (Read)
E=V
IL
,G=VIH, f = 6MHz
10 20 mA
I
CC2
Supply Current (Standby) TTL
E=V
IH
1mA
I
CC3
Supply Current (Standby) CMOS
E=V
CC
± 0.2V,
RP = V
CC
± 0.2V
35 150 µA
I
CC4
(1)
Supply Current (Program/Erase)
Program/Erase
Controller active
20 mA
V
IL
Input Low Voltage –0.5 0.8 V
V
IH
Input High Voltage 2
V
CC
+ 0.5
V
V
OL
Output Low Voltage
I
OL
= 5.8mA
0.45 V
V
OH
Output High Voltage TTL
I
OH
= –2.5mA
2.4 V
Output High Voltage CMOS
I
OH
= –100µAV
CC
–0.4
V
V
ID
Identification Voltage 11.5 12.5 V
I
ID
Identification Current
A9 = V
ID
100 µA
V
LKO
(1)
Program/Erase Lockout Supply
Voltage
3.2 4.2 V
Page 13
13/21
M29F080A
Figure 8. Read Mode AC Waveforms
AI02925
tAVAV
tAVQV tAXQX
tELQX tEHQZ
tGLQV
tGLQX tGHQX
VALID
A0-A19
G
DQ0-DQ7
E
tELQV tEHQX
tGHQZ
VALID
Table 11. Read AC Characteristics
(TA= 0 to 70°C, –40 to 85°C or –40 to 125°C)
Note: 1. Sampled only, not 100% tested.
Symbol Alt Parameter Test Condition
M29F080A
Unit
70 90 / 120
t
AVAV
t
RC
Address Valid to Next Address Valid
E=V
IL
,
G=V
IL
Min 70 90 ns
t
AVQV
t
ACC
Address Valid to Output Valid
E=V
IL
,
G=V
IL
Max 70 90 ns
t
ELQX
(1)
t
LZ
Chip Enable Low to Output Transition G = V
IL
Min 0 0 ns
t
ELQV
t
CE
Chip Enable Low to Output Valid
G=V
IL
Max 70 90 ns
t
GLQX
(1)
t
OLZ
Output Enable Low to Output
Transition
E=V
IL
Min 0 0 ns
t
GLQV
t
OE
Output Enable Low to Output Valid
E=V
IL
Max 30 35 ns
t
EHQZ
(1)
t
HZ
Chip Enable High to Output Hi-Z G = V
IL
Max 20 20 ns
t
GHQZ
(1)
t
DF
Output Enable High to Output Hi-Z
E=V
IL
Max 20 20 ns
t
EHQX
t
GHQX
t
AXQX
t
OH
Chip Enable, Output Enable or
Address Transition to Output Transition
Min 0 0 ns
Page 14
M29F080A
14/21
Figure 9. Write AC Waveforms, Write Enable Controlled
AI00524
E
G
W
A0-A19
DQ0-DQ7
VALID
VALID
V
CC
tVCHEL
tWHEH
tWHWL
tELWL
tAVWL
tWHGL
tWLAX
tWHDX
tAVAV
tDVWH
tWLWHtGHWL
RB
tWHRL
Table 12. Write AC Characteristics, Write Enable Controlled
(TA= 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)
Note: 1. Sampled only, not 100% tested.
Symbol Alt Parameter
M29F080A
Unit
70 90 / 120
t
AVAV
t
WC
Address Valid to Next Address Valid Min 70 90 ns
t
ELWL
t
CS
Chip Enable Low to Write Enable Low Min 0 0 ns
t
WLWH
t
WP
Write Enable Low to Write Enable High Min 45 45 ns
t
DVWH
t
DS
Input Valid to Write Enable High Min 30 45 ns
t
WHDX
t
DH
Write Enable High to Input Transition Min 0 0 ns
t
WHEH
t
CH
Write Enable High to Chip Enable High Min 0 0 ns
t
WHWL
t
WPH
Write Enable High to Write Enable Low Min 20 20 ns
t
AVWL
t
AS
Address Valid to Write Enable Low Min 0 0 ns
t
WLAX
t
AH
Write Enable Low to Address Transition Min 45 45 ns
t
GHWL
Output Enable High to Write Enable Low Min 0 0 ns
t
WHGL
t
OEH
Write Enable High to Output Enable Low Min 0 0 ns
t
WHRL
(1)
t
BUSY
Program/Erase Valid to RB Low Max 30 35 ns
t
VCHEL
t
VCS
VCCHigh to Chip Enable Low
Min 50 50 µs
Page 15
15/21
M29F080A
Table 13. Write AC Characteristics, Chip Enable Controlled
(TA= 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)
Note: 1. Sampled only, not 100% tested.
Symbol Alt Parameter
M29F080A
Unit
70 90 / 120
t
AVAV
t
WC
Address Valid to Next Address Valid Min 70 90 ns
t
WLEL
t
WS
Write Enable Low to Chip Enable Low Min 0 0 ns
t
ELEH
t
CP
Chip Enable Low to Chip Enable High Min 45 45 ns
t
DVEH
t
DS
Input Valid to Chip Enable High Min 30 45 ns
t
EHDX
t
DH
Chip Enable High to Input Transition Min 0 0 ns
t
EHWH
t
WH
Chip Enable High to Write Enable High Min 0 0 ns
t
EHEL
t
CPH
Chip Enable High to Chip Enable Low Min 20 20 ns
t
AVEL
t
AS
Address Valid to Chip Enable Low Min 0 0 ns
t
ELAX
t
AH
Chip Enable Low to Address Transition Min 45 45 ns
t
GHEL
Output Enable High Chip Enable Low Min 0 0 ns
t
EHGL
t
OEH
Chip Enable High to Output Enable Low Min 0 0 ns
t
EHRL
(1)
t
BUSY
Program/Erase Valid to RB Low Max 30 35 ns
t
VCHWL
t
VCS
VCCHigh to Write Enable Low
Min 50 50 µs
Figure 10. Write AC Waveforms, Chip Enable Controlled
AI00525
E
G
W
A0-A19
DQ0-DQ7
VALID
VALID
V
CC
tVCHWL
tEHWH
tEHEL
tWLEL
tAVEL
tEHGL
tELAX
tEHDX
tAVAV
tDVEH
tELEHtGHEL
RB
tEHRL
Page 16
M29F080A
16/21
Table 14. Reset/Block Temporary Unprotect AC Characteristics
(TA= 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)
Note: 1. Sampled only, not 100% tested.
Symbol Alt Parameter
M29F080A
Unit
70 90 / 120
t
PHWL
(1)
t
PHEL
t
PHGL
(1)
t
RH
RP High to Write Enable Low, Chip Enable Low,
Output Enable Low
Min 50 50 ns
t
RHWL
(1)
t
RHEL
(1)
t
RHGL
(1)
t
RB
RB High to Write Enable Low, Chip Enable Low,
Output Enable Low
Min 0 0 ns
t
PLPX
t
RP
RP Pulse Width Min 500 500 ns
t
PLYH
(1)
t
READY
RP Low to Read Mode Max 10 10 µs
t
PHPHH
(1)
t
VIDR
RP Rise Time to V
ID
Min 500 500 ns
Figure 11. Reset/Block Temporary Unprotect AC Waveforms
AI02931
RB
W,
RP
tPLPX
tPHWL, tPHEL, tPHGL
tPLYH
tPHPHH
E, G
tRHWL, tRHEL, tRHGL
Page 17
17/21
M29F080A
Table 15. OrderingInformation Scheme
Note: The last two characters of the ordering code may be replaced by a letter code for preprogrammed
parts, otherwise devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
Example: M29F080A 70 N 1 T
Device Type
M29
Operating Voltage
F=V
CC
=5V±10%
Device Function
080A = 8 Mbit (1Mb x8), Uniform Block
Speed
70 = 70 ns
90 = 90 ns
120 = 120ns
Package
N = TSOP40: 10 x 20 mm
M = SO44
Temperature Range
1=0to70°C
3 = –40 to 125 °C
6=–40to85°C
Option
T = Tape& Reel Packing
Page 18
M29F080A
18/21
Table 16. Revision History
Date Revision Details
July 1999 First Issue
09/21/99
Removed 55ns speed option
Chip Erase Max. specification added (Table6)
Block Erase Max. specification added (Table6)
Program Max. specification added (Table 6)
Chip Program Max. specification added (Table6)
I
CC1
Typ.specification added (Table 10)
I
CC3
Typ.specification added (Table 10)
10/04/99
I
CC3
TestCondition change (Table10)
11/12/99 Block Protection and Unprotection paragraph change
01/14/00 Command Interface paragraph change
03/30/00
New document template
Document type: from Preliminary Data to Data Sheet
Status Register bit DQ5 clarification
Data Polling Flowchart diagram change (Figure 4)
Data Toggle Flowchart diagram change (Figure 5)
Restrictive Read AC Characteristics removed
TSOP40 Package mechanical data change (Table17)
SO44 Package mechanical data change (Table18)
Page 19
19/21
M29F080A
Table 17. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data
Symbol
mm inches
Typ Min Max Typ Min Max
A 1.20 0.0472
A1 0.05 0.15 0.0020 0.0059
A2 0.95 1.05 0.0374 0.0413
B 0.17 0.27 0.0067 0.0106
C 0.10 0.21 0.0039 0.0083
D 19.80 20.20 0.7795 0.7953
D1 18.30 18.50 0.7205 0.7283
E 9.90 10.10 0.3898 0.3976
e 0.50 – – 0.0197 – –
L 0.50 0.70 0.0197 0.0276
α 0° 5° 0° 5°
N40 40
CP 0.10 0.0039
Figure 12. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20 mm, Package Outline
Drawing is not to scale.
TSOP-a
D1
E
1N
CP
B
e
A2
A
N/2
D
DIE
C
LA1 α
Page 20
M29F080A
20/21
Figure 13. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline
Drawing is not to scale.
SO-b
E
N
CP
B
e
A2
D
C
LA1 α
H
A
1
Table 18. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data
Symbol
mm inches
Typ Min Max Typ Min Max
A 2.42 2.62 0.0953 0.1031
A1 0.22 0.23 0.0087 0.0091
A2 2.25 2.35 0.0886 0.0925
B 0.50 0.0197
C 0.10 0.25 0.0039 0.0098
D 28.10 28.30 1.1063 1.1142
E 13.20 13.40 0.5197 0.5276
e 1.27 – – 0.0500 – –
H 15.90 16.10 0.6260 0.6339
L 0.80 – – 0.0315 – –
α 3° ––3°––
N44 44
CP 0.10 0.0039
Page 21
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M29F080A
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