Datasheet M28W160BT, M28W160BB Datasheet (SGS Thomson Microelectronics)

Download

Page 1

16 Mbit (1Mb x16, Boot Block) Low Voltage Flash Memory

■ SUPPLY VOLTAGE

= 2.7V to 3.6V: for Program, Erase and

–V

Read –V –V

■ ACCESS TIME

– 2.7V to 3.6V: 90ns – 2.7V to 3.6V: 100ns

■ PROGRAMMING TIME:

– 10µ s typical – Double Word Programming Option

■ PROGRAM/ERASE CONTROLLER (P/E.C.)

■ COMMON FLASH INTERFACE

– 64 bit Security Code

■ MEMORY BLOCKS

– Parameter Blocks (Top or Bottom location) – Main Blocks

■ BLOCK PROTECTION on TWO PARAMET ER

BLOCKS –WP

■ AUTOMATIC STAND-BY MODE

■ PROGRAM and ERASE SUSPEND

■ 100,000 PROGRAM/ERASE CYCL ES per

BLOCK

■ 20 YEARS of DATA RETENTION

– Defectivity below 1ppm/year

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h – Top Device Code, M28W160BT: 90h – Bottom Device Code, M28W160BB: 91h

= 1.65V or 2.7V: Input/Output option

DDQ

= 12V: o ptional Supply Voltage for fast

Program

for Block Protection

M28W16 0BT

M28W160BB

TSOP48 (N)

12 x 20mm

Figure 1. Logic Diagram

DDQVPP

A0-A19

M28W160BT M28W160BB

µBGA

µBGA46 (GB)

8 x 6 solder balls

DQ0-DQ15

AI02628

1/39May 2000

Page 2

M28W160BT, M28W160BB

Figure 2. µBG A Co nn e ct i ons (Top view through package)

87654321

DDQ

Figure 3. TSOP Connection s

A15 A14 A13 A12 A11 A10 DQ14

WP A19 A18 A17

A8 NC NC

12 13

24 25

M28W160BT M28W160BB

DQ15

37 36

AI02630

A8A11A13

DQ7V

DQ13

RP A18

DQ11

DQ12

DQ4

WP A19

DQ2

A7V

A5A17WA10A14

DQ0DQ9DQ3DQ6

DQ1DQ10V

A1A3A6A9A12A15

A0EDQ8DQ5DQ14A16

AI02629

Table 1. Signal Names

A16 V

DDQ

DQ15 DQ7

DQ6 DQ13 DQ5 DQ12 DQ4 V

DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G V

E A0

A0-A19 Address Inputs DQ0-DQ7 Data Input/Output, Command Inputs DQ8-DQ15 Data Input/Output E G W RP WP V

DDQ

Chip Enable Output Enable Write Enable Reset Write Protect Supply Voltage Power Supply for

Input/Output Buffers Optional Supply Voltage for

Fast Program & Erase Ground

NC Not Connected Internally

2/39

Page 3

M28W160BT, M28W160BB

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

BIAS

STG

, V

DDQ

Note: 1. Except for the ratin g " Operating Temperature Range", stresses abo ve those listed in the T able "Abs ol ute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indi cated in the Operating sections of this s pecification is not impli ed. Exposure to Absolute M aximum Rating conditions for extended per iods may aff ect device reliabilit y. Refer also to the STMicroel ectronics SURE Program an d other relevan t qual ity docum en ts .

2. Depends on range.

Ambient Operating Temperature

Temperature Under Bias –40 to 125 °C Storage Temperature –55 to 155 °C Input or Output Voltage Supply Voltage –0.6 to 4.1 V Program Voltage –0.6 to 13 V

DESCRIPTION

The M28W160B is a 16 Mbit non-volatile Flash memory that can be erased electrically at the block level and programmed i n-system on a Word-byWord basis. The device is of fered in the TS OP48

(10 x 20mm) and the µ BGA46, 0.75 mm ball pitch packages. When shipped, all bits of the M28W160B are in the ‘1’ state.

The array matrix organisation allows each block to be erased and reprogrammed without affecting other blocks. Each block can be programmed and erased over 100,000 cycles. V

DDQ

the I/O pin down t o 1.65V. An optional 12 V V power supply is provided to speed up the program phase at customer production line environment. An internal Command Interface (C.I.) decodes the instructions to access/modify the memory content. The Program/Erase Controller (P /E.C.) automatically executes the algorithms taking care of the timings necessary for program and erase operations. Verification is performed too, unburdening the microcontroller, while the Status Register tracks the status of th e operation.

The following instructions are executed by the M28W160B: Read Array , Read Electronic Signature, Read Status Register, Clear Status Register, Program, Double Word Program, Block Erase, Program/Erase Suspend, Program/Erase Resume and CFI Query.

(1)

(2)

allows to driv e

–40 to 85 °C

–0.6 to V

DDQ

+0.6

Organisation

The M28W160B is organised as 1 Mbit by 16 bits. A0-A19 are the address l ines; DQ0 -DQ15 are the Data Input/Output. Memory control is provided by Chip Enable E W

inputs. The Program and Erase operations are

, Output Enable G and Write Enable

managed automatically by the P/E.C. Block protection against Program or E rase provides additional data security.

The upper two (or lower two) parameter blocks can be protected to secure the code content of the memory . WP

controls protection and unprotection

operations.

Memory Blocks

The device features an asymmetrical blocked architecture. The M28W160B has an array of 39 blocks: 8 Parameter Blocks of 4 KWord and 31 Main Blocks of 32 KWord. M28W 160BT has the Parameter Blocks at the top of the memory address space while the M28W160BB locates the Parameter Blocks starting from the bottom. The memory maps are shown in Tables 3 and 4.

The two upper parameter block c an be protected from accidental programming or erasure using

. Each block can be erased separately. Erase

WP can be suspended in order to perform either read or program in any other b lock and then resum ed. Program can be s uspended to read data in any other block and then resumed.

3/39

Page 4

M28W160BT, M28W160BB

Table 3. Top Boot Block Addresses, M28W160BT

38 4 FF000-FFFFF 37 4 FE000-FEFFF 36 4 FD000-FDFFF 35 4 FC000-FCFFF 34 4 FB000-FBFFF 33 4 FA000-FAFFF 32 4 F9000-F9FFF 31 4 F8000-F8FFF 30 32 F0000-F7FFF 29 32 E8000-EFFFF 28 32 E0000-E7FFF 27 32 D8000-DFFFF 26 32 D0000-D7FFF 25 32 C8000-CFFFF 24 32 C0000-C7FFF 23 32 B8000-BFFFF 22 32 B0000-B7FFF 21 32 A8000-AFFFF 20 32 A0000-A7FFF 19 32 98000-9FFFF 18 32 90000-97FFF 17 32 88000-8FFFF 16 32 80000-87FFF 15 32 78000-7FFFF 14 32 70000-77FFF 13 32 68000-6FFFF 12 32 60000-67FFF 11 32 58000-5FFFF 10 32 50000-57FFF

9 32 48000-4FFFF 8 32 40000-47FFF 7 32 38000-3FFFF 6 32 30000-37FFF 5 32 28000-2FFFF 4 32 20000-27FFF 3 32 18000-1FFFF 2 32 10000-17FFF 1 32 08000-0FFFF 0 32 00000-07FFF

Size

(KWord)

Address Range

Table 4. Bottom Boot Block Addresses, M28W160BB

38 32 F8000-FFFFF 37 32 F0000-F7FFF 36 32 E8000-EFFFF 35 32 E0000-E7FFF 34 32 D8000-DFFFF 33 32 D0000-D7FFF 32 32 C8000-CFFFF 31 32 C0000-C7FFF 30 32 B8000-BFFFF 29 32 B0000-B7FFF 28 32 A8000-AFFFF 27 32 A0000-A7FFF 26 32 98000-9FFFF 25 32 90000-97FFF 24 32 88000-8FFFF 23 32 80000-87FFF 22 32 78000-7FFFF 21 32 70000-77FFF 20 32 68000-6FFFF 19 32 60000-67FFF 18 32 58000-5FFFF 17 32 50000-57FFF 16 32 48000-4FFFF 15 32 40000-47FFF 14 32 38000-3FFFF 13 32 30000-37FFF 12 32 28000-2FFFF 11 32 20000-27FFF 10 32 18000-1FFFF

9 32 10000-17FFF 8 32 08000-0FFFF 7 4 07000-07FFF 6 4 06000-06FFF 5 4 05000-05FFF 4 4 04000-04FFF 3 4 03000-03FFF 2 4 02000-02FFF 1 4 01000-01FFF 0 4 00000-00FFF

Size

(KWord)

Address Range

4/39

Page 5

M28W160BT, M28W160BB

SIGNAL DESCRIPTIONS

See Figure 1 and Table 1. Address Inputs (A0-A19). The address signals

are inputs driven with CMOS vol tage level s. They are latched during a write operation.

Data Input/Output (DQ0-DQ15). The data inputs, a word to be programmed or a comm and to the C.I., are latched on the Chip Enable E Enable W

rising edge, whichever occurs first. The

or Write

data output from the memory Array, the Electronic Signature or Status Register is valid when Chip Enable E

and Output Enable G are active. The

output is high impedance when the ch ip is deselected, the outputs are disabled or RP

is tied to VIL.

Commands are issued on DQ0-DQ7.

Chip Enable (E

). The Chip Enable input acti-

vates the memory control logic, input buffers, decoders and sense amplifiers. E

at VIH deselects the memory and red uces the power consumption to the stand-by level. E

can also be used to control writing to the command register and to the memory array, while W

Output Enable (G

remains at VIL.

). The Output Enable controls

the data Input/Output buffers.

Write Enable (W

). This input controls writing to

the Command Register, Input Address and Dat a latches.

Write Protect (WP

). Write Protect is an input to

protect or unprotect the two lockable parameter blocks. When WP

is at VIL, the locka ble bl ocks are protected. Program or erase operations are not achievable. When WP

is at VIH, the lockable blocks are unprotected and they can be programmed or erased (refer to Table 9).

Reset Input (RP

ware reset of the memory. When RP

). The RP input provides hard-

is at VIL, the memory is in reset mode : the outputs are put to High-Z and the current consumption is minimised. When RP

is at VIH, the device is in norm al operation. Exiting reset mode the device enters read array mode.

Supply Voltage (2.7V to 3.6V). VDD pro-

vides the power supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program and Erase). It ranges from 2.7V to 3.6V.

Supply Voltage (1.65V to VDD). V

DDQ

provides the power supply to the I/O pins and enables all Outputs to be powered independently from V

. V

can be tied to VDD or it can use a

DDQ

separate supply. It can be powered either from

1.65V to 2.2V or from 2.7V to 3.6V.

Program Supply Voltage (12V). VPP is

both a control input and a power supply pin. T he two functions are selected by the voltage range applied to the pin.

is kept in a low voltage range (0V to 3.6V)

If V

is seen as a control input. In this case a volt-

age lower than V against program or erase, whi le V ables these functions. V

gives an absolute protection

PPLK

value is only sampled

> V

PP1

en-

at the beginning of a program or erase; a cha nge in its value after the operation has been started does not have any effect and program or erase are carried on regu larl y.

is used in the range 11.4V to 12.6V acts as

If V

a power supply pin. In this condition V

value must be stable until P/E algorithm is completed (see Table 22 and 23).

Ground. VSS is the reference for all the volt-

age measurements.

5/39

Page 6

M28W160BT, M28W160BB

DEVICE OPERATIONS

Four control pins rule the hardware access t o the Flash memory: E

, G, W, RP. The following operations can be performed using the appropriate bus cycles: Read, Write the Command of an Instruction, Output Disable, Stand-by, Reset (see Table

5). Read. Read operations are used to output the

contents of the Memory Array, the Electronic Signature, the Status Register and the CFI. Both Chip Enable (E

) and Output Enabl e (G) must be at V in order to perform the read operation. The Chip Enable input should be used to enable the device. Output Enable shoul d be used to gate data onto the output indepe ndently of the device s election. The data read depend on the previous command written to the memory (see instructions RD, RSIG, RSR, RCFI). Read Array is the default state of the device when exiting Reset or after power-up.

Write. Write operations are used to give Commands to the memory or to latch Input Data to be programmed. A write operation is initiated when Chip Enable E Output Enable G

Table 5. User Bus Operations

Operation E G W RP WP

Read Write Output Disable Stand-by Reset X X X

Note: 1. X = VIL or VIH, V

and Write Enable W are at VIL with

at VIH. Comm ands, Inp ut Data

(1)

= 12V ± 5%.

PPH

and Addresses are latched on the rising edge of W or E, whichever occur first.

Output Disa bl e . The data outputs are high impedance when the Output Enable G

Stand-by. Stand-by disables most of the internal circuitry allowing a substantial reduction of the current consumption. The memory is in stand-by when Chip Enable E read mode. The power consumption is reduced to the stand-by level and the o utputs are set to high impedance, independently from the Output Enable

or Write Enable W inputs. If E switches to V during program or erase operation, the device enters in stand-by when finished.

Reset. During Reset mode all internal circuits are switched off, the memory is deselected and the outputs are put in high impedance. The memory is in Reset mode when RP sumption is reduced to the Stand-by level, independently from the Chip Enabl e E

or Write Enable W inputs. If RP is pulled to V

G during a Program or Erase, this operation is aborted and the memory content is no longer valid as it has been compromised by the aborted operation.

is at VIH.

is at VIH and the device is in

is at VIL. The power con-

, Output En able

X Don’t Care Data Output

X X Don’t Care Hi-Z X Don’t Care Hi-Z X Don’t Care Hi-Z

or V

PPH

DQ0-DQ15

Data Input

Table 6. Read Electronic Signature (RSIG Instruction)

Code Device E

Manufact. Code

M28W160BT

Device Code

M28W160BB

Note: 1. RP = VIH.

6/39

G W A0 A1-A7 A8-A19 DQ0-DQ7 DQ8-DQ15

V V V

V V

Don’t Care 20h 00h

Don’t Care 90h 00h

Don’t Care 91h 00h

Page 7

M28W160BT, M28W160BB

INSTRUCTIONS AND COMMANDS

Eleven instructions are available (see Tables 7 and 8) to perform Read Memory Array, Read Status Register, Read Electronic Signature, CFI Query, Erase, Program, Dou ble Word Program, Clear Status Register, Program/Erase Suspend and Program/Erase Resume. Status Register output may be read at any time, during programming or erase, to monitor the progress of the operation.

An internal Command Interface (C.I.) decodes the instructions while an internal Program/Erase Controller (P/E.C.) handles all timing and verifies the correct execution of the Program and Erase instructions. P/E.C. provides a Status Register whose bits indicate operation and exit status of the internal algorithms.

The Command Interface is reset to Read Array when power is first applied, when exiting from Reset or whenever V

is lower than V

LKO

. Command sequence must be followed exactly. Any invalid combination of commands will reset the device to Read Array.

Read (RD)

The Read instruction consists of one write cycle (refer to Device Operations section) giving the command FFh. Next read operations will read the addressed location and output the data. When a device reset occurs, the memo ry is in Read Array as default.

Read Status Register (RSR)

The Status Register indicates when a program or erase operation is complete and the success or failure of operation itself. Issue a Read Status Register Instruction (70h) to rea d the S tatu s Register content.

The Read Status Register instruction may be issued at any time, also when a Program/Erase operation is ongoing. The following Read operations output the content of the Status Register. The Status Register is latched on the falling edge of E G

signals, and can be read until E or G returns to

. Eithe r E or G must be t oggled to updat e the

latched data. Additionally, any read attempt during program or erase operation will autom atically ou tput the content of the Status Register.

Read Electronic Signature (RSIG)

The Read Electronic Signature instruction consists of one write cycle (refer to Device Operations

section) giving the command 90h. A subsequent read will output the Manufacturer or the Device Code (Electronic Signature) depending on the levels of A0 (see Tables 6). The Electronic Signature can be read from the memory allowing programming equipment or applications to automatically match their interface to the characteristics of M28W160B. The Manufacturer Code is output when the address lines A 0 is at V Code is output when A0 is at V must be kept to V

, other addresses are ignored.

, the Device

. Address A1-A7

The codes are output on DQ0-DQ7 with DQ8DQ15 at 00h.

CFI Query (RCFI)

The Common Flash Interface Query mode is entered by writing 98h. Next read operations will read the CFI data. The CFI data structure contains also a security area; in this section, a 64 bit unique security number is written, starting at address 80h. This area can be accessed only in read mode by the final use and there are no ways of chang ing the code after it has been written by ST. Write a read instruction to return to Read mode (refer to the Common Flash Interface section).

Table 7. Commands

Hex Code Command

00h, 01h, 60h,

2Fh, C0h

10h Alternative Program Set-up 20h Erase Set-up 30h Double Word Program Set-up 40h Program Set-up 50h Clear Status Register 70h Read Status Register

90h or 98h

B0h Program/Erase Suspend

D0h

FFh Read Array

Invalid/Reserved

Read Electronic Signature, or CFI Query

Program/Erase Resume, or Erase Confirm

7/39

Page 8

M28W160BT, M28W160BB

Table 8. Instructions

Mne-

monic

RSR

RSIG

RCFI CFI Qu ery 1+ Wri te 55h

EE Erase 2 Write X 20h Write

PG Progra m 2 Write X

DPG

CLRS

PES

PER

Note: 1. X = Don’t Care.

Instruction Cycles

Read Memory Array

Read Status Register

Read Electronic Signature

Double Word

(4)

Program Clear Status

Erase Suspend

Program/ Erase Resume

2. The first cyc le of the RD, RSR, RSIG o r RCFI in st ruction is followed by read oper ations to read me m ory array, Status Register or Electronic Signature codes. Any number of Read cycle can occur after one command cycle.

3. Signature address bit A0=V kept to V

4. Address 1 and Address 2 must be consecuti ve Addresses differing only for address bit A0.

. Other address bits are i gnored.

Operat.

1+ Write X FFh

1+ Write X 70h

1+ Write X

3 Write X 30h Write Address 1

1Write X 50h

1Write X B0h

1Write X D0h

1st Cycle 2nd Cy cle 3nd Cy cle

(1)

Addr.

will output Manufacturer code. Address bit A0=V

Data Operat. Addr. Data Operat. Addr. Data

Read

90h or

98h

98h or

90h

40h or

10h

(2)

Read

Write Address

(2)

Address

Signature

Address

CFI

Address

Bloc k

Address

Data

Status

Signatur e

(3)

Query

D0h

Data Input

will output Device code. Address A7-A1 must be

Write Address 2

Data

Input

Erase (EE)

Block erasure sets all the bits within the selected block to ’1’. One block at a time can be erased. It is not necessary to program the block with 00h as the P/E.C. will do it automatically before erasing. This instruction uses two write cycles. The first command written is the Erase Set up command 20h. The second command is the Erase Confirm command D0h. An address within the block to be erased is given and latched in to the mem ory during the input of t he second com mand. If the s econd command given is not an erase conf irm, the status register bits b4 and b5 are set and the instruction aborts.

Read operations output the status register after erasure has started.

8/39

Status Register bit b7 returns ’0’ while the erasure is in progress and ’1’ when it has completed. After completion the Status Register bit b5 returns ’1’ if there has been a n Erase Failure. S tatus register bit b1 returns ’1’ if the user is attempt ing to program a protected blo ck. S tat us Regi s ter bit b3 returns a ’1’ if V

is below V

Erase aborts if RP

turns to VIL. As da ta integ rity

PPLK

cannot be guaranteed when the erase operation is aborted, the erase must be repeated. A Clear Status Register instruction must be issued to reset b1, b3, b4 and b5 of th e Status Register. During the execution of the erase by t he P /E.C., the memory accepts only the RSR (Read Status Register) and PES (Program/Erase Suspend) instructions.

Page 9

Table 9. Memory Blocks Protection Truth Table

VPP

(1,3)

(2,4)

(1,4)

M28W160BT, M28W160BB

Lockable Blocks Other Blocks

or V

Note: 1. Notes:1. X ’ = Don’t Care

2. RP

3. V

4. V

5. V

(5)

PPH

(5)

PPH

is the Reset/Power Down.

is the program or erase supply volta ge.

are logic high and low levels.

IH/VIL

must be also gr eater than the Program V ol t age Lock-Out V

Table 10. Status Register Bits

Mnemonic Bit Name

P/ECS 7 P/E.C. Status

Erase

ESS 6

ES 5 Erase Status

PS 4

VPPS 3

PSS 2

BPS 1

Suspend Status

Program Status

Status

Program Suspend Status

Block Protection Status

X Protected Protected X Protected Protected

Logic

Level

Definition Note

Protected Unprotected

Unprotected Unprotected

PPLK

’1’ Ready Indicates the P/E.C. status, check during

Program or Erase, and on completion before

’0’ Busy

’1’ Suspended

In progress or

’0’

Completed

checking bits b4 or b5 for Program or Erase Success

On an Erase Suspend instruction P/ECS and ESS bits are set to ’1’. ESS bit remains ’1’ until an Erase Resume instruction is given.

’1’ Erase Error ES bit is set to ’1’ if P/E.C. has applied the

maximum number of erase pulses to the block

’0’ Erase Success ’1’ Program Error

’0’ Program Success

’1’

Invalid, Abort VPPS bit is set if the VPP voltage is below V

without achieving an erase verify. PS bit set to ’1’ if the P/E.C. has failed to program

a word.

when a Program or Erase instruction is executed.

is sampled only at the beginning of the

’0’

’1’ Suspended

In Progress or

’0’

Completed

Erase/Program operation. On a Program Suspend instruction P/ECS and

PSS bits are set to ’1’. PSS remains ’1’ until a Program Resume Instruction is given

Program/Erase on

’1’

protected Block, Abort

No operation to

’0’

protected blocks

BPS bit is set to ’1’ if a Program or Erase operation has been attempted on a protected block

PPLK

0 Reserved

Note: Logic level ’1’ is High, ’0’ is Low.

9/39

Page 10

M28W160BT, M28W160BB

Program (PG)

The memory array can be programmed word-byword. This instruction uses two write cycles. The first command written is the Program Set-up command 40h (or 10h). A second write operation latches the Address and the Data to be written and starts the P/E.C.

Read operations output the Status Register content after the programming has started. The Status

Register bit b7 returns ’0’ while t he programming is in progress and ’1’ when it has completed. After completion the Status register bit b4 returns ’1’ if there has been a Program Failure. Status register bit b1 returns ’1’ if the user is attempt ing to program a protected blo ck. S tatu s Regi s ter bit b3 returns a ’1’ if V aborts if RP

is below V

. Programming

PPLK

goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the memory location must be erased and reprogrammed. A Clear Status Register instruction must be issued to reset b4, b3 and b1 of the Status Register.

During the execution of the program by the P/E.C., the memory accepts only the RSR (Read Status Register) and PES (Program/Erase Suspe nd) instructions.

Doubl e Word Prog ram (DPG)

This feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel.The two words m ust differ only for the address A0. Programm ing should not b e att emp ted when V

is not at V

also be executed if V

. The operation can

PPH

is below V

PPH

but result could be uncertain. This instruction uses three write cycles. The first c ommand written is the Double Word Program Set-Up command 30h. A second write operation latc hes the Address and the Data of the first w ord to be wri tten, the third write operation latches the Address and the Data of the second word to be written and starts the P/E.C. Read operations output the Status Register content after the programming has started. The Status Register bit b7 returns ’0’ while t he programming is in progress and ’1’ when it has completed. After completion the Status register bit b4 returns ’1’ if there has been a Program Failure. Status register bit b1 returns ’1’ if the user is attempt ing to program a protected blo ck. S tatu s Regi s ter bit b3 returns a ’1’ if V aborts if RP

goes to VIL. As data integrity cannot

is below V

. Programming

PPLK

be guaranteed when the program operation is aborted, the memory location must be erased and

reprogrammed. A Clear Status Register instruction must be issued to reset b4, b3 and b1 of the Status Register.

During the execution of the program by the P/E.C., the memory accepts only the RSR (Read Status Register) and PES (Program/Erase Suspe nd) instructions.

Clear Status Register (CLRS)

The Clear Status Register uses a single write operation which clears bits b1, b3, b4 and b5 to ‘0’. Its use is necessary before any new operation when an error has been detected.

The Clear Status Register is executed w riting the command 50h.

Program/Erase Suspend (PES)

Program/Erase suspend is accepted only during the Program Erase instruction execu tion. When a Program/Erase Suspend command is written to the C.I., the P/E.C. freezes the Program/Erase operation. Program/Erase Res ume (P ER) cont inues the Program/Erase operation. Program/Erase Suspend consists of writing the command B0h without any specific address.

The Status Register bit b2 is set to ‘1’ (within 5µs) when the program has been sus pended . b2 is set to ‘0’ in case the program is completed or in progress. The Status Register bit b6 is set to ‘1’ (within 30µs) when the erase has been sus pended. b6 is s et t o ‘0’ in cas e th e e rase is com plet ed or in progress. The valid commands while erase is suspended are Program/Erase Resume, Program, Read Array, Read Status Register, Read Identifier, CFI Query. While program is suspended the same command set is valid except for program instruction. During program/erase suspend mode, the chip can be placed in a pseudo-stand-by mode by taking E sumption. Program/Erase is aborted if RP

to VIH. This reduces active current con-

turns to

Program/Erase Resume (PER)

If a Program/Erase Suspend instruction was previously executed, the program/erase operation may be resumed by issuing the command D0h. The status register bit b2/b6 is cleared when program/ erase resumes. Read operations output the status register after the program/erase is resumed.

The suggested flow charts for programs that use the programming, erasure and program/erase suspend/resume features of the memories are shown from Figures 10, 11, 12, 13 and 14.

10/39

Page 11

M28W160BT, M28W160BB

Table 11. Program, Erase Times and Program /Eras e Endur ance Cycles

= 0 to 70°C or –40 to 85°C; VDD = 2.7V to 3.6V)

Parameter Test Conditions

Word Program

Double Word Program

Main Block Program

Parameter Block Program

Main Block Erase

Parameter Block Erase

= 12V ±5%

= V

Program/Erase Cycles (per Block) 100,000 cycles

Note: TA = 25 °C.

Min

M28W160B

Typ

(1)

Max

Unit

10 200 µs 10 200 µs

0.16 5 sec

0.32 5 sec

0.02 4 sec

0.04 4 sec 110 sec 110 sec

0.8 10 sec

11/39

Page 12

M28W160BT, M28W160BB

BLOCK PROTECTION

Two parameter blocks (#0 and #1) can be protected against Program or Erase to ensure extra data security. Unprotected blocks can be programmed or erased.

tied to VIL protects the two lockable b locks.

WP V

below V

protects all the blo cks. A ny pro-

PPLK

gram or erase operation on protected blocks is aborted. The Status Register tracks when the event occurs.

Table 9 defines the protection methods.

POWER CONSUMPTION

The M28W160B puts itself in one o f four different modes depending on the statu s of the c ontrol signals: Active Power, Automatic Stand-by, Stand-by and Reset define decreasing levels of current consumption. These allow the memory power to be minimised, in turn decreasing the overall system power consumption. As different recovery time are linked to the different modes, please refer to the AC timing table to design your system.

Active Power

When E

is at VIL and RP is at VIH, the device is in active mode. Refer to DC Characteristics to get the values of the current supply consumption.

Automatic Stand-by

Automatic Stand-by provides a low power consumption state during read mode. Following a read operation, after a del ay c lose to the memory access time, the device enters Automatic Standby: the Supply Current is reduced to I

CC1

values. The device keeps the last output data s table, till a new location is accessed.

Stand-by or Reset

Refer to the Device Operations section.

Power Up

The Supply voltage V voltage V

can be applied in any order. The

and the Program S upply

memory Command Interface is reset on power up to Read Memory Array, but a negative transition of Chip Enable E

or a change of the addresses is required to ensure valid data outputs. Care must be taken to avoid w rites to t he memory when V above V ther E

. Writes can be inhibited by drivin g ei-

LKO

or W to VIH. The memory is disabled if RP

is at VIL.

Supply Rails

Normal precautions must be taken for supply voltage decoupling, each device in a system should have the V

0.1µF capacitor close to the V

and VPP rails decoupled with a

and VPP pins.

The PCB trace widths should be sufficient to carry the required V

program and erase currents.

12/39

Page 13

M28W160BT, M28W160BB

COMMON FLASH INTERFACE (CFI)

The Comm on Fl ash In ter fac e (C FI) spec if i cati on i s a JEDEC approved, standardised data structure that can be read from the Flash memory device. CFI allows a system software to query the flash device to determine various electrical a nd timing parameters, density information and functions supported by the device. CFI allows the system to easily interface to the Flash memory, to learn about its features and parameters, enabling the software to configure itself when necessary.

Tables 12, 13, 14, 15, 16 and 17 show the address used to retrieve each data.

The CFI data structure gives information on the device, such as the sectorization, the command set and some electrical specifications. Tab les 12, 13, 14 and 15 show the addresses used to retrieve each data. The CFI data structure contains also a security area; in this section, a 64 bit unique security number is written, starting at address 80h. This area can be accessed only in read mode by the final user and there are no ways of changing the code after it has been written by ST. Write a read instruction to return to Read mode. Refer to the CFI Query instruction to understand how the M28W160B enters the CFI Query mode.

Table 12. Query Structure Overview

Offset Sub-section Name Description

00h Reserved Reserved for algorithm-specific information 10h CFI Query Identification String Command set ID and algorithm data offset 1Bh System Interface Information Device timing & voltage information 27h Device Geometry Definition Flash device layout

P Primary Algorithm-specific Extended Query table

A Alternate Algorithm-specific Extended Query table

Note: T he Flash memory displ ay the CFI data structure whe n CFI Query com m and is issued. In this t able are listed the mai n sub-se ctions

detailed in Tables 13, 14, 15, 16 and 17. Query data are always presented on the lowest order data outputs.

Additional information specific to the Primary Algorithm (optional)

Additional information specific to the Alternate Algorithm (optional)

Table 13. CFI Query Identification String

Offset Data Description

00h 0020h Manufacturer Code

01h

02h-0Fh reserved Reserved

10h 0051h Query Unique ASCII String "QRY" 11h 0052h Query Unique ASCII String "QRY" 12h 0059h Query Unique ASCII String "QRY" 13h 0003h 14h 0000h 15h offset = P = 0035h 16h 0000h 17h 0000h 18h 0000h 19h value = A = 0000h

1Ah 0000h

Note: Query data are al ways prese nted on the lowest - order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’ .

0090h - top

0091h - bottom

Device Code

Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm

Address for Primary Algorithm extended Query table

Alternate V endor Command Set and Control Interface ID Code second vendor

- specified algorithm supported (note: 0000h means none exists)

Address for Alternate Algorithm extended Query table note: 0000h means none exists

13/39

Page 14

M28W160BT, M28W160BB

Table 14. CFI Query System Interface Information

Offset D ata Description

Logic Supply Minimum Program/Erase or Write voltage

1Bh 0027h

1Ch 0036h

1Dh 00B4h

1Eh 00C6h

1Fh 0004h

20h 0000h

21h 000Ah

22h 0000h

23h 0004h

24h 0000h

25h 0003h

26h 0000h

bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 mV

Logic Supply Maximum Program/Erase or Write voltage

bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 mV

[Programming] Supply Minimum Program/Erase voltage

bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV Note: This value must be 0000h if no V

[Programming] Supply Maximum Program/Erase voltage

bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV Note: This value must be 0000h if no V

Typical timeout per single byte/word program (multi-byte program count = 1), 2

(if supported; 0000h = not supported) Typical timeout for maximum-size multi-byte program or page write, 2

(if supported; 0000h = not supported)

Typical timeout per individual block erase, 2

(if supported; 0000h = not supported)

Typical timeout for full chip erase, 2

(if supported; 0000h = not supported)

Maximum timeout for byte/word program, 2

times typical (offset 1Fh)

(0000h = not supported) Maximum timeout for multi-byte program or page write, 2

(0000h = not supported) Maximum timeout per individual block erase, 2

(0000h = not supported)

Maximum timeout for chip erase, 2

times typical (offset 22h)

(0000h = not supported)

pin is present

times typical (offset 20h)

times typical (offset 21h)

µs

14/39

Page 15

Table 15. Device Geometry Definition

Offset Word

Mode

27h 0015h 28h 0001h

29h 0000h 2Ah 0000h 2Bh 0000h 2Ch 0002h Number of Erase Block Regions within device

M28W160BT M28W160BT Erase Block Region Information

2Dh 001Eh 2Eh 0000h

2Fh 0000h 30h 0001h 31h 0007h 32h 0000h 33h 0020h 34h 0000h

M28W160BB M28W160BB

2Dh 0007h 2Eh 0000h

2Fh 0020h 30h 0000h 31h 001Eh 32h 0000h 33h 0000h 34h 0001h

Data Description

Device Size = 2 Flash Device Interface Code description: Asynchronous x16

Maximum number of bytes in multi-byte program or page = 2

bit 7 to 0 = x = number of Erase Block Regions Note:1. x = 0 means no erase blocking, i.e. the device erases at once in "bulk."

2. x specifies the number of regions within the device containing one or more contiguous Erase Block s of t he sa me s ize. For e xamp le, a 128K B de vice ( 1Mb) having blocking of 16K B, 8KB, four 2KB , two 16KB, and on e 64KB is considered to have 5 Erase Bloc k Regions. Even tho ugh two region s both contain 16KB blocks, the fact that they are not contiguous me ans they are separate Erase Block Regions.

3. By definition, symmetrically block devices have only one blocking region.

bit 31 to 16 = z, where the Erase Block(s) within this Region are (z) times 256 bytes in size. The value z = 0 is used for 128 byte block size. e.g. for 64KB block size, z = 0100h = 256 => 256 * 256 = 64K

bit 15 to 0 = y, where y+1 = Number of Erase Blocks of identical size within the Erase Block Region: e.g. y = D15-D0 = FFFFh => y+1 = 64K blocks [maximum number]

y = 0 means no blocking (# blocks = y+1 = "1 block")

Note: y = 0 value must be used with number of block regions of one as indicated

by (x) = 0

in number of bytes

M28W160BT, M28W160BB

15/39

Page 16

M28W160BT, M28W160BB

Table 16. Primary Algorithm-Specific Extended Qu ery Ta bl e

Offset Data Description

(P)h = 35h 0050h

Primary Algorithm extended Query table unique ASCII string “PRI”0052h

0049h (P+3)h = 38h 0031h Major version number, ASCII (P+4)h = 39h 0030h Minor version number, ASCII (P+5)h = 3Ah 0006h Extended Query table contents for Primary Algorithm

0000h

(P+7)h 0000h (P+8)h 0000h

(P+9)h = 3Eh 0001h Supported Functions after Suspend

Read Array, Read Status Register and CFI Query are always supported during Erase or Program operation

(P+A)h = 3Fh 0000h Block Lock Status

(P+B)h 0000h

(P+C)h = 41h 0027h V

(P+D)h = 42h 00C0h V

Defines which bits in the Block Status Register section of the Query are implemented.

bit 0 Chip Erase supported (1 = Yes, 0 = No) bit 1 Erase Suspend supported (1 = Yes, 0 = No) bit 2 Program Suspend (1 = Yes, 0 = No) bit 3 Lock/Unlock supported (1 = Yes, 0 = No) bit 4 Quequed Erase supported (1 = Yes, 0 = No) bit 31 to 5 Reserved; undefined bits are ‘0’

bit 0 Program supported after Erase Suspend (1 = Yes, 0 = No) bit 7 to 1 Reserved; undefined bits are ‘0’

bit 0 Block Lock Status Register Lock/Unlock bit active (1 = Yes, 0 = No) bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No) bit 15 to 2 Reserved for future use; undefined bits are ‘0’

Logic Supply Optimum Program/Erase voltage (highest performance)

bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV

Supply Optimum Program/Erase voltage

bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV

(P+E)h 0000h Reserved

Table 17. Security Code Area

Offset Data Description

81h XXXX 82h XXXX 83h XXXX 84h XXXX

16/39

64 bits unique device number.

Page 17

M28W160BT, M28W160BB

Table 18. DC Characteristics

= 0 to 70°C or –40 to 85°C; VDD = V

Symbol Parameter Test Condition Min Typ Max Unit

Input Leakage Current

Output Leakage Current

I I

Supply Current (Read)

Supply Current (Stand-by or

CC1

Automatic Stand-by) Supply Current

CC2

(Reset)

Supply Current (Program)

CC3

Supply Current (Erase)

CC4

Supply Current

CC5

(Program/Erase Suspend) Program Current

(Read or Stand-by) Program Current

PP1

(Read or Stand-by) Program Current (Reset)

PP2

Program Current (Program)

PP3

Program Current (Erase)

PP4

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

Program Voltage (Program or

PP1

Erase operations) Program Voltage

(Program or Erase

PPH

operations)

Program Voltage

PPLK

(Program and Erase lock-out) VDD Supply Voltage (Program

LKO

and Erase lock-out)

= 2.7V to 3.6V)

DDQ

0V≤ V

= VSS, G = VIH, f = 5MHz

≤ V

≤V

OUT

= V

DDQ

± 0.2V,

± 0.2V

= VSS ± 0.2V

DDQ

Program in progress

= 12V ± 5%

Program in progress

= V

Erase in progress

= 12V ± 5%

Erase in progress

= V

DDQ

± 0.2V,

Erase suspended

> V

≤ V

= VSS ± 0.2V

Program in progress

= 12V ± 5%

Program in progress

= V

Erase in progress

= 12V ± 5%

Erase in progress

= V

≥ 2.7V

DDQ

≥ 2.7V 0.7 V

DDQ

= 100µA, VDD = V

= V

DDQ

= –100µA, VDD = V

DDQ

= V

DDQ

min

min,

±1 µA

±10 µA

10 20 mA 15 50 µA

15 50 µA

10 20 mA

520mA

50 µA

400 µA

5µA 5µA

10 mA

5µA

10 mA

5µA

–0.5 0.4 V –0.5 0.8 V

–0.4 V

DDQ

DDQ DDQ

+0.4 +0.4

0.1 V

–0.1

DDQ

1.65 3.6 V

11.4 12.6 V

V V

17/39

Page 18

M28W160BT, M28W160BB

Table 19. AC Measuremen t Cond itions

Input Rise and Fall Times ≤ 10ns Input Pulse Voltages Input and Output Timing Ref. Voltages

0 to V

DDQ

Figure 5. AC Testing Load Circuit

DDQ

1N914

3.3kΩ

Figure 4. AC Testing Input Output Waveform

DEVICE

UNDER

DDQ

AI00610

Table 20. Capacitance

(1)

(TA = 25 °C, f = 1 MHz)

Symbol Parameter Test Condition Min Max Unit

OUT

Note: 1. Sampled only, not 100% tested.

Input Capacitance Output Capacitance

TEST

CL includes JIG capacitance

= 0V

CL = 50pF

6pF

12 pF

OUT

AI00609B

18/39

Page 19

M28W160BT, M28W160BB

Table 21. Read AC Characteristics

(1)

(TA = 0 to 70°C or –40 to 85°C)

Symbol Alt P arameter

AVAV

AVQV

(2)

AXQX

(2)

EHQX

(2)

EHQZ

(3)

ELQV

(2)

ELQX

(2)

GHQX

(2)

GHQZ

(3)

GLQV

(2)

GLQX

PHQV

(2,4)

PLPH

Note: 1. See AC Testing Measurement condit i ons for timi ng measurements.

2. Sampled only, not 100% tested.

3. G

may be delayed by up to t

4. The device Reset is possibl e but not guara nteed if t

ACC

OLZ

PWH

Address Valid to Next Address Valid 90 100 ns Address Valid to Output Valid 90 100 ns

Address Transition to Output Transition 0 0 ns Chip Enable High to Output Transition 0 0 ns Chip Enable High to Output Hi-Z 25 30 ns Chip Enable Low to Output Valid 90 100 ns Chip Enable Low to Output Transition 0 0 ns

Output Enable High to Output Transition 0 0 ns Output Enable High to Output Hi-Z 25 30 ns Output Enable Low to Output Valid 30 35 ns Output Enable Low to Output Transition 0 0 ns

Reset High to Output Valid 150 150 ns Reset Pulse Width 100 100 ns

- t

ELQV

after the fal ling edge of E without increasi ng t

GLQV

PLPH

< 100ns.

M28W160B

90 100

= 2.7V to 3.6V

= 2.7V min

DDQ

= 2.7V to 3.6V

= 1.65V min

DDQ

Min Max Min Max

ELQV

Unit

19/39

Page 20

M28W160BT, M28W160BB

Figure 6. Read AC Waveforms

AI00619

tAXQX

tAVAV

VALID

tAVQV

tEHQX

tELQV

tEHQZ

tELQX

tGHQX

tGLQV

tGHQZ

tGLQX

VALID

STANDBY

DATA VALID

ENABLED

OUTPUTS

20/39

A0-A19

tPHQV

ADDRESS VALID

AND CHIP ENABLE

POWER-UP

AND STANDBY

DQ0-DQ15

Note: Wri te Enable (W) = High.

Page 21

M28W160BT, M28W160BB

Table 22. Write AC Characteristics, Write Enable Controlled

(TA = 0 to 70°C or –40 to 85°C)

Symbol Alt Parameter

AVAV

AVWH

DVWH

ELWL

PHWL

(2, 3)

PLPH

(2, 4)

PLRH

(2, 5)

QVVPL

QVWPL

VPHWH

WHAX

WHDX

WHEH

WHGL

(2)

t t t t t t

VPS

t t t

Write Cycle Time 90 100 ns

Address Valid to Write Enable High 50 50 ns

Data Valid to Write Enable High 50 50 ns

Chip Enable Low to Write Enable Low 0 0 ns

Reset High to Write Enable Low 90 100 ns

Reset Pulse Width 100 100 ns

Reset Low to Program/Erase Abort 30 30 µs

Output Valid to VPP Low Data Valid to Write Protect Low 0 0 ns VPP High to Write Enable High Write Enable High to Address Transition 0 0 ns

Write Enable High to Data Transition 0 0 ns

Write Enable High to Chip Enable High 0 0 ns

Write Enable High to Output Enable Low

DDQ

Min Max Min Max

200 200 ns

30 30 ns

(1)

M28W160B

90 100

= 2.7V to 3.6V

= 2.7V min

= 2.7V to 3.6V

= 1.65V min

DDQ

Unit

00ns

WHWL

WLWH

WPHWH

Note: 1. See AC Testing Measurement condit i ons for timi ng measurements.

2. Sampled only, not 100% tested.

3. The device Reset is possibl e but not guara nteed if t

4. The reset will co m plete wit hi n 100ns if RP

5. Appl i cable if V

WPH

Write Enable High to Write Enable Low 30 30 ns Write Enable Low to Write Enable High 50 50 ns

Write Protect High to Write Enable High 50 50 ns

is seen as a logic i nput (VPP < 3.6V ).

< 100ns.

is asserted while not in Program nor i n Erase mo de.

PLPH

21/39

Page 22

M28W160BT, M28W160BB

Figure 7. Write AC Waveforms, W Controlled

AI03572

tWHAX

PROGRAM OR ERASE

tAVAV

VALIDA0-A19

tAVWH

tWHGL

tWHQV

STATUS REGISTER

tQVWPL

tQVVPL

READ

1st POLLING

STATUS REGISTER

OR DATA INPUT

CONFIRM COMMAND

22/39

tELWL tWHEH

tWHWL

tWLWH

tWHDXtDVWH

DQ0-DQ15 COMMAND CMD or DATA

tPHWL

tWPHWH

tVPHWH

POWER-UP AND

SET-UP COMMAND

Page 23

M28W160BT, M28W160BB

Table 23. Write AC Characteristics, Chip Enable Controlled (TA = 0 to 70°C or –40 to 85°C)

Symbol Alt Parameter

(2)

t t t t

CPH

Write Cycle Time 90 100 ns

Address Valid to Chip Enable High 50 50 ns

Data Valid to Chip Enable High 50 50 ns

Chip Enable High to Address Transition 0 0 ns

Chip Enable High to Data Transition 0 0 ns

Chip Enable High to Chip Enable Low 30 30 ns Chip Enable High to Output Enable Low 30 30 ns

t t

Chip Enable High to Write Enable High 0 0 ns

Chip Enable Low to Chip Enable High 50 50 ns

Reset High to Chip Enable Low 90 100 ns

Reset Pulse Width 100 100 ns

Reset Low to Program/Erase Abort 30 30 µs

Output Valid to VPP Low Data Valid to Write Protect Low 0 0 ns

VPS

VPP High to Chip Enable High Write Enable Low to Chip Enable Low 0 0 ns

Write Protect High to Chip Enable High 50 50 ns

is seen as a logic i nput (VPP < 3.6V ).

< 100ns.

is asserted while not in Program nor i n Erase mo de.

PLPH

AVAV

AVEH

DVEH

EHAX

EHDX

EHEL

EHGL

EHWH

ELEH

PHEL

(2, 3)

PLPH

(2, 4)

PLRH

(2, 5)

QVVPL

QVWPL

VPHEH

WLEL

WPHEH

Note: 1. See AC Testing Measurement condit i ons for timi ng measurements.

2. Sampled only, not 100% tested.

3. The device Reset is possibl e but not guara nteed if t

4. The reset will co m plete wit hi n 100ns if RP

5. Appl i cable if V

(1)

M28W160B

90 100

= 2.7V to 3.6V

= 2.7V min

DDQ

= 2.7V to 3.6V

= 1.65V min

VDDQ

Unit

Min Max Min Max

00ns

200 200 ns

23/39

Page 24

M28W160BT, M28W160BB

Figure 8. Write AC Waveforms, E Controlled

AI03573

tEHAX

PROGRAM OR ERASE

tAVAV

VALIDA0-A19

tAVEH

tEHGL

tEHQV

CMD or DATA STATUS REGISTER

tQVWPL

tQVVPL

READ

1st POLLING

STATUS REGISTER

OR DATA INPUT

CONFIRM COMMAND

24/39

tWLEL tEHWH

tVPHEH

POWER-UP AND

SET-UP COMMAND

tWPHEH

tELEH

tEHDX

tDVEH

tPHEL

DQ0-DQ15 COMMAND

tEHEL

Page 25

Figure 9. Reset AC Waveform

M28W160BT, M28W160BB

Reset during Read Mode

tPLPH

tPHQV

Reset during Program with t

PLPH

Abort

Complete

tPLRH

tPLPH

Reset during Program/Erase with t

Abort

Complete

Reset

tPLRH

tPLPH

≤

PLPH

PLRH

tPHWL

tPHEL

> t

PLRH

tPHWL

tPHEL

AI03537

25/39

Page 26

M28W160BT, M28W160BB

Figure 10. Program Flowchart an d Ps e ud o C od e

Start

Write 40h or 10h

Command

Write Address

& Data

Read Status

b7 = 1

YES

b3 = 0

YES

b4 = 0

YES

b1 = 0

Suspend

Program to Protected

Block Error (1, 2)

YES

Suspend

VPP Invalid

Error (1, 2)

Program

Error (1, 2)

Program instruction: – write 40h or 10h command – write Address & Data (memory enters read status state after the Program instruction)

do: – read status register (E or G must be toggled) if PES instruction given execute suspend program loop

Loop

while b7 = 1

If b3 = 1, VPP invalid error: – error handler

If b4 = 1, Program error: – error handler

If b1 = 1, Program to protected block error: – error handler

YES

End

Note: 1. Status check of b1 (P ro te cte d Bl oc k) , b 3 ( VPP Invalid) and b4 (Program Error) can be made after each program operationor after a

sequence.

2. If an er ror is foun d, the Status Register m ust be cleared (CLRS instructi on) before fu rther P/E. C. operations.

AI03538

26/39

Page 27

Figure 11. Dou bl e W or d Pr ogram Flowc ha rt a nd Pseudo Code

Start

M28W160BT, M28W160BB

Write 30h

Command

Write Address 1

& Data 1 (3)

Write Address 2

& Data 2 (3)

Read Status

b7 = 1

YES

b3 = 0

YES

b4 = 0

Suspend

YES

Suspend

VPP Invalid

Error (1, 2)

Program

Error (1, 2)

DPG instruction: – write 30h command – write Address 1 & Data 1 (3) – write Address 2 & Data 2 (3) (memory enters read status state after the Program instruction)

do: – read status register (E or G must be toggled) if PES instruction given execute DPG suspend loop

Loop

while b7 = 1

If b3 = 1, VPP invalid error: – error handler

If b4 = 1, Program error: – error handler

YES

b1 = 0

End

Note: 1. Status check of b1 (Protected Blo ck ), b3 (VPP Invalid) and b4 (Program E rror) can be made af ter each program operation or af ter

a sequence.

2. If an er ror is foun d, the Status Register m ust be cleared (CLRS instructi on) before fu rther P/E. C. operations.

3. Address 1 and Address 2 must be consecuti ve addresses differin g only for bit A0 .

YES

Program to Protected

Block Error (1, 2)

If b1 = 1, Program to protected block error: – error handler

AI03539

27/39

Page 28

M28W160BT, M28W160BB

Figure 12. Program or DPG Suspend & Resume Flowchart and Pseudo Code

Start

Write B0h Command

Write 70h

Command

Read Status

b7 = 1

YES

b2 = 1

YES

Write a read

Command

Read data from

another address

Write D0h Command

Program Continues

Program Complete

Write FFh Command

Read Data

PES instruction: – write B0h command

do: – read status register (E or G must be toggled)

while b7 = 1

If b2 = 0 Program completed

PER instruction: – write D0h command to resume the program – if the program operation completed then this is not necessary. The device returns to Read Array as normal (as if the Program/Erase suspend was not issued).

28/39

AI03540

Page 29

Figure 13. Erase Flowchart and Pseudo Code

Start

M28W160BT, M28W160BB

Write 20h

Command

Write Block Address

& D0h Command

Read Status

b7 = 1

b3 = 0

b4, b5 = 0

b5 = 0 Erase Error (1)

YES

Suspend

Sequence Error (1)

VPP Invalid

Error (1)

Command

EE instruction: – write 20h command – write Block Address (A12-A20) & command D0h (memory enters read status state after the EE instruction)

do: – read status register (E or G must be toggled) if PES instruction given execute suspend erase loop

YES

Suspend

Loop

while b7 = 1

If b3 = 1, VPP invalid error: – error handler

If b4, b5 = 1, Command sequence error: – error handler

If b5 = 1, Erase error: – error handler

YES

b1 = 0

End

Note: 1. If an error is foun d, the Status Register m ust be cleared (CLRS instructi on) before further P/E . C. operations.

YES

Erase to Protected

Block Error (1)

If b1 = 1, Erase to protected block error: – error handler

AI03541

29/39

Page 30

M28W160BT, M28W160BB

Figure 14. Erase Suspend & Resume Flowchart an d Pseud o Code

Start

Write B0h Command

Write 70h

Command

Read Status

b7 = 1

YES

b6 = 1

YES

Read data from

another block

Program

Write D0h Command

Erase Continues

Erase Complete

Write FFh Command

Read Data

PES instruction: – write B0h command

do: – read status register (E or G must be toggled)

while b7 = 1

If b6 = 0, Erase completed

PER instruction: – write D0h command to resume erasure – if the erase operation completed then this is not necessary. The device returns to Read Array as normal (as if the Program/Erase suspend was not issued).

30/39

AI03549

Page 31

M28W160BT, M28W160BB

Figure 15. Command Interface and Program E rase Con trolle r Flowchart (a)

WAIT FOR

COMMAND

WRITE (1)

90h

YES

READ

STATUS

READ

SIGNATURE

98h

YES

CFI

QUERY

70h

YES

READ

STATUS

50h

YES

CLEAR

STATUS

40h or

10h

PROGRAM

SET-UP

YES

30h

YES

DPG

SET-UP

20h

YES

ERASE

SET-UP

FFh

READ

ARRAY

YES

D0h

YES

ERASE

COMMAND

ERROR

AI03547

Note: 1. If no comman d i s written, the C om m and Interface re m ai ns in its previous valid state. Upon power-u p, on exit f rom power-dow n or

falls below V

if V

2. P/E.C. status (Ready or Bus y) is read o n Status Regi ster bit 7.

, the Command Interface defaults to Read Arr ay mode.

LKO

31/39

Page 32

M28W160BT, M28W160BB

Figure 16. Command Interface and Program Erase Controller Flowchart (b)

READ

STATUS

READ

SIGNATURE

CFI

QUERY

SUSPENDED

YES

ERASE

YES

70h

90h

98h

YES

ERASE

READY

(2)

B0h

YES

ERASE

SUSPEND

READY

(2)

READ

STATUS

(READ STATUS)

READ

STATUS

PROGRAM

SET-UP

DPG

SET-UP

READ

ARRAY

YES

40h or

10h

YES

30h

NO (READ STATUS)

D0h

YES

Note: 2. P/E.C. status (Ready or Busy) is read on Status Register bit 7.

32/39

ERASE

RESUME

AI03548

Page 33

M28W160BT, M28W160BB

Figure 17. Command Interface and Program E rase Con trolle r Flowchart (c)

YES

PROGRAM

SUSPENDED

YES

PROGRAM

READY

(2)

B0h

YES

PROGRAM

SUSPEND

READY

(2)

(READ STATUS)

READ

STATUS

READ

STATUS

READ

SIGNATURE

CFI

QUERY

READ

ARRAY

Note: 2. P/E.C. status (Ready or Busy) is read on Status Register bit 7.

YES

70h

90h

98h

D0h

YES

PROGRAM

RESUME

READ

STATUS

(READ STATUS)

AI03545

33/39

Page 34

M28W160BT, M28W160BB

Table 24. Ordering Information Scheme

Example: M28W160BT 90 N 6 T

Device Type

M28

Operating Voltage

W = V

Device Function

160B = 16 Mbit (1Mb x16), Boot Block

Array Matrix

T = Top Boot B = Bottom Boot

Random Speed

90 = 90 ns 100 = 100 ns

Package

N = TSOP48: 12 x 20 mm

GB = µBGA46: 0.75 mm pitch

= 2.7V to 3.6V; V

= 1.65V or 2.7V

DDQ

Temperature Range

1 = 0 to 70 °C 6 = –40 to 85 °C

Option

T = Tape & Reel Packing

Devices are shipped from the factory with the memory content bits erased to ’1’.

Table 25. Daisy Chain Ordering Scheme

Example: M28W160B -GB T

Device Type

M28W160B

Daisy Chain

-GB = µBGA46: 0.75 mm pitch

Option

T = Tape & Reel Packing

For a list of available options (Speed, Pac kage, etc...) or for furthe r information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.

34/39

Page 35

Table 26. Revision History

Date Revision Details

July 1999 First Issue

M28W160BT, M28W160BB

09/21/99

10/20/99

Parameter Block Erase Typ. specification change (Table 11)

Added t

WHGL

and t

(Tables 22, 23 and Figures 7, 8)

EHGL

µBGA Package Mechanical Data change (Table 27)

Daisy Chain diagrams, Package and PCB Connections, added (Figures 20, 21)

Access Time conditions change

Reset mode function change to remove Power Down mode

Instructions description clarification

Change of Parameter Block Erase value (Table 11)

Block Protections description clarification

02/09/00

Security Code Area definition change (Table 17)

and I

CC2

value change (Tables 22, 23)

PLRH

value change (Table 18)

CC3

Program, Erase, Command Interface flowcharts clarification (Figures 10, 11, 12, 13, 14, 15, 16, 17)

µBGA Package Mechanical Data change (Table 28)

µBGA Package Outline diagram change (Figure 19)

Document type: from Preliminary Data to Data Sheet

04/19/00

Daisy Chain part numbering defined

µBGA Daisy Chain diagrams, Package and PCB Connections re-designed (Figure 20, 21)

05/17/00 µBGA Package Outline diagram change (Figure 19)

35/39

Page 36

M28W160BT, M28W160BB

Table 27. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Me chan ical Data

Symb

Typ Min Max Typ M in M ax

A 1.20 0.0472 A1 0.05 0.15 0.0020 0.0059 A2 0.95 1.05 0.0374 0.0413

B 0.17 0.27 0.0067 0.0106

C 0.10 0.21 0.0039 0.0083

D 19.80 20.20 0.7795 0.7953 D1 18.30 18.50 0.7205 0.7283

E 11.90 12.10 0.4685 0.4764

e 0.50 – – 0.0197 – –

L 0.50 0.70 0.0197 0.0276 α 0° 5° 0° 5°

N48 48

CP 0.10 0.0039

mm inch es

Figure 18. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline

1 N

N/2

DIE

TSOP-a

Drawing is not to scale.

LA1 α

36/39

Page 37

M28W160BT, M28W160BB

Table 28. µBGA46 - 8 x 6 balls, 0.75 mm pitch, Package Mechanical Data

Symbol

Typ Min Max Typ M in Max

A 1.000 0.0394 A1 0.180 0.0071 A2 0.700 – – 0.0276 – –

b 0 .350 0.300 0.400 0.0138 0.0118 0.0157

D 6 .390 6.340 6.440 0.2516 0.2496 0.2535

D1 5 .250 – – 0.2067 – –

ddd 0.008 0.0003

e 0 .750 – – 0.0295 – –

E 6.370 6.320 6.42 0 0.2508 0.2488 0.2528 E1 3.750 – – 0.1476 – –

FD 0.570 – – 0.0224 – – FE 1 .310 – – 0.0516 – – SD 0.375 – – 0.0148 – –

mm inch

SE 0.375 – – 0.01 48 – –

Figure 19. µBGA46 - 8 x 6 balls, 0.75 mm pitch, Bottom View Package Outline

E1E

BALL "A1"

ddd

Drawing is not to scale.

BGA-G05

37/39

Page 38

M28W160BT, M28W160BB

Figure 20. µBGA46 Daisy Chain - Package Connections (Top view through packag e)

87654321

AI03298

Figure 21. µBGA46 Daisy Chain - PCB Connections (Top view through package)

87654321

START

POINT

END

POINT

38/39

AI3299

Page 39

M28W160BT, M28W160BB

Information furnished is believed to be accurate and reliable. However, STMicroelec tronics as sumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implic ation or o th erwise u nder any pat ent or pat ent righ ts of STMicroelectron i cs. Specifications m entioned i n this publication are s ubject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as c ritical components in li f e support dev i ces or systems without express writ t en approval of STMicroel ectronics.

The ST log o i s registered trademark of STMic roelectronics

 2000 STMicroel e ctronics - All Ri ghts Rese rved

All other names are the property of their respective owners.

Australi a - Brazil - C hi na - Finland - F rance - Germ any - Hong Kong - India - Italy - Jap an - Malaysi a - M al ta - Morocco -

Singapor e - Spain - Sweden - Switz erl and - Unit ed K i ngdom - U.S.A.

STMicroelect ro n ics GRO UP OF COMPANI ES

http://www.st.com

39/39

Datasheet M28W160BT, M28W160BB Datasheet (SGS Thomson Microelectronics)

Specifications and Main Features

Frequently Asked Questions

User Manual