Page 1
64K (8K x 8) LOW VOLTAGE PARALLEL EEPROM
with SOFTWARE DATA PROTECTION
FASTACCESSTIME: 200ns
SINGLELOW VOLTAGEOPERATION
LOW POWER CONSUMPTION
FASTWRITE CYCLE:
– 64 BytesPage Write Operation
– Byte or Page Write Cycle: 3ms Max
ENHANCED END OF WRITE DETECTION:
– Ready/BusyOpenDrain Output
(only on theM28LV64)
– Data Polling
–ToggleBit
PAGE LOAD TIMER STATUS BIT
HIGHRELIABILITYSINGLE POLYSILICON,
CMOSTECHNOLOGY:
– Endurance>100,000 Erase/Write Cycles
– Data Retention >40 Years
JEDECAPPROVEDBYTEWIDEPIN OUT
SOFTWARE DATAPROTECTION
TheM28LV64 is replacedby the
M28C64-xxW
28
1
PDIP28 (P) PLCC32 (K)
28
1
SO28 (MS)
300 mils
Figure 1. Logic Diagram
M28LV64
NOT FOR NEW DESIGN
TSOP28 (N)
8x13.4mm
DESCRIPTION
The M28LV64 is an 8K x 8 low power Parallel
EEPROM fabricated with SGS-THOMSON pro-
V
CC
prietary single polysilicon CMOS technology.The
device offersfast accesstime with low power dissipationand requiresa 2.7Vto 3.6Vpower supply.
A0-A12
Table 1. Signal Names
A0 - A12 Address Input
DQ0 - DQ7 Data Input / Output
W Write Enable
E Chip Enable
G Output Enable
RB Ready / Busy
V
CC
V
SS
May 1997 1/18
This isinformation on a product still in production but not recommended for new designs.
Supply Voltage
Ground
Note: * RB function is only available on the M28LV64.
W
13
M28LV64
E
G
V
SS
8
DQ0-DQ7
RB *
AI01538B
Page 2
M28LV64
Figure2A. DIPPin Connections
RB V
1
A12
2
A7
3
A6
4
A5
5
A4
6
A3
7
8
9
10
11
M28LV64
A2
A1
A0
DQ0
12
DQ2
13
14
SS
Warning: NC =Not Connected.
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AI01539B
CC
W
NC
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V
Figure2B. LCC Pin Connections
CC
NC
DU
32
W
V
A8
A9
A11
NC
G
25
A10
E
DQ7
DQ6
DQ4
DQ5
AI01540B
RB
A7
A12
1
A6
A5
A4
A3
A2
9
M28LV64
A1
A0
NC
DQ0
17
SS
V
DQ1
DQ2DUDQ3
Warning: NC = Not Connected, DU = Don’t Use.
Figure2C. SO Pin Connections
RB
A12
DQ0
DQ1
DQ2
V
SS
Warning: NC =Not Connected.
A7
A6
A5
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
M28LV64
8
9
10
11
12
13
14
28
27
26
25
24
23 A11
22
21
20
19
18
17
16
15
AI01541B
V
CC
W
NC
A8
A9
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Figure2D. TSOPPin Connections
G
22
A11
A9
A8
NC
W
V
CC
RB
28
1
M28LV64
A12
A7
A6
A5
A4
A3
78
Warning: NC = Not Connected.
21
15
14
AI01542B
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
V
SS
DQ2
DQ1
DQ0
A0
A1
A2
2/18
Page 3
M28LV64
Table 2. Absolute Maximum Ratings
(1)
Symbol Parameter Value Unit
T
A
T
STG
V
CC
V
IO
V
V
ESD
Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
2. 100pF through1500Ω; MIL-STD-883C, 3015.7
Ambient Operating Temperature – 40 to 85 °C
Storage Temperature Range – 65 to 150 °C
Supply Voltage –0.3 to 6.5 V
Input/Output Voltage – 0.3 to VCC+0.6 V
Input Voltage –0.3 to 6.5 V
I
Electrostatic Discharge Voltage (Human Bodymodel)
cause permanent damage to the device. These are stress ratings only and operation ofthe deviceat these or any otherconditions
above thoseindicated in the Operating sections of this specification isnot implied. Exposure to Absolute Maximum Rating
conditions for extended periods mayaffect device reliability. Refer also to theSGS-THOMSON SURE Program and other
relevant quality documents.
(2)
4000 V
Figure3. Block Diagram
RB E G W
A6-A12
(Page Address)
A0-A5
VPPGEN RESET
ADDRESS
LATCH
ADDRESS
LATCH
Y DECODE
X DECODE
CONTROL LOGIC
64K ARRAY
SENSE ANDDATA LATCH
I/O BUFFERS
DQ0-DQ7
PAGE
LOAD
TIMER STATUS
TOGGLE BIT
DATA POLLING
AI01355
3/18
Page 4
M28LV64
Table 3. Operating Modes
Mode E G W DQ0 - DQ7
Standby 1 X X Hi-Z
Output Disable X 1 X Hi-Z
Write Disable X X 1 Hi-Z
Read 0 0 1 Data Out
Write 0 1 0 Data In
Note: 1. 0 = VIL;1=VIH;X=VILor VIH.
DESCRIPTION (cont’d)
The M28LV64 outputs the Ready/Busy write
status,theM28LV64-aaaX(aaa=access time)has
no Ready/Busy status and the relevant RB pin is
Not Connected (NC). The circuit has been designed to offer a flexible microcontroller interface
featuring both hardware and software handshaking with Ready/Busy,Data Polling and ToggleBit.
The M28LV64supports 64byte page writeoperation. A Software Data Protection (SDP) is also
possibleusing the standard JEDECalgorithm.
(1)
OPERATION
In order topreventdata corruptionandinadvertent
writeoperationsan internalV
Write operation if V
is below VWI(see Table 6).
CC
comparatorinhibits
CC
Accesstothememory inwritemodeisallowedafter
a power-upas specifiedin Table6.
Read
TheM28LV64isaccessedlikea staticRAM. When
E and G are low with W high, the data addressed
ispresented on the I/O pins. The I/Opins are high
impedancewhen eitherG or E is high.
Write
PINDESCRIPTION
Addresses (A0-A12). The address inputs select
an 8-bit memory location during a read or write
operation.
Chip Enable (E). The chip enable input must be
lowto enableallread/writeoperations.When Chip
Enableis high, power consumptionis reduced.
OutputEnable (G). TheOutput Enableinput controls the data output buffers and is used to initiate
readoperations.
DataIn/Out (DQ0 - DQ7).Data iswritten toorread
fromthe M28LV64 throughthe I/O pins.
WriteEnable(W).The WriteEnableinputcontrols
the writing of data to the M28LV64.
Ready/Busy (RB). Ready/Busy is an open drain
output that can be used to detect the end of the
internalwritecycle(thisfunctionappliesonly tothe
M28LV64).
Write operationsare initiated when both W and E
are low andG is high.TheM28LV64supports both
E and W controlled write cycles. The Address is
latched by the falling edge of E or W which ever
occurslast andthe Dataon the rising edge of E or
W which ever occurs first. Once initiated the write
operationis internallytimed untilcompletion.
Page Write
Page write allows up to 64 bytes to be consecutively latched into the memory prior to initiating a
programmingcycle. Allbytes must be located in a
single page address, that is A6-A12 must be the
samefor all bytes. Thepage writecan beinitiated
duringany byte writeoperation.
Following the first byte write instruction the host
may send another address and data with a minimum data transfer rate of t
(see Figure 13).
WHWH
If atransitionofEor Wisnotdetectedwithin t
the internal programmingcycle will start.
WHWH
4/18
Page 5
M28LV64
Microcontroller ControlInterface
The M28LV64provides two write operation status
bitsandonestatuspinthatcanbeusedto minimize
the system write cycle. Thesesignals are available
on the I/O port bits DQ7 or DQ6 of the memory
duringprogrammingcycleonly,oras theRBsignal
on a separatepin.
Figure4. Status Bit Assignment
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
DP TB PLTS Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
DP =Data Polling
TB = ToggleBit
PLTS = Page Load Timer Status
Data Polling bit (DQ7). During the internal write
cycle,any attempt to read the last bytewritten will
produce on DQ7 the complementary value of the
previouslylatched bit. Once the write cycle is finished the true logic value appears on DQ7 in the
readcycle.
Toggle bit (DQ6). The M28LV64 offers another
way for determiningwhen the internal write cycle
iscompleted.DuringtheinternalErase/Writecycle,
DQ6 will toggle from ”0” to ”1” and ”1” to ”0” (the
first read value is ”0”) on subsequent attempts to
read the memory. When the internalcycle is completed the togglingwill stopand the devicewill be
accessiblefor a new Read or Writeoperation.
Page Load Timer Status bit (DQ5). In the Page
Write mode data may be latched by E or W up to
100µs after theprevious byte. Upto 64bytes may
be input. The Data output (DQ5) indicates the
status of the internal Page Load Timer. DQ5 may
be read by asserting Output Enable Low (t
PLTS
DQ5 Low indicates the timer is running,High indicates time-out after which the write cyclewill start
and no new data may be input.
Ready/Busy p in (avail able only on the
M28LV64).TheRB pinprovidesa signalat itsopen
drain output which is low during the erase/write
cycle,butwhichis releasedatthecompletionof the
programmingcycle.
SoftwareData Protection
The M28LV64 offers a software controlled write
protection facility that allows the user to inhibit all
write modesto thedevice includingthe ChipErase
instruction. This can be useful in protecting the
memory from inadvertent write cycles that may
occurdue touncontrolled bus conditions.
The M28LV64isshippedasstandardinthe”unprotected” state meaning that the memory contents
can be changed as requiredby the user.After the
Software Data Protection enable algorithm is issued, the device enters the ”Protect Mode” of
operation where no further write commands have
any effect on the memory contents. The device
remains in this mode until a valid Software Data
Protection (SDP) disable sequence is received
whereby the device reverts to its ”unprotected”
state. The Software Data Protection is fully nonvolatile and is not changed by power on/off sequences.
Toenable the SoftwareData Protection(SDP) the
devicerequirestheusertowrite(withaPageWrite)
three specificdata bytes to three specificmemory
locations as per Figure 5. Similarly to disable the
Software Data Protection the user has to write
specificdata bytesintosixdifferentlocationsasper
Figure 6 (with a Page Write). This complexseries
ensures that the user will never enable or disable
the SoftwareData Protectionaccidentally.
).
5/18
Page 6
M28LV64
Figure5. Software DataProtection EnableAlgorithmand MemoryWrite
WRITE AAh in
Address 1555h
Page
Write
Instruction
(Note 1)
Note: 1.MSB Address bits (A6 to A12) differduringthese specific PageWrite operations.
WRITE 55h in
Address 0AAAh
WRITE A0h in
Address 1555h
SDP is set
SDP ENABLEALGORITHM
Page
Write
Instruction
(Note 1)
Figure6. Software DataProtection Disable Algorithm
WRITE AAh in
Address 1555h
WRITE 55h in
Address 0AAAh
WRITE A0h in
Address 1555h
Write
(1 up to 64 bytes)
WRITE IN
WHEN SDP IS SET
Page
MEMORY
AI01356B
WRITE
is enabled
Page
Write
Instruction
WRITE AAh in
Address 1555h
WRITE 55hin
Address 0AAAh
WRITE 80hin
Address 1555h
WRITE AAh in
Address 1555h
WRITE 55hin
Address 0AAAh
WRITE 20hin
Address 1555h
Unprotected State
AI01357
6/18
Page 7
M28LV64
AC MEASUREMENT CONDITIONS
Input Rise and Fall Times ≤ 20ns
Input Pulse Voltages 0V to V
CC
-0.3V
Figure 8. AC Testing Equivalent Load Circuit
V
CC
Input and Output Timing Ref. Voltages 1.5V
Note that Output Hi-Z is definedas the pointwhere data
is no longer driven.
DEVICE
UNDER
Figure7. ACTesting Input Output Waveforms
VCC–0.3V
0.5 V
CC
0V
AI01274
Table 4. Capacitance
(1)
(TA=25°C, f = 1MHz )
TEST
1.3kΩ
CLincludes JIG capacitance
Symbol Parameter TestCondition Min Max Unit
C
IN
C
OUT
Note: 1. Sampled only, not 100%tested.
Input Capacitance VIN=0V 6 pF
Output Capacitance V
=0V 12 pF
OUT
1.8kΩ
OUT
CL= 100pF
AI01396
Table 5. Read Mode DC Characteristics
= 0 to70°C or –40 to 85°C; VCC= 2.7V to 3.6V)
(T
A
Symbol Parameter TestCondition Min Max Unit
I
I
LO
I
CC
I
CC2
V
V
V
V
Note: 1. All I/O’s open circuit.
Table 6. Power Up Timing
Input Leakage Current 0V ≤ VIN≤ V
LI
Output Leakage Current 0V ≤ VIN≤ V
E=V
,G=VIL, f = 5 MHz, VCC= 3.3V 8 mA
Supply Current
(1)
(CMOS inputs)
Supply Current (Standby)
(1)
CMOS
Input Low Voltage – 0.3 0.6 V
IL
Input High Voltage 2 VCC+0.5 V
IH
Output Low Voltage IOL= 1 mA 0.2 V
OL
Output High Voltage IOH= 1mA 0.8 V
OH
(1)
(TA=0 to 70°C or –40 to 85°C; VCC= 2.7V to 3.6V)
IL
,G=VIL, f = 5 MHz, VCC= 3.6V 10 mA
E=V
IL
E>V
CC
CC
–0.3V 20 µA
CC
CC
Symbol Parameter Min Max Unit
t
PUR
t
PUW
V
WI
Note: 1. Sampled only, not 100%tested.
TimeDelay to Read Operation 1 µs
TimeDelay to Write Operation (once VCC≥ 4.5V) 15 ms
Write Inhibit Threshold 1.5 2.5 V
1019 µA
10 µA
CC
V
V
7/18
Page 8
M28LV64
Table 7. Read Mode AC Characteristics
=0to70°C or–40 to 85°C; VCC= 2.7V to 3.6V)
(T
A
Symbol Alt Parameter Test Condition
Address Validto Output
t
ACC
Valid
Chip Enable Low to Output
t
CE
Valid
Output Enable Low to
t
OE
Output Valid
Chip Enable High to
t
DF
Output Hi-Z
E=V
G=V
E=V
G=V
,G=V
IL
t
EHQZ
t
AVQV
t
ELQV
t
GLQV
(1,2)
M28LV64
-200 -250 -300
Unit
min max min max min max
IL
IL
IL
IL
200 250 300 ns
200 250 300 ns
100 150 150 ns
055060060ns
(1,2)
t
GHQZ
(2)
t
AXQX
Notes: 1. Output Hi-Z is defined as thepoint at which datais nolonger driven.
2. Guaranted, not 100% sampled.
Output Enable High to
t
DF
Output Hi-Z
Address Transitionto
t
OH
Output Transition
E=V
E=V
,G=V
IL
IL
Figure9. Read Mode AC Waveforms
A0-A12
tAVQV tAXQX
E
tGLQV tEHQZ
G
tELQV
DQ0-DQ7
VALID
055060060ns
000ns
IL
tGHQZ
DATA OUT
Hi-Z
Note: Write Enable (W)= High
8/18
AI00749B
Page 9
M28LV64
Table 8. Write ModeAC Characteristics
= 0 to70°C or –40 to 85°C; VCC= 2.7V to 3.6V)
(T
A
Symbol Alt Parameter TestCondition Min Max Unit
t
AVWL
t
AVEL
t
ELWL
t
GHWL
t
GHEL
t
WLEL
t
WLAX
t
ELAX
t
WLDV
t
ELDV
t
ELEH
t
WHEH
t
WHGL
t
EHGL
t
EHWH
t
t
t
t
t
t
t
t
t
AS
t
AS
CES
OES
OES
WES
t
AH
t
AH
t
DV
t
DV
t
WP
CEH
OEH
OEH
WEH
Address Validto Write Enable Low E= VIL,G=V
Address Validto Chip Enable Low G = VIH,W=V
Chip Enable Low to Write Enable Low G = V
Output Enable High to Write Enable
Low
Output Enable High to Chip EnableLow W = V
Write Enable Low to Chip Enable Low G = V
E=V
IH
IL
IL
IH
IH
IL
0ns
0ns
0ns
0ns
0ns
0ns
Write Enable Low to AddressTransition 100 ns
Chip EnableLow toAddress Transition 100 ns
Write Enable Low to Input Valid E= VIL,G=V
Chip Enable Low to Input Valid G = VIH,W=V
IH
IL
1 µs
1 µs
Chip Enable Low to Chip Enable High 100 1000 ns
Write Enable Highto Chip EnableHigh 0 ns
Write Enable Highto Output Enable
Low
0ns
Chip Enable High to Output Enable Low 0 ns
Chip Enable High to Write Enable High 0 ns
t
WHDX
t
EHDX
t
WHWL
t
WLWH
t
WHWH
t
WHRH
t
WHRL
t
EHRL
t
DVWH
t
DVEH
Note: 1.With a 3.3 kΩ external pull-up resistor.
t
t
t
WPH
t
t
BLC
t
t
t
t
t
DH
DH
WP
WC
DB
DB
DS
DS
Write Enable Highto Input Transition 0 ns
Chip Enable High to Input Transition 0 ns
Write Enable Highto Write Enable Low 50 ns
Write Enable Low to Write EnableHigh 100 ns
Byte Load RepeatCycle Time 0.2 100 µs
Write Cycle Time 3 ms
Write Enable Highto Ready/Busy Low Note 1 150 ns
Chip Enable High to Ready/Busy Low Note 1 150 ns
Data Validbefore Write Enable High 50 ns
Data Validbefore Chip Enable High 50 ns
9/18
Page 10
M28LV64
Figure10. Write Mode AC Waveforms- Write Enable Controlled
tAVWL
tELWL
VALID
tWLAX
tWLDV
DATA IN
A0-A12
E
G
tGHWL
W
DQ0-DQ7
RB
Figure11. Write Mode AC Waveforms - Chip Enable Controlled
tWHEH
tWHGLtWLWH
tWHWL
tWHDXtDVWH
tWHRL
AI00750
10/18
A0-A12
E
G
W
DQ0-DQ7
RB
tAVEL
tGHEL
tWLEL
VALID
tELAX
tELDV
tELEH
tEHGL
tEHWH
DATA IN
tEHDXtDVEH
tEHRL
AI00751
Page 11
Figure12. Page WriteMode AC Waveforms - WriteEnable Controlled
M28LV64
A0-A12
E
G
W
DQ0-DQ7
DQ5
RB
tWLWH
Addr 0
tWHWL
Byte 0 Byte 1 Byte 2 Byte n
Addr 1 Addr 2 Addr n
tWHWH
tWHRL
tPLTS
tWHRH
tWHWH
Byte n
AI00752C
Figure13. Software Protected Write Cycle Waveforms
G
E
tWLWH
W
tAVEL
A0-A5
A6-A12
DQ0-DQ7
Note: A6through A12 must specify the same pageaddress during each high to low transition ofW (or E) after the software code has been
entered. G mustbe high only when Wand E are bothlow.
1555h 0AAAh 1555h
tWLAX
tWHDX
tDVWH
tWHWL
Byte Address
Page Address
Byte 0
tWHWH
Byte 62 Byte 63AAh 55h A0h
AI01358
11/18
Page 12
M28LV64
Figure14. Data Polling Waveform Sequence
A0-A12
E
G
W
DQ7
Address of the last byte of the Page Write instruction
DQ7 DQ7DQ7 DQ7DQ7
Figure15. Toggle Bit WaveformSequence
READYLAST WRITE INTERNAL WRITE SEQUENCE
AI00753C
A0-A12
E
G
W
DQ6
Note: 1. First Togglebit is forced to ’0’
(1)
TOGGLE
INTERNAL WRITESEQUENCE
READYLAST WRITE
AI00754D
12/18
Page 13
ORDERING INFORMATION SCHEME
Example: M28LV64 -200 X K 1
M28LV64
Speed
-200 200ns
-250 250ns
-300 300ns
Write Monitoring
blank RB function
active
X No RB function
Package
P PDIP28
K PLCC32
MS SO28 300mils
N TSOP28
8 x 13.4mm
Temperature Range
1 0 to 70 °C
6 –40 to 85 °C
The M2864is replaced bythe M28C64-xxW.
Devicesare shipped fromthe factory withthe memory contentset at all ”1’s” (FFh).
Foralist ofavailableoptions(Speed,Package,etc...) orfor furtherinformationon any aspectof thisdevice,
pleasecontact the SGS-THOMSON SalesOffice nearestto you.
13/18
Page 14
M28LV64
PDIP28 - 28 pin Plastic DIP, 600 mils width
Symb
Typ Min Max Typ Min Max
A 3.94 5.08 0.155 0.200
A1 0.38 1.78 0.015 0.070
A2 3.56 4.06 0.140 0.160
B 0.38 0.56 0.015 0.021
B1 1.14 1.78 0.045 0.070
C 0.20 0.30 0.008 0.012
D 34.70 37.34 1.366 1.470
E 14.80 16.26 0.583 0.640
E1 12.50 13.97 0.492 0.550
e1 2.54 – – 0.100 – –
eA 15.20 17.78 0.598 0.700
L 3.05 3.82 0.120 0.150
S 1.02 2.29 0.040 0.090
α 0° 15° 0° 15°
N28 28
PDIP28
mm inches
Drawing is not to scale.
14/18
B1 B e1
D
S
N
1
A2A1A
L
Cα
eA
E1 E
PDIP
Page 15
PLCC32- 32 lead Plastic Leaded Chip Carrier, rectangular
M28LV64
Symb
Typ Min Max Typ Min Max
A 2.54 3.56 0.100 0.140
A1 1.52 2.41 0.060 0.095
B 0.33 0.53 0.013 0.021
B1 0.66 0.81 0.026 0.032
D 12.32 12.57 0.485 0.495
D1 11.35 11.56 0.447 0.455
D2 9.91 10.92 0.390 0.430
E 14.86 15.11 0.585 0.595
E1 13.89 14.10 0.547 0.555
E2 12.45 13.46 0.490 0.530
e 1.27 – – 0.050 – –
j 0.89 – – 0.035 – –
N32 32
Nd 7 7
Ne 9 9
CP 0.10 0.004
mm inches
PLCC32
Ne E1 E
Drawing is not to scale.
PLCC
D
D1
1N
Nd
D2/E2
A1
j
B1
e
B
A
CP
15/18
Page 16
M28LV64
SO28 - 28 lead Plastic Small Outline, 300 mils body width
Symb
Typ Min Max Typ Min Max
A 2.46 2.64 0.097 0.104
A1 0.13 0.29 0.005 0.011
A2 2.29 2.39 0.090 0.094
B 0.35 0.48 0.014 0.019
C 0.23 0.32 0.009 0.013
D 17.81 18.06 0.701 0.711
E 7.42 7.59 0.292 0.299
e 1.27 – – 0.050 – –
H 10.16 10.41 0.400 0.410
L 0.61 1.02 0.024 0.040
α 0° 8° 0° 8°
N28 28
CP 0.10 0.004
SO28
mm inches
Drawing is not to scale.
16/18
A2
A
C
B
e
CP
D
N
E
H
1
LA1 α
SO-b
Page 17
TSOP28 - 28 leadPlastic Thin Small Outline, 8 x 13.4mm
M28LV64
Symb
Typ Min Max Typ Min Max
A 1.25 0.049
A1 0.20 0.008
A2 0.95 1.15 0.037 0.045
B 0.17 0.27 0.007 0.011
C 0.10 0.21 0.004 0.008
D 13.20 13.60 0.520 0.535
D1 11.70 11.90 0.461 0.469
E 7.90 8.10 0.311 0.319
e 0.55 – – 0.022 – –
L 0.50 0.70 0.020 0.028
α 0° 5° 0° 5°
N28 28
CP 0.10 0.004
TSOP28
mm inches
Drawing is not to scale.
28
1
22
21
E
78
D1
D
DIE
TSOP-c
A2
e
B
A
CP
C
LA1 α
17/18
Page 18
M28LV64
Information furnished is believed to be accurate and reliable.However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringementof patents or other rights ofthird parties which may result from its use. No
license is granted by implication or otherwise under any patentor patentrights ofSGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are notauthorized foruseas critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.
1997 SGS-THOMSON Microelectronics - All Rights Reserved
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