Page 1
查询M28F201供应商
2 Mb (256K x 8, Chip Erase) FLASH MEMORY
5V ± 10% SUPPLYVOLTAGE
12V PROGRAMMINGVOLTAGE
FASTACCESSTIME: 70ns
BYTEPROGRAMMINGTIME: 10µs typical
ELECTRICALCHIP ERASEin 1s RANGE
LOW POWERCONSUMPTION
– ActiveCurrent: 15mAtypical
– Stand-byCurrent: 10µAtypical
10,000PROGRAM/ERASE CYCLES
INTEGRATED ERASE/PROGRAM-STOP
TIMER
OTPCOMPATIBLE PACKAGESand PINOUTS
ELECTRONIC SIGNATURE
– ManufacturerCode: 20h
– DeviceCode: F4h
M28F201
PLCC32 (K) TSOP32 (N)
8 x 20 mm
Figure 1. Logic Diagram
DESCRIPTION
The M28F201 FLASH Memory product is a nonvolatilememorieswhich may be erasedelectrically
at the chip level and programmed byte-by-byte. It
is organised as 256K bytes. It uses a command
registerarchitectureto select theoperating modes
and thus provide a simple microprocessor interface. The M28F201 FLASH Memory product is
suitablefor applicationswhere the memoryhas to
be reprogrammed in the equipment. The access
time of 70ns makes the device suitable for use in
high speed microprocessorsystems.
Table 1. Signal Names
A0-A17 Address Inputs
DQ0-DQ7 Data Inputs / Outputs
E Chip Enable
G Output Enable
W Write Enable
V
PP
V
CC
V
SS
Program Supply
SupplyVoltage
Ground
A0-A17
W
CC
M28F201
V
SS
V
PP
8
DQ0-DQ7
AI00637C
V
18
E
G
April 1997 1/21
Page 2
M28F201
Figure2A. LCCPin Connections
CC
VPPV
32
DQ3
DQ4
W
DQ5
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A16
A12
A15
1
9
DQ1
DQ2
M28F201
17
SS
V
A17
25
DQ6
A14
A13
A8
A9
A11
G
A10
E
DQ7
AI00638C
Figure 2B. TSOPPin Connections
A11 G
A13
A14
A17
V
CC
V
PP
A16
A15
A12
1
A9
A8
W
M28F201
8
(Normal)
9
A7
A6
A5
A4 A3
16 17
32
25
24
AI00639C
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
V
SS
DQ2
DQ1
DQ0
A0
A1
A2
Figure2C. TSOPReverse Pin Connections
A11G
321
2/21
A10
DQ7
DQ6
DQ5
DQ4
DQ3
V
SS
DQ2
DQ1
DQ0
A0
A1
A2
E
M28F201
8
(Reverse)
9
16 17
AI00640D
25
24
A9
A8
A13
A14
A17
W
V
CC
V
PP
A16
A15
A12
A7
A6
A5
A4A3
DEVICEOPERATION
TheM28F201 FLASHMemory product employsa
technologysimilar to a 2 Megabit EPROM but add
to the device functionality by providing electrical
erasure and programming. These functions are
managed by a command register. The functions
that are addressed via the command register depend on the voltage applied to the V
voltage, input. When V
is less than or equal to
PP
, program
PP
6.5V, the command register is disabled and the
M28F201functionsas a readonly memoryproviding operating modessimilar to anEPROM (Read,
Output Disable, Electronic Signature Read and
Standby).WhenV
israisedto 12Vthecommand
PP
register is enabled and this provides, in addition,
Eraseand Program operations.
READONLYMODES, V
PP
≤ 6.5V
For all Read Only Modes, except StandbyMode,
the Write Enable input W should be High. In the
StandbyMode this input is ’don’tcare’.
ReadMode. TheM28F201has twoenableinputs,
E and G, both of which must be Low in order to
outputdata from thememory. TheChipEnable(E)
isthe powercontroland shouldbe usedfor device
selection. Output Enable (G) is the output control
and should be used to gatedata on to the output,
independantof the deviceselection.
Page 3
Table 2. AbsoluteMaximumRatings
Symbol Parameter Value Unit
M28F201
T
A
T
STG
V
IO
V
CC
V
A9
V
PP
Note: Except for therating ”Operating Temperature Range”, stressesabove those listed in the Table”AbsoluteMaximum Ratings” may
cause permanent damage tothe device. These are stress ratings onlyand operation of the device at these or any other conditions above
those indicated in the Operating sections of this specificationis notimplied. Exposure to AbsoluteMaximum Ratingconditions for extended
periods may affect device reliability.Refer also to the SGS-THOMSON SURE Program and otherrelevant quality documents.
Table 3. Operations
ReadOnly V
Read/Write
Notes: 1. X = VILor VIH.
(2)
2. Refer also to the Command table.
Ambient Operating Temperature –40 to125 °C
Storage Temperature –65 to150 °C
Input or Output Voltages –0.6 to 7 V
Supply Voltage –0.6 to 7 V
A9 Voltage –0.6 to 13.5 V
Program Supply Voltage, during Erase
or Programming
(1)
V
PP
Operation E G W A9 DQ0 - DQ7
Read V
PPL
Output Disable V
Standby V
Electronic Signature V
Read V
V
PPH
Write V
Output Disable V
Standby V
IL
IL
IH
IL
IL
IL
IL
IH
V
IL
V
IH
X X X Hi-Z
V
IL
V
IL
V
IH
V
IH
X X X Hi-Z
–0.6 to 14 V
V
IH
V
IH
V
IH
V
IH
A9 Data Output
X Hi-Z
V
ID
A9 Data Output
VILPulse A9 Data Input
V
IH
X Hi-Z
Codes
Table 4. Electronic Signature
Identifier A0 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Hex Data
Manufacturer’s Code V
Device Code V
IL
IH
00100000 20h
11110100 F4h
3/21
Page 4
M28F201
Table 5. Commands
Command Cycles
Read 1 Write X 00h
Electronic
Signature
Setup Erase/
Erase Write X 20h
Erase Verify 2 Write A0-A17 A0h Read X Data Output
Setup Program/
Program Write A0-A17 Data Input
Program Verify 2 Write X C0h Read X Data Output
Reset 2 Write X FFh Write X FFh
Notes: 1. X = VILor VIH.
(2)
2. Refer also to the Electronic Signaturetable.
Standby Mode. In the Standby Mode the maximum supply current is reduced. The device is
placed in the Standby Mode by applying a High
level to the Chip Enable (E) input. When in the
StandbyModetheoutputsare ina highimpedance
state, independantof theOutput Enable (G)input.
Output Disable Mode. When the Output Enable
(G) is High the outputs are in a high impedance
state.
ElectronicSignatureMode.Thismodeallowsthe
readout of two binary codesfromthe device which
identify the manufacturer and device type. This
mode is intended for use by programming equipment to automaticallyselect the correct eraseand
programmingalgorithms.The ElectronicSignature
Mode is activewhen a highvoltage (11.5Vto 13V)
isapplied toaddresslineA9withEandG Low.With
A0 Low the output data is the manufacturercode,
when A0 isHigh the output is thedevice code. All
other address lines should be maintained Low
while reading the codes. The electronicsignature
canalso be accessed in Read/Writemodes.
READ/WRITE MODES, 11.4V≤ V
When V
is High both read and write operations
PP
may be performed. These are defined by thecontents ofan internalcommand register.Commands
may be written to this register to set-up and execute,Erase,EraseVerify,Program,Program Verify
and Reset modes. Each of these modes needs 2
cycles. Each mode starts with a write operationto
set-upthe command,thisis followedby eitherread
or write operations. The device expects the first
cycle to be a write operation and doesnot corrupt
(1)
1st Cycle 2nd Cycle
Operation A0-A17 DQ0-DQ7 Operation A0-A17 DQ0-DQ7
2 Write X 80h or 90h
2
2
Write X 20h
Write X 40h
Read 00000h 20h
Read 00001h F4h
data at any location in the memory.Read modeis
set-upwith one cycle onlyand maybe followedby
any number of read operations to output data.
ElectronicSignatureRead modeis set-upwithone
cycle and followed by a read cycle to output the
manufactureror device codes.
Awriteto thecommandregisterismadebybringing
WLowwhileEisLow.ThefallingedgeofWlatches
Addresses, while the rising edge latches Data,
which are used for those commands that require
address inputs, command input or provide data
output. The supply voltage V
voltageV
canbe applied in any order. Whenthe
PP
CC
device is powered up or when V
contentsof thecommand register defaultsto 00h,
thus automatically setting-up Read operations. In
addition a specific command may be used to set
the commandregisterto 00h for readingthe memory. The system designer may chose to provide a
constanthigh V
anduse the registercommands
PP
for all operations,or to switch the V
high only when needing to erase or program the
memory. All command registeraccess is inhibited
≤12.6V
PP
whenV
age (V
fallsbelowthe Erase/WriteLockoutVolt-
CC
) of 2.5V.
LKO
If the device is deselected during Erasure, Programming or verifying it will draw active supply
currentsuntil the operationsare terminated.
The device is protected against stress caused by
long erase or programtimes.If theend ofErase or
Programming operations are not terminated by a
Verifycycle within a maximumtime permitted, an
internal stop timer automatically stops the operation.The deviceremainsin aninactivestate, ready
to start a Verifyor ResetMode operation.
and the program
is ≤ 6.5V the
PP
from low to
PP
4/21
Page 5
Table 6. AC Measurement Conditions
SRAM Interface Levels EPROM Interface Levels
Input Rise and Fall Times ≤ 10ns ≤ 10ns
Input PulseVoltages 0 to 3V 0.45V to 2.4V
Input and Output Timing Ref. Voltages 1.5V 0.8Vand 2V
M28F201
Figure3. AC Testing Input Output Waveform
SRAM Interface
3V
1.5V
0V
EPROM Interface
2.4V
0.45V
Table 7. Capacitance
Symbol Parameter TestCondition Min Max Unit
C
IN
C
OUT
Note: 1. Sampled only, not 100% tested.
Input Capacitance VIN=0V 6 pF
Output Capacitance V
(1)
(TA=25°C, f = 1 MHz )
2.0V
0.8V
AI01275
Figure4. AC Testing Load Circuit
1.3V
1N914
3.3kΩ
DEVICE
UNDER
TEST
CL= 30pF or 100pF
CL= 30pF for SRAM Interface
CL= 100pF for EPROM Interface
CLincludes JIG capacitance
=0V 12 pF
OUT
OUT
AI01276
Read Mode. The Read Mode is the default at
power up or may be set-up by writing 00h to the
command register. Subsequent read operations
outputdatafromthememory.Thememoryremains
in the Read Mode until a new command is written
to the commandregister.
ElectronicSignatureMode. Inorder to select the
correcterase and programmingalgorithmsfor onboard programming,the manufacturerand device
codesmay be read directly. It isnot neccessaryto
apply a high voltage to A9 when using the command register. The Electronic Signature Mode is
set-up by writing 80h or 90h to the command
register. The following read cycles, with address
inputs00000hor 00001h,outputthe manufacturer
or device codes. The command is terminated by
writing another valid command to the command
register(for exampleReset).
5/21
Page 6
M28F201
Table 8. DC Characteristics
= 0 to 70 °C, –40 to 85 °C or –40to 125 °C; VCC=5V±10%)
(T
A
Symbol Parameter Test Condition Min Max Unit
Input LeakageCurrent 0V ≤ VIN≤ V
LI
Output Leakage Current 0V ≤ V
Supply Current (Read) E = VIL, f = 10MHz 30 mA
Supply Current (Standby) TTL E = V
I
I
I
CC1
I
LO
CC
Supply Current (Standby) CMOS E = V
(1)
I
CC2
I
CC3
I
CC4
I
CC5
I
I
I
I
I
I
PP1
PP2
PP3
PP4
V
V
LPP
PP
Supply Current (Programming) During Programming 10 mA
(1)
Supply Current (Program Verify) During Verify 20 mA
(1)
Supply Current (Erase) During Erasure 20 mA
(1)
Supply Current (Erase Verify) During Erase Verify) 20 mA
Program Leakage Current VPP≤ V
Program Current (Read or
Standby)
(1)
Program Current (Programming) VPP=V
Program Current (Program
(1)
Verify)
(1)
Program Current (Erase) VPP=V
(1)
Program Current (Erase Verify) VPP=V
Input Low Voltage –0.5 0.8 V
IL
Input High VoltageTTL 2 VCC+ 0.5 V
IH
Input High Voltage CMOS 0.7 V
V
V
Output Low Voltage IOL= 5.8mA 0.45 V
OL
Output High Voltage CMOS
OH
Output High VoltageTTL I
V
PPL
V
PPH
V
I
ID
V
LKO
Note: 1. Not 100% tested. Characterisation Data available.
Program Voltage(Read
Operations)
Program Voltage(Read/Write
Operations)
A9 Voltage(Electronic Signature) 11.5 13 V
ID
(1)
A9 Current (Electronic Signature) A9 = V
Supply Voltage,Erase/Program
Lock-out
CC
≤ V
OUT
CC
IH
± 0.2V 100 µA
CC
CC
V
PP>VCC
≤ V
V
PP
CC
, During Programming 30 mA
PPH
V
PP=VPPH
, During Verify 5 mA
, During Erase 30 mA
PPH
, DuringErase Verify 5 mA
PPH
CC
I
= –100µAV
OH
I
= –2.5mA 0.85 V
OH
= –2.5mA 2.4 V
OH
– 0.4 V
CC
CC
0 6.5 V
11.4 12.6 V
ID
2.5 V
±1 µA
±10 µA
1mA
±10 µA
200 µA
±10 µA
VCC+ 0.5 V
200 µA
V
6/21
Page 7
Table9. Read Only Mode AC Characteristics
((T
= 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)
A
Symbol Alt Parameter Test Condition
t
WHGL
t
AVAV
t
AVQV
(1)
t
ELQX
t
ELQV
(1)
t
GLQX
t
GLQV
(1)
t
EHQZ
(1)
t
GHQZ
t
AXQX
Note: 1. Sampled only,not 100% tested
Write Enable High to
Output EnableLow
t
Read Cycle Time E = VIL,G=VIL70 90 120 150 ns
RC
Address Validto
t
ACC
Output Valid
Chip Enable Low to
t
LZ
Output Transition
Chip Enable Low to
t
CE
Output Valid
Output EnableLow
t
OLZ
to Output Transition
Output EnableLow
t
OE
to Output Valid
Chip Enable High to
Output Hi-Z
Output EnableHigh
t
DF
to Output Hi-Z
Address Transition
t
OH
to Output Transition
E=V
,G=V
IL
G=V
IL
G=V
IL
E=V
IL
E=V
IL
G=V
IL
E=V
IL
E=V
,G=VIL0000ns
IL
M28F201
M28F201
-70 -90 -120 -150
=
V
CC
5V±10%
EPROM
Interface
Min Max Min Max Min Max Min Max
6666µs
IL
70 90 120 150 ns
0000ns
70 90 120 150 ns
0000ns
25 30 35 40 ns
0 25 0 30 0 30 0 35 ns
0 25 0 30 0 30 0 35 ns
VCC=
5V±10%
EPROM
Interface
VCC=
5V±10%
EPROM
Interface
VCC=
5V±10%
EPROM
Interface
Unit
Erase and Erase Verify Modes. The memory is
erased by first Programming all bytes to 00h,the
Erase command then erases them to FFh. The
Erase Verify command is then used to read the
memory byte-by-byte for a content of FFh. The
Erase Mode is set-up by writing 20h to the command register. The write cycle is then repeated to
start the erase operation. Erasure starts on the
rising edge of W duringthis second cycle.Eraseis
followed by an Erase Verify which reads an addressed byte. Erase VerifyMode is set-up bywriting A0h tothe command register and at thesame
time supplying the address of the byte to be verified. The rising edge of W duringthe set-up of the
firstErase VerifyMode stops theEraseoperation.
Thefollowing read cycle is madewith an internally
generated margin voltage applied; reading FFh
indicatesthatallbitsof theaddressedbyte arefully
erased. The whole contents of the memory are
verified by repeating the Erase Verify Operation,
first writing the set-up code A0h with the address
of thebyte to be verified and thenreadingthe byte
contentsin a secondread cycle.
As the Erasealgorithm flow chart shows,when the
data read during Erase Verify is not FFh, another
Eraseoperation is performedand verificationcontinuesfromtheaddressofthelast verifiedbyte.The
command is terminated by writing another valid
command to the command register (for example
Programor Reset).
7/21
Page 8
M28F201
Figure5. Read Mode AC Waveforms
A0-A17
E
G
tGLQV
tGLQX
tAVAV
tAVQV tAXQX
tELQV
tELQX
tEHQZ
tGHQZ
DQ0-DQ7
Figure6. Read Command Waveforms
V
PP
tVPHEL
A0-A17
E
tELWL tWHEH
G
tGHWL
W
tWLWH
DATA OUT
AI00642
VALID
tAVQV
tELQV tEHQZ
tWHGL
tGLQV
tAXQX
tGHQZ
DQ0-DQ7 DATA OUTCOMMAND
8/21
tWHDXtDVWH
READREAD SET-UP
AI00643
Page 9
Figure7. Electronic Signature Command Waveforms
V
PP
tVPHEL
M28F201
A0-A17
E
tELWL tWHEH
G
tGHWL
W
tWLWH
tWHDXtDVWH
DQ0-DQ7 DATA OUTCOMMAND
READ
ELECTRONIC
SIGNATURE SET-UP
Program and Program Verify Modes. The ProgramModeisset-upbywriting40htothe command
register. This is followed by a second write cycle
which latchesthe addressand data of thebyte to
be programmed.The risingedge of W during this
second cycle starts the programming operation.
ProgrammingisfollowedbyaProgramVerifyofthe
data written.
ProgramVerifyModeisset-upbywritingC0hto the
commandregister.The rising edgeof Wduring the
set-up of the Program Verify Mode stopsthe Pro-
00000h-00001h
tAVQV
tELQV tEHQZ
tWHGL
tGLQV
READ
MANUFACTURER
OR DEVICE
tAXQX
tGHQZ
AI00644
gramming operation. The followingread cycle, of
the address already latched during programming,
is made with an internallygenerated margin voltageapplied,readingvaliddataindicatesthatallbits
have been programmed.
ResetMode.Thiscommandisusedtosafely abort
Erase or Program Modes. The Reset Mode is
set-up and performed by writing FFh two times to
the command register. The command should be
followed by writing a valid command to the the
commandregister (for exampleRead).
9/21
Page 10
M28F201
Table 10A. Read/Write Mode AC Characteristics,W and E Controlled
(T
= 0 to 70 °C, –40 to 85 °C or –40to 125 °C)
A
Symbol Alt Parameter
t
VPHEL
t
VPHWL
t
WHWH3tWC
t
EHEH3
t
AVWL
t
AVEL
t
WLAX
t
ELAX
t
ELWL
t
WLEL
t
GHWL
t
GHEL
t
DVWH
t
DVEH
t
WLWH
t
ELEH
t
WHDX
t
EHDX
t
WHWH1
t
EHEH1
t
WHWH2
t
EHEH2
t
WHEH
t
EHWH
t
WHWLtWPH
t
EHEL
t
WHGL
t
EHGL
t
AVQV
(1)
t
ELQX
t
ELQV
(1)
t
GLQX
t
GLQV
(1)
t
EHQZ
(1)
t
GHQZ
t
AXQX
Note: 1. Sampled only,not 100% tested
VPPHigh to Chip Enable Low 1 1 µs
VPPHigh to Write Enable Low 1 1 µs
Write Cycle Time(W controlled) 70 90 ns
t
Write Cycle Time(E controlled) 70 90 ns
WC
t
Address Valid to Write Enable Low 0 0 ns
AS
Address Valid to Chip Enable Low 0 0 ns
t
Write Enable Low to Address Transition 30 45 ns
AH
Chip Enable Low to Address Transition 30 45 ns
t
Chip Enable Low to Write Enable Low 0 0 ns
CS
Write Enable Low to Chip Enable Low 0 0 ns
Output Enable High to Write Enable Low 0 0 µs
Output Enable High to ChipEnable Low 0 0 µs
t
Input Valid to Write Enable High 30 45 ns
DS
Input Valid to Chip Enable High 30 45 ns
t
Write Enable Low to WriteEnable High (Write Pulse) 30 45 ns
WP
Chip Enable Low to Chip Enable High (Write Pulse) 50 60 ns
t
Write Enable High to InputTransition 10 10 ns
DH
Chip Enable High to Input Transition 10 10 ns
Duration of Program Operation (W contr.) 10 10 µs
Duration of Program Operation (E contr.) 10 10 µs
Duration of Erase Operation (W contr.) 9.5 9.5 ms
Duration of Erase Operation (E contr.) 9.5 9.5 ms
t
Write Enable High to Chip Enable High 0 0 ns
CH
Chip Enable High to Write Enable High 0 0 ns
Write Enable High to Write Enable Low 10 20 ns
Chip Enable High to Chip Enable Low 10 20 ns
Write Enable High to Output EnableLow 6 6 µs
Chip Enable High to Output Enable Low 6 6 µs
t
Addess Validto data Output 70 90 ns
ACC
t
Chip Enable Low to Output Transition 0 0 ns
LZ
t
Chip Enable Low to Output Valid 70 90 ns
CE
t
Output Enable Low to Output Transition 0 0 ns
OLZ
t
Output Enable Low to Output Valid 25 30 ns
OE
Chip Enable High to Output Hi-Z 25 30 ns
t
Output Enable High to Output Hi-Z 25 30 ns
DF
t
Address Transition to Output Transition 0 0 ns
OH
V
=5V±10% VCC=5V±10%
CC
EPROM
Interface
Min Max Min Max
M28F201
-70 -90
Unit
EPROM
Interface
10/21
Page 11
Table 10B. Read/Write Mode AC Characteristics,W and E Controlled
(T
= 0 to 70 °C, –40 to 85 °C or –40to 125 °C)
A
Symbol Alt Parameter
t
VPHEL
t
VPHWL
t
WHWH3tWC
t
EHEH3
t
AVWL
t
AVEL
t
WLAX
t
ELAX
t
ELWL
t
WLEL
t
GHWL
t
GHEL
t
DVWH
t
DVEH
t
WLWH
t
ELEH
t
WHDX
t
EHDX
t
WHWH1
t
EHEH1
t
WHWH2
t
EHEH2
t
WHEH
t
EHWH
t
WHWLtWPH
t
EHEL
t
WHGL
t
EHGL
t
AVQV
(1)
t
ELQX
t
ELQV
(1)
t
GLQX
t
GLQV
(1)
t
EHQZ
(1)
t
GHQZ
t
AXQX
Note: 1. Sampled only,not 100% tested
VPPHigh to Chip Enable Low 1 1 µs
VPPHigh to Write Enable Low 1 1 µs
Write Cycle Time(W controlled) 120 150 ns
t
Write Cycle Time(E controlled) 120 150 ns
WC
t
Address Valid to Write Enable Low 0 0 ns
AS
Address Valid to Chip Enable Low 0 0 ns
t
Write Enable Low to Address Transition 50 50 ns
AH
Chip Enable Low to Address Transition 60 80 ns
t
Chip Enable Low to Write Enable Low 0 0 ns
CS
Write Enable Low to Chip Enable Low 0 0 ns
Output Enable High to Write Enable Low 0 0 µs
Output Enable High to ChipEnable Low 0 0 µs
t
Input Valid to Write Enable High 50 50 ns
DS
Input Valid to Chip Enable High 50 50 ns
t
Write Enable Low to WriteEnable High (Write Pulse) 50 60 ns
WP
Chip Enable Low to Chip Enable High (Write Pulse) 70 80 ns
t
Write Enable High to InputTransition 10 10 ns
DH
Chip Enable High to Input Transition 10 10 ns
Duration of Program Operation (W contr.) 10 10 µs
Duration of Program Operation (E contr.) 10 10 µs
Duration of Erase Operation (W contr.) 9.5 9.5 ms
Duration of Erase Operation (E contr.) 9.5 9.5 ms
t
Write Enable High to Chip Enable High 0 0 ns
CH
Chip Enable High to Write Enable High 0 0 ns
Write Enable High to Write Enable Low 20 20 ns
Chip Enable High to Chip Enable Low 20 20 ns
Write Enable High to Output EnableLow 6 6 µs
Chip Enable High to Output Enable Low 6 6 µs
t
Addess Validto data Output 120 150 ns
ACC
t
Chip Enable Low to Output Transition 0 0 ns
LZ
t
Chip Enable Low to Output Valid 120 150 ns
CE
t
Output Enable Low to Output Transition 0 0 ns
OLZ
t
Output Enable Low to Output Valid 35 40 ns
OE
Chip Enable High to Output Hi-Z 30 35 ns
t
Output Enable High to Output Hi-Z 30 35 ns
DF
t
Address Transition to Output Transition 0 0 ns
OH
V
=5V±10% VCC=5V±10%
CC
EPROM
Interface
Min Max Min Max
M28F201
M28F201
-120 -150
Unit
EPROM
Interface
11/21
Page 12
M28F201
Figure8. Erase Set-up and Erase VerifyCommands Waveforms,W Controlled
VALID
tWLAX
tELQV tEHQZ
tWHEH
tGHQZtWHWH2
tWHGLtWHWL
tWLWH tGLQV
tWHDXtDVWH
DATA OUT
VERIFY
COMMAND
ERASE VERIFY
AI00645
READ
SET-UP
ERASE OPERATION
PP
V
tVPHEL
tAVWL
tWHWH3
A0-A17
E
tELWL
tELWL tWHEH
G
tGHWL
W
tWLWH
tWHDXtDVWH
COMMAND
ERASE SET-UP
(REPEAT OF 1st CYCLE)
ERASE SET-UP
DQ0-DQ7 COMMAND
12/21
Page 13
Figure9. Erase Set-upandErase Verify Commands Waveforms, EControlled
M28F201
VALID
tELAX
tGLQV
tEHWH
tGHQZtEHEH2
tEHGLtEHEL
tEHQZ
tELEH tELQV
tEHDXtDVEH
DATA OUT
VERIFY
COMMAND
ERASE VERIFY
AI01328
READ
SET-UP
ERASE OPERATION
PP
V
tVPHWL
A0-A17
tAVEL
tEHEH3
W
tWLEL
tWLEL tEHWH
COMMAND
ERASE SET-UP
tEHDXtDVEH
tELEH
tGHEL
G
E
DQ0-DQ7 COMMAND
(REPEAT OF 1st CYCLE)
ERASE SET-UP
13/21
Page 14
M28F201
Figure10. ProgramSet-up and ProgramVerify Commands Waveforms- W Controlled
PROGRAM OPERATION
tELQV tEHQZ
tWHEH
tGHQZ
tWHGLtWHWL
tWHWH1
tELWL
tWLWH tGLQV
tWHDXtDVWH
tWHDX
DATA OUT
VERIFY
COMMAND
PROGRAM
AI00646
READ
VERIFY SET-UP
V
PP
tVPHEL
VALID
A0-A17
tWLAX
tWHWH3
tAVWL
E
tWHEH
tELWL tWHEH
G
tELWL
tGHWL
W
tWLWH
tWHDX
tWLWH
tDVWH
tDVWH
DATA IN
ADDRESS AND
PROGRAM SET-UP
DQ0-DQ7 COMMAND
DATA LATCH
14/21
Page 15
Figure11. ProgramSet-up and Program Verify Commands Waveforms - E Controlled
M28F201
PROGRAM OPERATION
tELAX
tGLQV
tEHWH
tGHQZ
tEHGLtEHEL
tEHEH1
tWLEL
tELQV tEHQZ
tELEH
tELEH
tEHDXtDVEH
tEHDX
DATA OUT
VERIFY
COMMAND
PROGRAM
DATA IN
AI00648
READ
VERIFY SET-UP
tEHWH
VALID
tEHEH3
tAVEL
tVPHEL
tWLEL tEHWH
PP
V
A0-A17
W
tWLEL
tGHEL
G
E
tDVEH
tEHDX
tDVEH
tELEH
DQ0-DQ7 COMMAND
DATA LATCH
ADDRESS AND
PROGRAM SET-UP
15/21
Page 16
M28F201
Figure12. Erasing Flowchart
VPP= 12V
PROGRAM
BYTES TO 00h
n=0, Addr=00000h
ERASE SET-UP
Wait 10ms
ERASE VERIFY
Latch Addr.
Wait 6µs
READ DATA OUTPUT
Data
NO
OK
YES
Last
Addr
YES
READ COMMAND
VPP< 6.5V, PASS
VPP<
FAIL
YES
6.5V
NO
++n
=
1000
ALL
NO
Addr++
AI00649
Figure13. ProgrammingFlowchart
VPP= 12V
n=0
PROGRAM SET-UP
Latch Addr, Data
Wait 10µs
PROGRAM VERIFY
++n
READ DATAOUTPUT
NO
READ COMMAND
VPP< 6.5V, PASS
Wait 6µs
Data
OK
YES
Last
Addr
YES
NO
VPP<
FAIL
NO
YES
=25
6.5V
Addr++
AI00677
PRESTOF ERASEALGORITHM
The PRESTO F Erase Algorithm guarantees that
the device will be erased in a reliable way. The
algorithmfirstprogramsall bytes to 00h inorderto
ensureuniform erasure. The programmingfollows
the PRESTO F Programming Algorithm. Erase is
set-up by writing 20h to thecommand register,the
erasure is started by repeating this write cycle.
Erase Verify is set-up by writing A0h to the commandregister togetherwith the addressofthebyte
tobeverified.The subsequentreadcyclereadsthe
datawhichiscomparedtoFFh.Erase Verifybegins
ataddress0000h andcontinuesto the lastaddress
or until the comparisonof the data to FFh fails. If
this occurs, the address of the lastbyte checkedis
stored and a new Erase operation performed.
EraseVerifythencontinuesfromthe addressof the
stored location.
16/21
PRESTOF PROGRAM ALGORITHM
ThePRESTO F ProgrammingAlgorithm appliesa
series of10µs programmingpulses to a byte until
a correct verify occurs. Up to 25 programming
operations are allowed for one byte. Program is
set-upby writing 40h to thecommandregister,the
programming is started after the next write cycle
which also latches the address and data to be
programmed. Program Verify is set-up by writing
C0h to the commandregister, followed by a read
cycle and a compareof thedata read to the data
expected.DuringProgram and Program Verify operations a MARGIN MODE circuit is activated to
guaranteethatthecellisprogrammedwitha safety
margin.
Page 17
ORDERING INFORMATION SCHEME
Example: M28F201 -70 X N 1 TR
M28F201
Operating Voltage
F5V
Speed
-70 70ns
-90 90 ns
-120 120 ns
-150 150 ns
Power Supplies
blank V
XV
CC
CC
± 10%
± 5%
Package
K PLCC32
N TSOP32
8 x 20 mm
Option
R Reverse
Pinout
TR Tape& Reel
Packing
Temperature Range
1 0 to 70 °C
3 –40 to 125 °C
6 –40 to 85 °C
Devicesare shippedfrom the factorywiththe memory content erased (to FFh).
Foralist ofavailableoptions(Speed,Package,etc...)orfor furtherinformationonany aspectof thisdevice,
pleasecontact the SGS-THOMSONSales Office nearestto you.
17/21
Page 18
M28F201
PLCC32- 32 lead Plastic Leaded Chip Carrier, rectangular
Symb
Typ Min Max Typ Min Max
A 2.54 3.56 0.100 0.140
A1 1.52 2.41 0.060 0.095
B 0.33 0.53 0.013 0.021
B1 0.66 0.81 0.026 0.032
D 12.32 12.57 0.485 0.495
D1 11.35 11.56 0.447 0.455
D2 9.91 10.92 0.390 0.430
E 14.86 15.11 0.585 0.595
E1 13.89 14.10 0.547 0.555
E2 12.45 13.46 0.490 0.530
e 1.27 – – 0.050 – –
N32 32
Nd 7 7
Ne 9 9
CP 0.10 0.004
PLCC32
mm inches
Ne E1 E
Drawing is notto scale.
18/21
PLCC
D
D1
1N
Nd
D2/E2
A1
B1
e
B
A
CP
Page 19
M28F201
TSOP32 Normal Pinout - 32 lead Plastic Thin Small Outline, 8 x 20mm
Symb
Typ Min Max Typ Min Max
A 1.20 0.047
A1 0.05 0.17 0.002 0.006
A2 0.95 1.50 0.037 0.059
B 0.15 0.27 0.006 0.011
C 0.10 0.21 0.004 0.008
D 19.80 20.20 0.780 0.795
D1 18.30 18.50 0.720 0.728
E 7.90 8.10 0.311 0.319
e 0.50 – – 0.020 – –
L 0.50 0.70 0.020 0.028
α 0° 5° 0° 5°
N32 32
CP 0.10 0.004
TSOP32
mm inches
Drawing is notto scale.
1N
E
N/2
D1
D
DIE
TSOP-a
A2
e
B
A
CP
C
LA1 α
19/21
Page 20
M28F201
TSOP32 Reverse Pinout - 32 lead Plastic Thin Small Outline, 8 x 20mm
Symb
Typ Min Max Typ Min Max
A 1.20 0.047
A1 0.05 0.17 0.002 0.006
A2 0.95 1.50 0.037 0.059
B 0.15 0.27 0.006 0.011
C 0.10 0.21 0.004 0.008
D 19.80 20.20 0.780 0.795
D1 18.30 18.50 0.720 0.728
E 7.90 8.10 0.311 0.319
e 0.50 – – 0.020 – –
L 0.50 0.70 0.020 0.028
α 0° 5° 0° 5°
N32 32
CP 0.10 0.004
TSOP32
mm inches
Drawing is notto scale.
1N
E
N/2
D1
D
DIE
TSOP-b
A2
e
B
A
CP
C
LA1 α
20/21
Page 21
M28F201
Information furnished isbelieved to be accurate and reliable.However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringementof patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical componentsin life supportdevices or systemswithout express
written approval of SGS-THOMSON Microelectronics.
1997 SGS-THOMSON Microelectronics - All Rights Reserved
Australia - Brazil - Canada- China -France - Germany- Hong Kong - Italy -Japan - Korea- Malaysia - Malta - Morocco - The Netherlands -
Singapore- Spain - Sweden - Switzerland - Taiwan- Thailand - United Kingdom - U.S.A.
SGS-THOMSON Microelectronics GROUP OF COMPANIES
21/21
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