Datasheet M27W801 Datasheet (SGS Thomson Microelectronics)

Page 1
M27W801
8 Mbit (1Mb x8) Low Voltage UV EPROM and OTP EPROM
2.7V to 3.6V SUPPLY VOLTAGE in READ
OPERATION
ACCESS TIME:
–80nsatVCC= 3.0V to 3.6V – 100ns at VCC= 2.7V to 3.6V
PIN COMPATIBLE with M27C801
LOW POWER CONSUMPTION:
–15µA max Standby Current – 15mA max Active Current at 5MHz
PROGRAMMING TIME 50µs/byte
HIGH RELIABILITY CMOS TECHNOLOGY
– 2,000V ESD Protection – 200mA Latchup Protection Immunity
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h – Device Code: 42h
32
1
FDIP32W (F)
PLCC32 (K)
Figure 1. Logic Diagram
32
1
PDIP32 (B)
TSOP32 (N)
8 x 20 mm
DESCRIPTION
The M27W801 is a low voltage 8 Mbit EPROM of­fered in the two ranges UV (ultra violet erase) and OTP (one time programmable). It is ideally suited for microprocessor systems requiring large data or program storage and is organized as1,048,576by 8 bits.
The M27W801 operates in the read mode with a supply voltage as low as 2.7V at –40 to 85°C tem­perature range. The decrease in operating power allows either a reduction of the size of the battery or an increase in the time between battery re­charges.
The FDIP32W (window ceramic frit-seal package) has a transparent lids which allow the user to ex­pose the chip to ultraviolet light to erase thebitpat­tern. A new pattern can then be written to the device by following the programming procedure.
For applications wherethe content is programmed only one time and erasure is not required, the M27W801 is offered in PDIP32, PLCC32 and TSOP32 (8 x 20 mm) packages.
V
CC
20
A0-A19 Q0-Q7
GV
E
PP
M27W801
V
SS
8
AI02363
1/16April 2000
Page 2
M27W801
Figure 2A. DIP Connections
A19 V
1 2
A15
3
A12
4
A7
5
A6
6
A5
7
A4
8 A3 A2 A1 A0
Q0
Q2 SS
M27W801
9
10
11
12
13
14
15
16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
AI02671
CC
A18A16 A17 A14 A13 A8 A9 A11 GV A10 E Q7 Q6 Q5Q1 Q4 Q3V
PP
Figure 2B. PLCC Connections
CC
A16
A7 A6 A5 A4 A3 A2 A1 A0
Q0
A12
9
Q1
A19
A15
1
32
M27W801
17
Q2
Q3
SS
V
V
Q4
A18
Q5
A17
25
Q6
A14 A13 A8 A9 A11 GV A10 E Q7
AI02365
PP
Figure 2C. TSOP Connections
A11 GV
A9
A8 A13 A14 A17 A18
V
CC
A19 A16 A15 A12
A7
A6
A5
A4 A3
1
M27W801
8
(Normal)
9
16 17
32
25 24
AI02366
A10 E Q7 Q6 Q5 Q4 Q3 V
SS
Q2 Q1 Q0 A0 A1 A2
PP
Table 1. Signal Names
A0-A19 Address Inputs
Q0-Q7 Data Outputs
E Chip Enable
GV
V
V
PP
CC
SS
Output Enable / Program Supply
Supply Voltage
Ground
2/16
Page 3
M27W801
Table 2. Absolute Maximum Ratings
(1)
Symbol Parameter Value Unit
T
A
T
BIAS
T
STG
(2)
V
IO
V
CC
(2)
V
A9
V
PP
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of thedevice at theseor anyother conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi­tions for extendedperiods may affect device reliability. Refer alsoto the STMicroelectronics SUREProgram andotherrelevant qual­ity documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC voltage on Output is V
3. Depends on range.
Ambient Operating Temperature Temperature Under Bias –50 to 125 °C Storage Temperature –65 to 150 °C
Input or Output Voltage (except A9) –2 to 7 V Supply Voltage –2 to 7 V A9 Voltage –2 to 13.5 V Program Supply Voltage –2 to 14 V
+0.5V with possible overshoot to VCC+2V for a period less than 20ns.
CC
(3)
–40 to 125 °C
Table 3. Operating Modes
Mode E
Read Output Disable V Program
V Program Inhibit V Standby Electronic Signature
Note: X = VIHor VIL,VID= 12V ± 0.5V.
V
IL
IL
Pulse V
IL
IH
V
IH
V
IL
GV
V
V
PP
V
IL
IH
PP
PP
A9 Q7-Q0
X Data Out X Hi-Z X Data In X Hi-Z
X X Hi-Z
V
IL
V
ID
Codes
Table 4. Electronic Signature
Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data
Manufacturer’s Code Device Code
V
IL
V
IH
00100000 20h 01000010 42h
3/16
Page 4
M27W801
Table 5. AC Measurement Conditions
High Speed Standard
Input Rise and Fall Times 10ns 20ns (10% to 90%) Input Pulse Voltages 0 to 3V 0.4V to 2.4V Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V
Figure 3. AC Testing Input Output Waveform
High Speed
3V
1.5V
0V
Standard
2.4V
0.4V
Table 6. Capacitance
Symbol Parameter Test Condition Min Max Unit
C
IN
C
OUT
Note: 1. Sampled only, not 100% tested.
(1)
(TA=25°C, f = 1 MHz)
Input Capacitance Output Capacitance
2.0V
0.8V
AI01822
Figure 4. AC Testing Load Circuit
1.3V
DEVICE
UNDER
TEST
CL= 30pFfor HighSpeed CL= 100pF for Standard CLincludes JIG capacitance
V
=0V
IN
V
=0V
OUT
1N914
3.3k
C
L
6pF
12 pF
OUT
AI01823B
DEVICE OPERATION
The operating modes of the M27W801 are listed in the Operating Modes table. A single power supply is required in the read mode. All inputs are TTL levels except for GVPPand 12V on A9 for Elec­tronic Signature and Margin Mode Set or Reset.
Read Mode
The M27W801 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable(G)is the output control and should be used to gate data to the output pins, indepen­dent of device selection. Assuming that the ad­dresses are stable, the address access time
4/16
(t
) is equal to the delay from E to output
AVQV
(t
). Data is available attheoutputafteradelay
ELQV
of t
from the falling edge of G, assuming that
GLQV
E has been low and the addresses have been sta­ble for at least t
AVQV-tGLQV
.
Standby Mode
The M27W801 has a standby mode which reduc­es the supply current from 15mA to 20µA with low voltage operation VCC≤ 3.6V, see ReadMode DC Characteristics table for details. The M27W801 is placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the GVPPinput.
Page 5
M27W801
Table 7. Read Mode DC Characteristics
(1)
(TA= –40 to 85 °C; VCC= 2.7V to 3.6V; VPP=VCC)
Symbol Parameter Test Condition Min Max Unit
I
I
I
CC
I
CC1
I
CC2
I V
V
IH
V
V
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
Two Line Output Control
Because EPROMs are usually used in larger memory arrays, the product features a 2 line con­trol function which accommodates the use of mul­tiple memory connection. The two line control function allows:
a. the lowest possible memory power dissipation, b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control lines, Eshould be decoded and used as the prima­ry device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system controlbus. This ensures that all deselect­ed memory devices are intheir low power standby mode and that the output pins are only active when data is required from a particular memory device.
Input Leakage Current
LI
Output Leakage Current
LO
Supply Current
Supply Current (Standby) TTL Supply Current (Standby) CMOS Program Current
PP
Input Low Voltage –0.6
IL
(2)
Input High Voltage Output Low Voltage
OL
Output High VoltageTTL
OH
2. Maximum DC voltage on Output is V
CC
+0.5V.
E=V
0V V
0V V
,GVPP=VIL,I
IL
f = 5MHz, V
E>V
CC
V
IN
CC
V
OUT
E=V
–0.2V,VCC≤ 3.6V
V
PP=VCC
I
= 2.1mA
OL
I
= –1mA
OH
CC
IH
CC
OUT
3.6V
System Considerations
The power switching characteristics of Advanced CMOS EPROMs require careful decoupling of the devices. The supply current, ICC, has three seg­ments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the falling and rising edges of E. The magnitude of the transient current peaks is dependent on the capacitive and inductive loading of the device at the output. The associatedtransient voltagepeaks can be suppressed by complying with the two line outputcontrol and byproperly selected decoupling capacitors.It is recommended that a 0.1µFceram­ic capacitor be used on every device between V and VSS. This should be a high frequency capaci­tor of low inherent inductance and should be placed as close to the device as possible. In addi­tion, a 4.7µF bulk electrolytic capacitor should be used between VCCand VSSfor every eight devic-
= 0mA,
±10 µA ±10 µA
15 mA
1mA 15 µA 10 µA
0.2 V
CC
0.7 V
CCVCC
3.6 V
+ 0.5
0.4 V
es. The bulk capacitor should be located near the power supply connection point. The purposeof the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces.
V V
CC
5/16
Page 6
M27W801
Table 8. Read Mode AC Characteristics
(1)
(TA= –40 to 85 °C; VCC= 2.7V to 3.6V; VPP=VCC)
M27W801
(3)
Symbol Alt Parameter
Test
Condition
VCC= 3.0V to 3.6V VCC= 2.7V to 3.6V VCC= 2.7V to 3.6V
Min Max Min Max Min Max
E=V
G=V
G=V
E=V
G=V
E=V
E=V
G=V
,
IL
IL
IL
IL
IL
IL
,
IL
IL
0 50 0 60 0 70 ns
0 50 0 60 0 70 ns
000ns
t
AVQV
t
ELQV
t
GLQV
(2)
t
EHQZ
(2)
t
GHQZ
t
AXQX
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC measurement conditions.
Address Valid to
t
ACC
Output Valid Chip Enable Low to
t
CE
Output Valid Output Enable Low
t
OE
to Output Valid Chip Enable High
t
DF
to Output Hi-Z Output Enable High
t
DF
to Output Hi-Z Address Transition
t
OH
to Output Transition
-100
80 100 120 ns
80 100 120 ns
50 60 70 ns
-120
(-150/-200)
Unit
Figure 5. Read Mode AC Waveforms
A0-A19
tAVQV
E
G
tELQV
Q0-Q7
VALID
tGLQV
VALID
tAXQX
tEHQZ
tGHQZ
Hi-Z
AI01583B
6/16
Page 7
M27W801
Table 9. Programming Mode DC Characteristics
(1)
(TA=25°C; VCC= 6.25V ± 0.25V; VPP= 12.75V ± 0.25V)
Symbol Parameter Test Condition Min Max Unit
I
LI
I
CC
I
PP
V V
V
OL
V
OH
V
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
Input Leakage Current Supply Current 50 mA Program Current Input Low Voltage –0.3 0.8 V
IL
Input High Voltage 2 VCC+ 0.5 V
IH
Output Low Voltage Output High Voltage TTL IOH= –1mA 3.6 V A9 Voltage 11.5 12.5 V
ID
Table 10. MARGIN MODE AC Characteristics
(1)
V
IL
I
OL
VIN≤ V
E=V
IL
= 2.1mA
IH
±10 µA
50 mA
0.4 V
(TA=25°C; VCC= 6.25V ± 0.25V; VPP= 12.75V ± 0.25V)
Symbol Alt Parameter Test Condition Min Max Unit
t
A9HVPH
t
VPHEL
t
A10HEH
t
A10LEH
t
EXA10X
t
EXVPX
t
VPXA9X
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
t t
t
AS10VA10
t
AS10VA10
t
AH10
t t
VA9High to VPPHigh
AS9
VPPHigh to Chip Enable Low
VPS
Chip Enable Transition to V Chip Enable Transition to VPPTransition 2 µs
VPH
VPPTransition to VA9Transition
AH9
High to Chip Enable High (Set) Low to Chip Enable High (Reset)
Transition
A10
2 µs 2 µs 1 µs 1 µs 1 µs
2 µs
Programming
The M27W801 hasbeen designedto be fully com­patible with the M27C801 and has the same elec­tronic signature. As a result the M27W801 can be programmed as the M27C801 on the same pro­gramming equipmentapplying 12.75V on VPPand
6.25V on VCCby the use ofthe same PRESTO IIB algorithm. When delivered (and after each‘1’s era­sure for UV EPROM), all bits of the M27W801 are in the ”1” state. Data is introduced by selectively programming ”0”s into the desired bit locations.Al-
though only ’0’ will be programmed, both ”1” and ”0” can be present in the data word. The only way to change a ‘0’ to a ‘1’ is by die exposure to ultra­violet light (UV EPROM). The M27W801 is in the programming mode when VPPinput is at 12.75V and E is pulsed toVIL. The data to be programmed is applied to 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. VCCis specified to be 6.25V ±
0.25V.
7/16
Page 8
M27W801
Table 11. Programming Mode AC Characteristics
(1)
(TA=25°C; VCC= 6.25V ± 0.25V; VPP= 12.75V ± 0.25V)
Symbol Alt Parameter Test Condition Min Max Unit
t
AVEL
t
QVEL
t
VCHEL
t
VPHEL
t
VPLVPH
t
ELEH
t
EHQX
t
EHVPX
t
VPLEL
t
ELQV
(2)
t
EHQZ
t
EHAX
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
t t
t
VCS
t
OES
t
PRT
t
PW
t
t
OEH
t t
t
DFP
t
Address Valid to Chip Enable Low 2 µs
AS
Input Valid to Chip Enable Low 2 µs
DS
VCCHigh to Chip Enable Low VPPHigh to Chip Enable Low
2 µs
2 µs VPPRise Time 50 ns Chip Enable Program Pulse Width (Initial) 45 55 µs Chip Enable High to Input Transition 2 µs
DH
Chip Enable High to VPPTransition VPPLow to Chip Enable Low
VR
Chip Enable Low to Output Valid 1 µs
DV
2 µs
2 µs
Chip Enable High to Output Hi-Z 0 130 ns Chip Enable High to Address Transition 0 ns
AH
Figure 6. MARGIN MODE AC Waveforms
V
CC
A8
A9
tA9HVPH tVPXA9X
GV
PP
E
A10 Set
A10 Reset
tVPHEL
tA10HEH
tA10LEH
tEXVPX
tEXA10X
AI00736B
Note: A8 High level = 5V; A9 High level = 12V.
8/16
Page 9
Figure 7. Programming and Verify Modes AC Waveforms
M27W801
A0-A19
tAVEL
Q0-Q7
tQVEL
V
CC
tVCHEL
GV
PP
tVPHEL
E
Figure 8. Programming Flowchart
VCC= 6.25V, VPP= 12.75V
SET MARGIN MODE
n=0
E=50µs Pulse
NO
NO
VERIFY
YES
Last
NO
Addr
YES
RESET MARGINMODE
CHECK ALL BYTES
1st: VCC=5V
2nd: VCC= 2.7V
++ Addr
YES
++n
=25
FAIL
VALID
DATA IN DATAOUT
tEHQX
tEHVPX tELQV
tVPLEL
tELEH
PROGRAM VERIFY
PRESTO IIB Programming Algorithm
PRESTO IIB Programming Algorithm allows the whole array to be programmed with a guaranteed margin, in a typical timeof 52.5 seconds. This can be achieved with STMicroelectronics M27W801 due to several design innovations to improve pro­gramming efficiency and to provide adequate mar­gin for reliability. Before starting the programming the internal MARGIN MODE circuit must be set in order to guarantee that each cell is programmed with enough margin. Then a sequence of 50µs program pulses are applied to each byte until a correct verify occurs (see Figure 8). No overpro­gram pulses are applied since the verify in MAR­GIN MODE at VCCmuch higher than 3.6V, provides the necessary margin.
Program Inhibit
Programming of multiple M27W801s in parallel with different data is alsoeasily accomplished. Ex­cept for E, alllike inputs including GVPPof the par­allel M27W801 may be common. A TTL low level pulse applied to a M27W801’s E input, with VPPat
12.75V, will program that M27W801. A high level E input inhibits the other M27W801s from being programmed.
Program Verify
A verify (read) should be performed on the pro­grammed bits to determinethat they were correct-
AI01271C
ly programmed. The verify is accomplished with G at VIL. Data should be verified with t falling edge of E.
tEHAX
tEHQZ
AI01270
ELQV
after the
9/16
Page 10
M27W801
On-Board Programming
The M27W801 can be directly programmed in the application circuit. See the relevant Application Note AN620.
Electronic Signature
The Electronic Signature (ES) mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. The ES mode is functional in the 25°C ± 5°C am­bient temperaturerange that is required when pro­gramming the M27W801. To activate the ES mode, the programming equipment must force
11.5V to 12.5V on address line A9 of the M27W801. Two identifier bytes may then be se­quenced from the device outputs by toggling ad­dress line A0 from VILto VIH. All other address lines must be held at VILduring Electronic Signa­ture mode.
Byte 0 (A0 = VIL) represents the manufacturer code and byte 1 (A0 = VIH) the device identifier code. For the STMicroelectronics M27W801, these two identifier bytes are given in Table 4 and can be read-out on outputs Q7 to Q0.
Note that the M27W801 and M27C801 have the same identifier byte.
ERASURE OPERATION (applies to UV EPROM)
The erasure characteristics of the M27W801 is such that erasure begins when the cells are ex­posed to light with wavelengths shorter than ap­proximately 4000 Å. It should be noted that sunlight and some type of fluorescent lamps have wavelengths in the 3000-4000 Å range.
Research shows that constant exposure to room level fluorescent lighting could erase a typical M27W801 in about 3years, while it would take ap­proximately 1 week to cause erasure when ex­posed to direct sunlight. If the M27W801 is to be exposed to these types of lighting conditions for extended periods of time, it is suggested that opaque labels be put over the M27W801 window to prevent unintentional erasure. The recommend­ed erasure procedure for the M27W801 is expo­sure to short wave ultraviolet light which has wavelength 2537 Å. The integrated dose (i.e. UV intensity x exposure time) for erasure should be a minimum of 30 W-sec/cm2. The erasure time with this dosage is approximately 30 to 40 minutes us­ing an ultraviolet lamp with 12000 µW/cm2power rating. The M27W801 should be placed within 2.5 cm (1 inch) of the lamp tubes during the erasure. Some lamps have a filter on their tubes which should be removed before erasure.
10/16
Page 11
Table 12. Ordering Information Scheme
Example: M27W801 -80 K 6 TR
Device Type
M27
Supply Voltage
W = 2.7V to 3.6V
Device Function
801 = 8 Mbit (1Mb x8)
Speed
(1,2)
-100
-120 = 120 ns
=80ns
M27W801
Not For New Design
(3)
-150 = 150 ns
-200 = 200 ns
Package
F = FDIP32W
(4)
B = PDIP32 K = PLCC32
N = TSOP32: 8 x 20 mm
(4)
Temperature Range
6=–40to85°C
Options
TR = Tape& Reel Packing
Note: 1. High Speed, see AC Characteristics section for further information.
2. This speed also guarantees 80ns access time at V
3. These speeds are replaced by the 120ns.
4. Packages option available on request. Please contact STMicroelectronics local Sales Office.
= 3.0V to 3.6V.
CC
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de­vice, please contact the STMicroelectronics Sales Office nearest to you.
Table 13. Revision History
Date Revision Details
July 1999 First Issue
FDIP32W Package Dimension, L Max added (Table 14)
03/15/00
04/21/00
TSOP32 Package Dimension changed (Table 17) 0to70°C Temperature Range deleted Programming Time changed
Read Mode AC Characteristics: t
AVQV,tELQV,tGLQV,tEHQZ,tGHQZ
changed (Table 8)
11/16
Page 12
M27W801
Table 14. FDIP32W - 32 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data
Symb
A 5.72 0.225 A1 0.51 1.40 0.020 0.055 A2 3.91 4.57 0.154 0.180 A3 3.89 4.50 0.153 0.177
B 0.41 0.56 0.016 0.022 B1 1.45 0.057
C 0.23 0.30 0.009 0.012 D 41.73 42.04 1.643 1.655
D2 38.10 1.500
E 15.24 0.600 – E1 13.06 13.36 0.514 0.526
e 2.54 0.100 – eA 14.99 0.590 – eB 16.18 18.03 0.637 0.710
L 3.18 4.10 0.125 0.161
S 1.52 2.49 0.060 0.098
K 6.60 0.260 – K1 10.67 0.420
α 4° 11° 4° 11°
N32 32
Typ Min Max Typ Min Max
mm inches
Figure 9. FDIP32W - 32 pin Ceramic Frit-seal DIP with window, Package Outline
A2
B1 B e1
A3A1A
L
α
C
eA
D2
eB
D
S
N
E1 E
K
1
Drawing is not to scale.
K1
FDIPW-b
12/16
Page 13
M27W801
Table 15. PDIP32 - 32 pin Plastic DIP, 600 mils width, Package Mechanical Data
Symb
Typ Min Max Typ Min Max
A 5.08 0.200 A1 0.38 0.015 – A2 3.56 4.06 0.140 0.160
B 0.38 0.51 0.015 0.020 B1 1.52 0.060
C 0.20 0.30 0.008 0.012 D 41.78 42.04 1.645 1.655
D2 38.10 1.500
E 15.24 0.600 – E1 13.59 13.84 0.535 0.545
e1 2.54 0.100 – eA 15.24 0.600 – eB 15.24 17.78 0.600 0.700
L 3.18 3.43 0.125 0.135 S 1.78 2.03 0.070 0.080 α 0° 10° 0° 10°
N32 32
mm inches
Figure 10. PDIP32 - 32 pin Plastic DIP, 600 mils width, Package Outline
A2A1A
L
B1 B e1
D2
α
eA eB
D
S
N
E1 E
1
Drawing is not to scale.
C
PDIP
13/16
Page 14
M27W801
Table 16. PLCC32 - 32lead Plastic Leaded Chip Carrier, Package Mechanical Data
Symb
A 2.54 3.56 0.100 0.140 A1 1.52 2.41 0.060 0.095 A2 0.38 0.015
B 0.33 0.53 0.013 0.021 B1 0.66 0.81 0.026 0.032
D 12.32 12.57 0.485 0.495 D1 11.35 11.56 0.447 0.455 D2 9.91 10.92 0.390 0.430
E 14.86 15.11 0.585 0.595 E1 13.89 14.10 0.547 0.555 E2 12.45 13.46 0.490 0.530
e 1.27 0.050
F 0.00 0.25 0.000 0.010
R 0.89 0.035
N32 32 Nd 7 7 Ne 9 9
CP 0.10 0.004
Typ Min Max Typ Min Max
mm inches
Figure 11. PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Outline
D
D1
1N
Ne E1 E
F
D2/E2
0.51 (.020)
1.14 (.045)
Nd
R
PLCC
Drawing is not to scale.
A1
A2
B1
e
B
A
CP
14/16
Page 15
M27W801
Table 17. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Mechanical Data
Symbol
Typ Min Max Typ Min Max
A 1.200 0.0472 A1 0.050 0.150 0.0020 0.0059 A2 0.950 1.050 0.0374 0.0413
B 0.150 0.270 0.0059 0.0106
C 0.100 0.210 0.0039 0.0083 D 19.800 20.200 0.7795 0.7953
D1 18.300 18.500 0.7205 0.7283
e 0.500 0.0197
E 7.900 8.100 0.3110 0.3189
L 0.500 0.700 0.0197 0.0276
α 0° 5° 0° 5°
CP 0.100 0.0039
N32 32
mm inch
Figure 12. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Outline
A2
1N
e
E
B
N/2
D1
D
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