Datasheet M27W256 Datasheet (SGS Thomson Microelectronics)

Download

Page 1

M27W256

256 Kbit (32Kb x 8) Low Voltage UV EPROM and OTP EPROM

■ 2.7V to 3.6V SUPPLY VOLTAGEin READ

OPERATION

■ ACCESS TIME:

–70nsatVCC= 3.0V to 3.6V –80nsatVCC= 2.7V to 3.6V

■ PIN COMPATIBLE with M27C256B

■ LOW POWER CONSUMPTION:

–15µA max Standby Current – 15mA max Active Currentat 5MHz

■ PROGRAMMING TIME 100

■ HIGH RELIABILITY CMOS TECHNOLOGY

s/byte

– 2,000V ESDProtection – 200mA Latchup Protection Immunity

■ ELECTRONIC SIGNATURE

– Manufacturer Code:20h – Device Code: 3Dh

DESCRIPTION

The M27W256 is a low voltage 256 Kbit EPROM offered in the two ranges UV (ultra violet erase) and OTP (one time programmable). It is ideally suited for microprocessor systems and is organized as 32,768 by 8 bits.

The M27W256 operates in the read mode with a supply voltage as low as 3V. The decrease in operating power allows either a reduction of the size of the battery or an increase in the time between battery recharges.

The FDIP28W (windowceramic frit-seal package) has a transparent lid which allows the user to expose thechipto ultraviolet light to erase thebit pattern. A new pattern can then be written to the device by following the programming procedure.

For applications wherethe contentis programmed only one time and erasure is not required, the M27W256 is offered in PDIP28, PLCC32 and TSOP28 (8 x13.4 mm) packages.

FDIP28W (F) PDIP28 (B)

PLCC32 (K) TSOP28 (N)

Figure 1. Logic Diagram

A0-A14 Q0-Q7

M27W256

8 x 13.4mm

AI03629

1/15March 2000

Page 2

M27W256

Figure 2A. DIP Connections

A12

7 A2 A1 A0

Q2 SS

M27W256

28 27 26 25 24 23 22 21 20 19 18 17 16 15

AI03627

A14 A13 A8 A9 A11 G A10 E Q7 Q6 Q5Q1 Q4 Q3V

Figure 2B. LCC Connections

A6 A5 A4 A3 A2 A1 A0

A12

M27W256

A14

A13

A8 A9 A11 NC G A10 E Q7 Q6

AI03626

Figure 2C. TSOP Connections

A11

A8 A13 A14

A12

M27W256

15 14

AI03628

A10 E Q7 Q6 Q5 Q4 Q3 V

Q2 Q1 Q0 A0 A1 A2

Table 1. Signal Names

A0-A14 Address Inputs Q0-Q7 Data Outputs E Chip Enable G Output Enable V

NC Not Connected Internally DU Don’t Use

Program Supply Supply Voltage Ground

2/15

Page 3

M27W256

Table 2. Absolute Maximum Ratings

(1)

Symbol Parameter Value Unit

BIAS

STG

(2)

Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may

cause permanent damage to the device.These are stressratings only and operationof the device atthese or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Referalso to the STMicroelectronics SURE Program andother relevant quality documents.

2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC voltage on Output is V

3. Depends on range.

Ambient Operating Temperature Temperature Under Bias –50 to 125 °C Storage Temperature –65 to 150 °C

Input or Output Voltage (except A9) –2 to 7 V Supply Voltage –2 to 7 V A9 Voltage –2 to 13.5 V Program Supply Voltage –2 to 14 V

+0.5V with possible overshoot to VCC+2V for a period less than 20ns.

(3)

–40 to 125 °C

Table 3. Operating Modes

Mode E G A9

Read Output Disable V Program

V Verify V Program Inhibit Standby Electronic Signature

Note: X = VIHor VIL,VID= 12V ± 0.5V.

Pulse V

X XVCCHi-Z X XVPPData Out X

Data Out

Q7-Q0

Data In

Hi-Z Hi-Z

Codes

Table 4. Electronic Signature

Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data

Manufacturer’s Code Device Code

00100000 20h 10001101 8Dh

3/15

Page 4

M27W256

Table 5. AC Measurement Conditions

High Speed Standard

Input Rise and Fall Times ≤ 10ns ≤ 20ns Input Pulse Voltages 0 to 3V 0.4V to 2.4V Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V

Figure 3. AC Testing Input Output Waveform

High Speed

1.5V

Standard

2.4V

0.4V

Table 6. Capacitance

Symbol Parameter Test Condition Min Max Unit

OUT

Note: 1. Sampled only,not 100% tested.

Input Capacitance Output Capacitance

(1)

(TA=25°C, f = 1 MHz)

2.0V

0.8V

AI01822

Figure 4. AC Testing Load Circuit

1.3V

1N914

3.3kΩ

DEVICE UNDER

TEST

CL= 30pF for HighSpeed CL= 100pF for Standard CLincludes JIG capacitance

OUT

=0V

6pF

12 pF

OUT

AI01823B

DEVICE OPERATION

The modesof operationoftheM27W256 are listed in the Operating Modes. A single power supply is required in the read mode. All inputs are TTL levels except for VPPand 12V on A9 for Electronic Signature.

Read Mode

The M27W256 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable(G) is the output controland should be used to gate data to the output pins, indepen-

4/15

dent of device selection. Assuming that the addresses are stable, the address access time (t

) is equal to the delay from E to output

AVQV

). Data is available at the output after delay

ELQV

of t

from the falling edge of G, assuming that

GLQV

E has been lowand the addresses havebeen stable forat least t

AVQV-tGLQV

Standby Mode

The M27W256 has a standby mode which reduces the supply current from 10mA to 10µA with low voltage operation VCC≤ 3.6V, see Read ModeDC Characteristics table for details. The M27W256 is placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the G input.

Page 5

M27W256

Table 7. Read Mode DC Characteristics

(1)

(TA= –40to 85°C; VCC= 2.7V to 3.6V; VPP=VCC)

Symbol Parameter Test Condition Min Max Unit

CC1

CC2

I V

Note: 1. VCCmust be applied simultaneously with orbefore VPPand removed simultaneously orafter VPP.

Input Leakage Current

Output Leakage Current

0V ≤ V

E=V

Supply Current

OUT

Supply Current (Standby) TTL

Supply Current (Standby) CMOS

Program Current

Input Low Voltage –0.6

(2)

Input High Voltage Output Low Voltage

Output High Voltage TTL

2. Maximum DC voltage on Output is V

+0.5V.

E>V

≤ V

OUT

,G=VIL,

= 0mA, f = 5MHz,

≤ 3.6V

E=V

– 0.2V,

≤ 3.6V

PP=VCC

= 2.1mA

= –400µA

±10 µA ±10 µA

15 mA

1mA

15 µA

100 µA

0.2 V

0.7 V

CCVCC

+ 0.5

0.4 V

2.4 V

V V

Table 8. Read Mode AC Characteristics

(1)

(TA= –40to 85°C; VCC= 2.7V to 3.6V; VPP=VCC)

M27W256

(3)

Symbol Alt Parameter

Test

Condition

VCC= 3.0V to 3.6V VCC= 2.7V to 3.6V VCC= 2.7V to 3.6V

Min Max Min Max Min Max

E=V

G=V

E=V

G=V

E=V

G=V

0 40 0 50 0 60 ns

000ns

AVQV

ELQV

GLQV

(2)

EHQZ

(2)

GHQZ

AXQX

Note: 1. VCCmust be applied simultaneously with orbefore VPPand removed simultaneously orafter VPP.

2. Sampled only, not 100% tested.

3. Speed obtained with High Speed AC measurement conditions.

Address Valid to

ACC

Output Valid Chip EnableLow to

Output Valid Output Enable Low

to Output Valid Chip Enable High

to Output Hi-Z Output EnableHigh

to Output Hi-Z Address Transition

to Output Transition

-80

70 80 100 ns

40 50 60 ns

-100

(-120/-150/-200)

Unit

5/15

Page 6

M27W256

Figure 5. Read Mode AC Waveforms

A0-A14

Q0-Q7

VALID

tAVQV

tGLQV

tELQV

Two Line Output Control

Because EPROMs are usually used in larger memory arrays, thisproduct features a 2 line control function whichaccommodates the use of multiple memory connection. The two line control function allows:

a. the lowest possible memory power dissipation, b. complete assurance that output bus contention

will not occur.

For the most efficient use of these two control lines, Eshouldbe decoded and usedas the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system controlbus. This ensures that all deselected memory devices are in their low powerstandby mode andhat the output pins areonly activewhen data is desired from a particular memory device.

VALID

tAXQX

tEHQZ

tGHQZ

Hi-Z

AI00758B

System Considerations

The power switching characteristics of Advance CMOS EPROMs requirecareful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the fallingand rising edges of E. Themagnitude of this transient current peaks is dependent on the capacitive and inductive loading of the device at the output. The associatedtransient voltage peaks can be suppressed by complying with the two line outputcontrol and byproperly selected decoupling capacitors.It isrecommended that a0.1µFceramic capacitorbe used on everydevice betweenV

and VSS. This should be a high frequency capacitor of low inherent inductance and should be placed as close to the device as possible. Inaddition, a 4.7µF bulk electrolytic capacitor should be used between VCCand VSSfor every eight devices. The bulkcapacitor should be located near the power supply connection point. The purposeof the bulk capacitor is to overcome the voltage drop caused bythe inductive effects of PCB traces.

6/15

Page 7

M27W256

Table 9. Programming Mode DC Characteristics

(1)

(TA=25°C; VCC= 6.25V±0.25V; VPP= 12.75V±0.25V)

Symbol Parameter Test Condition Min Max Unit

Note: VCCmust be applied simultaneously with or before VPPand removed simultaneously orafter VPP.

Table 10. Programming Mode AC Characteristics

Input Leakage Current

≤ VIN≤ V

±10 µA Supply Current 50 mA Program Current

E=V

50 mA

Input Low Voltage –0.3 0.8 V

Input High Voltage 2

+ 0.5

Output Low Voltage IOL= 2.1mA 0.4 V

Output High Voltage TTL

= –1mA

3.6 V

A9 Voltage 11.5 12.5 V

(1)

(TA=25°C; VCC= 6.25V±0.25V; VPP= 12.75V±0.25V

Symbol Alt Parameter Min Max Unit

AVEL

QVEL

VPHEL

VCHEL

ELEH

EHQX

QXGL

GLQV

GHQZ

GHAX

Note: VCCmust be applied simultaneously with or before VPPand removed simultaneously orafter VPP.

t t

VPS

VCS

t t

OES

DFP

Address Valid to Chip Enable Low 2 µs Input Validto Chip Enable Low 2 µs VPPHigh to Chip Enable Low VCCHigh to Chip Enable Low

2 µs

2 µs Chip EnableProgram Pulse Width 95 105 µs Chip EnableHigh to Input Transition 2 µs Input Transition to Output Enable Low 2 µs Output Enable Lowto Output Valid 100 ns Output Enable High to Output Hi-Z 0 130 ns Output Enable High to Address Transition 0 ns

Programming

The M27W256 hasbeen designedto be fully compatible with the M27C256B and has the same electronic signature. Asa result theM27W256 can be programmed as the M27C256B on the same programming equipments applying 12.75V onV

and 6.25V on VCCby the use of the same PRESTO II algorithm. When delivered (and after each erasure for UV EPROM), all bits of the M27W256 are inthe ’1’ state.Data is introduced by selectively programming ’0’s into the desired bit locations.

Although only ’0’s will be programmed, both ’1’s and ’0’s can be present in thedata word. Theonly way tochangea ’0’to a ’1’is bydie exposure toultraviolet light (UV EPROM). The M27W256 is in the programming mode when VPPinput is at

12.75V, G is atVIHandE ispulsedto VIL. Thedata to be programmed is appliedto 8 bits in parallel to the data output pins. The levels required for the address anddata inputs areTTL. VCCis specified to be 6.25 V ± 0.25 V.

7/15

Page 8

M27W256

Figure 6. Programming and Verify Modes AC Waveforms

A0-A14

tAVEL

Q0-Q7

DATA IN DATA OUT

tQVEL

tVPHEL

tVCHEL

tELEH

Figure 7. Programming Flowchart

VCC= 6.25V, VPP= 12.75V

n=0

P = 100µs Pulse

VERIFY

YES

Last

Addr

YES

CHECK ALL WORDS

1st: VCC=5V

2nd: VCC= 2.7V

++ Addr

YES

++n

=25

FAIL

VALID

tEHQX

tGLQV

tQXGL

PROGRAM VERIFY

PRESTO II Programming Algorithm

PRESTO II Programming Algorithm allows to program the wholearray witha guaranteedmargin, in a typical time of 3.5 seconds. Programming with PRESTO IIinvolves the application of asequence of 100µs program pulses to each byte until a cor- rect verify occurs (see Figure 7). During programming and verify operation, a MARGIN MODE circuit is automatically activated in order to guarantee that each cell is programmed with enough margin. No overprogram pulse isapplied since the verify in MARGIN MODEat VCCmuch higher than

3.6V provides necessary margin to each programmed cell.

Program Inhibit

Programming of multiple M27W256s in parallel with different datais alsoeasily accomplished. Except for E, all likeinputs including Gof the parallel M27W256 may becommon. ATTL low level pulse applied to aM27W256’s E input, with VPPat12.75 V, will program that M27W256.A highlevelE input inhibits the other M27W256s from being programmed.

Program Verify

AI00707D

A verify (read) should be performed on the programmed bitsto determinethat theywere correctly programmed.The verify is accomplished with G at VIL, E at VIH,VPPat 12.75V and VCCat 6.25V.

tGHQZ

tGHAX

AI00759

8/15

Page 9

M27W256

On-Board Programming

The M27W256 can be directly programmed in the application circuit. See the relevant Application Note AN620.

Electronic Signature

The Electronic Signature (ES) mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment to automatically matchthe device to be programmed with its corresponding programming algorithm. The ES mode is functional in the 25°C±5°C ambient temperaturerange that isrequired when programming the M27W256. To activate the ES mode, the programming equipment must force

11.5V to 12.5V on address line A9 of the M27W256, with VCC=VPP= 5V. Two identifier bytes maythen be sequenced fromthedeviceoutputs bytoggling addressline A0 from VILtoVIH. All other address lines must be held at VILduring Electronic Signature mode. Byte 0 (A0 = VIL) represents the manufacturer code and byte 1 (A0 = VIH) the device identifier code. For the STMicroelectronics M27W256,thesetwo identifier bytes are given in Table 4 and can beread-out on outputs Q7 to Q0. Note that the M27W256 and M27C256B have the same identifier bytes.

ERASURE OPERATION (applies for UV EPROM)

The erasure characteristics of the M27W256 is such that erasure begins when the cells are exposed to light with wavelengths shorter than approximately 4000 Å. It should be noted that sunlight and some type of fluorescent lamps have wavelengths in the 3000-4000Å range. Research shows that constant exposure to room level fluorescent lighting coulderase a typical M27W256 in about 3years, while it would takeapproximately 1 week to cause erasure when exposed to direct sunlight. If theM27W256 is tobeexposed tothese types of lighting conditions forextended periods of time, it is suggestedthat opaque labels beput over the M27W256 window to prevent unintentional erasure. The recommendederasureprocedure for the M27W256 is exposureto short wave ultraviolet light whichhas wavelength 2537Å. The integrated dose (i.e. UV intensityxexposure time) forerasure should be a minimum of 15 W-sec/cm2. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with 12000

W/cm2power rating. The M27W256 should be

placed within 2.5 cm (1 inch) of the lamp tubes during the erasure. Some lamps have a filter on their tubes which should be removed before erasure.

9/15

Page 10

M27W256

Table 11. OrderingInformation Scheme

Example: M27W256 -80 K 6 TR

Device Type

M27

Supply Voltage

W = 2.7V to 3.6V

Device Function

256 = 256 Kbit (32Kb x 8)

Speed

(1,2)

-80

-100 = 100 ns

=80ns

Not For New Design

(3)

-120 = 120 ns

-150 = 150 ns

-200 = 200 ns

Package

F = FDIP28W

(4)

B = PDIP28 K = PLCC32

N = TSOP28: 8 x 13.4 mm

(4)

Temperature Range

6=–40to85°C

Options

TR = Tape& Reel Packing

Note: 1. High Speed,see AC Characteristics section for further information.

2. This speed also guarantees 70ns access time at V

3. These speeds are replaced by the 100ns.

4. Packages option available on request. Please contact STMicroelectronics local Sales Office.

= 3.0V to 3.6V.

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contactthe STMicroelectronics Sales Office nearest to you.

10/15

Page 11

M27W256

Table 12. FDIP28W - 28 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data

Symb

A 5.72 0.225 A1 0.51 1.40 0.020 0.055 A2 3.91 4.57 0.154 0.180 A3 3.89 4.50 0.153 0.177

B 0.41 0.56 0.016 0.022 B1 1.45 – – 0.057 – –

C 0.23 0.30 0.009 0.012 D 36.50 37.34 1.437 1.470

D2 33.02 – – 1.300 – –

E 15.24 – – 0.600 – – E1 13.06 13.36 0.514 0.526

e 2.54 – – 0.100 – – eA 14.99 – – 0.590 – – eB 16.18 18.03 0.637 0.710

L 3.18 4.10 0.125 0.161

S 1.52 2.49 0.060 0.098

∅ 7.11 – – 0.280 – –

α 4° 11° 4° 11°

N28 28

Typ Min Max Typ Min Max

mm inches

Figure 8. FDIP28W - 28 pin Ceramic Frit-seal DIP, with window, Package Outline

B1 B e

A3A1A

∅

Drawing is notto scale.

E1 E

FDIPW-a

11/15

Page 12

M27W256

Table 13. PDIP28 - 28 pin Plastic DIP, 600 mils width, Package Mechanical Data

Symb

Typ Min Max Typ Min Max

A – 5.08 – 0.200 A1 0.38 – 0.015 – A2 3.56 4.06 0.140 0.160

B 0.38 0.51 0.015 0.020 B1 1.52 – – 0.060 – –

C 0.20 0.30 0.008 0.012 D 36.83 37.34 1.450 1.470

D2 33.02 – – 1.300 – –

E 15.24 – – 0.600 – – E1 13.59 13.84 0.535 0.545

e1 2.54 – – 0.100 – – eA 14.99 – – 0.590 – – eB 15.24 17.78 0.600 0.700

L 3.18 3.43 0.125 0.135 S 1.78 2.08 0.070 0.082 α 0° 10° 0° 10°

mm inches

N28 28

Figure 9. PDIP28 - 28 pin Plastic DIP, 600 mils width, Package Outline

A2A1A

B1 B e1

eA eB

E1 E

PDIP

Drawing is notto scale.

12/15

Page 13

M27W256

Table 14. PLCC32 - 32lead Plastic Leaded Chip Carrier, Package Mechanical Data

Symb

A 2.54 3.56 0.100 0.140 A1 1.52 2.41 0.060 0.095 A2 – 0.38 – 0.015

B 0.33 0.53 0.013 0.021 B1 0.66 0.81 0.026 0.032

D 12.32 12.57 0.485 0.495 D1 11.35 11.56 0.447 0.455 D2 9.91 10.92 0.390 0.430

E 14.86 15.11 0.585 0.595 E1 13.89 14.10 0.547 0.555 E2 12.45 13.46 0.490 0.530

e 1.27 – – 0.050 – –

F 0.00 0.25 0.000 0.010

R 0.89 – – 0.035 – –

N32 32 Nd 7 7 Ne 9 9

CP 0.10 0.004

Typ Min Max Typ Min Max

mm inches

Figure 10. PLCC32 - 32 lead Plastic Leaded ChipCarrier, Package Outline

Ne E1 E

D2/E2

0.51 (.020)

1.14 (.045)

PLCC

Drawing is notto scale.

13/15

Page 14

M27W256

Table 15. TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4 mm, Package Mechanical Data

Symbol

Typ Min Max Typ Min Max

A 1.250 0.0492 A1 0.200 0.0079 A2 0.950 1.150 0.0374 0.0453

B 0.170 0.270 0.0067 0.0106

C 0.100 0.210 0.0039 0.0083 D 13.200 13.600 0.5197 0.5354

D1 11.700 11.900 0.4606 0.4685

e 0.550 – – 0.0217 – –

E 7.900 8.100 0.3110 0.3189

L 0.500 0.700 0.0197 0.0276

α 0° 5° 0° 5°

CP 0.100 0.0039

N28 28

mm inch

Figure 11. TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4 mm, Package Outline

DIE

TSOP-c

Drawing is notto scale

LA1 α

14/15

Page 15

M27W256

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent orpatent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces allinformation previously supplied. STMicroelectronics products are not authorized for use as critical components in lifesupport devices or systems without express written approval of STMicroelectronics.

The ST logo is registered trademark of STMicroelectronics



All other names are the property of their respective owners.

Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco -

Singapore - Spain - Sweden -Switzerland - United Kingdom - U.S.A.

STMicroelectronics GROUP OF COMPANIES

http://www.st.com

15/15