Page 1
M27W102
1 Mbit (64Kb x16) Low Voltage UV EPROM and OTP EPROM
■ 2.7V to 3.6V LOW VOLTAGE in READ
OPERATION
■ READ ACCESS TIME:
–70nsatVCC= 3.0V to 3.6V
–80nsatVCC= 2.7V to 3.6V
■ PIN COMPATIBLE with M27C1024
■ LOW POWER CONSUMPTION:
–15µA max Standby Current
– 15mA max Active Current at 5MHz
■ PROGRAMMING TIME 100µs/word
■ HIGH RELIABILITY CMOS TECHNOLOGY
– 2,000V ESD Protection
– 200mA Latchup Protection Immunity
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Device Code: 008Ch
40
1
FDIP40W (F) PDIP40 (B)
PLCC44 (K) TSOP40 (N)
Figure 1. Logic Diagram
40
1
10 x 14 mm
DESCRIPTION
The M27W102 is a low voltage 1 Mbit EPROM offered in the two ranges UV (ultra violet erase) and
OTP (one time programmable). It is ideally suited
for microprocessor systems requiring large data or
program storage and is organized as 65,536
words by 16 bits.
The M27W102 operates in the read mode with a
supply voltage as low as 2.7V at –40 to 85°C temperature range. The decrease in operating power
allows either a reduction of the size of the battery
or an increase in the time between battery recharges.
The FDIP40W (window ceramic frit-seal package)
has a transparent lid which allows the user to expose the chip to ultraviolet lightto erase the bit pattern. A new pattern can then be written to the
device by following the programming procedure.
For application where the content is programmed
only one time and erasure is not required, the
M27w102 is offered in PDIP40, PLCC44 and
TSOP40 (10 x 14 mm) packages.
A0-A15
V
16
P
E
G
V
CC
M27W102
V
SS
PP
16
Q0-Q15
AI01922
1/15April 2000
Page 2
M27W102
Figure 2A. DIP Connections
V
1
PP
2
Q15
3
4
Q14
5
Q13
Q12
6
Q11
7
Q10
8
Q9
9
Q8
10
V
SS
Q7
Q6
Q5
Q4
Q3
Q2
Q0
M27W102
11
12
13
14
15
16
17
18
19
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
2120
AI02673
V
CC
PE
NC
A15
A14
A13
A12
A11
A10
A9
V
SS
A8
A7
A6
A5
A4
A3
A2Q1
A1
A0G
Figure 2B. LCC Connections
Q13
Q14
Q15
CC
NC
VPPE
1
44
P
V
Q12
Q11
Q10
Q9 A10
Q8
V
SS
12
M27W102
NC
Q6
Q5
Q4
23
G
A0
Q3
Q2
Q1
Q0
NC
A1
NC
A2
A15
A3
A14
34
A4
A13
A12
A11
A9
V
SS
NC
A8Q7
A7
A6
A5
AI01924
Figure 2C. TSOP Connections
A9
1
A10
A11
A12 A6
A13 A5
A14
A15
NC
P
V
CC
V
PP
E
DQ15
DQ14
DQ13
DQ12 DQ4
DQ11 DQ5
DQ10
DQ9
DQ8
M27W102
10
(Normal)
11
20 21
AI01925
40
31
30
V
SS
A8
A7
A4
A3
A2
A1
A0
G
DQ0
DQ1
DQ2
DQ3
DQ6
DQ7
V
SS
Table 1. Signal Names
A0-A15 Address Inputs
Q0-Q15 Data Outputs
E Chip Enable
G Output Enable
P Program
V
PP
V
CC
V
SS
NC Not Connected Internally
Program Supply
Supply Voltage
Ground
2/15
Page 3
M27W102
Table 2. Absolute Maximum Ratings
(1)
Symbol Parameter Value Unit
T
A
T
BIAS
T
STG
(2)
V
IO
V
CC
(2)
V
A9
V
PP
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or anyother conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affectdevice reliability. Referalso to theSTMicroelectronics SUREProgram andother relevant quality documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
3. Depends on range.
Ambient Operating Temperature
Temperature Under Bias –50 to 125 °C
Storage Temperature –65 to 150 °C
Input or Output Voltage (except A9) –2 to 7 V
Supply Voltage –2 to 7 V
A9 Voltage –2 to 13.5 V
Program Supply Voltage –2 to 14 V
+0.5V with possible overshoot to VCC+2V for a period less than 20ns.
CC
(3)
–40 to 85 °C
Table 3. Operating Modes
Mode E G P A9
Read
Output Disable V
Program
Verify V
Program Inhibit
Standby
Electronic Signature
Note: X = VIHor VIL,VID= 12V ± 0.5V.
V
IL
IL
V
IL
IL
V
IH
V
IH
V
IL
V
IL
V
IH
X
V
IL
V
IH
X
XXV
V
IL
Pulse
V
IH
X
XVPPData Output
XXX
XXX
V
IL
V
IH
V
ID
V
PP
V
or V
CC
SS
or V
CC
SS
V
PP
V
PP
V
or V
CC
SS
V
CC
Q15-Q0
Data Out
Hi-Z
Data Input
Hi-Z
Hi-Z
Codes
Table 4. Electronic Signature
Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data
Manufacturer’s Code
Device Code
Note: Outputs Q15-Q8 are set to ’0’.
V
IL
V
IH
00100000 20h
10001100 8Ch
3/15
Page 4
M27W102
Table 5. AC Measurement Conditions
High Speed Standard
Input Rise and Fall Times ≤ 10ns ≤ 20ns
Input Pulse Voltages 0 to 3V 0.4V to 2.4V
Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V
Figure 3. AC Testing Input Output Waveform
High Speed
3V
1.5V
0V
Standard
2.4V
0.4V
Table 6. Capacitance
Symbol Parameter Test Condition Min Max Unit
C
IN
C
OUT
Note: Sampled only, not 100% tested.
Input Capacitance
Output Capacitance
(1)
(TA=25°C, f = 1 MHz)
2.0V
0.8V
AI01822
Figure 4. AC Testing Load Circuit
1.3V
1N914
3.3kΩ
DEVICE
UNDER
TEST
C
L
CL= 30pFfor High Speed
CL= 100pF for Standard
CLincludes JIG capacitance
V
V
IN
OUT
=0V
=0V
6pF
12 pF
OUT
AI01823B
DEVICE OPERATION
The operating modes of theM27W102 arelisted in
the Operating Modes table. A single power supply
is required in the read mode. All inputs are TTL
levels except for VPPand 12V on A9 for Electronic
Signature.
Read Mode
The M27W102 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable(G)is the output control and should
be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time
4/15
(t
) is equal to the delay from E to output
AVQV
(t
). Data is available attheoutputaftera delay
ELQV
of tOEfrom the falling edge of G, assuming that E
has been low and the addresses have been stable
for at least t
AVQV-tGLQV
.
Standby Mode
The M27W102 has a standby mode which reduces the supply current from 15mA to 15µA with low
voltage operation VCC≤ 3.6V, see Read Mode DC
Characteristics table for details. The M27W102 is
placed in the standby mode by applying a CMOS
high signal to the E input. When in the standby
mode, the outputs are in a high impedance state,
independent of the G input.
Page 5
M27W102
Table 7. Read Mode DC Characteristics
(1)
(TA= –40 to 85°C; VCC= 2.7V to 3.6V; VPP=VCC)
Symbol Parameter Test Condition Min Max Unit
I
I
I
CC
I
CC1
I
CC2
I
V
V
IH
V
V
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
Input Leakage Current
LI
Output Leakage Current
LO
Supply Current
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current
PP
Input Low Voltage –0.6
IL
(2)
Input High Voltage
Output Low Voltage
OL
Output High Voltage TTL
OH
2. Maximum DC voltage on Output is V
CC
+0.5V.
I
OUT
0V ≤ V
0V ≤ V
E=V
E>V
I
≤ V
IN
CC
≤ V
OUT
CC
,G=VIL,
IL
= 0mA, f = 5MHz,
≤ 3.6V
V
CC
E=V
IH
– 0.2V,
CC
V
≤ 3.6V
CC
V
PP=VCC
I
= 2.1mA
OL
= –400µA
OH
±10 µA
±10 µA
15 mA
1mA
15 µA
10 µA
0.2 V
CC
0.7 V
CCVCC
2.4 V
+ 0.5
0.4 V
V
V
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, Eshould be decoded and used as the primary device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system controlbus. This ensures that all deselected memory devices are intheir low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, ICC, has three segments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
transient current peaks is dependent on the capacitive and inductive loading of the device at the
output. The associated transient voltage peaks
can be suppressed by complying with the two line
outputcontrolandbyproperly selected decoupling
capacitors.It is recommended that a 0.1µFceramic capacitor be used on every device between V
CC
and VSS. This should be a high frequency capacitor of low inherent inductance and should be
placed as close to the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be
used between VCCand VSSfor every eight devices. The bulk capacitor should be located near the
power supply connection point. The purposeofthe
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
5/15
Page 6
M27W102
Table 8. Read Mode AC Characteristics
(1)
(TA= –40 to 85°C; VCC= 2.7V to 3.6V; VPP=VCC)
M27W102
(3)
Symbol Alt Parameter
Test
Condition
VCC= 3.0V to 3.6V VCC= 2.7V to 3.6V VCC= 2.7V to 3.6V
Min Max Min Max Min Max
E=V
G=V
G=V
E=V
G=V
E=V
E=V
G=V
,
IL
IL
IL
IL
IL
IL
IL
IL
0 40 0 50 0 60 ns
0 40 0 50 0 60 ns
,
000ns
t
AVQV
t
ELQV
t
GLQV
(2)
t
EHQZ
(2)
t
GHQZ
t
AXQX
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC measurement conditions.
Address Valid to
t
ACC
Output Valid
Chip Enable Low to
t
CE
Output Valid
Output Enable Low
t
OE
to Output Valid
Chip Enable High
t
DF
to Output Hi-Z
Output EnableHigh
t
DF
to Output Hi-Z
Address Transition
t
OH
to Output Transition
-80
70 80 100 ns
70 80 100 ns
40 50 60 ns
-100
(-120/-150/-200)
Unit
Figure 5. Read Mode AC Waveforms
A0-A15
tAVQV
E
G
tELQV
Q0-Q15
VALID
tGLQV
VALID
tAXQX
tEHQZ
tGHQZ
Hi-Z
AI00705B
6/15
Page 7
M27W102
Table 9. Programming Mode AC Characteristics
(1)
(TA=25°C; VCC= 6.25V ± 0.25V; VPP= 12.75V ± 0.25V)
Symbol Parameter Test Condition Min Max Unit
I
LI
I
CC
I
PP
V
IL
V
IH
V
OL
V
OH
V
ID
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
Table 10. Programming Mode AC Characteristics
Input Leakage Current
0V ≤ V
≤ V
IN
IH
±10 µA
Supply Current 50 mA
Program Current
E=V
IL
50 mA
Input Low Voltage –0.3 0.8 V
V
Input High Voltage 2
CC
+ 0.5
Output Low Voltage IOL= 2.1mA 0.4 V
I
Output High Voltage TTL
= –400µA
OH
2.4 V
A9 Voltage 11.5 12.5 V
(1)
(TA=25°C; VCC= 6.25V ± 0.25V; VPP= 12.75V ± 0.25V)
Symbol Alt Parameter Test Condition Min Max Unit
t
AVPL
t
QVPL
t
VPHPL
t
VCHPL
t
ELPL
t
PLPH
t
PHQX
t
QXGL
t
GLQV
(2)
t
GHQZ
t
GHAX
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
t
t
t
VPS
t
VCS
t
CES
t
t
t
OES
t
t
DFP
t
Address Valid to Program Low 2 µs
AS
Input Valid to Program Low 2 µs
DS
VPPHigh to Program Low
VCCHigh to Program Low
2 µs
2 µs
Chip Enable Low to Program Low 2 µs
Program Pulse Width 95 105 µs
PW
Program High to Input Transition 2 µs
DH
Input Transition to Output Enable Low 2 µs
Output Enable Low to Output Valid 100 ns
OE
Output Enable High to Output Hi-Z 0 130 ns
Output Enable High to Address
AH
Transition
0ns
V
Programming
The M27W102 hasbeen designed to be fully compatible withthe M27C1024 and hasthesameelectronic signature. As a result the M27W102 can be
programmed as the M27C1024 on the same programming equipmentapplying 12.75V on VPPand
6.25V on VCCby the use of the same PRESTO II
algorithm. When delivered (andafter each‘1’serasure for UV EPROM), all bits of the M27W102 are
in the ’1’ state. Data is introduced by selectively
programming ’0’sinto the desired bit locations. Al-
though only ’0’s will be programmed, both ’1’s and
’0’scanbe presentin the data word. The only way
to change a ‘0’ to a ‘1’ is by die exopsure to ultraviolet light (UV EPROM). The M27W102 is in the
programming mode when VPPinput is at 12.75V,
EisatVILand P is pulsed to VIL. The data to be
programmed is applied to 16 bits in parallel to the
data output pins. The levels required for the address and data inputs are TTL. VCCis specified to
be 6.25V ± 0.25V.
7/15
Page 8
M27W102
Figure 6. Programming and Verify Modes AC Waveforms
A0-A15
tAVPL
Q0-Q15
tQVPL
V
PP
tVPHPL
V
CC
tVCHPL
E
tELPL
P
tPLPH
G
Figure 7. Programming Flowchart
VCC= 6.25V, VPP= 12.75V
n=0
P = 100µs Pulse
NO
NO
VERIFY
YES
Last
NO
Addr
YES
CHECK ALL WORDS
1st: VCC=5V
2nd: VCC= 2.7V
++ Addr
YES
++n
=25
FAIL
VALID
DATA IN DATA OUT
tPHQX
tGLQV
tQXGL
PROGRAM VERIFY
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows programming of the whole array with a guaranteed
margin, in a typical time of 6.5 seconds. Programming with PRESTO II consists of applying a sequence of 100µs program pulses to each word
until a correct verify occurs (see Figure 7). During
programming and verify operation, a MARGIN
MODE circuit is automatically activated in order to
guarantee that each cell is programmed with
enough margin. No overprogram pulse is applied
since the verify in MARGIN MODE at VCCmuch
higher than 3.6V, provides necessary margin to
each programmed cell.
Program Inhibit
Programming of multiple M27W102s in parallel
with different data is also easily accomplished. Except for E, all like inputs including G of the parallel
M27W102 may be common. A TTL low level pulse
applied to a M27W102’s P input, with E low and
VPPat12.75V, willprogramthat M27W102.A high
level E input inhibits theotherM27W102sfrombeing programmed.
Program Verify
AI00707D
A verify (read) should be performed on the programmed bits to determine that they were correctly programmed. The verify is accomplished with E
and G at VIL, P at VIH,VPPat 12.75V and VCCat
6.25V.
tGHQZ
tGHAX
AI00706
8/15
Page 9
M27W102
On-Board Programming
The M27W102 can be directly programmed in the
application circuit. See the relevant Application
Note AN620.
Electronic Signature
The Electronic Signature (ES) mode allows the
reading out of a binary code froman EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically match the device to be programmed
with its corresponding programming algorithm.
The ES mode is functional in the 25°C ± 5°C ambient temperaturerangethat is required when programming the M27W102. To activate the ES
mode, the programming equipment must force
11.5V to 12.5V on address line A9 of the
M27W102 with VPP=VCC= 5V. Two identifier
bytes may then be sequenced from the device outputs by togglingaddress line A0from VILtoVIH. All
other address lines must be held at VILduring
Electronic Signature mode. Byte 0 (A0 = VIL) represents the manufacturer code and byte 1
(A0 = VIH) the device identifier code. For the
STMicroelectronics M27W102, these two identifier
bytes are given in Table 4 and can be read-out on
outputs Q7 to Q0.
Note that the M27W102 and M27C1002 have the
same byte identifier.
ERASUREOPERATION(appliesto UV EPROM)
The erasure characteristics of the M27W102 is
such that erasure begins when the cells are exposed to light with wavelengths shorter than approximately 4000Å.Itshould benoted thatsunlight
and some type of fluorescent lamps have wavelengths in the 3000-4000Å range. Research
shows that constant exposure to room level fluorescent lighting could erase a typical M27W102 in
about 3 years, while it would take approximately 1
week to cause erasure when exposed to direct
sunlight. If the M27W102 is to be exposed to these
types of lighting conditions for extended periods of
time, itissuggestedthatopaque labels beputover
the M27W102 window to prevent unintentional
erasure. The recommended erasure procedure for
the M27W102is exposuretoshortwave ultraviolet
light which has a wavelength of 2537Å. The integrated dose (i.e. UV intensity x exposure time) for
erasure should be a minimum of 15 W-sec/cm2.
The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with
12000 µW/cm2power rating. The M27W102
should be placed within 2.5 cm (1 inch) of the lamp
tubes during the erasure. Some lamps have a filter
on their tubes which should be removed before
erasure.
9/15
Page 10
M27W102
Table 11. Ordering Information Scheme
Example: M27W102 -80 K 6 TR
Device Type
M27
SupplyVoltage
W = 2.7V to 3.6V
Device Function
102 = 1 Mbit (64Kb x16)
Speed
(1,2)
-80
-100 = 100 ns
=80ns
Not For New Design
(3)
-120 = 120 ns
-150 = 150 ns
-200 = 200 ns
Package
F = FDIP40W
(4)
B = PDIP40
K = PLCC44
N = TSOP40:10 x 14 mm
(4)
Temperature Range
6=–40to85°C
Options
TR = Tape& Reel Packing
Note: 1. High Speed, see AC Characteristics section for further information.
2. This speed also guarantees 70ns access time at V
3. These speeds are replaced by the 100ns.
4. Packages option available on request. Please contact STMicroelectronics local Sales Office.
= 3.0V to 3.6V.
CC
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
Table 12. Revision History
Date Revision Details
July 1999 First Issue
FDIP40W Package Dimension, L Max added (Table13)
04/04/00
10/15
TSOP40 Package Dimension changed (Table 16)
0to70°C Temperature Range deleted
I
changed (Table 7)
PP
Page 11
M27W102
Table 13. FDIP40W - 40 pin Ceramic Frit-seal DIP with window, Package Mechanical Data
Symbol
A 5.72 0.225
A1 0.51 1.40 0.020 0.055
A2 3.91 4.57 0.154 0.180
A3 3.89 4.50 0.153 0.177
B 0.41 0.56 0.016 0.022
B1 1.45 – – 0.057 – –
C 0.23 0.30 0.009 0.012
D 51.79 52.60 2.039 2.071
D2 48.26 – – 1.900 – –
E 15.24 – – 0.600 – –
E1 13.06 13.36 0.514 0.526
e 2.54 – – 0.100 – –
eA 14.99 – – 0.590 – –
eB 16.18 18.03 0.637 0.710
L 3.18 4.10 0.125 0.161
S 1.52 2.49 0.060 0.098
∅ 8.13 – – 0.320 – –
α 4° 11° 4° 11°
N40 40
Typ Min Max Typ Min Max
mm inches
Figure 8. FDIP40W - 40 pin Ceramic Frit-seal DIP with window, Package Outline
A2
B1 B e
A3A1A
L
α
C
eA
D2
eB
D
S
N
∅
1
Drawing is not to scale.
E1 E
FDIPW-a
11/15
Page 12
M27W102
Table 14. PDIP40 - 40 pin Plastic DIP, 600 mils width, Package Mechanical Data
Symbol
Typ Min Max Typ Min Max
A 4.45 – – 0.175 – –
A1 0.64 0.38 – 0.025 0.015 –
A2 3.56 3.91 0.140 0.154
B 0.38 0.53 0.015 0.021
B1 1.14 1.78 0.045 0.070
C 0.20 0.31 0.008 0.012
D 51.78 52.58 2.039 2.070
D2 48.26 – – 1.900 – –
E 14.80 16.26 0.583 0.640
E1 13.46 13.99 0.530 0.551
e1 2.54 – – 0.100 – –
eA 15.24 – – 0.600 –
eB 15.24 17.78 0.600 0.700
L 3.05 3.81 0.120 0.150
S 1.52 2.29 0.060 0.090
α 0° 15° 0° 15°
N40 40
mm inches
Figure 9. PDIP40 - 40 pin Plastic DIP, 600 mils width, Package Outline
A2A1A
L
α
B1 B e1
D2
D
S
N
E1 E
1
Drawing is not to scale.
C
eA
eB
PDIP
12/15
Page 13
M27W102
Table 15. PLCC44 - 44 lead Plastic Leaded Chip Carrier, Package Mechanical Data
Symbol
Typ Min Max Typ Min Max
A 4.20 4.70 0.165 0.185
A1 2.29 3.04 0.090 0.120
A2 – 0.51 – 0.020
B 0.33 0.53 0.013 0.021
B1 0.66 0.81 0.026 0.032
D 17.40 17.65 0.685 0.695
D1 16.51 16.66 0.650 0.656
D2 14.99 16.00 0.590 0.630
E 17.40 17.65 0.685 0.695
E1 16.51 16.66 0.650 0.656
E2 14.99 16.00 0.590 0.630
e 1.27 – – 0.050 – –
F 0.00 0.25 0.000 0.010
R 0.89 – – 0.035 – –
N44 44
CP 0.10 0.004
mm inches
Figure 10. PLCC44 - 44 lead Plastic Leaded Chip Carrier, Package Outline
D
D1
1N
Ne E1 E
F
D2/E2
0.51 (.020)
1.14 (.045)
Nd
R
PLCC
Drawing is not to scale.
A1
A2
B1
e
B
A
CP
13/15
Page 14
M27W102
Table 16. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 14 mm, Package Mechanical Data
Symbol
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 0.950 1.050 0.0374 0.0413
B 0.170 0.270 0.0067 0.0106
C 0.100 0.210 0.0039 0.0083
D 13.800 14.200 0.5433 0.5591
D1 12.300 12.500 0.4843 0.4921
e 0.500 – – 0.0197 – –
E 9.900 10.100 0.3898 0.3976
L 0.500 0.700 0.0197 0.0276
α 0° 5° 0° 5°
CP 0.100 0.0039
N40 40
mm inch
Figure 11. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 14 mm, Package Outline
A2
1N
e
E
B
N/2
D1
D
DIE
A
CP
C
TSOP-a
Drawing is not to scale.
LA1 α
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M27W102
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