Page 1
M27W101
1 Mbit (128Kb x8) Low Voltage UV EPROM and OTP EPROM
■ 2.7V to 3.6V LOW VOLTAGE in READ
OPERATION
■ ACCESS TIME:
–70nsatVCC= 3.0V to 3.6V
–80nsatVCC= 2.7V to 3.6V
■ PIN COMPATIBLE with M27C1001
■ LOW POWER CONSUMPTION:
– Active Current 15mA at 5MHz
– Standby Current 15µA
■ PROGRAMMING TIME 100µs/byte
■ HIGH RELIABILITY CMOS TECHNOLOGY
– 2,000V ESD Protection
– 200mA Latchup Protection Immunity
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 05h
DESCRIPTION
The M27W101 is a low voltage 1 Mbit EPROM offered intwo range UV (ultra violet erase) and OTP
(one timeprogrammable).Itisideallysuitedfor microprocessor systems requiring large data or program storage and is organized as 131,072 by 8
bits.
The M27W101 operates in the read mode with a
supply voltage aslow as 2.7V at –40to 85 °Ctemperature range.
The decrease in operating power allows either a
reduction of the size of the battery or an increase
in the time between battery recharges.
The FDIP32W (window ceramic frit-seal package)
has a transparent lid which allows the user to expose the chipto ultraviolet lightto erase the bit pattern. A new pattern can then be written to the
device by following the programming procedure.
For application where the content is programmed
only one time and erasure is not required, the
M27W101 is offered in PDIP32, PLCC32 and
TSOP32 (8 x 20 mm) packages.
32
1
FDIP32W (F) PDIP32 (B)
PLCC32 (K) TSOP32 (N)
Figure 1. Logic Diagram
V
17
A0-A16
P
E
G
32
V
CC
M27W101
V
SS
1
8 x 20 mm
PP
8
Q0-Q7
AI01587
1/15April 2000
Page 2
M27W101
Figure 2A. DIP Connections
V
1
PP
2
A15
3
A12
4
A7
5
A6
6
A5
7
A4
8
A3
A2
A1
A0
Q0
Q2
SS
M27W101
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
AI02674
V
CC
PA16
NC
A14
A13
A8
A9
A11
G
A10
E
Q7
Q6
Q5Q1
Q4
Q3V
Figure 2B. LCC Connections
A16
A7
A6
A5
A4
A3
A2
A1
A0
Q0
A12
9
Q1
VPPV
A15
1
32
M27W101
17
Q2
Q3
SS
V
Q4
CC
P
Q5
NC
25
Q6
A14
A13
A8
A9
A11
G
A10
E
Q7
AI01588
Figure 2C. TSOP Connections
A11 G
A9
A8
A13
A14
NC
V
CC
V
PP
A16
A15
A12
A7
A6
A5
A4 A3
1
P
M27W101
8
(Normal)
9
16 17
32
25
24
AI01589
A10
E
Q7
Q6
Q5
Q4
Q3
V
SS
Q2
Q1
Q0
A0
A1
A2
Table 1. Signal Names
A0-A16 Address Inputs
Q0-Q7 Data Outputs
E Chip Enable
G Output Enable
P Program
V
PP
V
CC
V
SS
NC Not Connected Internally
Program Supply
Supply Voltage
Ground
2/15
Page 3
M27W101
Table 2. Absolute Maximum Ratings
(1)
Symbol Parameter Value Unit
T
A
T
BIAS
T
STG
(2)
V
IO
V
CC
(2)
V
A9
V
PP
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at theseor any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affectdevice reliability. Referalso to theSTMicroelectronics SUREProgram andother relevant quality documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
3. Depends on range.
Ambient Operating Temperature
Temperature Under Bias –50 to 125 °C
Storage Temperature –65 to 150 °C
Input or Output Voltage (except A9) –2 to 7 V
Supply Voltage –2 to 7 V
A9 Voltage –2 to 13.5 V
Program Supply Voltage –2 to 14 V
+0.5V with possible overshoot to VCC+2V for a period less than 20ns.
CC
(3)
–40 to 85 °C
Table 3. Operating Modes
Mode E G P A9
Read
Output Disable V
Program
Verify V
Program Inhibit
Standby
Electronic Signature
Note: X = VIHor VIL,VID= 12V ± 0.5V.
V
IL
IL
V
IL
IL
V
IH
V
IH
V
IL
V
IL
V
IH
V
IH
V
IL
X
XX
XXV
VILPulse
V
IH
X
XVPPData Out
XX
XXX
V
IL
V
IH
V
ID
V
PP
V
or V
CC
SS
or V
CC
SS
V
PP
V
PP
V
or V
CC
SS
V
CC
Q7-Q0
Data Out
Hi-Z
Data In
Hi-Z
Hi-Z
Codes
Table 4. Electronic Signature
Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data
Manufacturer’s Code
Device Code
V
IL
V
IH
00100000 20h
00000101 05h
3/15
Page 4
M27W101
Table 5. AC Measurement Conditions
High Speed Standard
Input Rise and Fall Times ≤ 10ns ≤ 20ns
Input Pulse Voltages 0 to 3V 0.4V to 2.4V
Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V
Figure 3. AC Testing Input Output Waveform
High Speed
3V
1.5V
0V
Standard
2.4V
0.4V
Table 6. Capacitance
Symbol Parameter Test Condition Min Max Unit
C
IN
C
OUT
Note: 1. Sampled only, not 100% tested.
Input Capacitance
Output Capacitance
(1)
(TA=25°C, f = 1 MHz)
2.0V
0.8V
AI01822
Figure 4. AC Testing Load Circuit
1.3V
1N914
3.3kΩ
DEVICE
UNDER
TEST
C
L
CL= 30pFfor High Speed
CL= 100pF for Standard
CLincludes JIG capacitance
V
V
IN
OUT
=0V
=0V
6pF
12 pF
OUT
AI01823B
DEVICE OPERATION
The operating modes of theM27W101arelisted in
the Operating Modes table. A single power supply
is required in the read mode. All inputs are TTL
levels except for VPPand 12V on A9 for Electronic
Signature.
Read Mode
The M27W101 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable(G)is the output control and should
be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time
4/15
(t
) is equal to the delay from E to output
AVQV
(t
). Data is available attheoutputaftera delay
ELQV
of t
from the falling edge of G, assuming that
GLQV
E has been low and the addresses havebeen stable for at least t
AVQV-tGLQV
.
Standby Mode
The M27W101 has a standby mode which reduces the supply current from 15mA to 15µA with low
voltage operation VCC≤ 3.6V, see Read Mode DC
Characteristics table for details. The M27W101 is
placed in the standby mode by applying a CMOS
high signal to the E input. When in the standby
mode, the outputs are in a high impedance state,
independent of the G input.
Page 5
M27W101
Table 7. Read Mode DC Characteristics
(1)
(TA= –40 to 85°C; VCC= 2.7V to 3.6V; VPP=VCC)
Symbol Parameter Test Condition Min Max Unit
I
I
I
CC
I
CC1
I
CC2
I
V
V
IH
V
V
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
Input Leakage Current
LI
Output Leakage Current
LO
Supply Current
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current
PP
Input Low Voltage –0.6
IL
(2)
Input High Voltage
Output Low Voltage
OL
Output High Voltage TTL
OH
2. Maximum DC voltage on Output is V
CC
+0.5V.
I
OUT
0V ≤ V
0V ≤ V
E=V
E>V
I
OH
≤ V
IN
CC
≤ V
OUT
IL
= 0mA, f = 5MHz,
V
CC
E=V
CC
V
CC
V
PP=VCC
I
= 2.1mA
OL
= –400µA
CC
,G=VIL,
≤ 3.6V
IH
– 0.2V,
≤ 3.6V
±10 µA
±10 µA
15 mA
1mA
15 µA
10 µA
0.2 V
CC
0.7 V
CCVCC
2.4 V
+ 0.5
0.4 V
V
V
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection.
The two line control function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, Eshould be decoded and used as the primary device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system controlbus. This ensures that all deselected memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, ICC, has three segments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
the transient current peaks is dependent on the
capacitive and inductive loading of the device at
the output. The associatedtransientvoltagepeaks
can be suppressed by complying with the two line
outputcontrolandbyproperlyselected decoupling
capacitors.It is recommended that a 0.1µFceramic capacitor be used on every device between V
CC
and VSS. This should be a high frequency capacitor of low inherent inductance and should be
placed as close to the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be
used between VCCand VSSfor every eight devices. The bulk capacitor should be located near the
power supply connection point. The purposeofthe
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
5/15
Page 6
M27W101
Table 8. Read Mode AC Characteristics
(1)
(TA= –40 to 85°C; VCC= 2.7V to 3.6V; VPP=VCC)
M27W101
(3)
Symbol Alt Parameter
Test
Condition
VCC= 3.0V to 3.6V VCC= 2.7V to 3.6V VCC= 2.7V to 3.6V
Min Max Min Max Min Max
E=V
G=V
G=V
E=V
G=V
E=V
E=V
G=V
,
IL
IL
IL
IL
IL
IL
,
IL
IL
0 40 0 50 0 60 ns
0 40 0 50 0 60 ns
000ns
t
AVQV
t
ELQV
t
GLQV
(2)
t
EHQZ
(2)
t
GHQZ
t
AXQX
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC measurement conditions.
Address Valid to
t
ACC
Output Valid
Chip Enable Low to
t
CE
Output Valid
Output Enable Low
t
OE
to Output Valid
Chip Enable High
t
DF
to Output Hi-Z
Output EnableHigh
t
DF
to Output Hi-Z
Address Transition
t
OH
to Output Transition
-80
70 80 100 ns
70 80 100 ns
40 50 60 ns
-100
(-120/-150/-200)
Unit
Figure 5. Read Mode AC Waveforms
A0-A16
tAVQV
E
G
tELQV
Q0-Q7
VALID
tGLQV
VALID
tAXQX
tEHQZ
tGHQZ
Hi-Z
AI00713B
6/15
Page 7
M27W101
Table 9. Programming Mode DC Characteristics
(1)
(TA=25°C; VCC= 6.25V ± 0.25V; VPP= 12.75V ± 0.25V)
Symbol Parameter Test Condition Min Max Unit
I
LI
I
CC
I
PP
V
IL
V
IH
V
OL
V
OH
V
ID
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
Table 10. Programming Mode AC Characteristics
Input Leakage Current
≤ VIN≤ V
V
IL
IH
±10 µA
Supply Current 50 mA
Program Current
E=V
IL
50 mA
Input Low Voltage –0.3 0.8 V
V
Input High Voltage 2
CC
+ 0.5
Output Low Voltage IOL= 2.1mA 0.4 V
I
Output High Voltage TTL
= –400µA
OH
2.4 V
A9 Voltage 11.5 12.5 V
(1)
(TA=25°C; VCC= 6.25V ± 0.25V; VPP= 12.75V ± 0.25V
Symbol Alt Parameter Test Condition Min Max Unit
t
AVPL
t
QVPL
t
VPHPL
t
VCHPL
t
ELPL
t
PLPH
t
PHQX
t
QXGL
t
GLQV
(2)
t
GHQZ
t
GHAX
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
t
t
t
VPS
t
VCS
t
CES
t
t
t
OES
t
t
DFP
t
Address Valid to Program Low 2 µs
AS
Input Valid to Program Low 2 µs
DS
VPP High to Program Low 2 µs
VCC High to Program Low 2 µs
Chip Enable Low to Program Low 2 µs
Program Pulse Width 95 105 µs
PW
Program High to Input Transition 2 µs
DH
Input Transition to Output Enable Low 2 µs
Output Enable Low to Output Valid 100 ns
OE
Output Enable High to Output Hi-Z 0 130 ns
Output Enable High to Address
AH
Transition
0ns
V
Programming
The M27W101 hasbeen designed to be fully compatible withthe M27C1001and hasthe same electronic signature. As a result the M27W101 can be
programmed as the M27C1001 on the same programming equipmentapplying 12.75V on VPPand
6.25V on VCCusing the same PRESTO II algorithm. Whendelivered (and after each ‘1’s erasure
for UVEPROM), allbits of theM27W101 areinthe
’1’ state. Data is introduced by selectively programming ’0’s into the desired bit locations. Al-
though only ’0’s will be programmed, both ’1’sand
’0’scanbe presentin the data word. The only way
to change a ‘0’ to a ‘1’ is by die exposure to ultraviolet light (UV EPROM). The M27W101 is in the
programming mode when VPPinput is at 12.75V,
EisatVILand P is pulsed to VIL. The data to be
programmed is applied to 8 bits in parallel to the
data output pins. The levels required for the address and data inputs are TTL. VCCis specified to
be 6.25V ± 0.25V.
7/15
Page 8
M27W101
Figure 6. Programming and Verify Modes AC Waveforms
A0-A16
tAVPL
Q0-Q7
tQVPL
V
PP
tVPHPL
V
CC
tVCHPL
E
tELPL
P
tPLPH
G
Figure 7. Programming Flowchart
VCC= 6.25V, VPP= 12.75V
n=0
P = 100µs Pulse
NO
NO
VERIFY
YES
Last
NO
Addr
YES
CHECK ALL BYTES
1st: VCC=5V
2nd: VCC= 2.7V
++ Addr
YES
++n
=25
FAIL
VALID
DATA IN DATA OUT
tPHQX
tGLQV
tQXGL
PROGRAM VERIFY
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows the
whole array to be programmed, with a guaranteed
margin, in a typical time of 13 seconds. Programming with PRESTO II involves in applying a sequence of 100µs program pulsesto eachbyte until
a correct verify occurs (see Figure 7). During programming and verify operation, a MARGIN MODE
circuit is automatically activated in order to guarantee that each cell is programmed with enough
margin. Nooverprogram pulse is applied since the
verify in MARGIN MODE at VCCmuch higher than
3.6V, provides necessary margin to each programmed cell.
Program Inhibit
Programming of multiple M27W101s in parallel
with different data is also easily accomplished. Except for E, all like inputs including G of the parallel
M27W101 may be common. A TTL low level pulse
applied to a M27W101’s P input, with E low and
VPPat12.75V, willprogramthat M27W101.A high
level E input inhibits theotherM27W101sfrombeing programmed.
Program Verify
AI00715D
A verify (read) should be performed on the programmed bits to determine that they were correctly programmed. The verify is accomplished with E
and G at VIL, P at VIH,VPPat 12.75V and VCCat
6.25V.
tGHQZ
tGHAX
AI00714
8/15
Page 9
M27W101
On-Board Programming
The M27W101 can be directly programmed in the
application circuit. See the relevant Application
Note AN620.
Electronic Signature
The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically match the device to be programmed
with its corresponding programming algorithm.
The ES mode is functional in the 25°C ± 5°C ambient temperature range that is required when programming the M27W101. To activate the ES
mode, the programming equipment must force
11.5V to 12.5V on address line A9 of the
M27W101, with VPP=VCC= 5V. Two identifier
bytes may then be sequenced from the deviceoutputs by toggling address line A0 fromVILtoVIH.All
other address lines must be held at VILduring
Electronic Signature mode.
Byte 0 (A0 = VIL) represents the manufacturer
code and byte 1 (A0 = VIH) the device identifier
code. For the STMicroelectronics M27W101,
these two identifier bytes are given in Table 4 and
can be read-out on outputs Q7 to Q0.
Note that the M27W101 and M27C1001 have the
same identifier byte.
ERASURE OPERATION (applies to UV EPROM)
The erasure characteristics of the M27W101 is
such that erasure begins when the cells are exposed to light with wavelengths shorter than approximately 4000 Å. It should be noted that
sunlight and some type of fluorescent lamps have
wavelengths in the 3000-4000 Å range. Research
shows that constant exposure to room level fluorescent lighting could erase a typical M27W101 in
about 3 years, while it would take approximately 1
week to cause erasure when exposed to direct
sunlight. If the M27W101 is to beexposed to these
types of lighting conditions for extended periods of
time, itissuggestedthatopaque labels beputover
the M27W101 window to prevent unintentional
erasure. The recommended erasure procedure for
the M27W101is exposuretoshortwaveultraviolet
light which has a wavelength of 2537 Å. The integrated dose (i.e. UV intensity x exposure time) for
erasure should be a minimum of 15 W-sec/cm2.
The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with
12000 µW/cm2power rating. The M27W101
should be placed within 2.5 cm (1 inch)of the lamp
tubes during the erasure. Some lamps have afilter
on their tubes which should be removed before
erasure.
9/15
Page 10
M27W101
Table 11. Ordering Information Scheme
Example: M27W101 -80 K 6 TR
Device Type
M27
Supply Voltage
W = 2.7V to 3.6V
Device Function
101 = 1 Mbit (128Kb x8)
Speed
(1,2)
-80
-100 = 100 ns
=80ns
Not For New Design
(3)
-120 = 120 ns
-150 = 150 ns
-200 = 200 ns
Package
F = FDIP32W
(4)
B = PDIP32
K = PLCC32
N = TSOP32: 8 x 20 mm
(4)
Temperature Range
6=–40to85°C
Options
TR = Tape& Reel Packing
Note: 1. High Speed, see AC Characteristics section for further information.
2. This speed also guarantees 70ns access time at V
3. These speeds are replaced by the 100ns.
4. Packages option available on request. Please contact STMicroelectronics local Sales Office.
= 3.0V to 3.6V.
CC
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
Table 12. Revision History
Date Revision Details
July 1999 First Issue
FDIP32W Package Dimension, L Max added (Table 13)
04/04/00
10/15
TSOP32 and PLCC32 Package Dimension changed (Table16 and 15)
0to70°C Temperature Range deleted
Programming Time changed
Page 11
M27W101
Table 13. FDIP32W - 32 pin Ceramic Frit-seal DIP with window, Package Mechanical Data
Symb
A 5.72 0.225
A1 0.51 1.40 0.020 0.055
A2 3.91 4.57 0.154 0.180
A3 3.89 4.50 0.153 0.177
B 0.41 0.56 0.016 0.022
B1 1.45 – – 0.057 – –
C 0.23 0.30 0.009 0.012
D 41.73 42.04 1.643 1.655
D2 38.10 – – 1.500 – –
E 15.24 – – 0.600 – –
E1 13.06 13.36 0.514 0.526
e 2.54 – – 0.100 – –
eA 14.99 – – 0.590 – –
eB 16.18 18.03 0.637 0.710
L 3.18 4.10 0.125 0.161
S 1.52 2.49 0.060 0.098
∅ 7.11 – – 0.280 – –
α 4° 11° 4° 11°
N32 32
Typ Min Max Typ Min Max
mm inches
Figure 8. FDIP32W - 32 pin Ceramic Frit-seal DIP with window, Package Outline
A2
B1 B e
A3A1A
L
α
C
eA
D2
eB
D
S
N
∅
1
Drawing is not to scale.
E1 E
FDIPW-a
11/15
Page 12
M27W101
Table 14. PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Mechanical Data
Symb
Typ Min Max Typ Min Max
A – 5.08 – 0.200
A1 0.38 – 0.015 –
A2 3.56 4.06 0.140 0.160
B 0.38 0.51 0.015 0.020
B1 1.52 – – 0.060 – –
C 0.20 0.30 0.008 0.012
D 41.78 42.04 1.645 1.655
D2 38.10 – – 1.500 – –
E 15.24 – – 0.600 – –
E1 13.59 13.84 0.535 0.545
e1 2.54 – – 0.100 – –
eA 15.24 – – 0.600 – –
eB 15.24 17.78 0.600 0.700
L 3.18 3.43 0.125 0.135
S 1.78 2.03 0.070 0.080
α 0° 10° 0° 10°
N32 32
mm inches
Figure 9. PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Outline
A2A1A
L
B1 B e1
D2
α
eA
eB
D
S
N
E1 E
1
Drawing is not to scale.
C
PDIP
12/15
Page 13
M27W101
Table 15. PLCC32 - 32lead Plastic Leaded Chip Carrier, Package Mechanical Data
Symb
A 2.54 3.56 0.100 0.140
A1 1.52 2.41 0.060 0.095
A2 0.38 – 0.015 –
B 0.33 0.53 0.013 0.021
B1 0.66 0.81 0.026 0.032
D 12.32 12.57 0.485 0.495
D1 11.35 11.56 0.447 0.455
D2 9.91 10.92 0.390 0.430
E 14.86 15.11 0.585 0.595
E1 13.89 14.10 0.547 0.555
E2 12.45 13.46 0.490 0.530
e 1.27 – – 0.050 – –
F 0.00 0.25 0.000 0.010
R 0.89 – – 0.035 – –
N32 32
Nd 7 7
Ne 9 9
CP 0.10 0.004
Typ Min Max Typ Min Max
mm inches
Figure 10. PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Outline
D
D1
1N
Ne E1 E
F
D2/E2
0.51 (.020)
1.14 (.045)
Nd
R
PLCC
Drawing is not to scale.
A1
A2
B1
e
B
A
CP
13/15
Page 14
M27W101
Table 16. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Mechanical Data
Symbol
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 0.950 1.050 0.0374 0.0413
B 0.150 0.270 0.0059 0.0106
C 0.100 0.210 0.0039 0.0083
D 19.800 20.200 0.7795 0.7953
D1 18.300 18.500 0.7205 0.7283
e 0.500 – – 0.0197 – –
E 7.900 8.100 0.3110 0.3189
L 0.500 0.700 0.0197 0.0276
α 0° 5° 0° 5°
CP 0.100 0.0039
N32 32
mm inch
Figure 11. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Outline
A2
1N
e
E
B
N/2
D1
D
DIE
A
CP
C
TSOP-a
Drawing is not to scale.
LA1 α
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M27W101
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