Datasheet M27V801 Datasheet (SGS Thomson Microelectronics)

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Page 1

M27V801

8 Mbit (1Mb x8) Low Voltage UV EPROM and OTP EPROM

■ LOW VOLTAGEREAD OPERATION:

3V to 3.6V

■ FAST ACCESS TIME: 120ns

■ LOW POWER CONSUMPTION:

– Active Current15mA at 5MHz – Standby Current 20µA

■ PROGRAMMING VOLTAGE: 12.75V ± 0.25V

■ PROGRAMMING TIME: 100µs/byte (typical)

■ ELECTRONIC SIGNATURE

– Manufacturer Code:20h – Device Code: 42h

DESCRIPTION

The M27V801 is a low voltage 8 Mbit EPROM offered in the two ranges UV (ultraviolet erase) and OTP (one time programmable). It is ideally suited for microprocessorsystems requiringlarge data or program storageandisorganized as 1,048,576 by 8 bits.

The M27V801 operates in the read mode with a supply voltage as low as 3V. The decrease in operating power allowseither a reduction of the size of the battery or an increase in the time between battery recharges.

The FDIP32W (window ceramic frit-seal package) has transparent lid which allows the user to expose thechipto ultraviolet lightto erase the bit pattern. A new pattern can then be written to the device by followingthe programmingprocedure.

FDIP32W (F) PDIP32 (B)

PLCC32 (K) TSOP32 (N)

Figure 1. Logic Diagram

A0-A19 Q0-Q7

8 x20 mm

Table 1. Signal Names

A0-A19 Address Inputs Q0-Q7 Data Outputs E Chip Enable GV V V

Output Enable / Program Supply Supply Voltage Ground

M27V801

AI01902

1/16May 1998

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M27V801

Figure 2A. DIP Pin Connections

A19 V

A15 A12

A7 A6 A5 A4 A3 A2 A1 A0

Q2 SS

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

M27V801

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

AI01903

A18A16 A17 A14 A13 A8 A9 A11 GV A10 E Q7 Q6 Q5Q1 Q4 Q3V

Figure 2B. PLCC Pin Connections

A17

A19

A18

A7 A6 A5 A4 A3 A2 A1 A0

A16

A12

A15

M27V801

A14 A13 A8 A9 A11 GV A10 E Q7

AI01904

Figure 2C. TSOP Pin Connections

A11 GV

A8 A13 A14 A17 A18

A19 A16 A15 A12

A4 A3

M27V801

(Normal)

16 17

25 24

AI01905

A10 E Q7 Q6 Q5 Q4 Q3 V

Q2 Q1 Q0 A0 A1 A2

For applications wherethe content is programmed only one time and erasure is not required, the M27V801 is offered in PDIP32, PLCC32 and TSOP32 (8 x 20 mm) packages.

DEVICE OPERATION

The operating modes of the M27V801 arelisted in the Operating Modes table.A single power supply is required in the read mode. All inputs are TTL levels except for GVPPand 12V on A9 for Electronic Signature and Margin Mode Set or Reset .

Read Mode

The M27V801 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G)is the outputcontroland should be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time (t

) is equal to the delay from E to output

AVQV

). Data is available atthe outputafteradelay

ELQV

of t

from the falling edge of G, assuming that

GLQV

E has been low andthe addresseshavebeen stable for at least t

AVQV-tGLQV

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M27V801

Table 2. Absolute Maximum Ratings

(1)

Symbol Parameter Value Unit

BIAS

STG

(2)

Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may

cause permanent damage to the device. These are stress ratings only and operation of the device atthese or anyother conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periodsmay affect device reliability. Refer alsotothe STMicroelectronics SURE Program and otherrelevant quality documents.

2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC voltage on Output is V

3. Depends on range.

Ambient Operating Temperature Temperature Under Bias –50 to 125 °C Storage Temperature –65 to 150 °C

Input or Output Voltage (except A9) –2 to 7 V Supply Voltage –2 to 7 V A9 Voltage –2 to 13.5 V Program Supply Voltage –2 to 14 V

+0.5V with possible overshoot to VCC+2V for a period less than 20ns.

(3)

–40 to 125 °C

Table 3. Operating Modes

Mode E

Read Output Disable Program V Program Inhibit Standby Electronic Signature

Note: X = VIHor VIL,VID= 12V ± 0.5V.

Pulse V

IH PP PP

A9 Q0-Q7

X Data Out X Hi-Z X Data In X Hi-Z

X X Hi-Z

Codes

Table 4. Electronic Signature

Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data

Manufacturer’s Code Device Code V

Standby Mode

The M27V801 has a standby modewhich reduces the active current from 15mA to 20µA withlowvolt- age operation VCC≤ 3.6V, see Read Mode DC Characteristics table for details.The M27V801 is placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the GVPPinput.

Two Line Output Control

Because EPROMs are usually used in larger memory arrays, the product features a 2 line control function which accommodates the use of multiple memory connection.

00100000 20h 01000010 42h

The two line control functionallows: a. the lowest possible memory power dissipation, b. complete assurance that output bus contention

will not occur.

For the most efficient use of these two control lines, E should bedecoded andused as theprimary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselected memory devicesare intheir low power standby mode and that the output pins are only active when data is required from a particular memory device.

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M27V801

Table 5. AC Measurement Conditions

High Speed Standard

Input Rise and Fall Times ≤ 10ns ≤ 20ns Input Pulse Voltages 0 to3V 0.4V to 2.4V Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V

Figure 3. Testing Input Output Waveform

High Speed

1.5V

Standard

2.4V

0.4V

Table 6. Capacitance

Symbol Parameter Test Condition Min Max Unit

OUT

Note: 1. Sampled only,not 100% tested.

(1)

(TA=25°C, f = 1 MHz)

Input Capacitance Output Capacitance V

2.0V

0.8V

AI01822

Figure 4. AC Testing Load Circuit

1.3V

1N914

3.3kΩ

DEVICE

UNDER

TEST

CL= 30pF for High Speed CL= 100pF for Standard CLincludes JIG capacitance

=0V

=0V 12 pF

OUT

6pF

OUT

AI01823B

System Considerations

The power switching characteristics of Advanced CMOS EPROMs requirecareful decoupling ofthe devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the fallingand rising edgesof E. The magnitude of the transient current peaks is dependent on the capacitive and inductive loading of the device at the output.

The associated transient voltage peaks can be suppressed by complying with the two line output

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control and by properly selected decoupling capacitors. It is recommended that a 0.1µF ceramic capacitor be used on every device between V

and VSS. This should be a high frequency capacitor of low inherent inductance and should be placed as close to the device aspossible. In addition, a 4.7µF bulk electrolytic capacitor should be used between VCCand VSSfor every eight devices. The bulk capacitor should be located near the power supply connection point. Thepurposeof the bulk capacitor is to overcome the voltage drop caused by the inductive effectsof PCB traces.

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M27V801

Table 7. Read Mode DC Characteristics

(1)

(TA= 0 to 70 °Cor –40 to 85 °C; VCC= 3.3V ± 10%)

Symbol Parameter Test Condition Min Max Unit

CC1

CC2

I V

Note: 1. VCCmust be applied simultaneously with orbefore VPPand removed simultaneously or after VPP.

Table 8A. Read Mode AC Characteristics

Input Leakage Current

Output Leakage Current

Supply Current

E=V

f = 5MHz, V

0V ≤ V

,G=VIL,I

Supply Current (Standby) TTL Supply Current (Standby) CMOS Program Current

Input Low Voltage –0.3 0.8 V

(2)

Input High Voltage 2 Output Low Voltage

Output High Voltage TTL

Output High Voltage CMOS

2. Maximum DC voltage on Output is V

+0.5V.

(1)

E>V

I I

≤ V

OUT

= 0mA,

OUT

≤ 3.6V

E=V

–0.2V,VCC≤ 3.6V

PP=VCC

= 2.1mA

= –400µA

= –100µAV

2.4 V –0.7V

±10 µA ±10 µA

15 mA

1mA 20 µA 10 µA

0.4 V

(TA= 0 to 70 °Cor –40 to 85 °C; VCC= 3.3V ± 10%; VPP=VCC)

M27V801

Symbol Alt Parameter Test Condition

Min Max Min Max

AVQV

ELQV

GLQV

EHQZ

GHQZ

AXQX

Note: 1. VCCmust be applied simultaneously with orbefore VPPand removed simultaneously or after V

2. Sampled only, not 100% tested.

(2)

ACC

t t

Address Valid to Output Valid Chip EnableLow to Output Valid

Output Enable Low to Output Valid

Chip EnableHigh to Output Hi-Z

Output Enable High to Output Hi-Z

Address Transition to Output Transition

E=V

,GVPP=V

PP=VIL

E=V

PP=VIL

E=V

,GVPP=V

120 150 ns 120 150 ns

60 80 ns

050050ns

050050ns 00ns

Unit-120 -150

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M27V801

Table 8B. Read Mode AC Characteristics

(1)

(TA= 0 to 70 °Cor –40 to 85 °C; VCC= 3.3V ± 10%; VPP=VCC)

Symbol Alt Parameter Test Condition

AVQV

ELQV

GLQV

EHQZ

GHQZ

AXQX

Note: 1. VCCmust be applied simultaneously with orbefore VPPand removed simultaneously or after V

2. Sampled only, not 100% tested.

(2)

ACC

t t

Address Valid to Output Valid Chip EnableLow to Output Valid

Output Enable Low to Output Valid E = V

Chip EnableHigh to Output Hi-Z

Output Enable High to Output Hi-Z

Address Transition to Output Transition

E=V

,GVPP=V

PP=VIL

E=V

,GVPP=V

Figure 5. Read Mode AC Waveforms

M27V801

Unit-180 -200

Min Max Min Max

180 200 ns 180 200 ns

90 100 ns 050070ns 050070ns 00ns

A0-A19

Q0-Q7

tAVQV

tELQV

VALID

tGLQV

VALID

tAXQX

tEHQZ

tGHQZ

Hi-Z

AI01583B

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M27V801

Table 9. Programming Mode DC Characteristics

(1)

(TA=25°C; VCC= 6.25V ± 0.25V; VPP= 12.75V ± 0.25V)

Symbol Parameter Test Condition Min Max Unit

V V

Note: 1. VCCmust be applied simultaneously with orbefore VPPand removed simultaneously or after VPP.

Input Leakage Current Supply Current 50 mA Program Current Input Low Voltage –0.3 0.8 V

Input High Voltage 2.4 VCC+ 0.5 V

Output Low Voltage Output High Voltage TTL IOH= –1mA 3.6 V A9 Voltage 11.5 12.5 V

Table 10. MARGIN MODE AC Characteristics

(1)

≤ VIN≤ V

E=V

= 2.1mA

±10 µA

50 mA

0.4 V

(TA=25°C; VCC= 6.25V ± 0.25V; VPP= 12.75V ± 0.25V)

Symbol Alt Parameter Test Condition Min Max Unit

A9HVPH

VPHEL

A10HEH

A10LEH

EXA10X

EXVPX

VPXA9X

Note: 1. VCCmust be applied simultaneously with orbefore VPPand removed simultaneously or after VPP.

t t

AS10VA10

AH10

t t

VA9High to VPPHigh

AS9

VPPHigh to Chip Enable Low

VPS

Chip Enable Transition to V Chip Enable Transition to VPPTransition 2 µs

VPH

VPPTransition to VA9Transition

AH9

High to Chip Enable High (Set) Low to Chip Enable High (Reset)

Transition

A10

2 µs 2 µs 1 µs 1 µs 1 µs

2 µs

Programming

The M27V801 has been designed to befully compatible with the M27C801 and has the same electronic signature. As a result the M27V801 can be programmed as the M27C801 on the same programming equipments applying 12.75V on V

and 6.25V on VCCby the use of the same PRESTO IIB algorithm. When delivered (and after each erasure for UV EPROM), all bits of the M27V801 are inthe ’1’ state. Data is introduced byselectively programming ’0’s into the desired bit locations. Although only ’0’will be programmed, both ’1’ and ’0’ can be present in the data word. The only way to changea ’0’to a ’1’is by die exposure toultravi-

olet light (UV EPROM). The M27V801 is in the programming mode when VPPinput is at 12.75V and E ispulsed toVIL. The data to be programmed is applied to 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. VCCis specified to be 6.25V ±

0.25V. The M27V801 can usePRESTO IIBProgramming

Algorithm that drastically reduces the programming time (typically 52 seconds). Nevertheless to achieve compatibility with all programming equipments, PRESTO Programming Algorithm can be used.

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M27V801

Table 11. Programming Mode AC Characteristics

(1)

(TA=25°C; VCC= 6.25V ± 0.25V; VPP= 12.75V ± 0.25V)

Symbol Alt Parameter Test Condition Min Max Unit

AVEL

QVEL

VCHEL

VPHEL

VPLVPH

ELEH

EHQX

EHVPX

VPLEL

ELQV

(2)

EHQZ

EHAX

Note: 1. VCCmust be applied simultaneously with orbefore VPPand removed simultaneously or after VPP.

2. Sampled only, not 100% tested.

t t

VCS

OES

PRT

OEH

t t

DFP

Address Valid to Chip Enable Low 2 µs

Input Valid to Chip Enable Low 2 µs

VCCHigh to Chip Enable Low VPPHigh to Chip Enable Low

2 µs

2 µs VPPRise Time 50 ns Chip Enable Program Pulse Width (Initial) 45 55 µs Chip Enable High to Input Transition 2 µs

Chip Enable High to VPPTransition VPPLow to Chip Enable Low

Chip Enable Low to Output Valid 1 µs

2 µs

Chip Enable High to Output Hi-Z 0 130 ns Chip Enable High to Address Transition 0 ns

Figure 6. MARGIN MODE AC Waveforms

tA9HVPH tVPXA9X

A10 Set

A10 Reset

tVPHEL

tA10HEH

tA10LEH

tEXVPX

tEXA10X

AI00736B

Note: A8 High level = 5V; A9 High level = 12V.

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Page 9

Figure 7. Programming and Verify Modes AC Waveforms

M27V801

A0-A19

tAVEL

Q0-Q7

tQVEL

tVCHEL

tVPHEL

Figure 8. Programming Flowchart

VCC= 6.25V, VPP= 12.75V

SET MARGIN MODE

n=0

E=50µs Pulse

VERIFY

YES

Last

Addr

YES

RESETMARGIN MODE

CHECK ALL BYTES

1st: VCC=6V

2nd: VCC= 4.2V

++ Addr

YES

++n

=25

FAIL

VALID

DATA IN DATA OUT

tEHQX

tEHVPX tELQV

tVPLEL

tELEH

PROGRAM VERIFY

PRESTO IIB Programming Algorithm

PRESTO IIB Programming Algorithm allows the whole array to be programmed with a guaranteed margin, in atypical timeof 52.5 seconds. Thiscan be achieved with STMicroelectronics M27V801 due to several design innovations to improve programming efficiency and to provideadequate margin for reliability. Before starting the programming the internal MARGIN MODE circuit is set in order to guarantee that each cell is programmed with enough margin. Then a sequence of 50µs program pulses are applied to each byte until a correct verify occurs. No overprogram pulses are applied since the verify in MARGIN MODE provides the necessary margin.

Program Inhibit

Programming of multiple M27V801s in parallel with different datais also easily accomplished.Except for E, all like inputsincluding GVPPof the parallel M27V801 may be common. A TTL low level pulse applied to a M27V801’s E input, with VPPat

12.75V, will programthatM27V801. Ahigh level E input inhibits the other M27V801s from being programmed.

Program Verify

A verify (read) should be performed on the programmed bitsto determine that theywere correctly programmed. The verify is accomplished with G

AI01271B

at VIL. Data should be verified with t falling edge of E.

tEHAX

tEHQZ

AI01270

ELQV

after the

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M27V801

On-Board Programming

The M27V801 can be directly programmed in the application circuit. See the relevant Application Note AN620.

Electronic Signature The Electronic Signature (ES) mode allows the

reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment to automatically matchthe device to be programmed with its corresponding programming algorithm. The ES mode is functional in the 25°C ± 5°C ambient temperaturerangethat is required when programming theM27V801. To activate the ESmode, the programming equipment must force 11.5V to

12.5V on address line A9 of the M27V801. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VILto VIH. All other address lines must be held at VILduring Electronic Signature mode.

Byte 0(A0=VIL) represents the manufacturer code and byte1 (A0=VIH) thedeviceidentifier code. For the STMicroelectronicsM27V801, these two identifier bytes are given in Table 4 and can be readout on outputs Q0 to Q7. Note that the M27V801 and M27C801 have the same identifier bytes.

ERASUREOPERATION(applies to UV EPROM)

The erasure characteristics of the M27V801 is such that erasure begins when the cells are exposed to light with wavelengths shorter than approximately 4000 Å. It should be noted that sunlight and some type of fluorescent lamps have wavelengths in the 3000-4000 Å range.

Research shows that constant exposure to room level fluorescent lighting could erase a typical M27V801 in about 3 years, while it would takeapproximately 1 week to cause erasure when exposed to direct sunlight. If the M27V801 is to be exposed to these types of lighting conditions for extended periods of time, it is suggested that opaque labels be put over theM27V801windowto prevent unintentional erasure. The recommended erasureprocedure for theM27V801 is exposureto short wave ultraviolet light which has wavelength 2537 Å. The integrated dose (i.e. UV intensity x exposure time) for erasure should be a minimum of 30 W-sec/cm2. The erasure time with this dosage is approximately 30 to 40 minutes using an ultraviolet lamp with 12000 µW/cm2power rating. The M27V801 should be placed within 2.5 cm (1 inch) of the lamp tubes during the erasure. Some lamps have a filter on theirtubes which should be removed before erasure.

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Page 11

Table 12. Ordering Information Scheme

Example: M27V801 -100 K 1 TR

Device Type

Operating Voltage

V=3V

Speed

-120 = 120 ns

-150 = 150 ns

-180 = 180 ns

-200 = 200 ns

Package

F = FDIP32W P = PDIP32 K = PLCC32 N =TSOP32: 8 x 20mm

Temperature Range

1 =–0 to 70 °C 6 =–40 to 85 °C

M27V801

Option

TR =Tape & Reel Packing

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.

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M27V801

Table 13. FDIP32W - 32 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data

Symb

A 5.72 0.225 A1 0.51 1.40 0.020 0.055 A2 3.91 4.57 0.154 0.180 A3 3.89 4.50 0.153 0.177

B 0.41 0.56 0.016 0.022 B1 1.45 – – 0.057 – –

C 0.23 0.30 0.009 0.012 D 41.73 42.04 1.643 1.655

D2 38.10 – – 1.500 – –

E 15.24 – – 0.600 – – E1 13.06 13.36 0.514 0.526

e 2.54 – – 0.100 – – eA 14.99 – – 0.590 – – eB 16.18 18.03 0.637 0.710

L 3.18 0.125

S 1.52 2.49 0.060 0.098

K 6.60 – – 0.260 – – K1 10.67 – – 0.420 – –

α 4° 11° 4° 11°

N32 32

Typ Min Max Typ Min Max

mm inches

Figure 9. FDIP32W - 32 pin Ceramic Frit-seal DIP, with window, Package Outline

B1 B e1

A3A1A

E1 E

Drawing is not to scale.

FDIPW-b

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M27V801

Table 14. PDIP32 - 32 pin Plastic DIP, 600 mils width, Package MechanicalData

Symb

Typ Min Max Typ Min Max

A – 5.08 – 0.200 A1 0.38 – 0.015 – A2 3.56 4.06 0.140 0.160

B 0.38 0.51 0.015 0.020 B1 1.52 – – 0.060 – –

C 0.20 0.30 0.008 0.012 D 41.78 42.04 1.645 1.655

D2 38.10 – – 1.500 – –

E 15.24 – – 0.600 – – E1 13.59 13.84 0.535 0.545

e1 2.54 – – 0.100 – – eA 15.24 – – 0.600 – – eB 15.24 17.78 0.600 0.700

L 3.18 3.43 0.125 0.135 S 1.78 2.03 0.070 0.080 α 0° 10° 0° 10°

N32 32

mm inches

Figure 10. PDIP32 - 32 pin Plastic DIP, 600 mils width, Package Outline

A2A1A

B1 B e1

eA eB

E1 E

Drawing is not to scale.

PDIP

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M27V801

Table 15. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Mechanical Data

Symb

A 2.54 3.56 0.100 0.140 A1 1.52 2.41 0.060 0.095 A2 – 0.38 – 0.015

B 0.33 0.53 0.013 0.021 B1 0.66 0.81 0.026 0.032

D 12.32 12.57 0.485 0.495 D1 11.35 11.56 0.447 0.455 D2 9.91 10.92 0.390 0.430

E 14.86 15.11 0.585 0.595 E1 13.89 14.10 0.547 0.555 E2 12.45 13.46 0.490 0.530

e 1.27 – – 0.050 – –

F 0.00 0.25 0.000 0.010

R 0.89 – – 0.035 – –

N32 32 Nd 7 7 Ne 9 9

CP 0.10 0.004

Typ Min Max Typ Min Max

mm inches

Figure 11. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Outline

Ne E1 E

D2/E2

0.51 (.020)

1.14 (.045)

PLCC

Drawing is not to scale.

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M27V801

Table 16. TSOP32 - 32 leadPlastic Thin Small Outline, 8 x 20mm, Package Mechanical Data

Symb

Typ Min Max Typ Min Max

A 1.20 0.047 A1 0.05 0.15 0.002 0.007 A2 0.95 1.05 0.037 0.041

B 0.15 0.27 0.006 0.011

C 0.10 0.21 0.004 0.008 D 19.80 20.20 0.780 0.795

D1 18.30 18.50 0.720 0.728

E 7.90 8.10 0.311 0.319

e 0.50 – – 0.020 – –

L 0.50 0.70 0.020 0.028

α 0° 5° 0° 5°

N32 32

CP 0.10 0.004

mm inches

Figure 12. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Outline

N/2

DIE

TSOP-a

Drawing is not to scale.

LA1 α

15/16

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M27V801

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use ofsuch information nor for any infringement ofpatentsorother rights of thirdparties which may result from itsuse. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in lifesupport devices or systems without express written approval of STMicroelectronics.

The ST logo is registered trademark of STMicroelectronics

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