Datasheet M27V800 Datasheet (SGS Thomson Microelectronics)

Low Voltage UV EPROM and OTP EPROM

■ LOW VOLTAGE READ OPERATION:

3V to3.6V

■ FAST ACCESS TIME: 100ns

■ BYTE-WIDE or WORD-WIDE

CONFIGURABLE

■ 8 Mbit MASK ROMREPLACEMENT

■ LOW POWER CONSUMPTION

– Active Current 30mA at 8MHz
– Standby Current 20µA

■ PROGRAMMING VOLTAGE: 12.5V± 0.25V

■ PROGRAMMING TIME: 100µs/byte (typical)

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 0020h
– Device Code: 00B2h

M27V800

8 Mbit (1Mb x8 or 512Kb x16)

42

1

FDIP42W (F) PDIP42 (B)

44

1

SO44 (M) PLCC44 (K)

42

1

DESCRIPTION

The M27V800 is a lowvoltage 8 Mbit EPROM of­fered inthetwo ranges UV(ultra violet erase) and
OTP (one time programmable). It is ideally suited
for microprocessor systems requiringlarge data or
program storage. It is organised as either 1 Mbit
words of8bit or 512 Kbit words of 16 bit. The pin­out is compatible with a 8 Mbit Mask ROM.

Table 1. Signal Names

A0-A18 Address Inputs
Q0-Q7 Data Outputs
Q8-Q14 Data Outputs
Q15A–1 Data Output / Address Input
E Chip Enable
G Output Enable
BYTEV

V

CC

PP

Byte Mode / Program Supply
Supply Voltage

Figure 1. Logic Diagram

V

CC

19

A0-A18

BYTEV

E

G

PP

M27V800

V

SS

Q15A–1

15

Q0-Q14

AI01851

V

SS

Ground

1/16September 1998

M27V800

Figure 2A. DIP Pin Connections

A18 NC

A7
A6
A5
A4
A3
A2
A1
A0

V

SS

Q0
Q8
Q1
Q9

Q10

Q3

Q11

1
2
3
4
5
6
7
8
9
10
11

M27V800

E

12

G

13
14
15
16
17
18
19
20
21

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

AI01852

A8A17
A9
A10
A11
A12
A13
A14
A15
A16
BYTEV
V

SS

Q15A-1
Q7
Q14
Q6
Q13
Q5Q2
Q12
Q4
V

CC

PP

Figure 2B. SO Pin Connections

NC NC

1
2

A17 A8

A7
A6
A5
A4
A3
A2
A1
A0

V

SS

Q0
Q8

3
4
5
6
7
8
9
10
11
12

M27V800

E

13

G

14
15
16
17Q1

Q9

18
19

Q10

Q3

20
21

Q11

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
2322

AI01853

NCA18

A9
A10
A11
A12
A13
A14
A15
A16
BYTEV
V

SS

Q15A-1
Q7
Q14
Q6
Q13
Q5Q2
Q12
Q4
V

CC

PP

Warning: NC = Not Connected.

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

T

A

T

BIAS

T

STG

(2)

V

IO

V

CC

(2)

V

A9

V

PP

Note: 1. Except for the rating ”Operating Temperature Range”, stresses above thoselisted in the Table ”Absolute Maximum Ratings” may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi­tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual­ity documents.

2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V

3. Depends on range.

Ambient Operating Temperature
Temperature Under Bias –50 to 125 °C
Storage Temperature –65 to 150 °C

Input or Output Voltage (except A9) –2 to 7 V
Supply Voltage –2 to 7 V
A9 Voltage –2 to 13.5 V
Program Supply Voltage –2 to 14 V

+0.5V with possible overshoot to VCC+2V for a period less than20ns.

CC

(1)

(3)

Warning: NC = Not Connected.

–40 to 125 °C

2/16

Table 3. Operating Modes

Mode E G BYTEV

Read Word-wide
Read Byte-wide Upper V
Read Byte-wide Lower
Output Disable
Program
Verify
Program Inhibit
Standby
Electronic Signature

Note: X = VIHor VIL,VID= 12V ± 0.5V.

V

IL

V

IL

IL

V

IL

V

IL

Pulse V

V

IH

V

IH

V

IH

V

IL

V

IL

V

IL

V

IL

V

IH

IH

V

IL

V

IH

X X X Hi-Z Hi-Z Hi-Z

V

IL

V

IH

V

IL

V

IL

X X Hi-Z Hi-Z Hi-Z

V

PP

V

PP

V

PP

V

IH

A9 Q0-Q7 Q8-Q14 Q15A–1

PP

X Data Out Data Out Data Out
X Data Out Hi-Z V
X Data Out Hi-Z

X Data In Data In Data In
X Data Out Data Out Data Out
X Hi-Z Hi-Z Hi-Z

V

ID

Codes Codes Code

Table 4. Electronic Signature

Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data

M27V800

IH

V

IL

Manufacturer’s Code V
Device Code

Note: Outputs Q8-Q15 are set to ’0’.

IL

V

IH

00100000 20h
10110010 B2h

The M27V800 operates in the read mode with a
supply voltage as low as 3V. The decrease in op­erating power allows either a reduction of the size
of the battery or an increase in the time between
battery recharges.

The FDIP42W (window ceramic frit-seal package)
has a transparent lid which allows the user to ex­pose the chipto ultraviolet lightto erasethe bit pat­tern. A new pattern can then be written rapidly to
the device by following the programming proce­dure.

For applications where the content is programmed
only one time and erasure is not required, the
M27V800 is offered in PDIP42, SO44 and
PLCC44 package.

DEVICE OPERATION

The operating modes ofthe M27V800are listed in
the OperatingModes Table.A single power supply
is required in the read mode. All inputs are TTL
compatible except for VPPand 12V on A9 for the
Electronic Signature.

Read Mode

The M27V800 has two organisations, Word-wide
and Byte-wide.The organisation is selected by the
signal level onthe BYTEVPPpin. When BYTEV

PP

is at VIHthe Word-wide organisation is selected
and the Q15A–1 pin is usedfor Q15 Data Output.
When the BYTEVPPpinis at VILthe Byte-wideor­ganisation is selected and theQ15A–1 pin is used
for the Address Input A–1. When the memory is
logically regarded as 16 bit wide, but read in the
Byte-wide organisation, then with A–1 at VILthe
lower 8bits of the16bit data are selected and with
A–1 at VIHthe upper 8 bits of the 16 bit data are
selected.

The M27V800 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. In addition the Word-wide or
Byte-wide organisation must be selected.

Chip Enable (E) is thepower control and should be
used fordevice selection. OutputEnable (G)is the
output control and should be used to gate data to
the output pins independent of device selection.
Assuming that the addresses are stable, the ad­dress access time (t
from E to output (t

ELQV

output after a delay of t

) is equal to the delay

AVQV

). Data is available at the

from the falling edge

GLQV

of G, assuming that E has been low and the ad­dresseshave been stable forat least t

AVQV-tGLQV

.

3/16

M27V800

Table 5. AC Measurement Conditions

High Speed Standard

Input Rise and Fall Times ≤ 10ns ≤ 20ns
Input Pulse Voltages 0 to 3V 0.4V to2.4V
Input and Output Timing Ref.Voltages 1.5V 0.8V and 2V

Figure 3. Testing Input Output Waveform

High Speed

3V

1.5V

0V

Standard

2.4V

0.4V

Table 6. Capacitance

(1)

(TA=25°C, f= 1 MHz)

2.0V

0.8V

AI01822

Figure 4. AC Testing Load Circuit

1.3V

1N914

3.3kΩ

DEVICE
UNDER

TEST

C

L

CL= 30pF for HighSpeed
CL= 100pF for Standard
CLincludes JIG capacitance

OUT

AI01823B

Symbol Parameter Test Condition Min Max Unit

C

Input Capacitance (except BYTEVPP)V

IN

C

OUT

Note: Sampled only, not 100% tested.

Input Capacitance (BYTEV
Output Capacitance

)V

PP

=0V

IN

= 0V 120 pF

IN

V

=0V

OUT

10 pF

12 pF

Standby Mode

The M27V800 hasa standby modewhich reduces
the supply current from 20mA to 20µA with low
voltage operationVCC≤ 3.6V, seeRead Mode DC
Characteristics table for details.The M27V800 is
placed in the standby mode by applying a CMOS
high signal to the E input. When in the standby
mode, the outputs are in a high impedance state,
independent of the G input.

4/16

Two Line Output Control

Because EPROMs are usually used in larger
memory arrays, thisproduct features a 2 line con­trol function which accommodates the use of mul­tiple memory connection. The two line control
function allows:

a. the lowest possible memory powerdissipation,
b. complete assurance that output bus contention

will not occur.

M27V800

Table 7. Read Mode DC Characteristics

(1)

(TA= 0 to70 °C; VCC= 3.3V± 10%; VPP=VCC)

Symbol Parameter Test Condition Min Max Unit

I

I

I

CC

I

CC1

I

CC2

I
V

V

IH

V

V

Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.

Input Leakage Current

LI

Output Leakage Current

LO

Supply Current

Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current

PP

Input Low Voltage –0.3 0.8 V

IL

(2)

Input High Voltage 2
Output Low Voltage

OL

Output High VoltageTTL

OH

2. Maximum DC voltage on Output is V

CC

+0.5V.

E=V

IL

f = 8MHz, V

E=V

IL

f = 5MHz, V

E>V

0V ≤ V

0V ≤ V

,G=VIL,I

,G=VIL,I

CC

I

OH

≤ V

IN

CC

≤ V

OUT

E=V

–0.2V,VCC≤ 3.6V

V

PP=VCC

I

= 2.1mA

OL

= –400µA

CC

CC

IH

CC

OUT

≤ 3.6V

OUT

≤ 3.6V

= 0mA,

= 0mA,

2.4 V

±1 µA

±10 µA

30 mA

20 mA

1mA
20 µA
10 µA

V

+1

CC

0.4 V

V

For the most efficient use of these two control
lines, E should be decoded and usedas the prima­ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system controlbus. This ensures that alldeselect­ed memory devices are intheir low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.

System Considerations

The power switching characteristics of Advanced
CMOS EPROMsrequire carefull decoupling of the
supplies to the devices. The supply current ICC
has three segments of importance to the system
designer: the standby current, the active current
and the transient peaks that are produced by the
falling andrising edges of E.

The magnitude of the transient current peaks is
dependant on the capacititive and inductive load­ing of the device outputs. The associatedtransient
voltage peaks can be supressed by complying
with the two line output control and by properly se­lected decoupling capacitors. It is recommended
that a 0.1µF ceramic capacitor is used on every
device between VCCand VSS. This should be a
high frequency type of low inherent inductance
and should be placed as close as possible to the
device. In addition, a 4.7µF electrolytic capacitor
should be used between VCCand VSSfor every
eight devices. This capacitor should be mounted
near the power supply connection point. The pur­pose of this capacitor is to overcome the voltage
drop caused by the inductive effects of PCB trac­es.

5/16

M27V800

Table 8. Read Mode AC Characteristics

(1)

(TA= 0 to70 °C; VCC= 3.3V± 10%; VPP=VCC)

M27V800

Symbol Alt Parameter Test Condition

Min Max Min Max Min Max

t

AVQV

t

BHQV

t

ELQV

t

GLQV

(2)

t

BLQZ

(2)

t

EHQZ

(2)

t

GHQZ

t

AXQX

t

BLQX

Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after V

2. Sampled only, not 100% tested.

Address Validto

t

ACC

Output Valid
BYTE High to Output

t

ST

Valid
Chip Enable Low to

t

CE

Output Valid
Output Enable Low to

t

OE

Output Valid
BYTE Low to Output

t

STD

Hi-Z
Chip Enable High to

t

DF

Output Hi-Z
Output Enable High to

t

DF

Output Hi-Z
Address Transition to

t

OH

Output Transition
BYTE Low to Output

t

OH

Transition

E=V

E=V

E=V

E=V

E=V

,G=V

IL

,G=V

IL

G=V

E=V

,G=V

IL

G=V

E=V

,G=V

IL

,G=V

IL

IL

IL

IL

IL

IL

IL

IL

IL

IL

100 120 150 ns

100 120 150 ns

100 120 150 ns

50 60 70 ns

45 50 60 ns

045050060ns

045050060ns

555ns

555ns

Unit-100 -120 -150

PP

Figure 5. Word-Wide Read Mode AC Waveforms

A0-A18

E

G

Q0-Q15

Note: BYTEVPP=VIH.

VALID

tAVQV

tGLQV

tELQV

VALID

tAXQX

tEHQZ

tGHQZ

Hi-Z

AI01596B

6/16

Figure 6. Byte-Wide Read Mode AC Waveforms

M27V800

A–1,A0-A18

E

G

Q0-Q7

Note: BYTEVPP=V

IL.

VALID

tAVQV

tGLQV

tELQV

Figure 7. BYTE Transition ACWaveforms

A0-A18

VALID

tAXQX

VALID

tEHQZ

tGHQZ

Hi-Z

AI01597B

A–1

tAVQV

BYTEV

PP

Q0-Q7

tBLQX

Q8-Q15

tBLQZ

Note: Chip Enable (E) and Output Enable (G) = VIL.

VALID

tAXQX

tBHQV

DATA OUT

Hi-Z

DATA OUT

AI01598C

7/16

M27V800

Table 9. Programming Mode DC Characteristics

(1)

(TA=25°C; VCC= 6.25V ± 0.25V; VPP= 12.5V ± 0.25V)

Symbol Parameter Test Condition Min Max Unit

I

LI

I

CC

I

PP

V
V

V

OL

V

OH

V

Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.

Input Leakage Current
Supply Current 50 mA
Program Current
Input Low Voltage –0.3 0.8 V

IL

Input High Voltage 2.4 VCC+ 0.5 V

IH

Output Low Voltage
Output High VoltageTTL IOH= –2.5mA 3.5 V
A9 Voltage 11.5 12.5 V

ID

Table 10. Programming Mode AC Characteristics

0 ≤ V

I

OL

(1)

≤ V

IN

E=V

IL

= 2.1mA

CC

±1 µA

50 mA

0.4 V

TA=25°C; VCC= 6.25V ± 0.25V; VPP= 12.5V ± 0.25V)

Symbol Alt Parameter Test Condition Min Max Unit

t

AVEL

t

QVEL

t

VPHAV

t

VCHAV

t

ELEH

t

EHQX

t

QXGL

t

GLQV

(2)

t

GHQZ

t

GHAX

Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously orafter VPP.

2. Sampled only, not 100% tested.

t
t

t

VPS

t

VCS

t

t

t

OES

t

t

DFP

t

Address Validto Chip Enable Low 2 µs

AS

Input Valid to Chip Enable Low 2 µs

DS

VPPHigh to Address Valid
VCCHigh to Address Valid
Chip Enable Program Pulse Width 45 55 µs

PW

Chip Enable High to Input Transition 2 µs

DH

2 µs
2 µs

Input Transition to Output Enable Low 2 µs
Output Enable Low to Output Valid 120 ns

OE

Output Enable High to Output Hi-Z 0 130 ns
Output Enable High to Address

AH

Transition

0ns

Programming

The M27V800 hasbeen designedto be fully com­patible with the M27C800 and has the same elec­tronic signature. As a result the M27V800 can be
programmed as the M27C800 on the same pro­gramming equipments applying 12.75V on V

PP

and 6.25V on VCCby the use of the same PRES­TO III algorithm. When delivered (and after each
erasure for UV EPROM), all bits of the M27V800
are in the ’1’ state. Data is introduced byselective-

8/16

ly programming ’0’s into the desired bit locations.
Although only ’0’s will be programmed, both ’1’s
and ’0’scan be present in the data word. The only
way to change a ’0’ to a ’1’is by die exposition to
ultraviolet light (UV EPROM). The M27V800 is in
the programming mode when VPPinput is at

12.5V, G is at VIHand E is pulsed to VIL. The data
to be programmed is applied to 16 bits in parallel
to the data output pins. The levels required for the
address and data inputs are TTL. VCCis specified
to be 6.25V ± 0.25V.

Figure 8. Programming and Verify Modes AC Waveforms

M27V800

A0-A18

Q0-Q15

BYTEV

PP

tVPHAV

V

CC

tVCHAV

E

G

Figure 9. Programming Flowchart

VCC= 6.25V, VPP= 12.5V

n=0

E=50µs Pulse

NO

NO

VERIFY

YES

Last

NO

Addr

YES

CHECK ALL WORDS

BYTEVPP=V

1st: VCC=6V

2nd: VCC= 3.3V

IH

++ Addr

YES

++n

=25

FAIL

VALID

tAVEL

DATA IN DATA OUT

tQVEL

tELEH

PROGRAM VERIFY

tEHQX

tQXGL

PRESTO III Programming Algorithm

The PRESTO III Programming Algorithm allows
the whole array to be programed with a guaran­teed margin in a typical time of 26 seconds. Pro­gramming with PRESTO III consists of applying a
sequence of 50µs program pulses to each word
until a correct verify occurs (see Figure 9). During
programing and verify operation a MARGIN
MODE circuit is automatically activated to guaran­tee that each cell is programed with enough mar­gin. No overprogram pulse is applied since the
verify in MARGIN MODE at VCCmuch higher than

3.6V provides the neccessarymargin to each pro­grammed cell.

Program Inhibit

Programming of multiple M27V800s in parallel
with different data is also easily accomplished.Ex­cept for E,all likeinputs including G of the parallel
M27V800 may be common. A TTL low level pulse
applied to a M27V800’s E inputand VPPat 12.5V,
will program that M27V800.A high level E input in­hibits the other M27V800s from being pro­grammed.

Program Verify

A verify (read) should be performed on the pro-

AI00901

grammed bits to determine that theywere correct­ly programmed. Theverify is accomplished with E
at VIHand G at VIL,VPPat 12.5V and VCCat

6.25V.

tGLQV

tGHQZ

tGHAX

AI01599

9/16

M27V800

On-Board Programming

The M27V800 can be directly programmed in the
application circuit. See the relevant Application
Note AN620.

Electronic Signature

The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically matchthe device to be programmed
with its corresponding programming algorithm.
The ES mode is functional in the 25°C ± 5°C am­bient temperaturerange that is required when pro­gramming theM27V800. To activatethe ES mode,
the programming equipment must force 11.5V to

12.5V on address line A9 of the M27V800, with
VPP=VCC=5V. Two identifier bytes may then be
sequenced from the device outputs by toggling ad­dress line A0 from VILto VIH. All other address
lines must be held at VILduring Electronic Signa­ture mode.

Byte 0(A0=VIL) represents themanufacturer code
and byte 1 (A0=VIH) the device identifier code. For
the STMicroelectronicsM27V800, these two iden­tifier bytes are given in Table 4 and can be read­out on outputs Q0 to Q7. Note that the M27V800
and M27C800have the same identifier bytes.

ERASUREOPERATION (applies to UV EPROM)

The erasure characteristics of the M27V800 is
such that erasure begins when the cells are ex­posed to light with wavelengths shorter than ap­proximately 4000 Å. It should be noted that
sunlight and some type of fluorescent lamps have
wavelengths in the 3000-4000 Å range. Research
shows that constant exposure to room level fluo­rescent lighting could erase a typical M27V800 in
about 3 years, while it would takeapproximately 1
week to cause erasure when exposed to direct
sunlight. If the M27V800 isto be exposed to these
types of lighting conditions for extended periods of
time, itis suggested that opaque labels beput over
the M27V800 window to prevent unintentional era­sure. The recommended erasure procedure for
M27V800 is exposure to short wave ultraviolet
light which has a wavelength of 2537 Å. The inte­grated dose (i.e. UV intensity x exposure time) for
erasure should be a minimum of 30 W-sec/cm2.
The erasure time withthis dosage isapproximate­ly 30 to410 minutes using an ultraviolet lamp with
12000 µW/cm2power rating. The M27V800
should be placed within 2.5cm (1inch) of the lamp
tubes during the erasure.Some lamps have afilter
on their tubes which should be removed before
erasure.

10/16

Table 11. Ordering Information Scheme

Example: M27V800 -100 X M 1 TR

Device Type

Speed

-100 = 100 ns

-120 = 120 ns

-150 = 150 ns

V

Tolerance

CC

blank = ± 10%
X=±5%

Package

F = FDIP42W
B = PDIP42
K = PLCC44
M = SO44

Temperature Range

1 = –0 to 70 °C

M27V800

Option

TR = Tape & Reel Packing

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de­vice, please contactthe ST Sales Office nearest to you.

11/16

M27V800

Table 12. FDIP42W - 42 pin Ceramic Frit-seal DIP,with window, Package Mechanical Data

Symb

A 5.72 0.225
A1 0.51 1.40 0.020 0.055
A2 3.91 4.57 0.154 0.180
A3 3.89 4.50 0.153 0.177

B 0.41 0.56 0.016 0.022
B1 1.45 – – 0.057 – –

C 0.23 0.30 0.009 0.012

D 54.41 54.86 2.142 2.160
D2 50.80 – – 2.000 – –

E 15.24 – – 0.600 – –
E1 14.50 14.90 0.571 0.587

e 2.54 – – 0.100 – –
eA 14.99 – – 0.590 – –
eB 16.18 18.03 0.637 0.710

L 3.18 0.125

S 1.52 2.49 0.060 0.098
K 9.40 – – 0.370 – –

K1 11.43 – – 0.450 – –

α 4° 11° 4° 11°
N42 42

Typ Min Max Typ Min Max

mm inches

Figure 10. FDIP42W - 42 pin Ceramic Frit-seal DIP, with window, Package Outline

A2

B1 B e1

A3A1A

L

α

C

eA

D2

eB

D

S

N

E1 E

K

1

Drawing is not to scale.

K1

FDIPW-b

12/16

M27V800

Table 13. PDIP42 - 42 pin Plastic DIP, 600 mils width, Package Mechanical Data

Symb

Typ Min Max Typ Min Max

A – 5.08 – 0.200
A1 0.25 – 0.010 –
A2 3.56 4.06 0.140 0.160

B 0.38 0.53 0.015 0.021
B1 1.27 1.65 0.050 0.065

C 0.20 0.36 0.008 0.014

D 52.20 52.71 2.055 2.075
D2 50.80 – – 2.000 – –

E 15.24 – – 0.600 – –
E1 13.59 13.84 0.535 0.545

e1 2.54 – – 0.100 – –
eA 14.99 – – 0.590 – –
eB 15.24 17.78 0.600 0.700

L 3.18 3.43 0.125 0.135
S 0.86 1.37 0.034 0.054
α 0° 10° 0° 10°
N42 42

mm inches

Figure 11. PDIP42 - 42 pin Plastic DIP, 600 mils width, Package Outline

A2A1A

L

B1 B e1

D2

α

eA

eB

D

S

N

E1 E

1

Drawing is not to scale.

C

PDIP

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M27V800

Table 14. PLCC44 - 44lead Plastic Leaded ChipCarrier, square, Package Mechanical Data

Symb

Typ Min Max Typ Min Max

A 4.20 4.70 0.165 0.185

A1 2.29 3.04 0.090 0.120
A2 – 0.51 – 0.020

B 0.33 0.53 0.013 0.021

B1 0.66 0.81 0.026 0.032

D 17.40 17.65 0.685 0.695

D1 16.51 16.66 0.650 0.656
D2 14.99 16.00 0.590 0.630

E 17.40 17.65 0.685 0.695

E1 16.51 16.66 0.650 0.656
E2 14.99 16.00 0.590 0.630

e 1.27 – – 0.050 – –
F 0.00 0.25 0.000 0.010
R 0.89 – – 0.035 – –

mm inches

N44 44

CP 0.10 0.004

Figure 12. PLCC44 - 44lead Plastic Leaded Chip Carrier, square, Package Outline

D

D1

1N

Ne E1 E

A2

F

D2/E2

A1

B

0.51 (.020)

1.14 (.045)

PLCC

Nd

R

CP

A

B1

e

Drawing is not to scale.

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M27V800

Table 15. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data

Symb mm inches

Typ Min Max Typ Min Max

A 2.42 2.62 0.095 0.103

A1 0.22 0.23 0.009 0.010
A2 2.25 2.35 0.089 0.093

B 0.50 0.020
C 0.10 0.25 0.004 0.010
D 28.10 28.30 1.106 1.114
E 13.20 13.40 0.520 0.528

e 1.27 – – 0.050 – –
H 15.90 16.10 0.626 0.634

L 0.80 – – 0.031 – –
α 3° ––3°––
N44 44

CP 0.10 0.004

Figure 13. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline

A2

A

C

B

e

CP

D

N

E

H

1

LA1 α

SO-b

Drawing is not to scale.

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M27V800

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