Datasheet M27V512 Datasheet (SGS Thomson Microelectronics)

M27V512

512 Kbit (64Kb x8) Low Voltage UV EPROM and OTP EPROM

■ LOW VOLTAGE READ OPERATION:

3V to 3.6V

■ FAST ACCESS TIME: 100ns

■ LOW POWER CONSUMPTION:

V

CC

M27V512

28

1

8 x 13.4mm

8

Q0-Q7

– Active Current 10mA at 5MHz
– Standby Current 10µA

■ PROGRAMMING VOLTAGE: 12.75V ± 0.25V

■ PROGRAMMING TIME: 100µs/byte (typical)

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h
– Device Code: 3Dh

DESCRIPTION

The M27V512 is a low voltage 512 Kbit EPROM
offered in the two ranges UV (ultra viloet erase)
and OTP (one time programmable). It is ideally
suited for microprocessor systems and is orga­nized as 65,536 by 8 bits.

The M27V512 operates in the read mode with a
supply voltage as low as 3V. The decrease in op­erating power allows either a reduction of the size
of the battery or an increase in the time between
battery recharges.

The FDIP28W (window ceramic frit-seal package)
has transparent lid which allows the user to ex­pose the chiptoultraviolet light to erase the bit pat­tern. A new pattern can then be written to the
device by following the programming procedure.

For applications where the content is programmed
only one time and erasure is not required, the
M27V512 is offered in PDIP28, PLCC32 and
TSOP28 (8 x 13.4 mm) packages.

Table 1. Signal Names

A0-A15 Address Inputs

28

1

FDIP28W (F) PDIP28 (B)

PLCC32 (K) TSOP28 (N)

Figure 1. Logic Diagram

16

A0-A15

E

GV

PP

Q0-Q7 Data Outputs
E Chip Enable
GV
V
V

PP

CC

SS

Output Enable
Supply Voltage
Ground

V

SS

AI00732B

1/16May 1998

M27V512

Figure 2A. DIP Pin Connections

A15 V
A12

A7
A6
A5
A4
A3
A2
A1
A0

Q0

Q2
SS

1
2
3
4
5
6
7
8
9
10
11
12
13
14

M27V512

28
27
26
25
24
23
22
21
20
19
18
17
16
15

AI01907

CC

A14
A13
A8
A9
A11
GV
A10
E
Q7
Q6
Q5Q1
Q4
Q3V

PP

Figure 2B. LCC Pin Connections

CC

A13

DU

32

DU

V

Q3

A14

Q4

25

Q5

A8
A9
A11
NC
GV
A10
E
Q7
Q6

AI00733B

A15

A7

A12

A6
A5
A4
A3
A2

9
A1
A0

NC

Q0

Q1

Warning: NC = Not Connected, DU = Don’t Use

1

M27V512

17

Q2

SS

V

PP

Figure 2C. TSOP Pin Connections

GV

A11

A13
A14

V

A15
A12

PP

A9
A8

CC

A7
A6
A5
A4
A3

22

28

M27V512

1

78

21

15
14

AI00734B

A10
E
Q7
Q6
Q5
Q4
Q3
V

SS

Q2
Q1
Q0
A0
A1
A2

DEVICE OPERATION

The operating modes of the M27V512 are listed in
the Operating Modes table. A single power supply
is required in the read mode. All inputs are TTL
levels except for GVPPand 12V on A9 for Elec­tronic Signature.

Read Mode

The M27V512 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, indepen­dent of device selection. Assuming that the ad­dresses are stable, the address access time
(t

) is equal to the delay from E to output

AVQV

(t

). Datais availableatthe output afteradelay

ELQV

of t

from the falling edge of G, assuming that

GLQV

E has been low and the addresses have been sta­ble for at least t

AVQV-tGLQV

.

Standby Mode

The M27V512 has a standby mode which reduces
the supply current from 10mA to 10µA with low
voltage operation VCC≤ 3.6V, see Read Mode DC
Characteristics table for details.The M27V512 is
placed in the standby mode by applying a CMOS
high signal to the E input. When in the standby
mode, the outputs are in a high impedance state,
independent of the GVPPinput.

2/16

M27V512

Table 2. Absolute Maximum Ratings

(1)

Symbol Parameter Value Unit

T

A

T

BIAS

T

STG

(2)

V

IO

V

CC

(2)

V

A9

V

PP

Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi­tions for extended periods may affect device reliability. Refer alsoto the STMicroelectronics SUREProgram and other relevant qua­lity documents.

2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V

3. Depends on range.

Ambient Operating Temperature
Temperature Under Bias –50 to 125 °C
Storage Temperature –65 to 150 °C

Input or Output Voltage (except A9) –2 to 7 V
Supply Voltage –2 to 7 V
A9 Voltage –2 to 13.5 V
Program Supply Voltage –2 to 14 V

+0.5V with possible overshoot to VCC+2V for a period less than 20ns.

CC

(3)

–40 to 125 °C

Table 3. Operating Modes

Mode E

Read
Output Disable V
Program

V
Program Inhibit V
Standby
Electronic Signature

Note: X = VIHor VIL,VID= 12V ± 0.5V.

V

IL

IL

Pulse V

IL

IH

V

IH

V

IL

GV

V

PP

V

IL

V

IH

PP

PP

A9 Q0-Q7

X Data Out
X Hi-Z
XDataIn
X Hi-Z

X X Hi-Z

V

IL

V

ID

Codes

Table 4. Electronic Signature

Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data

Manufacturer’s Code
Device Code

V

IL

V

IH

Two Line Output Control

Because EPROMs are usually used in larger
memory arrays, the product features a 2 line con­trol function which accommodates the use of mul­tiple memory connection. The two line control
function allows:

a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention

will not occur.

00100000 20h
00111101 3Dh

For the most efficient use of these two control
lines, Eshouldbedecoded and used astheprima­ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect­ed memory devices are intheir lowpower standby
mode and that the output pins are only active
when data is required from a particular memory
device.

3/16

M27V512

Table 5. AC Measurement Conditions

High Speed Standard

Input Rise and Fall Times ≤ 10ns ≤ 20ns
Input Pulse Voltages 0 to 3V 0.4V to 2.4V
Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V

Figure 3. Testing Input Output Waveform

High Speed

3V

1.5V

0V

Standard

2.4V

0.4V

Table 6. Capacitance

Symbol Parameter Test Condition Min Max Unit

C

IN

C

OUT

Note: 1. Sampled only, not 100% tested.

Input Capacitance
Output Capacitance

(1)

(TA=25°C, f = 1 MHz)

2.0V

0.8V

AI01822

Figure 4. AC Testing Load Circuit

1.3V

1N914

3.3kΩ

DEVICE
UNDER

TEST

C

L

CL= 30pF for HighSpeed
CL= 100pF for Standard
CLincludes JIG capacitance

V

V

IN

OUT

=0V

=0V

6pF

12 pF

OUT

AI01823B

System Considerations

The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, ICC, has three seg­ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edgesof E. The magnitude of
the transient current peaks is dependent on the
capacitive and inductive loading of the device at
the output.

The associated transient voltage peaks can be
suppressed by complying with the two line output

4/16

control and by properly selected decoupling ca­pacitors. It is recommended that a 0.1µF ceramic
capacitor be used on every device between V

CC

and VSS. This should be a high frequency capaci­tor of low inherent inductance and should be
placed as close to the device as possible. In addi­tion, a 4.7µF bulk electrolytic capacitor should be
used between VCCand VSSfor every eight devic­es. The bulk capacitor should be located near the
power supplyconnection point.The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.

M27V512

Table 7. Read Mode DC Characteristics

(1)

(TA= 0 to 70 °C or –40 to 85 °C; VCC= 3.3V ± 10%; VPP=VCC)

Symbol Parameter Test Condition Min Max Unit

I

I

I

CC

I

CC1

I

CC2

I
V

V

IH

V
V
V

Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.

Table 8A. Read Mode AC Characteristics

Input Leakage Current

LI

Output Leakage Current

LO

Supply Current

E=V

IL

f = 5MHz, V

0V ≤ V

0V ≤ V

,G=VIL,I

Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current

PP

Input Low Voltage –0.3 0.8 V

IL

(2)

Input High Voltage 2
Output Low Voltage

OL

Output High Voltage TTL

OH

Output High Voltage CMOS

OH

2. Maximum DC voltage on Output is V

CC

+0.5V.

(1)

E>V

CC

I
I

OH

OH

≤ V

IN

CC

≤ V

OUT

E=V

CC

IH

CC

OUT

≤ 3.6V

= 0mA,

– 0.2V,VCC≤ 3.6V

V

PP=VCC

I

= 2.1mA

OL

= –400µA
= –100µAV

2.4 V
– 0.7V

CC

±10 µA
±10 µA

10 mA

1mA
10 µA
10 µA

V

+1

CC

0.4 V

(TA= 0 to 70 °C or –40 to 85 °C; VCC= 3.3V ± 10%; VPP=VCC)

M27V512

Symbol Alt Parameter Test Condition

(3)

-100

Min Max Min Max

-120

V

V

Unit

t

AVQV

t

ELQV

t

GLQV

t

EHQZ

t

GHQZ

t

AXQX

Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.

2. Sampled only, not 100% tested.

3. Speed obtained with High Speed AC measurement conditions.

(2)

(2)

t

Address Valid to Output Valid E = VIL,G=V

ACC

t

Chip Enable Low to Output Valid

CE

t

Output Enable Low to Output Valid

OE

t

Chip Enable High to Output Hi-Z G = V

DF

t

Output Enable High to Output Hi-Z

DF

Address Transition to Output

t

OH

Transition

E=V

G=V
E=V

E=V

,G=V

IL

IL

IL

IL

IL

IL

IL

0 30 0 35 ns
0 30 0 35 ns

00ns

100 120 ns
100 120 ns

45 45 ns

5/16

M27V512

Table 8B. Read Mode AC Characteristics

(1)

(TA= 0 to 70 °C or –40 to 85 °C; VCC= 3.3V ± 10%; VPP=VCC))

M27V512

Symbol Alt Parameter Test Condition

Min Max Min Max

t

AVQV

t

ELQV

t

GLQV

t

EHQZ

t

GHQZ

t

AXQX

Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.

2. Sampled only, not 100% tested.

(2)

(2)

t

Address Valid to Output Valid

ACC

t

Chip Enable Low to Output Valid

CE

t

Output Enable Low to Output Valid E = V

OE

t

Chip Enable High to Output Hi-Z

DF

t

Output Enable High to Output Hi-Z

DF

Address Transition to Output

t

OH

Transition

E=V

E=V

,G=V

IL

G=V

G=V
E=V

,G=V

IL

IL

IL

IL

IL

IL

IL

0 40 0 50 ns
0 40 0 50 ns

00ns

Figure 5. Read Mode AC Waveforms

A0-A15

tAVQV

VALID

tAXQX

VALID

Unit-150 -200

150 200 ns
150 200 ns

50 60 ns

E

tGLQV

G

tELQV

Q0-Q7

Programming

The M27V512 has been designed to be fully com­patible with the M27C512 and has the same elec­tronic signature. As a result the M27V512 can be
programmed as the M27C512 on the same pro­gramming equipments applying 12.75V on V

PP

and 6.25V on VCCby the use of the same PRES­TO IIB algorithm. When delivered (and after each
erasure for UV EPROM), all bits of the M27V512
are inthe ’1’ state. Data is introduced by selective­ly programming ’0’s into the desired bit locations.
Although only ’0’s will be programmed, both ’1’s
and ’0’s can be present in the data word. Theonly
way tochange a ’0’to a ’1’is by die exposure to ul-

tEHQZ

tGHQZ

Hi-Z

AI00735B

traviolet light(UV EPROM). The M27V512 is in the
programming mode when VPPinput is at 12.75V
and E is pulsed toVIL. The data to be programmed
is applied to 8 bits in parallel to the data output
pins.The levels required for the address and data
inputs are TTL. VCCis specified to be 6.25V ±

0.25V.
The M27V512 can use PRESTO IIBProgramming

Algorithm that drastically reduces the program­ming time (typically less than 6 seconds). Never­theless to achieve compatibility with all
programming equipments, PRESTO Program­ming Algorithm can be used as well.

6/16

M27V512

Table 9. Programming Mode AC Characteristics

(1)

(TA=25°C; VCC= 6.25V ± 0.25V; VPP= 12.75V ± 0.25V)

Symbol Parameter Test Condition Min Max Unit

I

LI

I

CC

I

PP

V

IL

V

IH

V

OL

V

OH

V

ID

Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.

Input Leakage Current
Supply Current 50 mA
Program Current
Input Low Voltage –0.3 0.8 V
Input High Voltage 2 VCC+ 0.5 V
Output Low Voltage
Output High Voltage TTL IOH= –1mA 3.6 V
A9 Voltage 11.5 12.5 V

Table 10. MARGIN MODE AC Characteristics

V

<= VIN<=V

IL

E=V

I

= 2.1mA

OL

(1)

IH

IL

±10 µA

50 mA

0.4 V

(TA=25°C; VCC= 6.25V ± 0.25V; VPP= 12.75V ± 0.25V

Symbol Alt Parameter Test Condition Min Max Unit

t

A9HVPH

t

VPHEL

t

A10HEH

t

A10LEH

t

EXA10X

t

EXVPX

t

VPXA9X

Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after V

t
t

t

AS10VA10

t

AS10VA10

t

AH10

t
t

VA9High to VPPHigh

AS9

VPPHigh to Chip Enable Low

VPS

Chip Enable Transition to V
Chip Enable Transition to VPPTransition 2 µs

VPH

VPPTransition to VA9Transition

AH9

High to Chip Enable High (Set)
Low to Chip Enable High (Reset)

Transition

A10

2 µs
2 µs
1 µs
1 µs
1 µs

2 µs

PP.

7/16

M27V512

Table 11. Programming Mode AC Characteristics

(1)

(TA=25°C; VCC= 6.25V ± 0.25V; VPP= 12.75V ± 0.25V)

Symbol Alt Parameter Test Condition Min Max Unit

t

AVEL

t

QVEL

t

VCHEL

t

VPHEL

t

VPLVPH

t

ELEH

t

EHQX

t

EHVPX

t

VPLEL

t

ELQV

(2)

t

EHQZ

t

EHAX

Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.

2. Sampled only, not 100% tested.

t
t

t

VCS

t

OES

t

PRT

t

t

t

OEH

t
t

t

DFP

t

Address Validto Chip Enable Low 2 µs

AS

Input Valid to Chip Enable Low 2 µs

DS

VCCHigh to Chip Enable Low
VPPHigh to Chip Enable Low

2 µs

2 µs
VPPRise Time 50 ns
Chip Enable Program Pulse Width (Initial) 95 105 µs

PW

Chip Enable High to Input Transition 2 µs

DH

Chip Enable High to VPPTransition
VPPLow to Chip Enable Low

VR

Chip Enable Low to Output Valid 1 µs

DV

2 µs

2 µs

Chip Enable High to Output Hi-Z 0 130 ns
Chip Enable High to Address Transition 0 ns

AH

Figure 6. MARGIN MODE AC Waveforms

V

CC

A8

A9

tA9HVPH tVPXA9X

GV

PP

E

A10 Set

A10 Reset

Note: A8 Highlevel = 5V; A9 High level = 12V.

tVPHEL

tA10HEH

tA10LEH

tEXVPX

tEXA10X

AI00736B

8/16

Figure 7. Programming and Verify Modes AC Waveforms

M27V512

A0-A15

tAVEL

Q0-Q7

tQVEL

V

CC

tVCHEL

GV

PP

tVPHEL

E

Figure 8. Programming Flowchart

VCC= 6.25V, VPP= 12.75V

SET MARGIN MODE

n=0

E = 100µs Pulse

NO

NO

VERIFY

YES

Last

NO

Addr

YES

RESET MARGINMODE

CHECK ALL BYTES

1st: VCC=6V

2nd: VCC= 4.2V

++ Addr

YES

++n

=25

FAIL

DATA IN

AI00738B

tELEH

PROGRAM

VALID

tEHAX

DATA OUT

tEHQX

tELQV

tEHVPX

tVPLEL

VERIFY

tEHQZ

AI00737

PRESTO IIB Programming Algorithm

PRESTO IIB Programming Algorithm allows the
whole array to be programmed with a guaranteed
margin, in a typical time of 6.5 seconds. This can
be achieved with STMicroelectronics M27V512
due to several design innovations described in the
M27V512 datasheet to improve programming effi­ciency and to provide adequate marginfor reliabil­ity. Before starting the programming the internal
MARGIN MODE circuit is set inorder to guarantee
that each cell is programmed with enough margin.
Then asequence of 100µs program pulses are ap­plied to each byte until a correct verify occurs. No
overprogram pulses are applied since the verify in
MARGIN MODE provides the necessary margin.

Program Inhibit

Programming of multiple M27V512s in parallel
with different data is also easily accomplished. Ex­cept for E, all like inputs including GVPPof thepar­allel M27V512 may be common. A TTL low level
pulse applied to a M27V512’s E input, with VPPat

12.75V, will programthat M27V512. A high level E
input inhibits the other M27V512s from being pro­grammed.

Program Verify

A verify (read) should be performed on the pro­grammed bits to determinethat they were correct­ly programmed. The verify is accomplished with G
at VIL. Data should be verified with t

ELQV

after the

falling edge of E.

9/16

M27V512

On-Board Programming

The M27V512 can be directly programmed in the
application circuit. See the relevant Application
Note AN620.

Electronic Signature

The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically matchthe device to be programmed
with its corresponding programming algorithm.
The ES mode is functional in the 25°C ± 5°C am­bient temperaturerange that is required when pro­gramming theM27V512. To activate the ES mode,
the programming equipment must force 11.5V to

12.5V on address line A9 of the M27V512. Two
identifier bytes may then be sequenced from the
device outputs by toggling address line A0 from
VILto VIH. All other address lines must be held at
VILduring Electronic Signature mode.

Byte 0 (A0=VIL) represents themanufacturer code
and byte 1 (A0=VIH) the device identifier code. For
the STMicroelectronics M27V512, these two iden­tifier bytes are given in Table 4 and can be read­out on outputs Q0 to Q7. Note that the M27V512
and M27C512 have the same identifier bytes.

ERASURE OPERATION (applies for UV EPROM)

The erasure characteristics of the M27V512 is
such that erasure begins when the cells are ex­posed to light with wavelengths shorter than ap­proximately 4000 Å. It should be noted that
sunlight and some type of fluorescent lamps have
wavelengths in the 3000-4000 Å range.

Research shows that constant exposure to room
level fluorescent lighting could erase a typical
M27V512 in about 3 years, while it would take ap­proximately 1 week to cause erasure when ex­posed to direct sunlight. If the M27V512 is to be
exposed to these types of lighting conditions for
extended periods of time, it is suggested that
opaque labels be put over the M27V512 window to
prevent unintentional erasure. The recommended
erasureprocedure for the M27V512 is exposureto
short wave ultraviolet light which has wavelength
2537 Å. The integrated dose (i.e. UV intensity x
exposure time) for erasure should be a minimum
of 15 W-sec/cm2. The erasure time with this dos­age is approximately 15 to 20 minutes using an ul­traviolet lamp with 12000 µW/cm2power rating.
The M27V512 should be placed within 2.5 cm (1
inch) of the lamp tubes during the erasure. Some
lamps have a filter on their tubes which should be
removed before erasure.

10/16

Table 12. Ordering Information Scheme

Example: M27V512 -100 K 1 TR

Device Type

Speed

(1)

-100

-120 = 120 ns

-150 = 150 ns

-200 = 200 ns

Package

F = FDIP28W
B = PDIP28
K = PLCC32
N = TSOP28: 8 x 13.4mm

Temperature Range

1 = –0 to 70 °C
6=–40to85°C

= 100 ns

M27V512

Option

TR = Tape& Reel packing

Note: 1. High Speed, see AC Characteristics section for further information.

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de­vice, please contact the ST Sales Office nearest to you.

11/16

M27V512

Table 13. FDIP28W - 28 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data

Symb

Typ Min Max Typ Min Max

A 5.71 0.225
A1 0.50 1.78 0.020 0.070
A2 3.90 5.08 0.154 0.200

B 0.40 0.55 0.016 0.022
B1 1.17 1.42 0.046 0.056

C 0.22 0.31 0.009 0.012

D 38.10 1.500

E 15.40 15.80 0.606 0.622
E1 13.05 13.36 0.514 0.526

e1 2.54 – – 0.100 – –
e3 33.02 – – 1.300 – –

eA 16.17 18.32 0.637 0.721

L 3.18 4.10 0.125 0.161

S 1.52 2.49 0.060 0.098

∅ 7.11 – – 0.280 – –

α 4° 15° 4° 15°

mm inches

N28 28

Figure 9. FDIP28W - 28 pin Ceramic Frit-seal DIP, with window, Package Outline

A2

B1 B e

A3A1A

L

α

C

eA

D2

eB

D

S

N

∅

1

E1 E

FDIPW-a

Drawing is not to scale.

12/16

Table 14. PDIP28 -28 pin Plastic DIP, 600 mils width, Package Mechanical Data

mm inches

Symb

Typ Min Max Typ Min Max

A – 5.08 – 0.200
A1 0.38 – 0.015 –
A2 3.56 4.06 0.140 0.160

B 0.38 0.51 0.015 0.020
B1 1.52 – – 0.060 – –

C 0.20 0.30 0.008 0.012
D 36.83 37.34 1.450 1.470

D2 33.02 – – 1.300 – –

E 15.24 – – 0.600 – –
E1 13.59 13.84 0.535 0.545

e1 2.54 – – 0.100 – –
eA 14.99 – – 0.590 – –
eB 15.24 17.78 0.600 0.700

L 3.18 3.43 0.125 0.135
S 1.78 2.08 0.070 0.082
α 0° 10° 0° 10°

M27V512

N28 28

Figure 10. PDIP28 - 28 pin Plastic DIP, 600 mils width, Package Outline

A2A1A

L

B1 B e1

Cα

eA

D

S

N

E1 E

1

PDIP

Drawing is not to scale.

13/16

M27V512

Table 15. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Mechanical Data

Symb

A 2.54 3.56 0.100 0.140

A1 1.52 2.41 0.060 0.095
A2 – 0.38 – 0.015

B 0.33 0.53 0.013 0.021

B1 0.66 0.81 0.026 0.032

D 12.32 12.57 0.485 0.495

D1 11.35 11.56 0.447 0.455
D2 9.91 10.92 0.390 0.430

E 14.86 15.11 0.585 0.595

E1 13.89 14.10 0.547 0.555
E2 12.45 13.46 0.490 0.530

e 1.27 – – 0.050 – –

F 0.00 0.25 0.000 0.010
R 0.89 – – 0.035 – –
N32 32

Nd 7 7
Ne 9 9

CP 0.10 0.004

Typ Min Max Typ Min Max

mm inches

Figure 11. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Outline

D

D1

1N

Ne E1 E

F

D2/E2

A2

B

0.51 (.020)

1.14 (.045)

PLCC

Drawing is not to scale.

Nd

R

CP

A

A1

B1

e

14/16

M27V512

Table 16. TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4mm, Package Mechanical Data

Symb

Typ Min Max Typ Min Max

A 1.25 0.049
A1 0.20 0.008
A2 0.95 1.15 0.037 0.045

B 0.17 0.27 0.007 0.011

C 0.10 0.21 0.004 0.008

D 13.20 13.60 0.520 0.535
D1 11.70 11.90 0.461 0.469

E 7.90 8.10 0.311 0.319

e 0.55 – – 0.022 – –

L 0.50 0.70 0.020 0.028

α 0° 5° 0° 5°

N28 28
CP 0.10 0.004

mm inches

Figure 12. TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4mm, Package Outline

A2

22

21

e

28

1

E

B

78

D1

D

DIE

A

CP

C

TSOP-c

Drawing is not to scale

LA1 α

15/16

M27V512

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