Datasheet M27V402 Datasheet (SGS Thomson Microelectronics)

M27V402

4 Mbit (256Kb x 16) Low Voltage UV EPROM and OTP EPROM

■ LOW VOLTAGEREAD OPERATION:

3V to 3.6V

■ FAST ACCESS TIME: 120ns

■ LOW POWERCONSUMPTION:

– Active Current15mA at 5MHz
– Standby Current 20µA

■ PROGRAMMING VOLTAGE: 12.75V ± 0.25V

■ PROGRAMMING TIME: 100µs/byte (typical)

■ ELECTRONIC SIGNATURE

– Manufacturer Code:20h
– Device Code: 8Dh

DESCRIPTION

The M27V402 is a low voltage, low power 4 Mbit
UV erasable and electrically programmable
EPROM, ideally suited for handheld and portable
microprocessor systems requiring large programs.
It is organized as 262,144 by16 bits.

The M27V402 operates in the read mode with a
supply voltage as low as 3V. The decrease in op­erating power allowseither a reduction of the size
of the battery or an increase in the time between
battery recharges.

The FDIP40W (window ceramic frit-seal package)
has a transparent lid which allows the user to ex­pose thechip to ultraviolet light to erase the bit pat­tern. A new pattern can then be written to the
device by followingthe programming procedure.

40

1

FDIP40W (F) PDIP40 (B)

PLCC44 (K) TSOP40 (N)

Figure 1. Logic Diagram

V

18

A0-A17 Q0-Q15

CC

40

V

PP

1

10 x 20 mm

16

Table 1. Signal Names

A0-A17 Address Inputs
Q0-Q15 Data Outputs
E Chip Enable
G Output Enable
V

PP

V

CC

V

SS

Program Supply
Supply Voltage
Ground

E

G

M27V402

V

SS

AI01819

1/15May 1998

M27V402

Figure 2A. DIP Pin Connections

V

PP

Q15
Q14
Q13
Q12
Q11
Q10

Q9
Q8

V

SS
Q7

Q6
Q5
Q4
Q3
Q2

Q0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

M27V402

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
2120

AI01862

V

CC

A17E
A16
A15
A14
A13
A12
A11
A10
A9
V

SS

A8
A7
A6
A5
A4
A3
A2Q1
A1
A0G

Figure 2B. LCC Pin Connections

CC

VPPE

Q15

Q13

Q14

Q12
Q11
Q10

Q9 A10
Q8

V

SS

NC

Q6
Q5
Q4

12

Q3

Q2

Q1

Q0

M27V402

23

G

A17

V

NC

1

NC

44

A0

A1

A16

A2

A15

A3

A14

34

A4

A13
A12
A11

A9
V

SS

NC
A8Q7
A7
A6
A5

AI01820

Figure 2C. TSOP Pin Connections

A9
A10
A11
A12 A6
A13
A14
A15
A16
A17

V

CC

V

PP

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

DQ9
DQ8

1

M27V402

10

(Normal)

11

E

20 21

40

31
30

AI01821

V

SS

A8
A7

A5
A4
A3
A2
A1
A0
G
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
V

SS

Warning: NC = Not Connected.

For applications wherethe content isprogrammed
only one time and erasure is not required, the
M27V256 is offered in PDIP40, PLCC44 and
TSOP40 (10 x 20 mm) packages.

DEVICE OPERATION

The operating modes of the M27V402 arelisted in
the OperatingModes table. A single power supply
is required in the read mode. All inputs are TTL
levels except for VPPand 12V on A9 forElectronic
Signature.

Read Mode

The M27V402 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output controland should
be used to gate data to the output pins,
independent of device selection. Assuming that
the addresses arestable, the address accesstime
(t

) is equal to the delay from E to output

AVQV

(t

). Data is availableattheoutput after a delay

ELQV

of t

from the falling edge of G, assuming that

GLQV

E has been low and the addresses have been
stable for at least t

AVQV-tGLQV

.

2/15

M27V402

Table 2. Absolute Maximum Ratings

(1)

Symbol Parameter Value Unit

T

A

T

BIAS

T

STG

(2)

V

IO

V

CC

(2)

V

A9

V

PP

Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may

cause permanent damage to the device. These are stress ratings onlyand operation of the device atthese or anyother conditions
above those indicated in the Operating sections of this specification is not implied. Exposure toAbsolute Maximum Rating condi­tions for extended periods may affect device reliability. Referalso to the STMicroelectronics SUREProgram andotherrelevant qual­ity documents.

2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V

3. Depends on range.

Ambient Operating Temperature
Temperature Under Bias –50 to 125 °C
Storage Temperature –65 to 150 °C

Input or Output Voltage (except A9) –2 to 7 V
Supply Voltage –2 to 7 V
A9 Voltage –2 to 13.5 V
Program Supply Voltage –2 to 14 V

+0.5V with possible overshoot to VCC+2V for a period less than20ns.

CC

(3)

–40 to 125 °C

Table 3. Operating Modes

Mode E G A9

Read
Output Disable V
Program

V
Verify V
Program Inhibit
Standby
Electronic Signature

Note: X = VIHor VIL,VID= 12V ± 0.5V.

V

IL

IL

Pulse V

IL

IH

V

IH

V

IH

V

IL

V

IL

V

IH

IH

V

IL

V

IH

X
XV
X
XVPPData Out
X

XX

V

IL

V

ID

V

PP

V

or V

CC

SS

or V

CC

SS

V

PP

V

PP

V

or V

CC

SS

V

CC

Q0-Q15

Data Out

Hi-Z

Data In

Hi-Z
Hi-Z

Codes

Table 4. Electronic Signature

Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data

Manufacturer’s Code
Device Code

V

IL

V

IH

Standby Mode

The M27V402 has a standbymode which reduces
the supply current from 20mA to 20µA with low
voltage operationVCC≤ 3.6V, see Read Mode DC

00100000 20h
10001101 8Dh

Characteristics table for details. The M27V402 is
placed in the standby mode by applying a CMOS
high signal to the E input. When in the standby
mode, the outputs are in a high impedance state,
independent of the G input.

3/15

M27V402

Table 5. AC Measurement Conditions

High Speed Standard

Input Rise and Fall Times ≤ 10ns ≤ 20ns
Input Pulse Voltages 0 to3V 0.4V to 2.4V
Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V

Figure 3. AC Testing Input OutputWaveform

High Speed

3V

1.5V

0V

Standard

2.4V

0.4V

Table 6. Capacitance

(1)

(TA=25°C, f = 1 MHz)

2.0V

0.8V

AI01822

Figure 4. AC Testing Load Circuit

1.3V

1N914

3.3kΩ

DEVICE
UNDER

TEST

C

L

CL= 30pF for HighSpeed
CL= 100pF for Standard
CLincludes JIG capacitance

OUT

AI01823B

Symbol Parameter Test Condition Min Max Unit

V

C

IN

C

OUT

Note: Sampled only, not 100% tested.

Input Capacitance
Output Capacitance V

=0V

IN

=0V 12 pF

OUT

6pF

Two Line Output Control

Because EPROMs are usually used in larger
memory arrays, the product features a 2 line con­trol function whichaccommodates the use of mul­tiple memory connection. The two line control
function allows:

a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention

will not occur.

4/15

For the most efficient use of these two control
lines, E should bedecodedand used asthe prima­ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect­ed memory devicesare intheir lowpower standby
mode and that the output pins are only active
when data is required from a particular memory
device.

M27V402

Table 7. Read Mode DC Characteristics

(1)

(TA = 0to 70°C, –20 to 70°C, –20 to 85°C or –40 to 85°C; VCC= 3.3V ± 10%; VPP=VCC)

Symbol Parameter TestCondition Min Max Unit

I

I

I

CC

I

CC1

I

CC2

I
V

V

IH

V

V

Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.

Input Leakage Current

LI

Output Leakage Current

LO

Supply Current

Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current

PP

Input Low Voltage –0.3 0.8 V

IL

(2)

Input High Voltage 2
Output Low Voltage

OL

Output High Voltage TTL

OH

Output High Voltage CMOS

2. Maximum DC voltage on Output is V

CC

+0.5V.

E=V

IL

f = 5MHz, V

E>V

0V ≤ V

0V ≤ V

,G=VIL,I

CC

I

OH

I

OH

≤ V

IN

CC

≤ V

OUT

CC

= 0mA,

OUT

= 3.6V

CC

E=V

IH

– 0.2V, VCC= 3.6V

V

PP=VCC

I

= 2.1mA

OL

= –400µA
= –100µAV

2.4 V
–0.7V

CC

±10 µA
±10 µA

20 mA

1mA
20 µA
10 µA

V

+1

CC

0.4 V

V

V

System Considerations

The power switching characteristics of Advanced
CMOS EPROMs requirecareful decoupling of the
devices. The supply current, ICC, has three seg­ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the fallingand rising edgesof E. The magnitudeof
the transient current peaks is dependent on the
output capacitive and inductive loading of the de­vice.

The associated transient voltage peaks can be
suppressed by complying with the two line output
control and by properly selected decoupling ca­pacitors. It is recommended that a 0.1µF ceramic
capacitor be used on every device between V

CC

and VSS. This should be a high frequency capaci­tor of low inherent inductance and should be
placed as close to the device as possible. In addi­tion, a 4.7µF bulk electrolytic capacitor should be

used between VCCand VSSfor every eight devic­es. The bulk capacitor should be located near the
power supply connection point.Thepurpose of the
bulk capacitor is to overcome the voltage drop
caused bythe inductive effects of PCB traces.

Programming

When delivered (and after each erasure for UV
EPROM), all bits of the M27V402 are in the ’1’
state. Data is introduced by selectively program­ming ’0’s into the desired bit locations. Although
only ’0’s will beprogrammed, both ’1’s and ’0’s can
be present in the data word. The only way to
change a ’0’ to a’1’is by die exposure to ultraviolet
light (UV EPROM). The M27V402 is in the pro­gramming modewhen VPPinput is at12.75V, Gia
at VIHand E is pulsed to VIL. The data to be pro­grammedis applied to16 bitsin paralleltothe data
output pins.

The levels required for the address and data in­puts are TTL. VCCis specified to be 6.25V ±

0.25V.

5/15

M27V402

Table 8. Read Mode AC Characteristics

(1)

(TA = 0to 70°C, –20 to 70°C, –20 to 85°C or –40 to 85°C; VCC= 3.3V ± 10%; VPP=VCC)

M27V402

Symbol Alt Parameter Test Condition

Min Max Min Max Min Max

t

AVQV

t

ELQV

t

GLQV

(2)

t

EHQZ

(2)

t

GHQZ

t

AXQX

Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.

2. Sampled only, not 100% tested.

Address Validto

t

ACC

Output Valid
Chip Enable Low to

t

CE

Output Valid
Output Enable Low to

t

OE

Output Valid
Chip Enable High to

t

DF

Output Hi-Z
Output EnableHigh to

t

DF

Output Hi-Z
Address Transition to

t

OH

Output Transition

E=V

G=V

G=V

E=V

,G=V

IL

E=V

E=V

,G=V

IL

IL

IL

IL

IL

IL

IL

120 150 200 ns

120 150 200 ns

60 80 100 ns

0 50 0 50 0 50 ns

0 50 0 50 0 50 ns

500ns

Figure 5. Read Mode AC Waveforms

Unit-120 -150 -200

A0-A17

E

G

Q0-Q15

tAVQV

tELQV

tGLQV

VALID

tAXQX

DATA OUT

tEHQZ

tGHQZ

Hi-Z

AI00731

6/15

M27V402

Table 9. Programming Mode DC Characteristics

(1)

(TA=25°C; VCC= 6.25V ± 0.25V; VPP= 12.75V ± 0.25V)

Symbol Parameter Test Condition Min Max Unit

I

I

CC

I

PP

V
V

V

OL

V

OH

V

Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.

Input Leakage Current

LI

Supply Current 50 mA
Program Current
Input Low Voltage –0.3 0.8 V

IL

Input High Voltage 2 VCC+ 0.5 V

IH

Output Low Voltage
Output High Voltage TTL IOH= –400µA 2.4 V
A9 Voltage 11.5 12.5 V

ID

Table 10. ProgrammingMode AC Characteristics

0 ≤ V

I

OL

(1)

≤ V

IN

E=V

= 2.1mA

CC

IL

±10 µA

50 mA

0.4 V

(TA=25°C; VCC= 6.25V ± 0.25V; VPP= 12.75V ± 0.25V)

Symbol Alt Parameter Test Condition Min Max Unit

t

AVEL

t

QVEL

t

VPHEL

t

VCHEL

t

ELEH

t

EHQX

t

QXGL

t

GLQV

t

GHQZ

t

GHAX

Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.

2. Sampled only, not 100% tested.

t
t

t

VPS

t

VCS

t

PW

t

DH

t

OES

t

OE

t

DFP

t

AS

DS

AH

Address Valid to Chip Enable Low 2 µs
Input Validto Chip Enable Low 2 µs
VPPHigh to Chip Enable Low
VCCHigh to Chip Enable Low

2 µs

2 µs
Chip Enable Program Pulse Width 95 105 µs
Chip Enable High to Input Transition 2 µs
Input Transition to Output Enable Low 2 µs
Output Enable Low to Output Valid 100 ns
Output Enable High to Output Hi-Z 0 130 ns
Output Enable High to Address

Transition

0ns

7/15

M27V402

Figure 6. Programming and Verify Modes AC Waveforms

A0-A17

tAVEL

Q0-Q15

V

PP

V

CC

E

G

DATA IN

tQVEL

tVPHEL

tVCHEL

tELEH

Figure 7. Programming Flowchart

VCC= 6.25V, VPP= 12.75V

n=0

E = 100µs Pulse

NO

NO

VERIFY

YES

Last

NO

Addr

YES

CHECK ALL WORDS

1st: VCC=6V

2nd: VCC= 4.2V

++ Addr

YES

++n

=25

FAIL

VALID

DATA OUT

tEHQX

tGLQV

tQXGL

PROGRAM VERIFY

PRESTO II Programming Algorithm

PRESTO II Programming Algorithm allows the
whole array to be programmed with a guaranteed
margin, in a typical time of 26.5 seconds. Pro­gramming with PRESTO II consists of applying a
sequence of 100µs program pulses to each byte
until a correct verify occurs (see Figure 7). During
programming and verify operation, a MARGIN
MODE circuitis automatically activated in order to
guarantee that each cell is programmed with
enough margin. No overprogram pulse is applied
since the verify in MARGIN MODE at VCCmuch
higher than 3.6V provides necessary margin to
each programmedcell.

Program Inhibit

Programming of multiple M27V402s in parallel
with different datais also easilyaccomplished. Ex­cept for E, all like inputs including G of the parallel
M27V402 may be common. A TTL low level pulse
applied to a M27V402’s E input, with VPPat

12.75V, will programthat M27V402. A high levelE
input inhibits the other M27V402s from being pro­grammed.

Program Verify

A verify (read) should be performed on the pro-

AI00726C

grammed bitsto determine that they were correct­ly programmed. The verifyis accomplished with G
at VIL, E at VIH,VPPat 12.75V and VCCat 6.25V.

tGHQZ

tGHAX

AI00730

8/15

M27V402

On-Board Programming

The M27V402 can be directly programmed in the
application circuit. See the relevant Application
Note AN620.

Electronic Signature

The Electronic Signature (ES) mode allows the
reading out of a binary codefrom an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically matchthe deviceto be programmed
with its corresponding programming algorithm.
The ES mode is functional in the 25°C ± 5°C am­bient temperaturerange that is required when pro­gramming theM27V402. To activate the ESmode,
the programming equipment must force 11.5V to

12.5V on address line A9 of the M27V402 with
VPP=VCC=5V. Two identifier bytes may then be
sequenced from thedeviceoutputsby toggling ad­dress line A0 from VILto VIH. All other address
lines must be held at VILduring Electronic Signa­ture mode. Byte 0 (A0=VIL) represents the manu­facturer code and byte 1 (A0=VIH) the device
identifier code. For the STMicroelectronics
M27V402, these two identifier bytes are given in
Table 4 and canbe read-out onoutputs Q0to Q7.

ERASUREOPERATION (applies to UVEPROM)

The erasure characteristics of the M27V402 is
such that erasure begins when the cells are ex­posed to light with wavelengths shorter than ap­proximately 4000Å. Itshould benoted thatsunlight
and some type of fluorescent lamps have wave­lengths in the 3000-4000Å range. Research
shows that constant exposure to room level fluo­rescent lighting could erase a typical M27V402 in
about 3years, while it would takeapproximately 1
week to cause erasure when exposed to direct
sunlight. Ifthe M27V402 is to be exposed to these
types of lighting conditions forextended periods of
time, it is suggestedthat opaque labels be put over
the M27V402 windowto prevent unintentional era­sure. The recommended erasure procedure for
the M27V402is exposure to shortwave ultraviolet
light which has a wavelength of 2537Å. The inte­grated dose (i.e. UV intensity xexposure time) for
erasure should be a minimum of 15 W-sec/cm2.
The erasure time with this dosage is approximate­ly 15 to 20 minutes using an ultraviolet lamp with
12000 µW/cm2power rating. The M27V402
should be placed within2.5 cm (1inch) of the lamp
tubes during theerasure.Some lamps haveafilter
on their tubes which should be removed before
erasure.

9/15

M27V402

Table 11. OrderingInformation Scheme

Example: M27V402 -120 K 1 TR

Device Type

Speed

-120 = 120 ns

-150 = 150 ns

-200 = 200 ns

Package

F = FDIP40W
B = PDIP40
K = PLCC44
N =TSOP40: 10 x 20mm

Temperature Range

1 =–0 to 70°C
4 =–20 to 70°C
5 =–20 to 85°C
6 =–40 to 85°C

Option

TR =Tape& Reel Packing

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de­vice, please contact the ST SalesOffice nearest to you.

10/15

M27V402

Table 12. FDIP40W - 40 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data

Symb

A 5.72 0.225
A1 0.51 1.40 0.020 0.055
A2 3.91 4.57 0.154 0.180
A3 3.89 4.50 0.153 0.177

B 0.41 0.56 0.016 0.022
B1 1.45 – – 0.057 – –

C 0.23 0.30 0.009 0.012

D 51.79 52.60 2.039 2.071

D2 48.26 – – 1.900 – –

E 15.24 – – 0.600 – –
E1 13.06 13.36 0.514 0.526

e 2.54 – – 0.100 – –
eA 14.99 – – 0.590 – –
eB 16.18 18.03 0.637 0.710

L 3.18 0.125

S 1.52 2.49 0.060 0.098

∅ 7.62 – – 0.300 – –

α 4° 11° 4° 11°

N40 40

Typ Min Max Typ Min Max

mm inches

Figure 8. FDIP40W - 40 pin Ceramic Frit-seal DIP, with window, Package Outline

A2

B1 B e

A3A1A

L

α

C

eA

D2

eB

D

S

N

∅

1

Drawing is notto scale.

E1 E

FDIPW-a

11/15

M27V402

Table 13. PDIP40 - 40 pin Plastic DIP, 600 mil width, Package Mechanical Data

Symb

Typ Min Max Typ Min Max

A 4.45 – – 0.175 – –
A1 0.64 0.38 – 0.025 0.015 –
A2 3.56 3.91 0.140 0.154

B 0.38 0.53 0.015 0.021
B1 1.14 1.78 0.045 0.070

C 0.20 0.31 0.008 0.012
D 51.78 52.58 2.039 2.070

D2 48.26 – – 1.900 – –

E 14.80 16.26 0.583 0.640
E1 13.46 13.99 0.530 0.551
e1 2.54 – – 0.100 – –
eA 15.24 – – 0.600 – –
eB 15.24 17.78 0.600 0.700

L 3.05 3.81 0.120 0.150

S 1.52 2.29 0.060 0.090

α 0° 15° 0° 15°

N40 40

mm inches

Figure 9. PDIP40 - 40 pin Plastic DIP, 600 mil width, Package Outline

A2A1A

L

α

B1 B e1

D2

D

S

N

E1 E

1

Drawing is notto scale.

C

eA
eB

PDIP

12/15

M27V402

Table 14. PLCC44 - 44 lead Plastic Leaded Chip Carrier,square, Package Mechanical Data

Symb

Typ Min Max Typ Min Max

A 4.20 4.70 0.165 0.185
A1 2.29 3.04 0.090 0.120
A2 – 0.51 – 0.020

B 0.33 0.53 0.013 0.021
B1 0.66 0.81 0.026 0.032

D 17.40 17.65 0.685 0.695

D1 16.51 16.66 0.650 0.656
D2 14.99 16.00 0.590 0.630

E 17.40 17.65 0.685 0.695
E1 16.51 16.66 0.650 0.656
E2 14.99 16.00 0.590 0.630

e 1.27 – – 0.050 – –

F 0.00 0.25 0.000 0.010
R 0.89 – – 0.035 – –
N44 44

CP 0.10 0.004

mm inches

Figure 10. PLCC44 -44 lead Plastic Leaded Chip Carrier, square, Package Outline

D

D1

1N

Ne E1 E

F

D2/E2

A2

B

0.51 (.020)

1.14 (.045)

Nd

R

PLCC

Drawing is notto scale.

CP

A1

B1

e

A

13/15

M27V402

Table 15. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data

Symb

Typ Min Max Typ Min Max

A 1.20 0.047

A1 0.05 0.15 0.002 0.006
A2 0.95 1.05 0.037 0.041

B 0.17 0.27 0.007 0.011
C 0.10 0.21 0.004 0.008
D 19.80 20.20 0.780 0.795

D1 18.30 18.50 0.720 0.728

E 9.90 10.10 0.390 0.398

e 0.50 - - 0.020 - -

L 0.50 0.70 0.020 0.028

α 0° 5° 0° 5°
N40 40

CP 0.10 0.004

mm inches

Figure 11. TSOP40 -40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline

A2

1N

e

E

B

N/2

D1

D

DIE

A

CP

C

TSOP-a

Drawing is notto scale

LA1 α

14/15

M27V402

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of use ofsuch information norfor any infringement of patents orother rightsof third parties which may result from itsuse. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces allinformation previously supplied. STMicroelectronics products are not
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